EETimes ae DESIGNLINES | POWER MANAGEMENT DESIGNLINE* htos/woww catines.com/designline/power-management-esignlinel> Choosing The Right Switching Frequency For Buck Converter 8y Rlcbrd Nowakowas and rin King, Texas neues ne, 10252008 0 Doct curronto-rectcutent(2CIDC) conv ors wih fastrsuitehng requonces ste becoming papules ave to thelr bitte decrease the 122. On the ator hand, tne demands fom the point of oad (POL) power supply ‘We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By clicking “Accept A", you consent to the use of ALL the cookies. However, you may vist “Cookie Settings” to provide a controlled consent Cookie Settings Acceptsuch ap DSP. ASIC or FPGA. Te bound the filer design and performance expectations, the allowable roplavoage is 20 mV. which is ‘bout one percent of he output vatag, and the pa to-peak inductor curtent' chosen st 1A Independent designs at raquences of 360, 700, and 1600 kHz wil be compared iustate the benefis and obstacles. The TPSS4317, 1.8 Nz, low-voltage, 3A synctronous-buck DCIDC converter wit inlogratod MOSFET was chosen asthe regulator in each example. The power pin-t-oad applications. 8 programmable frequency, extemal compensation and Is rtended for Nh-densty processor PARTNER CONTENT IEW ALL ))< HTTPS./WWNW_EETIMES COMIC ATEGORY/SPONSORED-CONTENT/> GUC GUC Taped Out 3nm 8.6Gbps HBM3 and STbpsimm GLink-25D IP Using TSMC Advanced Packaging Technology < btw eeimes com/que taped out f pee Corp. 04.05.2028, scomlgues 1 ‘road D¢-DC Converter Portfolio Dominates Supplier Selection < hitps:/ww.cetimes.comprosd-de-de-converter PUKE "PYF postfoie-dominates-sunplier-slection> bns-hbmnd-and-Stbps-mm-slinks2-Sdepusing emeadvan ‘SinRBDUKE Technology 04.08.2023, Boees We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” to provide a controled consent, Cookie Setings Accept Alugernt: Foeeitkdie ReBANGEREL = Vout x(1-D)(21x Fs) whlthBOS = + A peak-to-peak; D = 1.8 WIS V=0.36 seated rogue Gadi Fearangng ©=2471(0xF9x79) vir 7V= 207, = 1A peakpeak hitpsuhwwwsetimes.com/document asp?doc id=13340038utm_sourcs Formal 2 assumes a capactoris used that has negligible series resistance, which is tue for ceramic capacitor. Ceramic capactors were chosen fr all tee designs because of ther low resistance ang smal ie, The muti of wo shown above inthe rearranged Equation 2 ‘counts for capacitance drop associated wih DC bas, since his effects nt accounted fori the datasheats of mest ceramic capacitors ‘The ciruitin Figure 4 was used to evaluat the prformance ofeach design on the bonch, a caemTonl - HI] 4 io se cooks on our nes oe eu th mst bart expen by remem your frre an eos ists. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” fo provide a controled consent, Cookie Sotings: Acceptdesigns are listed in Table 1 , and were chosen based on the resulls from the equations above. (Click to Enlarge Image) Table 1: Capacitor and inductor selections at 350kHz, ZOOkHz, and 1600 kHz. Note that the DC resistance of each inductor decreased as the frequency increased. This is due to less copper length needed for fewer turns. The error amplifier compensation components were designed independently for each switching frequency. The calculations for selecting the ‘compensation values are beyond the scope of this article. MINIMUM ON-TIME Digtal converere-c-digtal converter integrated ecu (1) are characterized with 9 ii on te minimum contllabi onine, whieh the ‘narrowest achivable pulse width of te pulse width modulation (PWM) cxcut. Ina buck converter, he percentage of time thatthe Fld effect trarsistor (FET) fs on during a swiching cycles called he duly cycle, and is ual tothe ratio of the output voltage Lo inp vlage We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” fo provide a controled consent, Cookie Sotings AcceptFrqueney | Minimum Duty Cyle | Minimum Vo @svin sia 052s D9 (Vie So0kT a O9V Vien Toit 2s DV SM ss av (Click to Enlarge Image) Table 2: Minimum output voltage with 150 ns minimum on-time. In this example, a 1.8V output can be generated with a 1.6 MHz switching frequency. However, ifthe frequency is 3MHz, the lowest possible output voltage is limited to 2.3 V and the DG/DC converter will skip pulses. The alternative is to lower the input voltage or reduce the frequency. It is a good idea to check the DGIDC converter datasheet for a guaranteed minimum controllable on-time before selecting a switching frequency. PULSE SKIPPING Pale skipping occurs when the DCIDC converter cannot extinguish the gate drive pulses fast enough to mainiain the desired ety cyte. The power suply wily to regulate the oul voltage, bul te pple voltage wil increase due to the pulkes being farther apa, Due tothe plea skipping, ha ull pc il ahi mub-harmonic eompananie, which may mean! nose ins. ala pai hat Ihc We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” fo provide a controled consent, Cookie Sotings: Accept(Click to Enlarge Image) ‘The loss components of interest from our three examples come from the FET driving loss, the FET ‘switching loss and the inductor loss. The FET resistance and IC loss are consistent since the same IC is used in all three designs. Since ceramic capacitors were chosen in each example, the capacitor loss is negligible due to their low equivalent series resistance. To show the effects of high frequency ‘switching, the efficiency of each example was measured and illustrated in Figure 2 ———— We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” to provide a controled consent, Cookie Sotings: Accept3 shows the inductor an capacter values withthe pas area required onthe printed crcl boar, (Click to Enlarge Image) Table 3: Component size and total area requirements ‘The recommended pad area of a capacitor or inductor is slightly larger than the individual component itself, and the pad area dimension is accounted for in each of the three design examples. Then, the total area was derived by adding the area occupied by each component, which includes the pad sizes for the IC, the fiter and all other small resistors and capacitors multiplied by a factor of two to account for component spacing. The total area savings from 350 kHz to 1600 kHz is significant and provides a 50 percent reduction in fiter size and a 35 percent reduction in board space, saving almost 100mm* Homaver, the law of diminishing retums apples since the capactance and inductance values cannot be reduced to nothing! In other words, ‘using the frequency higher wil not continually reduce the overalsize since there tnlaton to appropitey sed mass produced Incutors and eapackore ‘TRANSIENT RESPONSE We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” fo provide a controled consent, Cookie Sotings Accept(Click to Enlarge Image) Figure 3: Bode plots at 350 kHz, 700 kHz, and 1600 kHz. ‘The cross over frequency is approximately one-eighth of the switching frequency, When using a fast switching DC/DC converter, make sure the power IC error amplifier has enough bandwidth to support a high crossover frequency. The TPS54317 error amplifier unity gain bandwidth is typically SMHz. ‘The actual transient response times are shown in Table 4 with the associated voltage peak overshoot value. We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” to provide a controled consent, Cookie Sotings: AcceptFor example, four outpus canbe ted tageter switching at 50 KH each, or an effective frequency of 2 WH. The benefis are lower poe, ‘ecuced input bukeapactance, ose ransient response, and batter thermal management by spreading out the power dissipation over the Creu board. Up te eight TPS40140 devcos canbe connected and synchronized out of phase via dgta bus for a maximum effective ‘tequeney of 18m Conclusion ‘There ae tradeofs to designing hghrequency switching converters. Some ofthe advanlages shown in hs atl area sae Sze, faster transient response an smaller volage over and underehoots, On the other hand, the main penaly pad is a reduction of efciency an Increased heat issipation. There are potent pals to pushing the onvelope such as pulse sipping and noise Issues. When selecting a DDG converter for high frequency applications check the manufacture’ datashect for important specications suchas the minimum on-time, th gair-bandwith of the enor ampli, the FET resistance and swching los, Integrated orcs that perform well in these spetfeations wil costa premium, but ‘il be wort the pica and much easier to use when cornered with a ough design problem. Toleam more about simpitving power designs, esr for his free webinar tps:Hevent.on24 com/eventRegistration/EventLobbyServlet? target=r2920 jspzeferrer=Beventid=1629124&sesslonid=14key=896442262102AB81A857 1CCDEEIECT#O®Tag=Asourcepage=r ‘aster, “Simply Power Designs wih Meromodules Products" sponsored by Analog Devices [About the authors Both authors are witr Taxas Instruments Inc, Rich Nowakowsk has boos with Texas Instruments snes 1999 whore he serves a8 a Product Marketing Manager for OCIOG Convertors thin te High Performance Analog group Ha received both Ns Bachelors nElecncal Engineering and Masters in Business Acministration ‘fom North Dakota Stata University in Fara, ND. We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” to provide a controled consent, Cookie Sotings: AcceptWIRELESS INDUSTRY RESOURCES How far can a Bluetooth® signal go? Linux Study Guide Use ourineractve range estimator alto ‘Blstath® Tetnology for Liux Develops — alu oxpocted ange bases on varies Ko Team ceate Sistah prose ung teeronmert PHY, ad antenna gan yt, DBs and Bez, We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may visit Cookie Settings” fo provide a controled consent, Cookie Sotings: Acceptproved:otawap-aupport4or-poweran We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By Clicking “Accept AI, you consent tothe use of ALL the cookies. However, you may vsit"Cookie Settings” to provide a controled consent, Cookie Sotings Accept