Unit-4 Coa
Unit-4 Coa
General register :
A register is made up of flip-flops. In the CPU (Central Processing Unit), a
register is a one-of-a-kind, high-speed storage region. Combinational
circuits are used to implement data processing. Before processing, the data is
always defined in a register. Program implementation is faster thanks to the
registers.
The following are two essential functions implemented by registers in CPU
operation:
1. It can be used as a temporary data store site. This allows directly
implementing applications to have quick access to data when needed.
2. It can record the CPU's condition and information about the currently
executing programme.
The registers save the address of the next programme instruction,
signals from external devices, error messages, and various data.
If a CPU has some registers, these registers can be linked by a shared bus.
The below image depicts the general organization of seven CPU registers.
The control unit is in charge of the CPU bus system. The control unit
specifies the data flow via the ALU by selecting the ALU's function and
system components.
Let us consider R1←R2 + R3, and the functions implemented within the
CPU are as follows:
The term addressing modes refers to the way in which the operand of an
instruction is specified.
The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is actually executed.04-Sept-2019
Addressing Modes
The addressing modes help us specify the way in which an operand’s effective
address is represented in any given instruction.
The programs are generally written in high-level languages, as it’s a convenient way
in which one can define the variables along with the operations that a programmer
performs on the variables.
This program is later compiled so as to generate the actual machine code which
includes low-level instructions.
A set of low-level instructions has operands and opcodes. An addressing mode has no
relation with the opcode part. It basically focuses on presenting the address of the
operand in the instructions.
Implied Mode
Immediate Mode
Register Mode
In the implied mode, the operands are implicitly specified because, in this type
of instruction, the operand is implied in the accumulator register. All the register
reference instructions are implied-mode instructions that use an accumulator.
Immediate Mode
An operand field contains the actual operand that is to be used in conjunction with an
operation that is determined in the given instruction. The immediate-mode instructions
help initialize registers to a certain constant value.
Register Mode
In the register mode, the operands exist in those registers that reside within a CPU.
In this case, we select a specific register from a certain register field in the given
instruction..
In the register indirect mode, the instruction available to us defines that particular
register in the CPU whose contents provides the operand’s address in the memory
When the address stored in the register defines a data table in memory, it is very
crucial to decrement or increment the register after accessing the table every time. It can
be obtained using the decrement or increment instruction.
Direct Address Mode
In the direct address mode, the address part of the instruction is equal to the effective
address. The operand would reside in memory, and the address here is given directly by
the instruction’s address field. The address field would specify the actual branch
address in a branch-type instruction.
In an indirect address mode, control fetches the instruction available in the memory
and then uses its address part in order to (again) access memory to read its effective
address.
In the indexed addressing mode, the content of a given index register gets added to
an instruction’s address part so as to obtain the effective address.
The index register refers to a special CPU register that consists of an index value.
3. Explain about Data Transfer and Manipulation in computer organization ?
Data Transfer Instructions Data transfer instructions move information from one
place in the PC to one more without evolving the information content. The most well-
known moves are among memory and processor registers, between processor registers
and information or result, and between the processor registers themselves.
The data manipulation instructions in a typical computer are generally separated into
three essential sorts:
1. Arithmetic instructions
3. Shift instructions
Arithmetic instructions:
The logical instructions think about each piece of the operand independently
and treat it as a Boolean variable.
Shift Instructions:
Instructions to move the substance of an operand are very valuable and are
frequently given in a few varieties. Shifts are tasks in which the pieces of a word are
moved to the left or right. The piece moved in toward the finish of the word decides the
kind of shift utilized.
3.The number of bits is directly proportional to the memory range. i.e., the larger the
range requirement, the more number bits will be required.
4.If a system supports the virtual memory, then the memory range that needs to be
addressed by the instruction will be larger than the physical memory.
The operating system loads the machine instructions into the RAM. The CPU starts the
execution by fetching these instructions one by one. These fetched instructions are
stored in the instruction registers. In machine instructions, the bits are grouped based on
instruction format. Each bit gives specific information to the CPU to decode.
Information required by the CPU includes the address of the data and the operation to
be performed.
The instruction format is depicted in a rectangular box, symbolizing the instruction bits
in memory words or a control register.
The bits grouped are divided into three parts:
Addressing Mode:
The addressing mode indicates how the data is represented.
Opcode:
The opcode part indicates the operation type on the data.
Operand:
The operand part indicates either the data or the address of the data.
These instruction formats are a sequence of bits (0 and 1). These bits, when grouped,
are known as fields. Each field of the machine provides specific information to the CPU
related to the operation and location of the data.
The instruction format also defines the layout of the bits for an instruction. It can be of
variable lengths with multiple numbers of addresses.
These address fields in the instruction format vary as per the organization of the
registers in the CPU. The formats supported by the CPU depend upon the Instructions
Set Architecture implemented by the processor.
Depending on the multiple address fields, the instruction is categorized as follows:
1. Three address instruction
2. Two address instruction
3. One address instruction
4. Zero address instruction
A RISC style instruction engages “one word” in memory. Execution of the RISC
instructions are faster and take one clock cycle per instruction.
The hardwired control unit produces control signals which regulate the working of
processors hardware.
This is because the registers are the ‘fastest’ available memory source.
The registers are physically small and are placed on the same chip where the ALU and
the control unit are placed on the processor. The RISC instructions operate on the
operands present in processor’s registers.
RISC architecture.
All instructions in RISC are simple and execute one instruction per cycle.
The instructions are hardwired and there is no need for control store. For each
operation, we will have as defined hardwire. Making an instruction hardwired is making
a function or operation in instruction permanent using connected circuits.
RISC instructions are simple and are of fixed size. Each RISC instruction engages
a single memory word.
RISC instructions operate on processor registers only. The instructions that have
arithmetic and logic operation should have their operand either in the processor
register or should be given directly in the instruction.
Add R2, R3
But initially, at the start of execution of the program, all the operands are in memory.
So, to access the memory operands, the RISC instruction set
has Load and Store instruction.
The Load instruction loads the operand present in memory to the processor register.
The load instruction is of the form:
The load instruction above will load the operand present at memory location A to the
processor register R2.
The Store instruction stores the operand back to the memory. Generally, the Store
instruction is used to store the intermediate result or the final result in the memory. It is
of the form:
The Store instruction above will store the content in register R2 into the A a memory
location.