TPS65982

SLVSD02E – MARCH 2015 – REVISED AUGUST 2021

TPS65982 USB Type-C® and USB PD Controller, Power Switch, and High-Speed
Multiplexer
– 1 I2C secondary port
1 Features
• This device is certified by the USB-IF for PD2.0
2 Applications
– PD2.0 is no longer certifiable on new designs • Rugged PC and laptop
as of June 2020 • Docking station
– All new designs requiring certification should • Flat panel monitor
use a PD3.0 compliant device
3 Description
– Article on PD2.0 vs PD3.0
• Fully configurable USB PD controller The TPS65982 device is a stand-alone USB Type-C
– Control for external DC/DC supplies through and Power Delivery (PD) controller providing cable-
GPIO plug and orientation detection at the USB Type-
• Ex: TPS65982EVM C connector. Upon cable detection, the TPS65982
– Port data multiplexer device communicates on the CC wire using the USB
PD protocol. After successful USB PD negotiation
• USB 2.0 HS data and low speed endpoint
is complete, the TPS65982 enables the appropriate
• Sideband-use data for alternate modes
power path and configures alternate mode settings for
– GUI tool to easily configure TPS65982 for
internal and (optional) external multiplexers.
various applications
– Support for DisplayPort alternate mode and The mixed-signal front end on the CC pins advertises
thunderbolt alternate mode default, 1.5 A or 3 A for USB Type-C power sources,
– For a more extensive selection guide and detects a plug event and determines the Type-C cable
getting started information, please refer to orientation, and autonomously negotiates USB PD
www.ti.com/usb-c and E2E guide contracts using a Bi-phase Marked Coding (BMC) and
• Integrated fully managed power paths: the Physical Layer (PHY) protocol.
– Integrated 5-V, 3-A, 50-mΩ sourcing switch Device Information(1)
– Integrated 5-V to 20-V, 3-A, 95-mΩ bi-
PART NUMBER PACKAGE BODY SIZE (NOM)
directional load switch
BGA MicroStar
– Gate control and current sense for external 5-V Junior (96)
TPS65982 6.00 mm × 6.00 mm
to 20-V, 5-A bidirectional switch (back-to-back
NFBGA (96)
NFETs)
– UL2367 cert#: E169910-20150728 (1) For all available packages, see the orderable addendum at
– IEC62368-1 cert #: 111895 the end of the data sheet.
• Integrated robust power path protection 5A
– Integrated reverse current protection, 5 to 20 V

undervoltage protection, overvoltage protection,

and slew rate control the high-voltage bi- 5 to 20 V
External FET Sense and CTRL
VBUS
3A
directional power path 5V
3A
– Integrated undervoltage and overvoltage 3.3 V
Type-C Cable
2 CC/VCONN
protection and current limiting for inrush current Host Host
Interface
Detection and
USB PD Controller
CC1/2
USB
Type-C
protection for the 5-V/3-A source power path Connector
USB_TP/TN 2 D±
• USB Type-C® Power Delivery (PD) controller USB2.0 and High
USB_BP/BN 2 D±
Sideband-Use Speed
– 8 configurable GPIOs Data Mux SBU1/2 2 SBU1/2
Alternate Mode Mux Ctrl
– BC1.2 charging support GND
POL
SEL
EN

TPS65982
– USB PD 2.0 certified
– USB Type-C specification certified SuperSpeed Mux
Copyright © 2016, Texas Instruments Incorporated
– Cable attach and orientation detection
– Integrated VCONN switch Simplified Diagram
– Physical layer and policy engine
– 3.3-V LDO output for dead battery support
– Power supply from 3.3 V or VBUS source
– 1 I2C primary port

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65982
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Table of Contents
1 Features............................................................................1 7.22 BUSPOWERZ Configuration Characteristics..........27
2 Applications..................................................................... 1 7.23 Thermal Shutdown Characteristics......................... 28
3 Description.......................................................................1 7.24 Oscillator Characteristics........................................ 28
4 Revision History.............................................................. 2 7.25 Single-Wire Debugger (SWD) Timing
5 Description (continued).................................................. 4 Requirements.............................................................. 28
6 Pin Configuration and Functions...................................5 7.26 HPD Timing Requirements..................................... 28
7 Specifications................................................................ 11 7.27 Typical Characteristics............................................ 29
7.1 Absolute Maximum Ratings...................................... 11 8 Parameter Measurement Information.......................... 30
7.2 ESD Ratings..............................................................11 9 Detailed Description......................................................32
7.3 Recommended Operating Conditions.......................12 9.1 Overview................................................................... 32
7.4 Thermal Information..................................................12 9.2 Functional Block Diagram......................................... 33
7.5 Power Supply Requirements and Characteristics.....13 9.3 Feature Description...................................................33
7.6 Power Supervisor Characteristics.............................14 9.4 Device Functional Modes..........................................70
7.7 Power Consumption Characteristics(4) .................... 14 9.5 Programming............................................................ 76
7.8 Cable Detection Characteristics................................15 10 Application and Implementation................................ 81
7.9 USB-PD Baseband Signal Requirements and 10.1 Application Information........................................... 81
Characteristics.............................................................16 10.2 Typical Applications................................................ 81
7.10 USB-PD TX Driver Voltage Adjustment 11 Power Supply Recommendations..............................90
Parameter....................................................................16 11.1 3.3-V Power............................................................ 90
7.11 Port Power Switch Characteristics.......................... 17 11.2 1.8 V Core Power....................................................90
7.12 Port Data Multiplexer Switching Characteristics..... 20 11.3 VDDIO.....................................................................90
7.13 Port Data Multiplexer Clamp Characteristics.......... 22 12 Layout...........................................................................92
7.14 Port Data Multiplexer SBU Detection 12.1 Layout Guidelines................................................... 92
Characteristics.............................................................22 12.2 Layout Example...................................................... 96
7.15 Port Data Multiplexer Signal Monitoring Pullup 13 Device and Documentation Support........................110
and Pulldown Characteristics...................................... 22 13.1 Device Support......................................................110
7.16 Port Data Multiplexer USB Endpoint 13.2 Documentation Support........................................ 110
Characteristics.............................................................22 13.3 Receiving Notification of Documentation Updates 110
7.17 Port Data Multiplexer BC1.2 Detection 13.4 Support Resources............................................... 110
Characteristics.............................................................23 13.5 Trademarks........................................................... 110
7.18 Analog-to-Digital Converter (ADC) 13.6 Electrostatic Discharge Caution............................ 110
Characteristics.............................................................23 13.7 Glossary................................................................ 110
7.19 Input/Output (I/O) Characteristics........................... 24 14 Mechanical, Packaging, and Orderable
7.20 I2C Slave Characteristics........................................ 26 Information.................................................................. 110
7.21 SPI Controller Characteristics.................................27

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2019) to Revision E (August 2021) Page
• Updated the numbering format for tables, figures and cross-references throughout the document ..................1
• Globally changed instances of legacy terminology to controller and peripheral where SPI is mentioned.......... 1
• Updated the Features list....................................................................................................................................1
• Updated the Applications section....................................................................................................................... 1

Changes from Revision C (August 2016) to Revision D (June 2019) Page

• Added NFBGA package to the Device Information table....................................................................................1
• Added NFBGA package to the Pin Configuration and Functions section...........................................................5
• Added NFBGA package to the Thermal Information table............................................................................... 12

Changes from Revision B (May 2016) to Revision C (August 2016) Page

• Added the HRESET I/O voltage parameter to the Absolute Maximum Ratings table.......................................11
• Changed the value for the HBM from ±2000 to ±1500 in the ESD Ratings table............................................. 11

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• Changed the maximum values for the ILDO_3V3 (50 to 70 mA) and ILDO_3V3EX (10 to 30 mA) current
parameters in the Power Supply Requirements and Characteristics .............................................................. 13
• Updated the GPIO_RPU parameter to show values for DEBUG_CTL1/2 separately in the Input/Output (I/O)
Characteristics table......................................................................................................................................... 24
• Added parameters for HRESET in the Input/Output (I/O) Characteristics table............................................... 24

Changes from Revision A (June 2015) to Revision B (May 2016) Page

• Completed editorial changes to fix typographical errors and improve consistency of terminology.....................1

Changes from Revision * (March 2015) to Revision A (June 2015) Page

• Initial release of Production Data sheet.............................................................................................................. 1

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5 Description (continued)
The port power switch provides up to 3 A downstream at 5 V for legacy and Type-C USB power. An additional
bidirectional switch path provides USB PD power up to 3 A at a maximum of 20 V as either a source (host), sink
(device), or source-sink.
The TPS65982 is also an upstream-facing port (UFP), downstream-facing port (DFP), or dual-role port for data.
The port data multiplexer passes data to or from the top or bottom D+/D– signal pair at the port for USB 2.0
HS; additionally, the Sideband-Use (SBU) signal pair is used for Alternate Modes. The power management
circuitry supports dead battery or no-battery operation using VBUS as a primary power supply when 3.3 V is not
available.

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6 Pin Configuration and Functions

1 2 3 4 5 6 7 8 9 10 11

A GND LDO_1V8D SPI_CLK SPI_POCI I2C_SDA2 PP_HV PP_HV PP_HV HV_GATE2 SENSEN PP_5V0

B VDDIO GPIO0 SPI_CSZ SPI_PICO I2C_SCL2 I2C_IRQ2Z PP_HV GND HV_GATE1 SENSEP PP_5V0

C I2C_IRQ1Z GPIO1 GPIO4 PP_5V0

D I2C_SDA1 I2C_SCL1 DEBUG_CTL2 HRESET GPIO7 GND GPIO2 PP_5V0

E LDO_BMC UART_TX DEBUG_CTL1 GND GND GND GND GPIO5 MRESET

F I2C_ADDR UART_RX SWD_DATA GND GND GND GND BUSPOWERZ RESETZ

G LDO_3V3 R_OSC SWD_CLK GND GND GND GND GPIO6 GPIO3

H VIN_3V3 VOUT_3V3 GND GND GPIO8 SS GND PP_CABLE VBUS

J AUX_P AUX_N VBUS VBUS

K LDO_1V8A DEBUG2 DEBUG4 LSX_P2R USB_RP_N C_USB_TP C_USB_BP C_SBU1 RPD_G1 RPD_G2 VBUS

L GND DEBUG1 DEBUG3 LSX_R2P USB_RP_P C_USB_TN C_USB_BN C_SBU2 C_CC1 C_CC2 NC

Figure 6-1. ZQZ and ZBH Package 96-Pin BGA MicroStar Junior and NFBGA Top View

Application
High Power Low Power Ground GPIOs No Connect
Specific

Legend for Pinout Drawing

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Table 6-1. Pin Functions

PIN
TYPE CATEGORY POR STATE DESCRIPTION
NO. NAME
Ground and no
A1 GND Ground — Ground. Connect all balls to ground plane.
connect pins
External HV-FET
Positive sense for external high-voltage power-path current-sense
A10 SENSEN Analog input control and sense Analog input
resistance. Short pin to VBUS when unused.
pins and soft start
High-current 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin
A11 PP_5V0 Power —
power pins to GND when unused.
Low-current Output of the 1.8-V LDO for core digital circuits. Bypass with capacitance
A2 LDO_1V8D Power —
power pins CLDO_1V8D to GND.
Digital Digital core I/O
A3 SPI_CLK Digital input SPI serial clock. Ground pin when unused
output and control pins
SPI serial controller input from peripheral. This pin is used during boot
Digital core I/O
A4 SPI_POCI Digital input Digital input sequence to determine if the flash memory is valid. Refer to the Boot Code
and control pins
section for more details. Ground pin when unused.
I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO
Digital core I/O
A5 I2C_SDA2 Digital I/O Digital input (depending on configuration) through a 10-kΩ resistance when used or
and control pins
unused.
A6
High-current HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to
A7 PP_HV Power —
power pins GND when unused.
A8
External HV-FET
Analog Short to External NFET gate control for high-voltage power path. Float pin when
A9 HV_GATE2 control and sense
output VBUS unused.
pins and soft start
VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO
Low-current instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When
B1 VDDIO Power —
power pins not tied to LDO_3V3 and used as a supply input, bypass with capacitance
CVDDIO to GND.
External HV-FET
Positive sense for external high-voltage power-path current-sense
B10 SENSEP Analog input control and sense Analog input
resistance. Short pin to VBUS when unused.
pins and soft start
High-current 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin
B11 PP_5V0 Power —
power pins to GND when unused.
General purpose digital I/O 0. Float pin if it is configured as a push-pull
Digital core I/O
B2 GPIO0 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.
Digital Digital core I/O
B3 SPI_CSZ Digital input SPI chipselect. Ground pin when unused.
output and control pins
Digital Digital core I/O
B4 SPI_PICO Digital input SPI serial controller output to peripheral. Ground pin when unused.
output and control pins
I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO
Digital core I/O
B5 I2C_SCL2 Digital I/O Digital input (depending on configuration) through a 10-kΩ resistance when used or
and control pins
unused.
Digital Digital core I/O I2C port 2 interrupt. Active-low. Implement externally as an open-drain with
B6 I2C_IRQ2Z Hi-Z
output and control pins a pullup resistance. Float pin when unused.
High-current HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to
B7 PP_HV Power —
power pins GND when unused.
Ground and no
B8 GND Ground — Ground. Connect all balls to ground plane.
connect pins
External HV-FET
Analog Short to External NFET gate control for high-voltage power path. Float pin when
B9 HV_GATE1 control and sense
output SENSEP unused.
pins and soft start
Digital Digital core I/O I2C port 1 interrupt. Active-low. Implement externally as an open-drain with
C1 I2C_IRQ1Z Hi-Z
output and control pins a pullup resistance. Float pin when unused.
General purpose digital I/O 4. Configured as hot-plug detect (HPD) TX,
GPIO4 Digital core I/O
C10 Digital I/O Hi-Z HPD RX, or both when DisplayPort mode is supported. Ground pin with a
(HPD TXRX) and control pins
1-MΩ resistor when unused in the application.
High-current 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin
C11 PP_5V0 Power —
power pins to GND when unused.
General purpose digital I/O 1. Float pin if it is configured as a push-pull
Digital core I/O
C2 GPIO1 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.

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Table 6-1. Pin Functions (continued)

PIN
TYPE CATEGORY POR STATE DESCRIPTION
NO. NAME
C3
C4
C5
Ground and no
C6 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
C7
C8
C9
I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO
Digital core I/O
D1 I2C_SDA1 Digital I/O Digital input (depending on configuration) through a 10-kΩ resistance when used or
and control pins
unused.
General purpose digital I/O 2. Float pin if it is configured as a push-pull
Digital core I/O
D10 GPIO2 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.
High-current 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin
D11 PP_5V0 Power —
power pins to GND when unused.
I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO
Digital core I/O
D2 I2C_SCL1 Digital I/O Digital input (depending on configuration) through a 10-kΩ resistance when used or
and control pins
unused.
D3 Ground and no
No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
D4 connect pins

DEBUG_CTL2
Digital core I/O General purpose digital I/O 17. At power-up, pin state is sensed to
D5 (GPIO17, I2C ADDR Digital I/O Hi-Z
and control pins determine bit 5 of the I2C address.
B5)
Digital core I/O Active high hardware reset input. Will re-load settings from external flash
D6 HRESET Digital I/O Hi-Z
and control pins memory. Ground pin when HRESET functionality is not used.
General purpose digital I/O 7. Float pin if it is configured as a push-pull
Digital core I/O
D7 GPIO7 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.
Ground and no
D8 GND Ground — Ground. Connect all balls to ground plane.
connect pins
Ground and no
D9 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Low-current Output of the USB-PD BMC transceiver output level LDO. Bypass with
E1 LDO_BMC Power —
power pins capacitance CLDO_BMC to GND.
General purpose digital I/O 5. Can be configured as Hot Plug Detect (HPD)
GPIO5 Digital core I/O RX when DisplayPort mode supported. Must be tied high or low through
E10 Digital I/O Hi-Z
(HPD RX) and control pins a 1-kΩ pullup or pulldown resistor when used as a configuration input.
Ground pin with a 1-MΩ resistor when unused in the application.
General purpose digital I/O 11. Forces RESETZ to assert. By default, this
MRESET Digital core I/O pin asserts RESETZ when pulled high. The pin can be programmed to
E11 Digital I/O Hi-Z
(GPIO11) and control pins assert RESETZ when pulled low. Ground pin with a 1MΩ resistor when
unused in the application.
UART serial transmit data. Connect pin to another TPS65982 UART_TX to
Digital Port multiplexer
E2 UART_TX UART_RX share firmware. Connect UART_RX to UART_TX when not connected to
output pins
another TPS65982.
Ground and no
E3 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
DEBUG_CTL1
Digital core I/O General purpose digital I/O 16. At power-up, pin state is sensed to
E4 (GPIO16, I2C ADDR Digital I/O Hi-Z
and control pins determine bit 4 of the I2C address.
B4)
E5
E6 Ground and no
GND Ground — Ground. Connect all balls to ground plane.
E7 connect pins

E8
Ground and no
E9 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Digital core I/O Sets the I2C address for both I2C ports as well as determine the master and
F1 I2C_ADDR Analog I/O Analog input
and control pins slave devices for memory code sharing.

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Table 6-1. Pin Functions (continued)

PIN
TYPE CATEGORY POR STATE DESCRIPTION
NO. NAME
General purpose digital I/O 10. Sampled by ADC at boot. Tie pin to
BUSPOWERZ Digital core I/O LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT
F10 Analog Input Input (Hi-Z)
(GPIO10) and control pins power paths during dead-battery or no-battery boot conditions. Refer to
the BUSPOWERZ table for more details.
RESETZ Digital core I/O Push-pull General purpose digital I/O 9. Active-low reset output when VOUT_3V3 is
F11 Digital I/O
(GPIO9) and control pins output (Low) low (driven low on start-up). Float pin when unused.
UART serial receive data. Connect pin to another TPS65982 UART_TX to
Port multiplexer
F2 UART_RX Digital input Digital input share firmware. Connect UART_RX to UART_TX when not connected to
pins
another TPS65982 and ground pin through a 100-kΩ resistance.
Ground and no
F3 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Port multiplexer Resistive pull
F4 SWD_DATA Digital I/O SWD serial data. Float pin when unused.
pins high
F5
F6 Ground and no
GND Ground — Ground. Connect all balls to ground plane.
F7 connect pins

F8
Ground and no
F9 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch.
Low-current
G1 LDO_3V3 Power — Main internal supply rail. Used to power external flash memory. Bypass with
power pins
capacitance CLDO_3V3 to GND.
General purpose digital I/O 6. Float pin if it is configured as a push-pull
Digital core I/O
G10 GPIO6 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.
General purpose digital I/O 3. Float pin if it is configured as a push-pull
Digital core I/O
G11 GPIO3 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.
Digital core I/O External resistance setting for oscillator accuracy. Connect R_OSC to GND
G2 R_OSC Analog I/O Hi-Z
and control pins through resistance RR_OSC.
Ground and no
G3 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Port multiplexer Resistive pull
G4 SWD_CLK Digital input SWD serial clock. Float pin when unused.
pins high
G5
G6 Ground and no
GND Ground — Ground. Connect all balls to ground plane.
G7 connect pins

G8
Ground and no
G9 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Low-current Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to
H1 VIN_3V3 Power —
power pins GND.
High-current 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND
H10 PP_CABLE Power —
power pins when not tied to PP_5V0. Tie pin to PP_5V0 when unused.
High-current 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass
H11 VBUS Power —
power pins with capacitance CVBUS to GND.
Low-current Output of supply switched from VIN_3V3. Bypass with capacitance
H2 VOUT_3V3 Power —
power pins COUT_3V3 to GND. Float pin when unused.
Ground and no
H3 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
H4 Ground and no
GND Ground — Ground. Connect all balls to ground plane.
H5 connect pins

General purpose digital I/O 8. Float pin if it is configured as a push-pull

Digital core I/O
H6 GPIO8 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
and control pins
the application.
External HV-FET
Analog
H7 SS control and sense Driven low Soft Start. Tie pin to capacitance CSS to ground.
output
pins and soft start

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Table 6-1. Pin Functions (continued)

PIN
TYPE CATEGORY POR STATE DESCRIPTION
NO. NAME
Ground and no
H8 GND Ground — Ground. Connect all balls to ground plane.
connect pins
Ground and no
H9 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
Port multiplexer System-side DisplayPort connection to port multiplexer. Ground pin with
J1 AUX_P Analog I/O Hi-Z
pins between 1-kΩ and 5-MΩ resistance when unused.
J10 High-current 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass
VBUS Power —
J11 power pins with capacitance CVBUS to GND.

Port multiplexer System-side DisplayPort connection to port multiplexer. Ground pin with
J2 AUX_N Analog I/O Hi-Z
pins between 1-kΩ and 5-MΩ resistance when unused.
J3
J4
J5
Ground and no
J6 No Ball Blank — Unpopulated ball for A1 marker and unpopulated inner ring.
connect pins
J7
J8
J9
Low-current Output of the 1.8-V LDO for core analog circuits. Bypass with capacitance
K1 LDO_1V8A Power —
power pins CLDO_1V8A to GND.
Tie pin to C_CC2 when configured to receive power in dead-battery or
K10 RPD_G2 Analog I/O Type-C port pins Hi-Z
no-power condition. Tie pin to GND otherwise.
High-current 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass
K11 VBUS Power —
power pins with capacitance CVBUS to GND.
General purpose digital I/O 14. Float pin if it is configured as a push-pull
DEBUG2 Digital core I/O
K2 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
(GPIO14) and control pins
the application.
General purpose digital I/O 12. Float pin if it is configured as a push-pull
DEBUG4 Digital core I/O
K3 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
(GPIO12) and control pins
the application.
System side low speed RX to system from port. This pin is configurable to
Digital Port multiplexer
K4 LSX_P2R Hi-Z be an output from the digital core or the crossbar multiplexer from the port.
output pins
Float pin when unused.
Port multiplexer System side USB2.0 high-speed connection to Port Multiplexer. Ground pin
K5 USB_RP_N Analog I/O Hi-Z
pins with between 1-kΩ and 5-MΩ resistance when unused.
K6 C_USB_TP Analog I/O Type-C port pins Hi-Z Port-side top USB D+ connection to port multiplexer.
K7 C_USB_BP Analog I/O Type-C port pins Hi-Z Port-side bottom USB D+ connection to port multiplexer.
K8 C_SBU1 Analog I/O Type-C port pins Hi-Z Port-side Sideband Use connection of port multiplexer.
Tie pin to C_CC1 when configured to receive power in dead-battery or
K9 RPD_G1 Analog I/O Type-C port pins Hi-Z
no-power condition. Tie pin to GND otherwise.
Ground and no
L1 GND Ground — Ground. Connect all balls to ground plane.
connect pins
Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2
L10 C_CC2 Analog I/O Type-C port pins Hi-Z
to GND.
Ground and no
L11 NC Blank — Populated ball that must remain unconnected.
connect pins
General purpose digital I/O 15. Float pin if it is configured as a push-pull
DEBUG1 Digital core I/O
L2 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
(GPIO15) and control pins
the application.
General purpose digital I/O 13. Float pin if it is configured as a push-pull
DEBUG3 Digital core I/O
L3 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in
(GPIO13) and control pins
the application.
System side low speed TX from system to port. This pin is configurable
Port multiplexer
L4 LSX_R2P Digital input Digital input to be an input to the digital core or the crossbar multiplexer to the port.
pins
Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
Port multiplexer System side USB2.0 high-speed connection to Port Multiplexer. Ground pin
L5 USB_RP_P Analog I/O Hi-Z
pins with between 1-kΩ and 5-MΩ resistance when unused.
L6 C_USB_TN Analog I/O Type-C port pins Hi-Z Port-side top USB D– connection to port multiplexer.

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Table 6-1. Pin Functions (continued)

PIN
TYPE CATEGORY POR STATE DESCRIPTION
NO. NAME
L7 C_USB_BN Analog I/O Type-C port pins Hi-Z Port-side bottom USB D– connection to port multiplexer.
L8 C_SBU2 Analog I/O Type-C port pins Hi-Z Port-side Sideband Use connection of port multiplexer.
Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1
L9 C_CC1 Analog I/O Type-C port pins Hi-Z
to GND.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
PP_CABLE, PP_5V0 –0.3 6
VIN_3V3 –0.3 3.6
VI Input voltage(2) V
SENSEP(3), SENSEN(3) –0.3 24
VDDIO, UART_RX –0.3 LDO_3V3 + 0.3
LDO_1V8A, LDO_1V8D, LDO_BMC, SS –0.3 2
LDO_3V3 –0.3 3.45
VOUT_3V3, RESETZ, I2C _IRQ1Z, I2C_IRQ2Z, SPI_PICO, SPI_CLK, SPI_CSZ,
–0.3 LDO_3V3 + 0.3
VIO Output voltage (2) LSX_P2R, SWD_CLK, UART_TX V
HV_GATE1, HV_GATE2 –0.3 30
HV_GATE1 (relative to SENSEP), –0.3 6
HV_GATE2 (relative to VBUS)
PP_HV, VBUS(3) –0.3 24
I2C_SDA1, I2C_SCL1, SWD_DATA, SPI_POCI, I2C_SDA2, I2C_SCL2, LSX_R2P,
USB_RP_P, USB_RP_N, AUX_N, AUX_P, DEBUG1, DEBUG2, DEBUG3, DEBUG4, –0.3 LDO_3V3 + 0.3
DEBUG_CTL1, DEBUG_CTL2, GPIOn, MRESET, BUSPOWERZ, GPIO0-8
R_OSC, I2C_ADDR –0.3 2
VIO I/O voltage (2) LDO_1V8D + V
HRESET –0.3
0.3
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (switches open) –2 6
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (switches
–0.3 6
closed)
C_CC1, C_CC2, RPD_G1, RPD_G2 –0.3 6
TJ Operating junction temperature –10 125 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(3) The 24-V maximum is based on keeping HV_GATE1/2 at or below 30 V. Fast voltage transitions (< 100 ns) may occur up to 30 V.

7.2 ESD Ratings

VALUE UNIT

Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500

V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN_3V3 2.85 3.45
PP_5V0 4.75 5.5
Input voltage
VI PP_CABLE 2.95 5.5 V
range(1)
PP_HV 4.5 22
VDDIO 1.7 3.45
VBUS 4 22
I/O voltage
VIO C_USB_PT, C_USB_NT, C_USB_PB, C_USB_NB, C_SBU1, C_SBU2 –2 5.5 V
range(1)
C_CC1, C_CC2 0 5.5
TA Ambient operating temperature range –10 85 °C
TB Operating board temperature range –10 100 °C
TJ Operating junction temperature range –10 125 °C

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

7.4 Thermal Information

TPS65982
THERMAL METRIC(1) ZQZ (BGA) ZBH (NFBGA) UNIT
96 BALLS 96 BALLS
RθJA Junction-to-ambient thermal resistance 42.4 42.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.4 12.4 °C/W
RθJB Junction-to-board thermal resistance 13 13 °C/W
ψJT Junction-to-top characterization parameter 0.3 0.3 °C/W
ψJB Junction-to-board characterization parameter 13 13 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Power Supply Requirements and Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL
VIN_3V3 Input 3.3-V supply 2.85 3.3 3.45 V
Input voltage to power C_CC pins. This input
PP_CABLE is also available to power core circuitry and the 2.95 5 5.5 V
VOUT_3V3 output
Bi-direction DC bus voltage. Output from the
VBUS 4 5 22 V
TPS65982 or input to the TPS65982
5V supply input to power VBUS. This supply does
PP_5V0 4.75 5 5.5 V
not power the TPS65982
VDDIO(1) Optional supply for I/O cells 1.7 3.45 V
INTERNAL
DC 3.3V generated internally by either a switch
VLDO_3V3 from VIN_3V3, an LDO from PP_CABLE, or an 2.7 3.3 3.45 V
LDO from VBUS
VDO_LDO3V3 Drop Out Voltage of LDO_3V3 from PP_CABLE ILOAD = 50 mA 250 mV
Drop Out Voltage of LDO_3V3 from VBUS 250 500 750 mV
VLDO_1V8D DC 1.8V generated for internal digital circuitry 1.7 1.8 1.9 V
VLDO_1V8A DC 1.8V generated for internal analog circuitry 1.7 1.8 1.9 V
DC voltage generated on LDO_BMC. Setting for
VLDO_BMC 1.05 1.125 1.2 V
USB-PD
DC current supplied by the 3.3V LDOs. This
ILDO_3V3 includes internal core power and external load on 70 mA
LDO_3V3
ILDO_3V3EX External DC current supplied by LDO_3V3 30 mA
IOUT_3V3 External DC current supplied by VOUT_3V3 100 mA
DC current supplied by LDO_1V8D. This is
ILDO_1V8D intended for internal loads only but small external 50 mA
loads may be added
ILDO_1V8DEX External DC current supplied by LDO_1V8D 5 mA
DC current supplied by LDO_1V8A. This is
ILDO_1V8A intended for internal loads only but small external 20 mA
loads may be added
ILDO_1V8AEX External DC current supplied by LDO_1V8A 5 mA
DC current supplied by LDO_BMC. This is
ILDO_BMC 5 mA
intended for internal loads only
ILDO_BMCEX External DC current supplied by LDO_BMC 0 mA
Forward voltage drop across VIN_3V3 to
VFWD_DROP ILOAD = 50 mA 25 60 90 mV
LDO_3V3 switch
Input switch resistance from VIN_3V3 to
RIN_3V3 VVIN_3V3 – VLDO_3V3 > 50 mV 0.5 1.1 1.75 Ω
LDO_3V3
Output switch resistance from VIN_3V3 to
ROUT_3V3 0.35 0.7 Ω
VOUT_3V3
10-90% rise time on VOUT_3V3 from switch
TR_OUT3V3 CVOUT_3V3 = 1 μF 35 120 µs
enable

(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before
LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.

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7.6 Power Supervisor Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Undervoltage threshold for LDO_3V3. Locks out 1.8-V
UV_LDO3V3 LDO_3V3 rising 2.2 2.325 2.45 V
LDOs
UVH_LDO3V3 Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling 20 80 150 mV
UV_VBUS_LDO Undervoltage threshold for VBUS to enable LDO VBUS rising 3.35 3.75 3.95 V
UVH_VBUS_LDO Undervoltage hysteresis for VBUS to enable LDO VBUS falling 20 80 150 mV
UV_PCBL Undervoltage threshold for PP_CABLE PP_CABLE rising 2.5 2.625 2.75 V
UVH_PCBL Undervoltage hysteresis for PP_PCABLE PP_CABLE falling 20 50 80 mV
UV_5V0 Undervoltage threshold for PP_5V0 PP_5V0 rising 3.5 3.725 3.95 V
UVH_5V0 Undervoltage hysteresis for PP_P5V0 PP_5V0 falling 20 80 150 mV
Overvoltage threshold for VBUS. This value is a 6-bit
OV_VBUS VBUS rising 5 24 V
programmable threshold
Overvoltage threshold step for VBUS. This value is the LSB
OVLSB_VBUS VBUS rising 328 mV
of the programmable threshold
OVH_VBUS Overvoltage hysteresis for VBUS VBUS falling, % of OV_VBUS 0.9% 1.3% 1.7%
Undervoltage threshold for VBUS. This value is a 6-bit
UV_VBUS VBUS falling 2.5 18.21 V
programmable threshold
Undervoltage threshold step for VBUS. This value is the
UVLSB_VBUS VBUS falling 249 mV
LSB of the programmable threshold
UVH_VBUS Undervoltage hysteresis for VBUS VBUS rising, % of UV_VBUS 0.9% 1.3% 1.7%
Setting 0 2.019 2.125 2.231
Setting 1 2.138 2.25 2.363
Setting 2 2.256 2.375 2.494

Configurable undervoltage threshold for VOUT_3V3 rising. Setting 3 2.375 2.5 2.625
UVR_OUT3V3 V
Deasserts RESETZ Setting 4 2.494 2.625 2.756
Setting 5 2.613 2.75 2.888
Setting 6 2.731 2.875 3.019
Setting 7 2.85 3 3.15
UVRH_OUT3V3 Undervoltage hysteresis for VOUT_3V3 falling OUT_3V3 falling 30 50 mV
Delay from falling VOUT_3V3 or MRESET assertion to
TUVRASSERT 75 μs
RESETZ asserting low
Configurable delay from VOUT_3V3 to RESETZ
TUVRDELAY 0 161.3 ms
deassertion

7.7 Power Consumption Characteristics(4)

Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN_3V3 = VDDIO = 3.45 V, VBUS = 0,
Sleep(1) 58 µA
PPCABLE = 0; 100-kHz oscillator running
VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE
Idle (2) = 0; 100-kHz oscillator running, 1.66 mA
IVIN_3V3
48-MHz oscillator running
VIN_3V3 = VDDIO = 3.45 V, VBUS = 0,
Active(3) PPCABLE = 0; 100-kHz Oscillator running, 5.64 mA
48-MHz oscillator running

(1) Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active.
(2) Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and a
selectable clock to the digital core of 3 MHz or 4 MHz.
(3) Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all
core functionality active, and the digital core is clocked at 12 MHz.
(4) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code
also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity).

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7.8 Cable Detection Characteristics

Recommended operating conditions; TA = -10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Source Current through each C_CC pin when in a disconnected
IH_CC_USB state and Configured as a DFP advertising Default USB current to 73.6 80 86.4 μA
a peripheral device
Source Current through each C_CC pin when in a disconnected
IH_CC_1P5 169 180 191 μA
state when Configured as a DFP advertising 1.5 A to a UFP
Source Current through each C_CC pin when in a disconnected
IH_CC_3P0 VIN_3V3 ≥ 3.135 V 303 330 356 μA
state and Configured as a DFP advertising 3.0 A to a UFP.
Voltage Threshold for detecting a DFP attach when configured as
VD_CCH_USB a UFP and the DFP is advertising Default USB current source 0.15 0.2 0.25 V
capability
Voltage Threshold for detecting a DFP advertising 1.5 A source
VD_CCH_1P5 0.61 0.66 0.7 V
capability when configured as a UFP
Voltage Threshold for detecting a DFP advertising 3 A source
VD_CCH_3P0 1.169 1.23 1.29 V
capability when configured as a UFP
Voltage Threshold for detecting a UFP attach when configured as
VH_CCD_USB IH_CC = IH_CC_USB 1.473 1.55 1.627 V
a DFP and advertising Default USB current source capability
Voltage Threshold for detecting a UFP attach when configured as
VH_CCD_1P5 IH_CC = IH_CC_1P5 1.473 1.55 1.627 V
a DFP and advertising 1.5 A source capability
Voltage Threshold for detecting a UFP attach when configured as IH_CC = IH_CC_3P0
VH_CCD_3P0 2.423 2.55 2.67 V
a DFP and advertising 3 A source capability VIN_3V3 ≥ 3.135 V
Voltage Threshold for detecting an active cable attach when
VH_CCA_USB configured as a DFP and advertising Default USB current 0.15 0.2 0.25 V
capability
Voltage Threshold for detecting active cables attach when
VH_CCA_1P5 0.35 0.4 0.45 V
configured as a DFP and advertising 1.5 A capability
Voltage Threshold for detecting active cables attach when
VH_CCA_3P0 0.76 0.8 0.84 V
configured as a DFP and advertising 3 A capability
Pulldown resistance through each C_CC pin when in a
RD_CC V = 1 V, 1.5 V 4.85 5.1 5.35 kΩ
disconnect state and configured as a UFP. LDO_3V3 powered
Pulldown resistance through each C_CC pin when in a
RD_CC_OPEN V = 0 V to LDO_3V3 500 kΩ
disconnect state and configured as a UFP. LDO_3V3 powered
Pulldown resistance through each C_CC pin when in a
V = 1.5 V, 2.0 V
RD_DB disconnect state and configured as a UFP when configured for 4.08 5.1 6.12 kΩ
RPD_Gn tied to C_CCn
dead battery (RPD_Gn tied to C_CCn). LDO_3V3 unpowered
Pulldown resistance through each C_CC pin when in a
V = 1.5 V, 2.0 V
RD_DB_OPEN disconnect state and configured as a UFP when not configured 500 kΩ
RPD_Gn tied to GND
for dead battery (RPD_Gn tied to GND). LDO_3V3 unpowered
Threshold Voltage of the pulldown FET in series with RD during
VTH_DB I_CC = 80 μA 0.5 0.9 1.2 V
dead battery
R_RPD Resistance between RPD_Gn and the gate of the pulldown FET 25 50 85 MΩ

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7.9 USB-PD Baseband Signal Requirements and Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
PD_BITRATE PD data bit rate 270 300 330 Kbps
UI(1) Unit interval (1/PD_BITRATE) 3.03 3.33 3.7 μs
Capacitance for a cable plug (each plug on a cable may have up
CCBLPLUG(2) 25 pF
to this value)
ZCABLE Cable characteristic impedance 32 65 Ω
Receiver capacitance. Capacitance looking into C_CCn pin when
CRECEIVER(3) 70 120 pF
in receiver mode
TRANSMITTER
TX output impedance. Source output impedance at the Nyquist
ZDRIVER frequency of USB2.0 low speed (750kHz) while the source is 33 75 Ω
driving the C_CCn line
Rise Time. 10% to 90% amplitude points, minimum is under an
TRISE 300 ns
unloaded condition. Maximum set by TX mask
Fall Time. 90% to 10% amplitude points, minimum is under an
TFALL 300 ns
unloaded condition. Maximum set by TX mask
RECEIVER
VRXTR Rx Receive Rising Input threshold 605 630 655 mV
VRXTF Rx Receive Falling Input threshold 450 470 490 mV
Number of transitions for signal detection (number to count to
NCOUNT(4) 3
detect non-idle bus)
TTRANWIN(4) Time window for detecting non-idle bus 12 20 μs
Does not include pullup or
pulldown resistance from
ZBMCRX Receiver input impedance 10 MΩ
cable detect. Transmitter is
Hi-Z.
Rx bandwidth limiting filter. Time constant of a single pole filter to
TRXFILTER(5) 100 ns
limit broadband noise ingression

(1) UI denotes the time to transmit an un-encoded data bit not the shortest high or low times on the wire after encoding with BMC. A single
data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the
transition at the start of the cell.
(2) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends to add capacitance
to bring the total pin capacitance to 300 pF for improved TX behavior.
(4) BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of NCOUNT
transitions occur at the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions,
the bus is declared idle.
(5) Broadband noise ingression is because of coupling in the cable interconnect.

7.10 USB-PD TX Driver Voltage Adjustment Parameter

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted(1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VTXP0 TX transmit peak voltage 1.615 1.7 1.785 V
VTXP1 TX transmit peak voltage 1.52 1.6 1.68 V
VTXP2 TX transmit peak voltage 1.425 1.5 1.575 V
VTXP3 TX transmit peak voltage 1.33 1.4 1.47 V
VTXP4 TX transmit peak voltage 1.235 1.3 1.365 V
VTXP5 TX transmit peak voltage 1.188 1.25 1.312 V
VTXP6 TX transmit peak voltage 1.14 1.2 1.26 V
VTXP7 TX transmit peak voltage 1.116 1.175 1.233 V
VTXP8 TX transmit peak voltage 1.092 1.15 1.208 V
VTXP9 TX transmit peak voltage 1.068 1.125 1.181 V

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7.10 USB-PD TX Driver Voltage Adjustment Parameter (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted(1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VTXP10 TX transmit peak voltage 1.045 1.1 1.155 V
VTXP11 TX transmit peak voltage 1.021 1.075 1.128 V
VTXP12 TX transmit peak voltage 0.998 1.05 1.102 V
VTXP13 TX transmit peak voltage 0.974 1.025 1.076 V
VTXP14 TX transmit peak voltage 0.95 1 1.05 V
VTXP15 TX transmit peak voltage 0.903 0.95 0.997 V

(1) VTXP voltage settings are determined by application code and the setting used must meet the needs of the application and adhere to
the USB-PD Specifications.

7.11 Port Power Switch Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS(3) MIN TYP MAX UNIT
RPPCC PP_CABLE to C_CCn power switch resistance 312 mΩ
RPP5V PP_5V0 to VBUS power switch resistance 50 60 mΩ
RPPHV PP_HV to VBUS power switch resistance 95 135 mΩ
Active quiescent current from PP_HV pin, mA
IHVACT 1
EN_HV = 1
Shutdown quiescent current from PP_HV pin, μA
IHVSD 100
EN_HV = 0
Active quiescent current from SENSEP pin, mA
Configured as source 1
EN_HV = 1
IHVEXTACT
Active quiescent current from VBUS pin, mA
Configured as sink 3.5
EN_HV = 1
Shutdown quiescent current from SENSEP pin, μA
IHVEXTSD 40
EN_HV = 0
IPP5VACT Active quiescent current from PP_5V0 1 mA
IPP5VSD Shutdown quiescent current from PP_5V0 100 μA
PP_HV current limit, setting 0 1.007 1.118 1.330 A
PP_HV current limit, setting 1 1.258 1.398 1.638 A
PP_HV current limit, setting 2 1.51 1.678 1.945 A
PP_HV current limit, setting 3 1.761 1.957 2.153 A
PP_HV current limit, setting 4 2.013 2.237 2.46 A
PP_HV current limit, setting 5 2.265 2.516 2.768 A
PP_HV current limit, setting 6 2.516 2.796 3.076 A
PP_HV current limit, setting 7 2.768 3.076 3.383 A
ILIMHV(5)
PP_HV current limit, setting 8 3.02 3.355 3.691 A
PP_HV current limit, setting 9 3.271 3.635 3.998 A
PP_HV current limit, setting 10 3.523 3.914 4.306 A
PP_HV current limit, setting 11 3.775 4.194 4.613 A
PP_HV current limit, setting 12 4.026 4.474 4.921 A
PP_HV current limit, setting 13 4.278 4.753 5.228 A
PP_HV current limit, setting 14 4.529 5.033 5.536 A
PP_HV current limit, setting 15 5.033 5.592 6.151 A

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7.11 Port Power Switch Characteristics (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS(3) MIN TYP MAX UNIT
PP_EXT current limit, setting 0 0.986 1.12 1.254 A
PP_EXT current limit, setting 1 1.231 1.399 1.567 A
PP_EXT current limit, setting 2 1.477 1.678 1.879 A
PP_EXT current limit, setting 3 1.761 1.957 2.153 A
PP_EXT current limit, setting 4 2.012 2.236 2.46 A
PP_EXT current limit, setting 5 2.263 2.515 2.767 A
PP_EXT current limit, setting 6 2.514 2.794 3.074 A
PP_EXT current limit, setting 7 2.765 3.073 3.381 A
ILIMHVEXT(4) (5)
PP_EXT current limit, setting 8 3.016 3.352 3.688 A
PP_EXT current limit, setting 9 3.267 3.631 3.995 A
PP_EXT current limit, setting 10 3.519 3.91 4.301 A
PP_EXT current limit, setting 11 3.77 4.189 4.608 A
PP_EXT current limit, setting 12 4.021 4.468 4.915 A
PP_EXT current limit, setting 13 4.272 4.747 5.222 A
PP_EXT current limit, setting 14 4.523 5.026 5.529 A
PP_EXT current limit, setting 15 5.025 5.584 6.143 A
PP_5V0 current limit, setting 0 1.006 1.118 1.330 A
PP_5V0 current limit, setting 1 1.132 1.258 1.484 A
PP_5V0 current limit, setting 2 1.258 1.398 1.638 A
PP_5V0 current limit, setting 3 1.384 1.538 1.691 A
PP_5V0 current limit, setting 4 1.51 1.677 1.845 A
PP_5V0 current limit, setting 5 1.636 1.817 1.999 A
PP_5V0 current limit, setting 6 1.761 1.957 2.153 A
PP_5V0 current limit, setting 7 1.887 2.097 2.307 A
ILIMPP5V(5)
PP_5V0 current limit, setting 8 2.013 2.237 2.46 A
PP_5V0 current limit, setting 9 2.139 2.376 2.614 A
PP_5V0 current limit, setting 10 2.265 2.516 2.768 A
PP_5V0 current limit, setting 11 2.39 2.656 2.922 A
PP_5V0 current limit, setting 12 2.516 2.796 3.075 A
PP_5V0 current limit, setting 13 2.642 2.936 3.229 A
PP_5V0 current limit, setting 14 2.768 3.075 3.383 A
PP_5V0 current limit, setting 15 3.019 3.355 3.69 A
PP_CABLE current limit (highest setting) 0.6 0.75 0.9 A
ILIMPPCC
PP_CABLE current limit (lowest setting) 0.35 0.45 0.55 A
I = 100 mA Reverse current A/V
3.25 5 6.75
blocking disabled

IHV_ACC(1) PP_HV current sense accuracy I = 200 mA 4 5 6 A/V

I = 500 mA 4.4 5 5.6 A/V
I≥1A 4.5 5 5.5 A/V
I = 100 mA , RSENSE = 10 mΩ A/V
3.5 5 6.5
Reverse current blocking disabled
PP_EXT current sense accuracy (excluding I = 200 mA, RSENSE = 10 mΩ 4 5 6 A/V
IHVEXT_ACC
RSENSE accuracy)
I = 500 mA, RSENSE = 10 mΩ 4.4 5 5.6 A/V
I ≥ 1 A, RSENSE = 10 mΩ 4.5 5 5.5 A/V
I = 100 mA Reverse current A/V
1.95 3 4.05
blocking disabled

IPP5V_ACC(1) PP_5V0 current sense accuracy I = 200 mA 2.4 3 3.6 A/V

I = 500 mA 2.64 3 3.36 A/V
I≥1A 2.7 3 3.3 A/V

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7.11 Port Power Switch Characteristics (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS(3) MIN TYP MAX UNIT
I = 100 mA 1 A/V
IPPCBL_ACC PP_CABLE current sense accuracy I = 200 mA 1 A/V
I = 500 mA 1 A/V
External Gate Drive Current on HV_GATE1 and μA
IGATEEXT(2) 4 5 6
HV_GATE2
VGSEXT VGS voltage driving external FETs 4.5 7.5 V
Configured as a source or as a sink ms
PP_HV path turn on time from enable to VBUS with soft start disabled. PP_HV =
TON_HV 8
= 95% of PP_HV voltage 20 V, CVBUS = 10 μF, ILOAD =
100 mA
Configured as a source or as a sink ms
PP_5V0 path turn on time from enable to VBUS with soft start disabled. PP_5V0 =
TON_5V 2.5
= 95% of PP_5V0 voltage 5 V, CVBUS = 10 μF, ILOAD = 100
mA
PP_CABLE path turn on time from enable to PP_CABLE = 5 V, C_CCn = 500 ms
TON_CC 2
C_CCn = 95% of the PP_CABLE voltage nF, ILOAD = 100 mA
ISS Soft start charging current 5.5 7 8.5 μA
RSS_DIS Soft start discharge resistance 0.6 1 1.4 kΩ
VTHSS Soft start complete threshold 1.35 1.5 1.65 V
TSSDONE Soft start complete time CSS = 220 nF 31.9 46.2 60.5 ms
Reverse current blocking voltage threshold for mV
VREVPHV 2 6 10
PP_HV switch
Reverse Current Blocking voltage Threshold for mV
VREVPEXT 2 6 10
PP_EXT external switches
Reverse current blocking voltage threshold for mV
VREV5V0 2 6 10
PP_5V0 switches
Voltage threshold above VIN at which the mV
VHVDISPD pulldown RHVDISPD on VBUS will disable 45 200 250
during a transition from PHV to 5V0
Voltage that is a safe 0 V per USB-PD V
VSAFE0V 0 0.8
Specifications
TSAFE0V Voltage transition time to VSAFE0V 650 ms
Voltage on PP_HV or PP_HVEXT above which V
VSO_HV the PP_HV or PP_EXT to PP_5V0 transition on 9.9
VBUS will meet transition requirements
Maximum slew rate for positive voltage V/μs
SRPOS 0.03
transitions
Maximum slew rate for negative voltage V/μs
SRNEG –0.03
transitions
EN to stable time for both positive and negative ms
TSTABLE 275
voltage transitions
Supply output tolerance beyond VSRCNEW V
VSRCVALID –0.5 0.5
during time TSTABLE
VSRCNEW Supply output tolerance –5 5 %

(1) The current sense in the ADC will not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the reverse
blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
(2) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short
circuit events.
(3) Maximum capacitance on VBUS when configured as a source must not exceed 12 µF.
(4) Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. Values will scale with a different RSENSE
resistance and application code setting.
(5) Settings selected automatically by application code for the current limit needed in the application.

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7.12 Port Data Multiplexer Switching Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWD MULTIPLEXER PATH(1)

On resistance of SWD_DATA/CLK to Vi = 3.3 V, IO = 20 mA 35 55

SWD_RON_U Ω
C_USB_TP/TN/BP/BN Vi = 1 V, IO = 20 mA 30 46
On resistance difference between P and N paths of
SWD_ROND_U Vi = 1 V to 3.3 V, IO = 20 mA –2.5 2.5 Ω
SWD_DATA/CLK to C_USB_ TP/TN/BP/BN
Vi = 3.3 V, IO = 20 mA 26 42
SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2 Ω
Vi = = 1 V, IO = 20 mA 24 37
On resistance difference between P and N paths of
SWD_ROND_S Vi = 1V to 3.3 V, IO = 20 mA –1.5 1.5 Ω
SWD_DATA/CLK to C_SBU1/2
Time from enable bit with charge
150
pump off
SWD_TON Switch on time from enable of SWD path μs
Time from enable bit at charge
10
pump steady state
Time from disable bit at charge
SWD_TOFF Switch off time from disable of SWD path 500 ns
pump steady state
SWD_BW 3 dB bandwidth of SWD path CL = 10 pF 200 MHz
DEBUG1/2 MULTIPLEXER PATH(1)
Vi = 3.3 V, IO = 20 mA 14 26
DB1_RON_U On resistance DEBUG1/2 to C_USB_TP/TN/BP/BN Ω
Vi = 1 V, IO = 20 mA 10 17
On resistance difference between P and N paths of
DB1_ROND_U Vi = 1 V to 3.3 V, IO = 20 mA –2.5 2.5 Ω
DEBUG1/2 to C_USB_TP/TN/BP/BN
Vi = 3.3 V, IO = 20 mA 9.5 17
DB1_RON_S On resistance of DEBUG1/2 to C_SBU1/2 Ω
Vi = 1 V, IO = 20 mA 6.5 12
On resistance difference between P and N paths of Debug
DB1_ROND_S Vi = 1 V to 3.3 V, IO = 20 mA –0.5 0.5 Ω
path DEBUG1/2 to C_SBU1/2
Time from enable bit with charge
150
pump off
DB1_TON Switch on time from enable of DEBUG path μs
Time from enable bit at charge
10
pump steady state
Time from disable bit at charge
DB1_TOFF Switch off time from disable of DEBUG path 500 ns
pump steady state
DB1_BW 3dB bandwidth of DEBUG path CL = 10 pF 200 MHz
DEBUG3/4 MULTIPLEXER PATH(1)
Vi = 3.3 V, IO = 20 mA 14 24
DB3_RON_U On resistance of DEBUG3/4 to C_USB_TP/TN/BP/BN Ω
Vi = 1 V, IO = 20 mA 9 17
On resistance difference between P and N paths of
DB3_ROND_U Vi = 1 V to 3.3V, IO = 20 mA –1.5 1.5 Ω
DEBUG3/4 to C_USB_ TP/TN/BP/BN
Vi = 3.3 V, IO = 20 mA 9.5 18
DB3_RON_S On resistance of DEBUG3/4 to C_SBU1/2 Ω
Vi = 1 V, IO = 20 mA 6.5 12
On resistance difference between P and N paths of
DB3_ROND_S Vi = 1 V to 3.3 V, IO = 20 mA –0.15 0.15 Ω
DEBUG3/4 to C_SBU1/2
Time from enable bit with charge
150
pump off
DB3_TON Switch on time from enable of DEBUG3/4 path μs
Time from enable bit at charge
10
pump steady state
Time from disable bit at charge
DB3_TOFF Switch off time from disable of DEBUG3/4 path 500 ns
pump steady state
DB3_BW 3dB bandwidth of DEBUG3/4 path CL = 10 pF 200 MHz

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7.12 Port Data Multiplexer Switching Characteristics (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LSX_R2P/P2R MULTIPLEXER PATH(1)
Vi = 3.3 V, IO = 20 mA 8.5 17
LSX_RON On resistance of LSX_P2R/R2P to C_SBU1/2 Ω
Vi = 1 V, IO = 20 mA 5.5 11
On resistance difference between P and N paths of LSX
LSX_ROND Vi = 1 V to 3.3 V, IO = 20 mA –0.3 0.3 Ω
path
Time from enable bit with charge
150
pump off
LSX_TON Switch on time from enable of LSX path μs
Time from enable bit at charge
10
pump steady state
Time from disable bit at charge
LSX_TOFF Switch off time from disable of LSX path 500 ns
pump steady state
LSX_BW 3dB bandwidth of LSX path CL = 10 pF 200 MHz
AUX MULTIPLEXER PATH(1)
Vi = 3.3 V, IO = 20 mA 3.5 7
AUX_RON On resistance of AUX_P/N to C_SBU1/2 Ω
Vi = 1 V, IO = 20 mA 2.5 5
On resistance difference between P and N paths of
AUX_ROND Vi = 1 V to 3.3 V, IO = 20 mA –0.25 0.25 Ω
AUX_P/N to C_SBU1/2
Time from enable bit with charge
150
pump off
AUX_TON Switch on time from enable of AUX_P/N to C_SBU1/2 μs
Time from enable bit at charge
15
pump steady state
Time from disable bit at charge
AUX_TOFF Switch off time from disable of AUX_P/N to C_SBU1/2 500 ns
pump steady state
AUX_BW 3dB bandwidth of AUX_P/N to C_SBU1/2 path CL = 10 pF 200 MHz
UART MULTIPLEXER PATH (2nd STAGE ONLY)(1) (2)
On resistance of UART buffers to C_USB_TP/TN/BP/BN or
UART_RON Vi = 3.3 V, IO = 20 mA 3.1 12 Ω
C_SBU1/2
Time from enable bit with charge
150
Switch on time from enable of UART buffer pump off
UART_TON µs
C_USB_TP/TN/BP/BN or C_SBU1/2 path Time from enable bit at charge
10
pump steady state
Time from disable bit at charge
UART_TOFF Switch off time from disable of UART buffer path 500 ns
pump steady state
UART_BW 3dB bandwidth of UART buffer path CL = 10 pF 200 MHz
USB_RP MULTIPLEXER PATH(1) (3)
Vi = 3 V, IO = 20 mA 4.5 10
USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN Ω
Vi = 400 mV, IO = 20 mA 3 7
On resistance difference between P and N paths of
USB_ROND Vi = 0.4 V to 3 V, IO = 20 mA –0.15 0.15 Ω
USB_RP to C_USB_TP/TN/BP/BN
Time from enable bit with charge
150
pump off
USB_TON Switch on time from enable of USB USB_RP path µs
Time from enable bit at charge
15
pump steady state
Time from disable bit at charge
USB_TOFF Switch off time from disable of USB_RP path 500 ns
pump steady state
USB_BW 3dB bandwidth of USB_RP path CL = 10 pF 850 MHz
RL = 50 Ω, VI = 800 mV, f = 240
USB_ISO Off Isolation of USB_RP path –19 dB
MHz
USB_XTLK Channel to Channel crosstalk of USB_RP path RL = 50 Ω, f = 240 MHz –26 dB
C_SBU1/2 OUTPUT
R_SBU_OPEN Resistance of the open C_SBU1/2 paths Vi = 0 V to LDO_3V3 1 MΩ
R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths Vi = 0 V to LDO_3V3 1 MΩ

(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum
difference between the two switches in a pair. ROND does not add to RON.

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(2) The UART switch path connects from the UART buffers to the port pins. See Section 7.19 for buffer specifications.
(3) See Section 7.16 for the USB_EP specifications.

7.13 Port Data Multiplexer Clamp Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCLMP_IND Clamp voltage triggering indicator to digital core 3.8 3.95 4.1 V
ICLMP_IND Clamp current at VCLMP_IND 10 250 μA
Time from clamp current crossing ICLMP_IND to
TCLMP_PRT(1) I ≥ ICLMP_IND rising 0 4 μs
interrupt signal assertion
V = LDO_3V3 250 nA
ICLMP USB_EP and USB_RP port clamp current
V = VCLMP_IND + 500 mV 3.5 15 mA

(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time
may be longer.

7.14 Port Data Multiplexer SBU Detection Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH_PORT Port switch detect input high voltage LDO_3V3 = 3.3 V 2 v
VIL_PORT Port switch detect input low voltage LDO_3V3 = 3.3 V 0.8 V

7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RPU05 500-Ω pullup and pulldown resistance LDO_3V3 = 3.3 V 350 500 650 Ω
RTPU5 5-kΩ pullup and pulldown resistance LDO_3V3 = 3.3 V 3.5 5 6.5 kΩ
RPU100 100-kΩ pullup and pulldown resistance LDO_3V3 = 3.3 V 70 100 130 kΩ

7.16 Port Data Multiplexer USB Endpoint Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSMITTER(1)
T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns
T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns
T_RRM_EP Rise/fall time matching Low-speed (1.5 Mbps) data rate only –20% 25%
V_XOVER_EP Output crossover voltage 1.3 2 V
RS_EP Source resistance of driver including 2nd stage port Ω
34
data multiplexer
DIFFERENTIAL RECEIVER (1)
VOS_DIFF_EP Input offset –100 100 mV
VIN_CM_EP Common mode range 0.8 2.5 V
RPU_EP D– Bias Resistance Receiving 1.425 1.575 kΩ
SINGLE ENDED RECEIVER(1)
VTH_SE_EP Single ended threshold Signal rising and falling 0.8 2 V
VHYS_SE_EP Single ended threshold hysteresis Signal falling 200 mV

(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for
VIN_3V3 ≥ 3.135 V

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7.17 Port Data Multiplexer BC1.2 Detection Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA CONTACT DETECT
IDP_SRC DCD source current LDO_3V3 = 3.3 V 7 10 13 μA
RDM_DWN DCD pulldown resistance 14.25 20 24.8 kΩ
VLGC_HI VC_USB_TP/BP ≥ V
Threshold for no connection VLGC_HILDO_3V3 = 3.3 V 2
LDO_3V3 = 3.3 V
VLGC_LO VC_USB_TP/BP ≤ VLGC_LO V
Threshold for connection 0.8
LDO_3V3 = 3.3 V
PRIMARY AND SECONDARY DETECT
VDX_SRC Source voltage 0.55 0.6 0.65 V
VDX_RSRC Total series resistance because of port data Ω
VDX_SRC = 0.65 V 65
multiplexer
VDX_ILIM VDX_SRC current limit 250 400 μA
IDX_SNK Sink current VC_USB_TN/BN ≥ 250 mV 25 75 125 μA

7.18 Analog-to-Digital Converter (ADC) Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RES_ADC ADC resolution 10 bits
F_ADC ADC clock frequency 1.477 1.5 1.523 MHz
T_ENA ADC enable time 42.14 43 43.86 μs
T_SAMPLEA ADC input sample time 10.5 10.67 10.9 μs
T_CONVERTA ADC conversion time 7.88 8 8.12 μs
T_INTA ADC interrupt time 1.31 1.33 1.35 μs
LSB Least significant bit 1.152 1.17 1.188 mV
DNL Differential non-linearity –0.65 0.65 LSB
INL Integral non-linearity –1.2 1.2 LSB
Gain error (divider) –1.5% 1.5%
GAIN_ERR
Gain error (no divider) –1 1
VOS_ERR Buffer offset error –10 10 mV
THERM_ACC Thermal sense accuracy –8 8 °C
THERM_GAIN Thermal slope 3.095 mV/°C
THERM_V0 Zero degree voltage 0.823 V

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7.19 Input/Output (I/O) Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SPI
SPI_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SPI_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SPI_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
SPI_ILKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 1 μA
IO = –8 mA, LDO_3V3=3.3 V 2.9 V
SPI_VOH SPI output high voltage
IO = –15 mA, LDO_3V3=3.3 V 2.5
IO = 10 mA 0.4 V
SPI_VOL SPI output low voltage
IO = 20 mA 0.8

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7.19 Input/Output (I/O) Characteristics (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWDIO
SWDIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SWDIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SWDIO_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
SWDIO_ILKG Leakage current Output is Hi-Z, VIN = 0 V to LDO_3V3 –1 1 μA
IO = –8 mA, LDO_3V3 = 3.3 V 2.9 V
SWDIO_VOH Output high voltage
IO = –15 mA, LDO_3V3 = 3.3 V 2.5
IO = 10 mA 0.4 V
SWDIO_VOL Output low voltage
IO = 20 mA 0.8
SWDIO_RPU Pullup resistance 2.8 4 5.2 kΩ
SWDIO_TOS SWDIO output skew to falling edge SWDCLK –5 5 ns
Input setup time required between SWDIO and rising 6 ns
SWDIO_TIS
edge of SWCLK
Input hold time required between SWDIO and rising edge 1 ns
SWDIO_TIH
of SWCLK
SWDCLK
SWDCL_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SWDCL_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SWDCL_THI SWDIOCLK HIGH period 0.05 500 μs
SWDCL_TLO SWDIOCLK LOW period 0.05 500 μs
SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V
SWDCL_RPU Pullup resistance 2.8 4 5.2 kΩ
GPIO (GPIO0-8, DEBUG1-4, DEBUG_CTL1/2, MRESET, RESETZ, BUSPOWERZ)
LDO_3V3 = 3.3 V 2 V
GPIO_VIH High-level input voltage
VDDDIO = 1.8 V 1.25
LDO_3V3 = 3.3 V 0.8
GPIO_VIL Low-level input voltage V
VDDIO = 1.8 V 0.63
LDO_3V3 = 3.3 V 0.2
GPIO_HYS Input hysteresis voltage V
VDDIO = 1.8 V 0.09
Pin is Hi-Z;
GPIO_ILKG Leakage current –1 1 μA
VIN = 0 V to VDD (VDDIO or LDO_3V3)
Pullup resistance (GPIO0-8, DEBUG1-4, MRESET,
Pullup enabled 50 100 150
GPIO_RPU RESETZ, BUSPOWERZ) kΩ
Pullup resistance (DEBUG_CTL1/2) Pullup enabled 2.5 5 7.5
Pulldown resistance (GPIO0-8, DEBUG1-4, MRESET,
GPIO_RPD Pulldown enabled 50 100 150 kΩ
RESETZ, BUSPOWERZ)(1)
GPIO_DG Digital input path deglitch 20 ns
IO = –2 mA, LDO_3V3 = 3.3 V 2.9
GPIO_VOH Output high voltage V
IO = –2 mA, VDDIO = 1.8 V 1.35
IO = 2 mA, LDO_3V3 = 3.3 V 0.4
GPIO_VOL Output low voltage V
IO = 2 mA, VDDIO = 1.8 V 0.45
HRESET
HRESET_VIH High-level input voltage 1.25 V
HRESET_VIL Low-level input voltage 0.63 V
HRESET_HYS Input hysteresis Voltage 0.09 V
HRESET_ILKG I/O leakage current VIN = 0 V to LDO_1V8D –1 1 μA
HRESET_THIGH HRESET minimum high time to assert a reset condition 2.0
ms
HRESET_TLOW HRESET minimum low time to deassert a reset condition 2.0
UART_RX/TX, LSX_P2R/R2P

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7.19 Input/Output (I/O) Characteristics (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDO_3V3 = 3.3 V 2
UARTRX_VIH High-level input voltage V
VDDDIO = 1.8 V 1.25
LDO_3V3 = 3.3 V 0.8
UARTRX_VIL Low-level input voltage V
VDDIO = 1.8 V 0.63
LDO_3V3 = 3.3 V 0.2
UARTRX_HYS Input hysteresis voltage V
VDDIO = 1.8 V 0.09
IO = –2 mA, LDO_3V3 = 3.3 V 2.9
UARTTX_VOH GPIO output high voltage V
IO = –2 mA, VDDIO = 1.8 V 1.35
IO = 2 mA, LDO_3V3 = 3.3 V 0.4
UARTTX_VOL GPIO output low voltage V
IO = 2 mA, VDDIO = 1.8 V 0.45
UARTTX_RO Output impedance, TX channel LDO_3V3 = 3.3 V 35 70 115 Ω
UARTTX_TRTF Rise and fall time, TX channel 10%–90%, CL = 20 pF 1 40 ns
UART_FMAX Maximum UART baud rate 1.1 Mbps
I2C_IRQ1Z, I2C_IRQ2Z
OD_VOL Low level output voltage IOL = 2 mA 0.4 V
OD_LKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 1 μA
SBU
SBU_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V
SBU_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V
SBU_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

(1) DEBUG_CTL1/2 do not have an internal pulldown resistance path.

7.20 I2C Slave Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA and SCL COMMON CHARACTERISTICS
ILEAK Input leakage current Voltage on Pin = LDO_3V3 –3 3 μA
IOL = 3mA, LDO_3V3 = 3.3 V 0.4
VOL SDA output low voltage V
IOL = 3mA, VDDIO = 1.8 V 0.36
VOL = 0.4 V 3
IOL SDA max output low current mA
VOL = 0.6 V 6
LDO_3V3 = 3.3 V 0.99
VIL Input low signal V
VDDIO = 1.8 V 0.54
LDO_3V3 = 3.3 V 2.31
VIH Input high signal V
VDDIO = 1.8 V 1.26
LDO_3V3 = 3.3 V 0.17
VHYS Input Hysteresis V
VDDIO = 1.8 V 0.09
TSP I2C pulse width suppressed 50 ns
CI Pin Capacitance 10 pF
SDA and SCL STANDARD MODE CHARACTERISTICS
FSCL I2C clock frequency 0 100 kHz
THIGH I2C clock high time 4 μs
TLOW I2C clock low time 4.7 μs
TSUDAT I2C serial data setup time 250 ns
THDDAT I2C serial data hold time 0 ns
TVDDAT I2C Valid data time SCL low to SDA output valid 3.4 μs
ACK signal from SCL low to SDA (out)
TVDACK I2C Valid data time of ACK condition 3.4 μs
low

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7.20 I2C Slave Characteristics (continued)

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TOCF I2C output fall time 10 pF to 400 pF bus 250 ns
TBUF I2C bus free time between stop and start 4.7 μs
TSTS I2C start or repeated Start condition setup time 4.7 μs
TSTH I2C Start or repeated Start condition hold time 4 μs
TSPS I2C Stop condition setup time 4 μs
SDA and SCL FAST MODE CHARACTERISTICS
FSCL I2C clock frequency 0 400 kHz
THIGH I2C clock high time 0.6 μs
TLOW I2C clock low time 1.3 μs
TSUDAT I2C serial data setup time 100 ns
THDDAT I2C serial data hold time 0 ns
TVDDAT I2C valid data time SCL low to SDA output valid 0.9 μs
ACK signal from SCL low to SDA (out)
TVDACK I2C valid data time of ACK condition 0.9 μs
low
10 pF to 400 pF bus, VDD = 3.3 V 12 250
TOCF I2C output fall time ns
10 pF to 400 pF bus, VDD = 1.8 V 6.5 250
TBUF I2C bus free time between stop and start 1.3 μs
TSTS I2Cstart or repeated Start condition setup time 0.6 μs
TSTH I2C Start or repeated Start condition hold time 0.6 μs
TSPS I2C Stop condition setup time 0.6 μs

7.21 SPI Controller Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSPI Frequency of SPI_CLK 11.82 12 12.18 MHz
TPER Period of SPI_CLK (1/F_SPI) 82.1 83.33 84.6 ns
TWHI SPI_CLK High Width 30 ns
TWLO SPI_CLK Low Width 30 ns
TDACT SPI_SZZ falling to SPI_CLK rising delay time 30 50 ns
TDINACT SPI_CLK falling to SPI_CSZ rising delay time 160 180 ns
TDPICO SPI_CLK falling to SPI_PICO Valid delay time –5 5 ns
TSUPOCI SPI_POCI valid to SPI_CLK falling setup time 21 ns
THDPOCI SPI_CLK falling to SPI_POCI invalid hold time 0 ns
10% to 90%, CL = 5 pF to 50 pF,
TRSPI SPI_CSZ/CLK/PICO rise time 0.1 8 ns
LDO_3V3 = 3.3 V
90% to 10%, CL = 5 pF to 50 pF,
TFSPI SPI_CSZ/CLK/PICO fall time 0.1 8 ns
LDO_3V3 = 3.3 V

7.22 BUSPOWERZ Configuration Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BUSPOWERZ Voltage for receiving VBUS Power through the V
VBPZ_EXT 0.8
PP_EXT path
BUSPOWERZ Voltage for receiving VBUS Power through the V
VBPZ_HV 0.8 2.4
PP_HV path
VBPZ_DIS BUSPOWERZ Voltage for disabling system power from VBUS 2.4 V

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7.23 Thermal Shutdown Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSD_MAIN Thermal shutdown temperature of the main thermal °C
Temperature rising 145 160 175
shutdown
TSDH_MAIN Thermal shutdown hysteresis of the main thermal shutdown Temperature falling 20 °C
TSD_PWR Thermal shutdown temperature of the power path block Temperature rising 135 150 165 °C
TSDH_PWR Thermal shutdown hysteresis of the power path block Temperature falling 37 °C
TSD_DG Programmable thermal shutdown detection deglitch time 0.1 ms

7.24 Oscillator Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FOSC_48M 48-MHz oscillator 47.28 48 48.72 MHz
FOSC_100K 100-kHz oscillator 95 100 105 kHz
RR_OSC External oscillator set resistance (0.2%) 14.985 15 15.015 kΩ

7.25 Single-Wire Debugger (SWD) Timing Requirements

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
MIN NOM MAX UNIT
FSWD Frequency of SWD_CLK 10 MHz
TPER Period of SWD_CLK (1 / FSWD) 100 ns
TWHI SWD_CLK high width 35 ns
TWLO SWD_CLK low width 35 ns
TDOUT SWD_CLK rising to SWD_DATA valid delay time 2 25 ns
TSUIN SWD_DATA valid to SWD_CLK rising setup time 9 ns
THDIN SWD_DATA hold time from SWD_CLK rising 3 ns
10% to 90%, CL = 5 pF to 50 pF, ns
TRSWD SWD output rise time 0.1 8
LDO_3V3 = 3.3 V
90% to 10%, CL = 5 pF to 50 pF, ns
TFSWD SWD output fall time 0.1 8
LDO_3V3 = 3.3 V

7.26 HPD Timing Requirements

Recommended operating conditions; TA = -10 to 85°C unless otherwise noted
PARAMETER MIN NOM MAX UNIT
DP SOURCE SIDE (HPD TX)
T_IRQ_MIN HPD IRQ minimum assert time 675 750 825 μs
T_3MS_MIN HPD assert 3 ms minimum time 3 3.33 3.67 ms
DP SINK SIDE (HPD RX)
HPD_HDB_SEL = 0 300 375 450 μs
T_HPD_HDB HPD high debounce time
HPD_HDB_SEL = 1 100 111 122 ms
T_HPD_LDB HPD low debounce time 300 375 450 μs
T_HPD_IRQ HPD IRQ limit time 1.35 1.5 1.65 ms

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7.27 Typical Characteristics

41 88

40 86

39 84
82
Resistance (m:)

Resistance (m:)
38
80
37
78
36
76
35
74
34 72
33 70
32 68
-10 0 10 20 30 40 50 60 70 80 90 100 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (qC) D001
Temperature (qC) D002

Figure 7-1. PP_5V0 Switch On-Resistance vs. Figure 7-2. PP_HV Switch On-Resistance vs.
Temperature Temperature
220

215

210
Resistance (m:)

205

200

195

190

185
-10 0 10 20 30 40 50 60 70 80 90 100
Temperature (qC) D003

Figure 7-3. PP_CABLE Switch On-Resistance vs Temperature

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8 Parameter Measurement Information

UVR_OUT3V3 UVR_OUT3V3 - UVRH_OUT3V3

VOUT_3V3

MRESET

TUVRDELAY TUVRASSERT TUVRDELAY TUVRASSERT

RESETZ

Figure 8-1. RESETZ Assertion Timing

T_ENA T_SAMPLEA T_CONVERTA T_INTA

ADC Clock

ADC Enable

ADC Sample

ADC Interrupt

ADC Output Previous or Invalid Output New Valid Output

Figure 8-2. ADC Enable and Conversion Timing

T_SAMPA T_CONVERTA T_INTA T_SAMPLE T_CONVERTA

ADC Clock

ADC Sample

ADC Interrupt

ADC Output New Valid Output New Valid Output

Figure 8-3. ADC Repeated Conversion Timing

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tf tr tSU;DAT

70 % 70 %
SDA
30 % 30 % cont.
tHD;DAT tVD;DAT
tf
tHIGH
tr
70 % 70 % 70 % 70 %
SCL 30 % 30 %
30 % 30 % cont.
tHD;STA tLOW
9th clock
S 1 / fSCL
1st clock cycle

tBUF

SDA

tVD;ACK
tSU;STA tHD;STA tSP tSU;STO

70 %
SCL 30 %
Sr P S
9th clock 002aac938

Figure 8-4. I2C Slave Interface Timing

tper twhigh twlow

SPI_CSZ

tdact tdinact

SPI_CLK

tdpico tdpico

SPI_PICO Valid Data

tsupoci

SPI_POCI Valid Data

thdpoci

Figure 8-5. SPI Controller Timing

tper twhigh t wlow

SWD_CLK

t dout t dout

SWD_DATA (Output) Valid Data

t hdin
tsuin

SWD_DATA (Input) Valid Data

Figure 8-6. SWD Timing

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9 Detailed Description
9.1 Overview
The TPS65982 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug
and orientation detection for a USB Type-C and PD plug or receptacle. The TPS65982 communicates with
the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port
power switches, controls an external high current port power switch, and multiplexes high-speed data to the
port for USB2.0 and supported Alternate Mode sideband information. The TPS65982 also controls an attached
super-speed multiplexer to simultaneously support USB3.0/3.1 data rates and DisplayPort video.
The TPS65982 is divided into six main sections: the USB-PD controller, the cable plug and orientation detection
circuitry, the port power switches, the port data multiplexer, the power management circuitry, and the digital core.
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible
USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, refer to the USB-PD Physical Layer section.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug
and orientation detection, a description of its features and more detailed circuitry, refer to the Cable Plug and
Orientation Detection section.
The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or
C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a
description of its features and more detailed circuitry, refer to the Port Power Switches section.
The port data multiplexer connects various input pairs to the system port through the C_USB_TP, C_USB_TN,
C_USB_BP, C_USB_BN, C_SBU1 and C_SBU2 pins. For a high-level block diagram of the port data
multiplexer, a description of its features and more detailed circuitry, refer to the USB Type-C Port Data
Multiplexer section.
The power management circuitry receives and provides power to the TPS65982 internal circuitry and to the
VOUT_3V3 and LDO_3V3 outputs. For a high-level block diagram of the power management circuitry, a
description of its features and more detailed circuitry, refer to the Power Management section.
The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as
handling control of all other TPS65982 functionality. A small portion of the digital core contains non-volatile
memory, called boot code, which is capable of initializing the TPS65982 and loading a larger, configurable
portion of application code into volatile memory in the digital core. For a high-level block diagram of the digital
core, a description of its features and more detailed circuitry, refer to the Digital Core section.
The digital core of the TPS65982 also interprets and uses information provided by the analog-to-digital converter
ADC (see the ADC section), is configurable to read the status of general purpose inputs and trigger events
accordingly, and controls general outputs which are configurable as push-pull or open-drain types with integrated
pullup or pulldown resistors and can operate tied to a 1.8 V or 3.3 V rail. The TPS65982 is an I2C slave to
be controlled by a host processor (see the I2C Slave Interface section), an SPI controller to write to and read
from an external flash memory (see the SPI Controller Interface section), and is programmed by a single-wire
debugger (SWD) connection (see the Single-Wire Debugger Interface section).
The TPS65982 also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs off of
accurate clocks provided by the integrated oscillators (see the Oscillators section).

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9.2 Functional Block Diagram

NMOS
PP_EXT

SENSEP SENSEN HV_GATE1 HV_GATE2

External FET Control and Sense

PP_HV VBUS
3A

PP_5V0
600 mA
PP_CABLE 3A
VDDIO
VIN_3V3 LDO_3V3
VOUT_3V3 LDO_1V8A
RESETZ Power Management and Supervisors
LDO_1V8D
MRESET LDO_BMC
HRESET

BUSPOWERZ
R_OSC Cable/Device
I2C_ADDR Detect,
9
GPIO1-9 C_CC1
3
I2C_SDA/SCL/IRQ1Z Digital Core Cable Power, RPD_G1
3
I2C_SDA/SCL/IRQ2Z C_CC2
4 and
SPI_PICO/POCI/CSZ/CLK RPD_G2
2
SWD_DATA/CLK USB-PD Phy
2
DEBUG_CTL1/2

2
UART_RX/TX
2 2
LSX_R2P/P2R C_USB_TP/TN
2 2
AUX_P/N C_USB_BP/BN
2 Port Data Multiplexer 2
USB_RP_P/N C_SBU1/2
2
DEBUG1/2
2
DEBUG3/4

GND

9.3 Feature Description

9.3.1 USB-PD Physical Layer
Figure 9-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block.

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Fast
current
limit
PP_CABLE

C_CC1/2 Gate Control C_CC1 Gate

and Current Limit Control
LDO_3V3

C_CC1
Digital Core USB-PD
Phy
LDO_3V3 C_CC2

C_CC2 Gate
Control

Figure 9-1. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry

USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (C_CC1 or C_CC2) that is DC biased because of the DFP (or UFP) cable attach mechanism
discussed in the Cable Plug and Orientation Detection section.
9.3.1.1 USB-PD Encoding and Signaling
Figure 9-2 shows the high-level block diagram of the baseband USB-PD transmitter. Figure 9-3 shows the
high-level block diagram of the baseband USB-PD receiver.

4b5b BMC
Data to PD_TX
Encoder Encoder

CRC

Figure 9-2. USB-PD Baseband Transmitter Block Diagram

BMC SOP 4b5b Data

from PD_RX
Decoder Detect Decoder

CRC

Figure 9-3. USB-PD Baseband Receiver Block Diagram

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The USB-PD baseband signal is driven on the C_CCn pins with a tri-state driver. The tri-state driver is slew
rate limited to reduce the high frequency components imparted on the cable and to avoid interference with
frequencies used for communication.
9.3.1.2 USB-PD Bi-Phase Marked Coding
The USBP-PD physical layer implemented in the TPS65982 is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 9-4 shows Biphase Mark Coding.
0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1
Data in

BMC

Figure 9-4. Biphase Mark Coding Example

The USB PD baseband signal is driven onto the C_CC1 or C_CC2 pins with a tri-state driver. The tri-state driver
is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending
the USB-PD preamble, the transmitter will start by transmitting a low level. The receiver at the other end will
tolerate the loss of the first edge. The transmitter will terminate the final bit by an edge to ensure the receiver
clocks the final bit of EOP.
9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded 1 contains a signal edge
at the beginning and middle of the UI, and the BMC coded 0 contains only an edge at the beginning, the masks
are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of
the Rx outer mask are specified to accommodate a change in signal amplitude because of the ground offset
through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the
boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks
are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate
that will have minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits
on the rise and fall times. Refer to the USB-PD Specifications for more details.
9.3.1.4 USB-PD BMC Transmitter
The TPS65982 transmits and receives USB-PD data over one of the C_CCn pins. The C_CCn pin is also
used to determine the cable orientation (see the Cable Plug and Orientation Detection section) and maintain
cable/device attach detection. Thus, a DC bias will exist on the C_CCn. The transmitter driver will overdrive the
C_CCn DC bias while transmitting, but will return to a Hi-Z state allowing the DC voltage to return to the C_CCn
pin when not transmitting. Figure 9-5 shows the USB-PD BMC TX/Rx driver block diagram.

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Digitally
Adjustable LDO_BMC
VREF

PD_TX Level
Driver
Shifter

C_CC1

PD_RX Level
C_CC2
Shifter
Digitally
Adjustable
USB-PD Modem VREF

Figure 9-5. USB-PD BMC TX/Rx Block Diagram

Figure 9-6 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere
between the minimum threshold for detecting a UFP attach (VD_CCH_USB) and the maximum threshold for
detecting a UFP attach to a DFP (VD_CCH_3P0) defined in the Cable Plugand Orientation Detection section.
This means that the DC bias can be below VOH of the transmitter driver or above VOH.
VOH

DC Bias DC Bias

VOL

DC Bias VOH DC Bias

VOL

Figure 9-6. TX Driver Transmission with DC Bias

The transmitter drives a digital signal onto the C_CCn lines. The signal peak VTXP is adjustable by application
code and sets the VOH/VOL for the BMC data that is transmitted, and is defined in USB-PD TX Driver Voltage
Adjustment Parameter. Keep in mind that the settings in a final system must meet the TX masks defined in the
USB-PD Specifications.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by
the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts
the noise ingression in the cable.
Figure 9-7 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is
bounded.
ZDRVER is defined by Equation 1.

RDRIVER
ZDRIVER =
1 + s ´ RDRIVER ´ CDRIVER (1)

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RDRIVER ZDRIVER
Driver
CDRIVER

Figure 9-7. ZDRIVER Circuit

9.3.1.5 USB-PD BMC Receiver

The receiver block of the TPS65982 receives a signal that falls within the allowed Rx masks defined in the
USB PD specification. The receive thresholds and hysteresis come from this mask. The values for VRXTR and
VRXTF are listed in USB-PD Baseband Signal Requirements and Characteristics.
Figure 9-8 shows an example of a multi-drop USB-PD connection. This connection has the typical UFP (device)
to DFP (host) connection, but also includes cable USB-PD TX/Rx blocks. Only one system can be transmitting at
a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can
exist on the wire as well as a typical DC bias setting circuit for attach detection.
DFP UFP
System System
Pullup
for Attach Cable
Connector Connector
Detection
Tx Tx
RD
CRECEIVER for Attach
CRECEIVER
Detection
CCBLPLUG CCBLPLUG
Rx Rx Rx

Tx
Rx
Tx

Figure 9-8. Example USB-PD Multi-Drop Configuration

9.3.2 Cable Plug and Orientation Detection

Figure 9-9 shows the plug and orientation detection block at each C_CC pin (C_CC1 and C_CC2). Each pin has
identical detection circuitry.
LDO_3V3

IH_CC_0P9 IH_CC_1P5 IH_CC_3P0

VREF1
C_CCn

VREF2

RD_CC

VREF3

Figure 9-9. Plug and Orientation Detection Block

9.3.2.1 Configured as a DFP

When configured as a DFP, the TPS65982 detects when a cable or a UFP is attached using the C_CC1 and
C_CC2 pins. When in a disconnected state, the TPS65982 monitors the voltages on these pins to determine
what, if anything, is connected. See the USB Type-C Specification for more information.

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Table 9-1 shows the high-level detection results. Refer to the USB Type-C Specification for more information.
Table 9-1. Cable Detect States for a DFP
C_CC1 C_CC2 CONNECTION STATE RESULTING ACTION
Continue monitoring both C_CC pins for attach. Power is not applied to VBUS or
Open Open Nothing attached
VCONN until a UFP connect is detected.
Rd Open UFP attached Monitor C_CC1 for detach. Power is applied to VBUS but not to VCONN (C_CC2).
Open Rd UFP attached Monitor C_CC2 for detach. Power is applied to VBUS but not to VCONN (C_CC1).
Powered Cable/No UFP Monitor C_CC2 for a UFP attach and C_CC1 for cable detach. Power is not applied to
Ra Open
attached VBUS or VCONN (C_CC1) until a UFP attach is detected.
Powered Cable/No UFP Monitor C_CC1 for a UFP attach and C_CC2 for cable detach. Power is not applied to
Open Ra
attached VBUS or VCONN (C_CC1) until a UFP attach is detected.
Provide power on VBUS and VCONN (C_CC1) then monitor C_CC2 for a UFP
Ra Rd Powered Cable/UFP Attached
detach. C_CC1 is not monitored for a detach.
Provide power on VBUS and VCONN (C_CC2) then monitor C_CC1 for a UFP
Rd Ra Powered Cable/UFP attached
detach. C_CC2 is not monitored for a detach.
Debug Accessory Mode
Rd Rd Sense either C_CC pin for detach.
attached
Audio Adapter Accessory
Ra Ra Sense either C_CC pin for detach.
Mode attached

When the TPS65982 is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin is
monitored for different states. When a UFP is attached to the pin, a pulldown resistance of Rd to GND will exist.
The current IH_CC is then forced across the resistance Rd generating a voltage at the C_CCn pin.
When configured as a DFP advertising Default USB current sourcing capability, the TPS65982 applies
IH_CC_USB to each C_CCn pin. When a UFP with a pulldown resistance Rd is attached, the voltage on the
C_CCn pin will pull below VH_CCD_USB. The TPS65982 can also be configured as a DFP to advertise default
(500 mA), 1.5 A and 3 A sourcing capabilities.
When the C_CCn pin is connected to an active cable VCONN (power to the active cable), the
pulldown resistance will be different (Ra). In this case, the voltage on the C_CCn pin will pull below
VH_CCA_USB/1P5/3P0 and the system will recognize the active cable.
The VH_CCD_USB/1P5/3P0 thresholds are monitored to detect a disconnection from each of these cases
respectively. When a connection has been recognized and the voltage on the C_CCn pin rises above the
VH_CCD_USB/1P5/3P0 threshold, the system will register a disconnection.
9.3.2.2 Configured as a UFP
When the TPS65982 is configured as a UFP, the TPS65982 presents a pulldown resistance RD_CC on each
C_CCn pin and waits for a DFP to attach and pullup the voltage on the pin. The DFP will pullup the C_CC pin
by applying either a resistance or a current. The UFP detects an attachment by the presence of VBUS. The UFP
determines the advertised current from the DFP by the pullup applied to the C_CCn pin.
9.3.2.3 Dead-Battery or No-Battery Support
Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source will provide a voltage
on VBUS. The TPS65982 is hardware-configurable to present this Rd during a dead-battery or no-battery
condition. Additional circuitry provides a mechanism to turn off this Rd when the port is acting as a source.
Figure 9-10 shows the RPD_Gn pin used to configure the behavior of the C_CCn pins, and elaborates on
the basic cable plug and orientation detection block shown in Figure 9-9. RPD_G1 and RPD_G2 configure
C_CC1 and C_CC2 respectively. A resistance R_RPD is connected to the gate of the pulldown FET on each
C_CCn pin. This resistance must be pin-strapped externally to configure the C_CCn pin to behave in one of
two ways: present an Rd pulldown resistance or present a Hi-Z when the TPS65982 is unpowered. During
normal operation, RD will be RD_CC; however, while dead-battery or no-battery conditions exist, the resistance
is un-trimmed and will be RD_DB. When RD_DB is presented during dead-battery or no-battery, application
code will switch to RD_CC.

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RPD_Gn

C_CCn

R_RPD RD_DB

RD_DB_EN

RD_CC

RD_CC_EN

Figure 9-10. C_CCn and RPD_Gn pins

When C_CC1 is shorted to RPD_G1 and C_CC2 is shorted to RPD_G2 in an application of the TPS65982,
booting from dead-battery or no-battery conditions will be supported. In this case, the gate driver for the pulldown
FET is Hi-Z at its output. When an external connection pulls up on C_CCn (the case when connected to a DFP
advertising with a pullup resistance Rp or pullup current), the connection through R_RPD will pull up on the FET
gate turning on the pulldown through RD_DB. In this condition, the C_CCn pin will act as a clamp VTH_DB in
series with the resistance RD_DB.
When RPD_G1 and RPD_G2 are shorted to GND in an application and not electrically connected to C_C1
and C_CC2, booting from dead-battery or no-battery conditions is not possible. In this case, the TPS65982 will
present a Hi-Z on the C_CC1 and C_CC2 pins and a USB Type-C source will never provide a voltage on VBUS.
9.3.3 Port Power Switches
Figure 9-11 shows the TPS65982 port power path including all internal and external paths. The port power path
provides to VBUS from PP_5V0, provides power to or from VBUS from or to PP_HV, provides power to or from
an external port power node (shown and refered to as PP_EXT) from or to VBUS, and provides power from
PP_CABLE to C_CC1 or C_CC2. The PP_CABLE to C_CCn switches shown in Figure 9-11 are the same as in
Figure 9-1, but are now shown without the analog USB Type-C cable plug and orientation detection circuitry.

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RSENSE NMOS
10 mΩ ± 1% 5A
PP_EXT

HV_GATE1

HV_GATE2
SENSEN
SENSEP
PP_HV Gate Control
and Current Limit

PP_HV
HV Gate Control and Sense
Fast
3A current
limit

PP_5V0 Gate Control

and Current Limit

PP_5V0 VBUS
Fast
3A current
limit

C_CC1/2 Gate Control C_CC1 Gate

and Current Limit Control

PP_CABLE C_CC1
Fast
current600mA
limit

C_CC2 Gate
Control

C_CC2

Figure 9-11. Port Power Paths

9.3.3.1 5V Power Delivery

The TPS65982 provides port power to VBUS from PP_5V0 when a low voltage output is needed. The switch
path provides 5 V at up to 3 A to from PP_5V0 to VBUS. Figure 9-11 shows a simplified circuit for the switch
from PP_5V0 to VBUS.
9.3.3.2 5V Power Switch as a Source
The PP_5V0 path is unidirectional, sourcing power from PP_5V0 to VBUS only. When the switch is on, the
protection circuitry limits reverse current from VBUS to PP_5V0. Figure 9-12 shows the I-V characteristics of the
reverse current protection feature. Figure 9-12 and the reverse current limit can be approximated using Equation
2.

IREV5V0 = VREV5V0/RPP5V (2)

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1/RPP5V

VREV5V0

V
IREV5V0

Figure 9-12. 5V Switch I-V Curve

9.3.3.3 PP_5V0 Current Sense

The current from PP_5V0 to VBUS is sensed through the switch and is available to be read digitally through the
ADC.
9.3.3.4 PP_5V0 Current Limit
The current through PP_5V0 to VBUS is limited to ILIMPP5V and is controlled automatically by the digital
core. When the current exceeds ILIMPP5V, the current-limit circuit activates. Depending on the severity of the
over-current condition, the transient response will react in one of two ways: Figure 9-13 and Figure 9-14 show
the approximate response time and clamping characteristics of the circuit for a hard short while Figure 9-15
shows the shows the approximate response time and clamping characteristics for a soft short with a load of 2 Ω.
12 6
I VBUS
VBUS
10 5

8 4

Voltage (V)
Current (A)

6 3

4 2

2 1

0 0

-2 -1
Time (5 Ps/div)
D004

Figure 9-13. PP_5V0 Current Limit with a Hard Short

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12 6
I VBUS
VBUS
10 5

8 4

Voltage (V)
Current (A)

6 3

4 2

2 1

0 0

-2 -1
Time (200 Ps/div)
D005

Figure 9-14. PP_5V0 Current Limit with a Hard Short (Extended Time Base)
6 6
I VBUS
VBUS

5 5

4 4

Voltage (V)
Current (A)

3 3

2 2

1 1

0 0
Time (200 Ps/div)
D006

Figure 9-15. PP_5V0 Current Limit with a Soft Short (2 Ω)

9.3.3.5 Internal HV Power Delivery

The TPS65982 has an integrated, bi-directional high-voltage switch that is rated for up to 3 Amps of current.
The TPS65982 is capable of sourcing or sinking high-voltage power through an internal switch path designed
to support USB-PD power up to 20 V at 3 A of current. VBUS and PP_HV are both rated for up to 22 V
as determined by Recommended Operating Conditions, and operate down to 0 V as determined by Absolute
Maximum Ratings. In addition, VBUS is tolerant to voltages up to 22 V even when PP_HV is at 0 V. Similarly,
PP_HV is tolerant up to 22 V while VBUS is at 0 V. The switch structure is designed to tolerate a constant
operating voltage differential at either of these conditions. Figure 9-11 shows a simplified circuit for the switch
from PP_HV to VBUS.
9.3.3.6 Internal HV Power Switch as a Source
The TPS65982 provides power from PP_HV to VBUS at the USB Type-C port as an output when operating as
a source. When the switch is on as a source, the path behaves resistively until the current reaches the amount

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calculated by Equation 3 and then blocks reverse current from VBUS to PP_HV. Figure 9-16 shows the diode
behavior of the switch as a source.

IREVHV = VREVHV/RPPHV (3)

1/RPPHV

VREVHV

V
IREVHV

Figure 9-16. Internal HV Switch I-V Curve as a Source

9.3.3.7 Internal HV Power Switch as a Sink

The TPS65982 can also receive power from VBUS to PP_HV when operating as a sink. When the switch is on
as a sink the path behaves as an ideal diode and blocks reverse current from PP_HV to VBUS. Figure 9-17
shows the diode behavior of the switch as a sink.

1/RPPHV
VREVHV/RPPHV

VBUS-PP_HV
VREVHV

Figure 9-17. Internal HV Switch I-V Curve as a Sink

9.3.3.8 Internal HV Power Switch Current Sense

The current from PP_HV to VBUS is sensed through the switch and is available to be read digitally through the
ADC only when the switch is sourcing power. When sinking power, the readout from the ADC will not reflect the
current.
9.3.3.9 Internal HV Power Switch Current Limit
The current through PP_HV to VBUS is current limited to ILIMPPHV (only when operating as a source) and
is controlled automatically by the digital core. When the current exceeds ILIMPPHV, the current-limit circuit
activates. Depending on the severity of the over-current condition, the transient response will react in one of two
ways: Figure 9-18 shows the approximate response time and clamping characteristics of the circuit for a hard
short while Figure 9-19 shows the approximate response time and clamping characteristics for a soft short of 7
Ω.

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30 30
I VBUS
VBUS
25 PP_HV 25

20 20

Voltage (V)
Current (A)

15 15

10 10

5 5

0 0

-5 -5
Time (10 Ps/div)
D007

Figure 9-18. PP_HV Current Limit Response with a Hard Short

5 25
I VBUS
VBUS
PP_HV
4 20

3 15

Voltage (V)
Current (A)

2 10

1 5

0 0

-1 -5
Time (200 Ps/div)
D008

Figure 9-19. PP_HV Current Limit Response with a Soft Short (7 Ω)

9.3.3.10 External HV Power Delivery

The TPS65982 is capable of controlling an external high-voltage, common-drain back-to-back NMOS FET switch
path to source or sink power up to the maximum limit of the USB PD specification: 20 V at 5 A of current. The
TPS65982 provides external control and sense to external NMOS power switches for currents greater than 3
A. This path is bi-directional for either sourcing current to VBUS or sinking current from VBUS. The external
NMOS switches are back-to-back to protect the system from large voltage differential across the FETs as well as
blocking reverse current flow. Each NFET has a separate gate control. HV_GATE2 is always connected to the
VBUS side and HV_GATE1 is always connected to the opposite side, referred to as PP_EXT. Two sense pins,
SENSEP and SENSEN, are used to implement reverse current blocking, over-current protection, and current
sensing. The external path may be used in conjunction with the internal path. For example, the internal path
may be used to source current from PP_HV to VBUS when the TPS65982 is acting as a power source and the
external path may be used to sink current from VBUS to PP_EXT to charge a battery when the TPS65982 is
acting as a sink. The internal and external paths must never be used in parallel to source current at the same

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time or sink current at the same time. The current limiting function will not function properly in this case and may
become unstable.
9.3.3.11 External HV Power Switch as a Source with RSENSE
Figure 9-11 shows the configuration when the TPS65982 is acting as a source for the external switch path.
The external FETs must be connected in a common-drain configuration and will not work in a common source
configuration. In this mode, current is sourced to VBUS. RSENSE provides an accurate current measurement
and is used to initiate the current limiting feature of the external power path. The voltage between SENSEP
(PP_EXT) and SENSEN (VBUS) is sensed to block reverse current flow. This measurement is also digitally
readable via the ADC.
9.3.3.12 External HV Power Switch as a Sink with RSENSE
Figure 9-20 shows the configuration when the TPS65982 is acting as a sink for the external switch path
with RSENSE used to sense current. Acting as a sink, the voltage between SENSEP (VBUS) and SENSEN
(PP_EXT) is sensed to provide an accurate current measurement and initiate the current limiting feature of the
external power path. This measurement is also digitally readable via the ADC.
RSENSE NMOS
10 mΩ ± 1% 5A
PP_EXT

HV_GATE1

HV_GATE2
SENSEN
SENSEP

VBUS

HV Gate Control and Sense

Figure 9-20. External HV Switch as a Sink with RSENSE

9.3.3.13 External HV Power Switch as a Sink without RSENSE

Figure 9-21 shows the configuration when the TPS65982 is acting as a sink for the external switch path without
an RSENSE resistor. In this mode, current is sunk from VBUS to an internal system power node, referred to as
PP_EXT. This is used for charging a battery or for providing a supply voltage for a bus-powered device. To block
reverse current, the VBUS and SENSEP pins monitor the voltage across the NFETs. To ensure that SENSEN
does not float, tie SENSEP to SENSEN in this configuration. When configured in this mode, the digital readout
from current from the ADC will be approximately zero.

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NMOS
5A
PP_EXT

HV_GATE1

HV_GATE2
SENSEN
SENSEP

VBUS
HV Gate Control and Sense

Figure 9-21. External HV Switch as a Sink without RSENSE

9.3.3.14 External Current Sense

The current through the external NFETs to VBUS is sensed through the RSENSE resistor and is available to be
read digitally through the ADC. When acting as a source, the readout from the ADC will only accurately reflect
the current through the external NFETs when the connection of SENSEP and SENSEN adheres to Figure 9-11.
When acting as a sink, the readout from the ADC will only accurately reflect the current through the external
NFETs when the connection of SENSEP and SENSEN adheres to Figure 9-20.
9.3.3.15 External Current Limit
The current through the external NFETs to VBUS is current limited when acting as a source or a sink. The
current is sensed across the external RSENSE resistance. The current limit is set by a combination of the
RSENSE magnitude and configuration settings for the voltage across the resistance. When the voltage across
the RSENSE resistance exceeds the automatically set voltage limit, the current-limit circuit is activated.
9.3.3.16 Soft Start
When configured as a sink, the SS pin provides a soft start function for each of the high-voltage power path
supplies (P_HV and external PP_EXT path) up to 5.5 V. The SS circuitry is shared for each path and only one
path will turn on as a sink at a time. The soft start is enabled by application code or via the host processor.
The SS pin is initially discharged through a resistance RSS_DIS. When the switch is turned on, a current ISS is
sourced from the pin to a capacitance CSS. This current into the capacitance generates a slow ramping voltage.
This voltage is sensed and the power path FETs turn on and the voltage follows this ramp. When the voltage
reaches the threshold VTHSS, the power path FET will be near being fully turned on, the output voltage will be
fully charged. At time TSSDONE, a signal to the digital core indicates that the soft start function has completed.
The ramp rate of the supply is given by Equation 4:

ISS
Ramp Rate = 9 ´
CSS (4)

The maximum ramp voltage for the supply is approximately 16.2 V. For any input voltage higher than this, the
ramp will stop at 16.2 V until the firmware disables the soft start. At this point, the voltage will step to the input
voltage at a ramp rate defined by approximately 7 μA into the gate capacitance of the switch. The TSSDONE
time is independent of the actual final ramp voltage.
9.3.3.17 BUSPOWERZ
At power-up, when VIN_3V3 is not present and a dead-battery condition is supported as described in Dead-
Battery or No-Battery Support, the TPS65982 will appear as a USB Type-C sink (device) causing a connected
USB Type-C source (host) to provide 5 V on VBUS. The TPS65982 will power itself from the 5-V VBUS rail (see
Power Management) and execute boot code (see Boot Code). The boot code will observe the BUSPOWERZ
voltage, which will fall into one of three voltage ranges: VBPZ_DIS, VBPZ_HV, and VBPZ_EXT (defined in

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BUSPOWERZ Configuration Characteristics). These three voltage ranges configure how the TPS65982 routes
the 5 V present on VBUS to the system in a dead-battery or no-battery scenario.
When the voltage on BUSPOWERZ is in the VBPZ_DIS range (when BUSPOWERZ is tied to LDO_3V3 as in
Figure 9-22), this indicates that the TPS65982 will not route the 5 V present on VBUS to the entire system.
In this case, the TPS65982 will load SPI-connected flash memory and execute this application code. This
configuration will disable both the PP_HV and PP_EXT high voltage switches and only use VBUS to power the
TPS65982.

LDO_3V3

LDO_1V8D

BUSPOWERZ ADC

Figure 9-22. BUSPOWERZ Configured to Disable Power from VBUS

The BUSPOWERZ pin can alternately configure the TPS65982 to power the entire system through the PP_HV
internal load switch when the voltage on BUSPOWERZ is in the VBPZ_HV range (when BUSPOWERZ is tied to
LDO_1V8D as in Figure 9-23).

LDO_3V3

LDO_1V8D

BUSPOWERZ ADC

Figure 9-23. BUSPOWERZ Configured with PP_HV as Input Power Path

The BUSPOWERZ pin can also alternately configure the TPS65982 to power the entire system through
the PP_EXT external load switch when the voltage on BUSPOWERZ is in the VBPZ_EXT range (when
BUSPOWERZ is tied to GND as in Figure 9-24).

LDO_3V3

LDO_1V8D

BUSPOWERZ ADC

Figure 9-24. BUSPOWERZ Configured with PP_EXT as Input Power Path

9.3.3.18 Voltage Transitions on VBUS through Port Power Switches

Figure 9-25 shows the waveform for a positive voltage transition. The timing and voltages apply to both a
transition from 0 V to PP_5V0 and a transition from PP_5V0 to PP_HV as well as a transition from PP_5V0 to
an PP_EXT. A transition from PP_HV to PP_EXT is possible and vice versa, but does not necessarily follow the
constraints in Figure 9-25. When a switch is closed to transition the voltage, a maximum slew-rate of SRPOS
occurs on the transition. The voltage ramp will remain monotonic until the voltage reaches VSRCVALID within
the final voltage. The voltage may overshoot the new voltage by VSRCVALID. After time TSTABLE from the

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start of the transition, the voltage will fall to within VSRCNEW of the new voltage. During the time TSTABLE, the
voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage.

VSRCVALID (max)

VSRCNEW (max)

New Voltage

VSRCNEW (min)
Voltage

VSRCVALID (min)

SRPOS

Old Voltage
TSTABLE

Time

Figure 9-25. Positive Voltage Transition on VBUS

Figure 9-26 shows the waveform for a negative voltage transition. The timing and voltages apply to both a
transition from PP_HV to PP_5V0 and a transition from PP_5V0 to 0V as well as a transition from PP_EXT to
PP_5V0. A transition from PP_HV to PP_EXT is possible and vice versa, but does not necessarily follow the
constraints in Figure 9-26. When a switch is closed to transition the voltage, a maximum slew-rate of SRNEG
occurs on the transition. The voltage ramp will remain monotonic until the voltage reaches TOLTRANUN within
the final voltage. The voltage may overshoot the new voltage by TOLTRANLN. After time TSTABLE from the
start of the transition, the voltage will fall to within VSRCNEW of the new voltage. During the time TSTABLE, the
voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage.
TSTABLE
Old Voltage

SRNEG
Voltage

VSRCVALID (max)

VSRCNEW (max)

New Voltage

VSRCNEW (min)

VSRCVALID (min)

Time

Figure 9-26. Negative Voltage Transition on VBUS

9.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS

The TPS65982 has an integrated active pulldown on VBUS when transitioning from PP_HV to PP_5V0, shown
in Figure 9-27. When the PP_HV switch is disabled and VBUS > PP_5V0 + VHVDISPD, amplifier turns on a
current source and pulls down on VBUS. The amplifier implements active slew rate control by adjusting the
pulldown current to prevent the slew rate from exceeding specification. When VBUS falls to within VHVDISPD of

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PP_5V0, the pulldown is turned off. The load on VBUS will then continue to pull VBUS down until the ideal diode
switch structure turns on connecting it to PP_5V0. When switching from PP_HV or PP_EXT to PP_5V0, PP_HV
or PP_EXT must be above VSO_HV to follow the switch-over shown in Figure 9-26.
PP_5V0 Gate Control
and Current Limit

PP_5V0 VBUS
Fast
current
limit

VHVDISPD

Slew Rate
Controlled
Pulldown

Figure 9-27. PP_5V0 Slew Rate Control

9.3.3.20 VBUS Transition to VSAFE0V

When VBUS transitions to near 0 V (VSAFE0V), the pulldown circuit in Figure 9-27 is turned on until VBUS
reaches VSAFE0V. This transition will occur within time TSAFE0V.
9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
The C_CC1 and C_CC2 pins are used to deliver power to active circuitry inside a connected cable and output
USB-PD data to the cable and connected device. Figure 9-11 shows the C_CC1, and C_CC2 outputs to the port.
Only one of these pins will be used to deliver power at a time depending on the cable orientation. The other pin
will be used to transmit USB-PD data through the cable to a connected device.
Figure 9-28 shows a high-level flow of connecting these pins based on the cable orientation. See the Section
9.3.2 section for more detailed information on plug and orientation detection.

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Firmware Loaded
Wait for Plug

no Plug
Detected?

yes

Detect Type and

Orientation

Connect yes no Connect

C_CC1 =
C_CC1 to C_CC2 to
Data line?
USB-PD Phy USB-PD Phy

no C_CC2 yes yes C_CC1 no

Powered? Powered?

Connect C_CC2 Connect C_CC1

C_CC2 Open C_CC1 Open
to PP_CABLE to PP_CABLE

Figure 9-28. Port C_CC and VCONN Connection Flow

Figure 9-29 and Figure 9-30 show the two paths from PP_CABLE to the C_CCn pins. When one C_CCn pin is
powered from PP_CABLE, the other is connected to the USB-PD BMC modem. The red line shows the power
path and the green line shows the data path.
Fast
current
limit
PP_CABLE

C_CC1/2 Gate Control C_CC1 Gate

and Current Limit Control
LDO_3V3

USB-PD Data

C_CC1 CC
Digital Core USB-PD
Phy Power
LDO_3V3 C_CC2 VCONN

Active
Cable
Circuitry

Cable Plug
C_CC2 Gate
Control

Figure 9-29. Port C_CC1 and C_CC2 Normal Orientation Power from PP_CABLE

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Fast
current
limit
PP_CABLE

C_CC1/2 Gate Control C_CC1 Gate

and Current Limit Control
LDO_3V3
Cable Plug

Active
Cable
Circuitry

C_CC1 VCONN
Digital Core USB-PD Power
Phy
LDO_3V3 C_CC2 CC

USB-PD Data

C_CC2 Gate
Control

Figure 9-30. Port C_CC1 and C_CC2 Reverse Orientation Power from PP_CABLE

9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture

Figure 9-11 shows the switch architecture for the PP_CABLE switch path to the C_CCc pins. Each path provides
a unidirectional current from PP_CABLE to C_CC1 and C_CC2. The switch structure blocks reverse current
from C_CC1 or C_CC2 to PP_CABLE.
9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
The PP_CABLE to C_CC1 and C_CC2 share current limiting through a single FET on the PP_CABLE side of
the switch. The current limit ILIMPPCC is adjustable between two levels. When the current exceeds ILIMPPCC,
the current-limit circuit activates. Depending on the severity of the over-current condition, the transient response
will react in one of two ways: Figure 9-31 and Figure 9-32 show the approximate response time and clamping
characteristics of the circuit for a hard short while Figure 9-33 shows the approximate response time and
clamping characteristics for a soft short. The switch does not have reverse current blocking when the switch is
enabled and current is flowing to either C_CC1 or C_CC2.

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7 10
I CC2
C_CC2
6 PP_CABLE 8

5 6

Voltage (V)
Current (A)

4 4

3 2

2 0

1 -2

0 -4
Time (10 Ps/div)
D009

Figure 9-31. PP_CABLE to C_CCn Current Limit with a Hard Short

6 6
I CC2
C_CC2
5 PP_CABLE 5

4 4

Voltage (V)
Current (A)

3 3

2 2

1 1

0 0

-1 -1
Time (500 Ps/div)
D010

Figure 9-32. PP_CABLE to C_CCn Current Limit with a Hard Short (Extended Time Base)

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3 6
I CC2
C_CC2
2.5 PP_CABLE 5

2 4

Voltage (V)
Current (A)

1.5 3

1 2

0.5 1

0 0

-0.5 -1
Time (50 Ps/div)
D011

Figure 9-33. PP_CABLE to C_CCn Current Limit Response with a Soft Short (2 Ω)

9.3.4 USB Type-C Port Data Multiplexer

The USB Type-C receptacle pin configuration is show in Figure 9-34. Not all signals shown are required for all
platforms or devices. The basic functionality of the pins deliver USB 2.0 (D+ and D–) and USB 3.1 (TX and RX
pairs) data buses, USB power (VBUS) and ground (GND). Configuration Channel signals (CC1 and CC2), and
two Reserved for Future Use (SBU) signal pins. The data bus pins (Top and Bottom D+/D– and the SBU pins)
are available to be used in non-USB applications as an Alternate Mode (i.e., DisplayPort, Thunderbolt™, etc.).
Figure 9-34. USB Type-C Receptacle Pin Configuration
A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A11 A12

GND TX1+ TX1– VBUS CC1 D+ D– SBU1 VBUS RX2– RX2+ GND

GND RX1+ RX1– VBUS SBU2 D– D+ CC2 VBUS TX2– TX2+ GND

B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

The TPS65982 USB Type-C interface multiplexers are shown in Table 9-2. The outputs are determined based
on detected cable orientation as well as the identified interface that is connected to the port. There are two USB
output ports that may or may not be passing USB data. When an Alternate Mode is connected, these same
ports may also pass that data (e.g. DisplayPort, Thunderbolt). Note, the TPS65982 pin to receptacle mapping is
shown in Table 9-2. The high-speed RX and TX pairs are not mapped through the TPS65982 as this would place
extra resistance and stubs on the high-speed lines and degrade signal performance.
Table 9-2. TPS65982 to USB Type-C Receptacle Mapping
DEVICE PIN Type-C RECEPTACLE PIN
VBUS VBUS (A4, A9, B4, B9)
C_CC1 CC1 (A5)
C_CC2 CC2 (B5)
C_USB_TP D+ (A6)
C_USB_TN D– (A7)
C_USB_BP D+ (B6)
C_USB_BN D– (B7)
C_SBU1 SBU1 (A8)

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Table 9-2. TPS65982 to USB Type-C Receptacle Mapping (continued)

DEVICE PIN Type-C RECEPTACLE PIN
C_SBU2 SBU2 (B8)

SWD_DATA

SWD_CLK

GPIO0

GPIO1

UART0 GPIO
1st Stage 2nd Stage
Digital Cross-Bar Mux SWD
UART1 CORE_ CORE_ CORE_
UART0 UART1 UART0 UART1 UART2

Digital Core

SWD_CLK/DATA C_USB_TP
USB_EP_P/N
USB_RP_P/N C_USB_TN
DEBUG1/2
UART_TX
DEBUG3/4
UART_RX

Charger
LSX_P2R
ID To ADC
LSX_R2P SBU_INT1
SBU_INT2
SWD_CLK/DATA
USB_RP_P
USB_RP
USB_RP_N USB_RP_P/N C_USB_BP
DEBUG1/2 USB_EP_P/N
DEBUG1 DEBUG3/4 C_USB_BN
DEBUG1/2
DEBUG2

DEBUG3
DEBUG3/4
DEBUG4
SWD_CLK/DATA
SBU_INT1
AUX_P C_SBU1
AUX_P/N SBU_INT2
AUX_N C_SBU2
DEBUG1/2
DEBUG3/4
AUX_P/N

Figure 9-35. Port Data Multiplexers

Table 9-3 shows the typical signal types through the switch path. The UART_RX/TX and LSX_P2R/R2P paths
are digitally buffered to allow tri-state control for these paths. All other switches are analog pass switches. The
LSX_P2R/R2P pair is also configurable to be analog pass switches as well. These switch paths are not limited to
the specified signal type. For the signals that interface with the digital core, the maximum data rate is dictated by
the clock rate at which the core is running.
Table 9-3. Typical Signals through Analog Switch Path
INPUT PATH SIGNAL TYPE SIGNAL FUNCTION
SWD_DATA/CLK Single Ended Data, Clock
UART_RX/TX Single Ended TX/Rx UART
LSX_P2R/R2P Single Ended TX/Rx UART
DEBUG1/2/3/4 Single Ended Debug
AUX_P/N Differential DisplayPort and Thunderbolt AUX channel
USB_EP_P/N Differential USB 2.0 Low Speed Endpoint
USB_RP_P/N Differential USB 2.0 High Speed Data Root Port

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9.3.4.1 USB Top and Bottom Ports

The Top (C_USB_TP and C_USB_TN) and Bottom (C_USB_BP and C_USB_BN) ports that correspond to the
Type-C top and bottom USB D+/D– pairs are swapped based on the detected cable orientation. The symmetric
pin order shown in Figure 9-34 from the A-side to the B-side allows the pins to connect to equivalent pins on the
opposite side when the cable orientation is reversed.
9.3.4.2 Multiplexer Connection Orientation
Table 9-4 shows the multiplexer connection orientation. For the USB D+/D– pair top and bottom port
connections, these connections are fixed. For the SBU port connections, the SBU crossbar multiplexer enables
flipping of the signal pair and the connections shown are for the upside-up orientation. The CORE_UARTn
connections come from a digital crossbar multiplexer that allows the UART_RX/TX, LSX_P2R/R2P, and
GPIO0/1 to be mapped to any of the 1st stage multiplexers.
Table 9-4. Data Multiplexer Connections
SBU MULTIPLEXER
SYSTEM PIN USB TOP PIN USB BOTTOM PIN
PIN
USB_RP_P C_USB_TP C_USB_BP
USB_RP_N C_USB_TN C_USB_BN
USB_EP_P C_USB_TP C_USB_BP
USB_EP_N C_USB_TN C_USB_BN
SWD_CLK C_USB_TP C_USB_BP SBU1
SWD_DATA C_USB_TN C_USB_BN SBU2
DEBUG1 C_USB_TP C_USB_BP SBU1
DEBUG2 C_USB_TN C_USB_BN SBU2
DEBUG3 C_USB_TP C_USB_BP SBU1
DEBUG4 C_USB_TN C_USB_BN SBU2
AUX_P C_USB_TP C_USB_BP SBU1
AUX_N C_USB_TN C_USB_BN SBU2
LSX_R2P SBU1
LSX_P2R SBU2
CORE_UART0_TX C_USB_TP
CORE_UART0_RX C_USB_TN
CORE_UART1_TX C_USB_BP
CORE_UART1_RX C_USB_BN
CORE_UART2_TX SBU1
CORE_UART2_RX SBU2

9.3.4.3 Digital Crossbar Multiplexer

The TPS65982 UART paths (UART_RX/TX and LSX_P2R/R2P) and GPIO0/1 all have digital inputs that pass
through a cross-bar multiplexer inside the digital core. Each of these pins is configurable as an input or output of
the cross-bar multiplexer. The digital cross-bar multiplexer then connects to the port data multiplexers as shown
in Figure 9-35. The connections are configurable via firmware. The default state at power-up is to connect a
buffered version of UART_RX to UART_TX providing a bypass through the TPS65982 for daisy chaining during
power on reset.
9.3.4.4 SBU Crossbar Multiplexer
The SBU Crossbar Multiplexer provides pins (C_SBU1 and C_SBU2) for future USB functionality as well as
Alternate Modes. The multiplexer swaps the output pair orientation based on the cable orientation. For more
information on Alternate Modes, refer to the USB PD Specification.

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9.3.4.5 Signal Monitoring and Pullup/Pulldown

The TPS65982 has comparators that may be enabled to interrupt the core when a switching event occurs on any
of the port inputs. The input parameters for the detection are listed in the Port Data Multiplexer Signal Monitoring
Pullup and Pulldown Characteristics table. These comparators are disconnected by application code when these
pins are not digital signals but an analog voltage.
The TPS65982 has pullups and pulldowns between the first and second stage multiplexers of the port switch for
each port output: C_SBU1/2, C_USB_TP/N, C_USB_BP/N. The configurable pullup and pulldown resistances
between each multiplexer are shown in Figure 9-36.
LDO_3V3 LDO_3V3

RP100 RP5

To Digital Core

1st Stage 2nd Stage

Mux Mux
RPD1 RP5 RP100

LDO_3V3 LDO_3V3

RP100 RP5

To Digital Core

RPD1 RP5 RP100

Figure 9-36. Port Detect and Pullup/Pulldown

9.3.4.6 Port Multiplexer Clamp

Each input to the 2nd stage multiplexer is clamped to prevent voltages on the port from exceeding the safe
operating voltage of circuits attached to the system side of the Port Data Multiplexer. Figure 9-37 shows the
simplified clamping circuit. When a path through the 2nd stage multiplexer is closed, the clamp is connected
to the one of the port pins (C_USB_TP/N, C_USB_BP/N, C_SBU1/2). When a path through the 2nd stage
multiplexer is not closed, then the port pin is not clamped. As the pin voltage rises above the VCLMP_IND
voltage, the clamping circuit activates, and sinks current to ground, preventing the voltage from rising further.

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2nd Stage Mux Input

VREF

Figure 9-37. Port Mux Clamp

9.3.4.7 USB2.0 Low-Speed Endpoint

The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based
accesses. The TPS65982 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to
provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for
advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes which
cannot be supported by the host, the Billboard class allows a means for the host to report back to the user
without any silent failures.
Figure 9-38 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the
Serial Interface Engine, and the Endpoint FIFOs and supports low speed operation.

USB_EP
LDO_3V3 C_USB_TP
USB_RP
RPU_EP C_USB_TN
1st Stage Mux

RS_EP 2nd Stage

EP_TX_DP
Mux

EP_TX_DN RS_EP

32 EP0 (EP1)
To Digital
Core TX/RX
FIFO
EP_RX_RCV USB_EP
Serial
Interface C_USB_BP
RX/TX Engine USB_RP
Digital Core C_USB_BN
Interrupts Status 1st Stage Mux
and Control Control
EP_RX_DP
2nd Stage
Mux

EP_RX_DN

Transceiver

Figure 9-38. USB Endpoint Phy

The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and
two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– of the selected
output of the Port Multiplexer. The signals pass through the 2nd Stage Port Data Multiplexer to the port pins.
When driving, the signal is driven through a source resistance RS_EP. RS_EP is shown as a single resistor in
USB Endpoint Phy but this resistance also includes the resistance of the 2nd Stage Port Data Multiplexer defined

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in Port Data Multiplexer Requirements and Characteristics. RPU_EP is disconnected during transmit mode of
the transceiver.
When the endpoint is in receive mode, the resistance RPU_EP is connected to the D– pin of the top or bottom
port (C_USB_TN or C_USB_BN) depending on the detected orientation of the cable. The RPU_EP resistance
advertises low speed mode only.
9.3.4.8 Battery Charger (BC1.2) Detection Block
The battery charger (BC1.2) detection block integrates circuitry to detect when the connected entity on the USB
D+/D– pins is a charger. To enable the required detection mechanisms, the block integrates various voltage
sources, currents, and resistances to the Port Data Multiplexers. Figure 9-39 shows the connections of these
elements to the Port Data Multiplexers.
VLGC_HI

IDP_SRC

C_USB_TP
USB_RP
C_USB_TN
To ADC USB_EP

To ADC
C_USB_BP
USB_RP
USB_EP C_USB_BN

VDX_SRC RDM_DWN IDX_SNK

Figure 9-39. BC1.2 Detection Circuitry

9.3.4.9 BC1.2 Data Contact Detect

Data Contact Detect follows the definition in the USB BC1.2 specification. The detection scheme sources a
current IDP_SRC into the D+ pin of the USB connection. The current is sourced into either the C_USB_TP (top)
or C_USB_BP (bottom) D+ pin based on the determined cable/device orientation. A resistance RDM_DWN is
connected between the D– pin and GND. Again, this resistance is connected to either the C_USB_TN (top) or
C_USB_BN (bottom) D– pin based on the determined cable/device orientation. The middle section of Figure
9-39, the current source IDP_SRC and the pulldown resistance RDM_DWN, is activated during data contact
detection.
9.3.4.10 BC1.2 Primary and Secondary Detection
The Primary and Secondary Detection follow the USB BC1.2 specification. This detection scheme looks for a
resistance between D+ and D– lines by forcing a known voltage on the first line, forcing a current sink on the
second line and then reading the voltage on the second line using the general purpose ADC integrated in the
TPS65982. To provide complete flexibility, 12 independent switches are connected to allow firmware to force
voltage, sink current, and read voltage on any of the C_USB_TP, C_USB_TN, C_USB_BP, and C_USB_BN.
The left and right sections of Figure 9-39, the voltage source VDX_SRC and the current source IDX_SNK, are
activated during primary and secondary detection.

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9.3.5 Power Management

The TPS65982 Power Management block receives power and generates voltages to provide power to the
TPS65982 internal circuitry. These generated power rails are LDO_3V3, LDO_1V8A, and LDO_1V8D. LDO_3V3
is also a low power output to load flash memory. VOUT_3V3 is a low power output that does not power internal
circuitry that is controlled by application code and can be used to power other ICs in some applications. The
power supply path is shown in Figure 9-40.
S1
VIN_3V3 VBUS
S2
VOUT_3V3
VREF
VREF LDO EN LDO_3V3_VB_EN
Digitally To Digital Core
adjustable
trip Point

LDO_3V3

VREF
LDO_1V8D LDO EN LDO_1V8A_EN

VREF
LDO_1V8A LDO EN LDO_1V8D_EN

Figure 9-40. Power Supply Path

The TPS65982 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. In this
mode, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3 V circuitry and the 3.3 V I/Os. A second
LDO steps the voltage down from LDO_3V3 to LDO_1V8D and LDO_1V8A to power the 1.8 V core digital
circuitry and 1.8 V analog circuits. When VIN_3V3 power is unavailable and power is available on the VBUS,
the TPS65982 will be powered from VBUS. In this mode, the voltage on VBUS is stepped down through an
LDO to LDO_3V3. Switch S1 in Figure 9-40 is unidirectional and no current will flow from LDO_3V3 to VIN_3V3
or VOUT_3V3. When VIN_3V3 is unavailable, this is an indicator that there is a dead-battery or no-battery
condition.
9.3.5.1 Power-On and Supervisory Functions
A power-on-reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present. In addition to the POR and supervisory circuits for the internal supplies, a separate
programmable voltage supervisor monitors the VOUT_3V3 voltage.
9.3.5.2 Supply Switch-Over
VIN_3V3 takes precedence over VBUS, meaning that when both supply voltages are present the TPS65982
will power from VIN_3V3. Refer to The Figure 9-40 for a diagram showing the power supply path block. There
are two cases in with a power supply switch-over will occur. The first is when VBUS is present first and then
VIN_3V3 becomes available. In this case, the supply will automatically switch-over to VIN_3V3 and brown-out
prevention is verified by design. The other way a supply switch-over will occur is when both supplies are present
and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65982 occurs prompting a
re-boot.
9.3.5.3 RESETZ and MRESET
The VIN_3V3 voltage is connected to the VOUT_3V3 output by a single FET switch (S2 in Figure 9-40).

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The enabling of the switch is controlled by the core digital circuitry and the conditions are programmable.
A supervisor circuit monitors the voltage at VOUT_3V3 for an undervoltage condition and sets the external
indicator RESETZ. The RESETZ pin is active low (low when an undervoltage condition occurs). The RESETZ
output is also asserted when the MRESET input is asserted. The MRESET input is active-high by default, but
is configurable to be active low. Figure 8-1 shows the RESETZ timing with MRESET set to active high. When
VOUT_3V3 is disabled, a resistance of RPDOUT_3V3 pulls down on the pin.
9.3.6 Digital Core
Figure 9-41 shows a simplified block diagram of the digital core. This diagram shows the interface between the
digital and analog portions of the TPS65982.

HRESET
MRESET

RESETZ

GPIO0-8

BUSPOWERZ
I2C_ADDR

R_OSC OSC

DEBUG_CTL1 I2C
Debug
DEBUG_CTL2 Port

I2C_SDA1
CBL_DET USB PD
I2C to I2C_SCL1 I2C Bias CTL
System Control Port 1 Phy
and USB-PD
I2C_IRQ1Z

I2C_SDA2
I2C to I2C_SCL2 I2C Digital Core
Auxiliary Control Port 2
I2C_IRQ2Z

SPI_CLK

SPI to SPI_PICO
Flash SPI
SPI_POCI
Temp
SPI_CSZ ADC Sense
ADC
Read Signals
SWD_DATA into ADC
SWD
SWD_CLK

Thermal
Shutdown

UART_TX
UART0
UART_RX
USB EP
LSX_P2R USB EP Phy
UART1
LSX_R2P

Figure 9-41. Digital Core Block Diagram

9.3.7 USB-PD BMC Modem Interface

The USB-PD BMC modem interface is a fully USB-PD compliant Type-C interface. The modem contains the
BMC encoder/decoder, the TX/Rx FIFOs, the packet engine for construction/deconstruction of the USB-PD
packet. This module contains programmable SOP values and processes all SOP headers.

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9.3.8 System Glue Logic

The system glue logic module performs various system interface functions such as control of the system
interface for RESETZ, MRESET, and VOUT_3V3. This module supports various hardware timers for digital
control of analog circuits.
9.3.9 Power Reset Congrol Module (PRCM)
The PRCM implements all clock management, reset control, and sleep mode control.
9.3.10 Interrupt Monitor
The Interrupt Control module handles all interrupt from the external GPIO as well as interrupts from internal
analog circuits.
9.3.11 ADC Sense
The ADC Sense module is a digital interface to the SAR ADC. The ADC converts various voltages and currents
from the analog circuits. The ADC converts up to 11 channels from analog levels to digital signals. The ADC can
be programmed to convert a single sampled value.
9.3.12 UART
Two digital UARTS are provided for serial communication. The inputs to the UART are selectable by a
programmable digital crossbar multiplexer. The UART may act as pass-through between the system and the
Type-C port or may filter through the digital core. The UART_RX/TX pins are typically used to daisy chain
multiple TPS65982s in series to share application code at startup.
9.3.13 I2C Slave
Two I2C interfaces provide interface to the digital core from the system. These interfaces are master/slave
configurable and support low-speed and full-speed signaling. See the Section 9.5.2 section for more information.
9.3.14 SPI Controller
The SPI controller provides a serial interface to an external flash memory. The recommended memory is the
W25Q80DV 8 Mbit Serial Flash Memory. A memory of at least 2 Mbit is required when the TPS65982 is using
the memory in an unshared manner. A memory of at least 8 Mbit is required when the TPS65982 is using the
memory in an shared manner. See the Section 9.5.1 section for more information.
9.3.15 Single-Wire Debugger Interface
The SWD interface provides a mechanism to directly master the digital core.
9.3.16 DisplayPort HPD Timers
To enable DisplayPort HPD signaling through PD messaging, two GPIO pins (GPIO4, GPIO5) are used as the
HPD input and output. When events occur on this pins during a DisplayPort connection through the Type-C
connector (configured in firmware), hardware timers trigger and interrupt the digital core to indicated needed
PD messaging. Table 9-5 shows each I/O function when GPIO4/5 are configured in HPD mode. When HPD
is not enabled via firmware, both GPIO4 and GPIO5 remain generic GPIO and may be programmed for other
functions. Figure 9-42 and Figure 9-43.
Table 9-5. HPD GPIO Configuration
HPD (Binary) Configuration GPIO4 GPIO5
00 HPD TX Generic GPIO
01 HPD RX Generic GPIO
10 HPD TX HPD RX
11 HPD TX/RX (bidirectional) Generic GPIO

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Enter DP
Alternate
Mode

Firmware enables
HPD RX

S0: HPD Low

Wait State

HPD GPIO
HPD GPIO is High
is low

Start HPD Timer

HPD GPIO goes
low before Timer
reaches High_Debounce
S1: HPD High
Debounce State

Timer passes
High_Debounce

Generate
HPD_High
interrupt,
Stop HPD Timer

S2: HPD High

Wait State

HPD GPIO
is high HPD GPIO
is low

Start HPD Timer

HPD GPIO goes
Generate high before Timer
HPD_LOW reaches Low_Debounce
Interrupt, S3: HPD Low
Stop HPD Timer Debounce State Generate
HPD_IRQ
Interrupt
Timer passes
Low_Debounce

Timer Passes
IRQ_Limit S4: HPD IRQ HPD GPIO goes
Detect State high before Timer
reaches IRQ_Limit

Figure 9-42. HPD RX Flow

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Enter DP
Alternate
Mode

Firmware enables
HPD RX

S0: HPD Low

Wait State

HPD GPIO
HPD GPIO is High
is low

Start HPD Timer

HPD GPIO goes
low before Timer
reaches High_Debounce
S1: HPD High
Debounce State

Timer passes
High_Debounce

Generate
HPD_High
interrupt,
Stop HPD Timer

S2: HPD High

Wait State

HPD GPIO
is high HPD GPIO
is low

Start HPD Timer

HPD GPIO goes
Generate high before Timer
HPD_LOW reaches Low_Debounce
Interrupt, S3: HPD Low
Stop HPD Timer Debounce State Generate
HPD_IRQ
Interrupt
Timer passes
Low_Debounce

Timer Passes
IRQ_Limit S4: HPD IRQ HPD GPIO goes
Detect State high before Timer
reaches IRQ_Limit

Figure 9-43. HPD TX Flow Diagram

9.3.17 ADC
The TPS65982 ADC is shown in Figure 9-44. The ADC is a 10-bit successive approximation ADC. The input
to the ADC is an analog input multiplexer that supports multiple inputs from various voltages and currents in
the device. The output from the ADC is available to be read and used by application firmware. Each supply
voltage into the TPS65982 is available to be converted including the port power path inputs and outputs. All
GPIO, the C_CCn pins, the charger detection voltages are also available for conversion. To read the port power
path current sourced to VBUS, the high-voltage and low-voltage power paths are sensed and converted to
voltages to be read by the ADC. For the external FET path, the difference in the SENSEP and SENSEN voltages

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is converted to detect the current (IPP_EXT) that is sourced through this path by dividing by the RSENSE
resistance.
GPIO5
GPIO0-8
C_CC1
C_CC2 Buffers
BC_ID
VBUS
PP_HV
PP_5V0
PP_CABLE
VIN_3V3
VOUT_3V3 Voltage 10 bits
LDO_3V3 Input
Dividers SAR ADC
LDO_1V8A Mux
LDO_1V8D
SENSEP
SENSEP-SENSEN (IPP_EXT)
I2C_ADDR

Thermal
Sense
IPP_HV
IPP_5V0 I-to-V
IPP_CABLE

Figure 9-44. SAR ADC

9.3.17.1 ADC Divider Ratios

The ADC voltage inputs are each divided down to the full-scale input of 1.2 V. The ADC current sensing
elements are not divided.
Table 9-6 shows the divider ratios for each ADC input. The table also shows which inputs are auto-sequenced
in the round robin automatic readout mode. The C_CC1 and C_CC2 pin voltages each have two conversions
values. The divide-by-5 (CCn_BY5) conversion is intended for use when the C_CCn pin is configured as
VCONN output and the divide-by-2 (CCn_BY2) conversion is intended for use when C_CCn pin is configured as
the CC data pin.
Table 9-6. ADC Divider Ratios
CHANNEL # SIGNAL TYPE AUTO-SEQUENCED DIVIDER RATIO BUFFERED
0 Thermal Sense Temperature Yes N/A No
1 VBUS Voltage Yes 25 No
2 SENSEP Voltage Yes 25 No
3 IPP_EXT Current Yes N/A No
4 PP_HV Voltage Yes 25 No
5 IPP_HV Current Yes N/A No
6 PP_5V0 Voltage Yes 5 No
7 IPP_5V0 Current Yes N/A No
8 CC1_BY5 Voltage Yes 5 Yes
9 IPP_CABLE Current Yes N/A No
10 CC2_BY5 Voltage Yes 5 Yes
11 GPIO5 Voltage No 1 No
12 CC1_BY2 Voltage No 2 Yes
13 CC2_BY2 Voltage No 2 Yes
14 PP_CABLE Voltage No 5 No
15 VIN_3V3 Voltage No 3 No
16 VOUT_3V3 Voltage No 3 No
17 BC_ID Voltage No 3 Yes
18 LDO_1V8A Voltage No 2 No
19 LDO_1V8D Voltage No 2 No

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Table 9-6. ADC Divider Ratios (continued)

CHANNEL # SIGNAL TYPE AUTO-SEQUENCED DIVIDER RATIO BUFFERED
20 LDO_3V3 Voltage No 3 No
21 I2C_ADDR Voltage No 3 Yes
22 GPIO0 Voltage No 3 Yes
23 GPIO1 Voltage No 3 Yes
24 GPIO2 Voltage No 3 Yes
25 GPIO3 Voltage No 3 Yes
26 GPIO4 Voltage No 3 Yes
27 GPIO5 Voltage No 3 Yes
28 GPIO6 Voltage No 3 Yes
29 GPIO7 Voltage No 3 Yes
30 GPIO8 Voltage No 3 Yes
31 BUSPOWERZ Voltage No 3 Yes

9.3.17.2 ADC Operating Modes

The ADC is configured into one of three modes: single channel readout, round robin automatic readout and one
time automatic readout.
9.3.17.3 Single Channel Readout
In Single Channel Readout mode, the ADC reads a single channel only. Once the channel is selected by
firmware, a conversion takes place followed by an interrupt back to the digital core. Figure 8-2 shows the timing
diagram for a conversion starting with an ADC enable. When the ADC is disabled and then enabled, there is
an enable time T_ADC_EN (programmable) before sampling occurs. Sampling of the input signal then occurs
for time T_SAMPLE (programmable) and the conversion process takes time T_CONVERT (12 clock cycles).
After time T_CONVERT, the output data is available for read and an Interrupt is sent to the digital core for time
T_INTA (2 clock cycles).
In Single Channel Readout mode, the ADC can be configured to continuously convert that channel. Figure
8-3 shows the ADC repeated conversion process. In this case, once the interrupt time has passed after a
conversion, a new sample and conversion occurs.
9.3.17.4 Round Robin Automatic Readout
When this mode is enabled, the ADC state machine will read from channel 0 to channel 11 and place the
converted data into registers. The host interface can request to read from the registers at any time. During
Round Robin Automatic Readout, the channel averaging must be set to 1 sample.
When the TPS65982 is running a Round Robin Readout, it will take approximately 696 μs (11 channels × 63.33
μs conversion) to fully convert all channels. Since the conversion is continuous, when a channel is converted, it
will overwrite the previous result. Therefore, when all channels are read, any given value may be 649 μs out of
sync with any other value.
9.3.17.5 One Time Automatic Readout
The One Time Automatic Readout mode is identical to the Round Robin Automatic Readout except the
conversion process halts after the final channel is converted. Once all 11 channels are converted, an interrupt
occurs to the digital core.
9.3.18 I/O Buffers
Table 9-7 lists the I/O buffer types and descriptions. Table 9-8 lists the pin to I/O buffer mapping for cross-
referencing a pin’s particular I/O structure. The following sections show a simplified version of the architecture of
each I/O buffer type.

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Table 9-7. I/O Buffer Type Description

BUFFER TYPE DESCRIPTION
IOBUF_GPIOHSSWD General Purpose High-Speed I/O
IOBUF_GPIOHSSPI General Purpose High-Speed I/O
IOBUF_GPIOLS General Purpose Low-Speed I/O
IOBUF_GPIOLSI2C General Purpose Low-Speed I/O with I2C deglitch time
IOBUF_I2C I2C Compliant Clock/Data Buffers
IOBUF_OD Open-Drain Output
IOBUF_UTX Push-Pull output buffer for UART
IOBUF_URX Input buffer for UART
IOBUF_PORT Input buffer between 1st/2nd stage Port Data Mux

Table 9-8. Pin to I/O Buffer Mapping

I/O GROUP/PIN BUFFER TYPE SUPPLY CONNECTION (DEFAULT FIRST)
DEBUG1/2/3/4 IOBUF_GPIOLS LDO_3V3, VDDIO
DEBUG_CTL1/2 IOBUF_GPIOLSI2C LDO_3V3, VDDIO
BUSPOWERZ IOBUF_GPIOLS LDO_3V3, VDDIO
GPIO0-8 IOBUF_GPIOLS LDO_3V3, VDDIO
I2C_IRQ1/2Z IOBUF_OD LDO_3V3, VDDIO
I2C_SDA1/2/SCL/1/2 IOBUF_I2C LDO_3V3, VDDIO
LSX_P2R IOBUF_UTX LDO_3V3, VDDIO
LSX_R2P IOBUF_URX LDO_3V3, VDDIO
MRESET IOBUF_GPIOLS LDO_3V3, VDDIO
RESETZ IOBUF_GPIOLS LDO_3V3, VDDIO
UART_RX IOBUF_URX LDO_3V3, VDDIO
UART_TX IOBUF_UTX LDO_3V3, VDDIO
PORT_INT IOBUF_PORT LDO_3V3
SPI_PICO/POCI/CLK/CSZ IOBUF_GPIOHSSPI LDO_3V3
SWD_CLK/DATA IOBUF_GPIOHSSWD LDO_3V3

9.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C

Figure 9-45 shows the GPIO I/O buffer for all GPIOn pins listed GPIO0-GPIO17 in Pin Configuration and
Functions. GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control
other ICs, interrupt a host processor, or receive input from another IC. This buffer is configurable to be a
push-pull output, a weak push-pull, or open drain output. When configured as an input, the signal can be a
deglitched digital input or an analog input to the ADC. The push-pull output is a simple CMOS output with
independent pulldown control allowing open-drain connections. The weak push-pull is also a CMOS output,
but with GPIO_RPU resistance in series with the drain. The supply voltage to this buffer is configurable to be
LDO_3V3 by default or VDDIO. For simplicity, the connection to VDDIO is not shown in Figure 9-45, but the
connection to VDDIO is fail-safe and a diode will not be present from GPIOn to VDDIO in this configuration. The
pullup and pulldown output drivers are independently controlled from the input and are enabled or disabled via
application code in the digital core.

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LDO_3V3
GPIO_OD_EN
GPIO_OE

GPIO_DO

GPIO_PU_EN

GPIO_RPU

GPIO_RPD

GPIO_PD_EN

20 ns
GPIO GPIO_DI
Deglitch

GPIO_AI_EN

To ADC

Figure 9-45. IOBUF_GPIOLS (General GPIO) I/O

Figure 9-46 shows the IOBUF_GPIOLSI2C that is identical to IOBUF_GPIOLS with an extended deglitch time.
LDO_3V3
GPIO_OD_EN
GPIO_OE

GPIO_DO

GPIO_PU_EN

GPIO_RPU

GPIO_RPD

GPIO_PD_EN

50 ns
DEBUG_CTL1/2 GPIO_DI
Deglitch

GPIO_AI_EN

To ADC

Figure 9-46. IOBUF_GPIOLSI2C (General GPIO) I/O with I2C De-glitch

9.3.18.2 IOBUF_OD
The open-drain output driver is shown in Figure 9-47 and is the same push-pull CMOS output driver as the GPIO
buffer. The output has independent pulldown control allowing open-drain connections.
OD
OD_DO

Figure 9-47. IOBUF_OD Output Buffer

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9.3.18.3 IOBUF_UTX
The push-pull output driver is shown in Figure 9-48. The output buffer has a UARTTX_RO source resistance.
The supply voltage to the system side buffer is configurable to be LDO_3V3 by default or VDDIO. This is not
shown in Figure 9-48. The supply voltage to the port side buffers remains LDO_3V3.

UARTTX_RO
CMOS
UART_TX UART_TXout
Output

Figure 9-48. IOBUF_UTX Output Buffer

9.3.18.4 IOBUF_URX
The input buffer is shown in Figure 9-49. The supply voltage to the system side buffer is configurable to be
LDO_3V3 by default or VDDIO. This is not shown in Figure 9-49. The supply voltage to the port side buffers
remains LDO_3V3.

UART_RX UART_RXin

Figure 9-49. IOBUF_URX Input

9.3.18.5 IOBUF_PORT
The input buffer is shown in Figure 9-50. This input buffer is connected to the intermediate nodes between
the 1st stage switch and the 2nd stage switch for each port output (C_SBU1/2, C_USB_TP/N, C_USB_BN/P).
The input buffer is enabled via firmware when monitoring digital signals and disabled when an analog signal
is desired. See theFigure 9-36 section for more detail on the pullup and pulldown resistors of the intermediate
node.

PORT_intx PORT_DETx

EN

Figure 9-50. IOBUF_PORT Input Buffer

9.3.18.6 IOBUF_I2C
The I2C I/O driver is shown in Figure 9-51. This I/O consists of an open-drain output and an input comparator
with deglitching. The supply voltage to this buffer is configurable to be LDO_3V3 by default or VDDIO. This is not
shown in Figure 9-51. Parameters for the I2C clock and data I/Os are found in Section 7.20.

50 ns
I2C_DI
Deglitch

I2C_IRQnZ
I2C_DO

Figure 9-51. IOBUF_I2C I/O

9.3.18.7 IOBUF_GPIOHSPI
Figure 9-52 shows the I/O buffers for the SPI interface.

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SPI_x SPIin

CMOS
SPIout
Output

SPI_OE

Figure 9-52. IOBUF_GPIOHSSPI

9.3.18.8 IOBUF_GPIOHSSWD
Figure 9-53 shows the I/O buffers for the SWD interface. The CLK input path is a comparator with a pullup
SWD_RPU on the pin. The data I/O consists of an identical input structure as the CLK input but with a tri-state
CMOS output driver.
LDO_3V3

SWD_RPU

SWD_CLK SWDCLKin

LDO_3V3

SWD_RPU

SWD_DATA SWDIOin

CMOS
SWDIOout
Output

SWD_OE

Figure 9-53. IOBUF_GPIOHSSWD

9.3.19 Thermal Shutdown

The TPS65982 has both a central thermal shutdown to the chip and a local thermal shutdown for the power path
block. The central thermal shutdown monitors the temperature of the center of the die and disables all functions
except for supervisory circuitry and halts digital core when die temperature goes above a rising temperature of
TSD_MAIN. The temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back
below this value, the device resumes normal operation. The power path block has an local thermal shutdown
circuit to detect an overtemperature condition because of overcurrent and quickly turn off the power switches.
The power path thermal shutdown values are TSD_PWR and TSDH_PWR. The output of the thermal shutdown
circuit is deglitched by TSD_DG before triggering. The thermal shutdown circuits interrupt to the digital core.
9.3.20 Oscillators
The TPS65982 has two independent oscillators for generating internal clock domains. A 48-MHz oscillator
generates clocks for the core during normal operation and clocks for the USB 2.0 endpoint physical layer. An
external resistance is placed on the R_OSC pin to set the oscillator accuracy. A 100-kHz oscillator generates
clocks for various timers and clocking the core during low-power states.

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9.4 Device Functional Modes

9.4.1 Boot Code
The TPS65982 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal.
The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core
and the boot code starts executing. Figure 9-54 provides the TPS65982 boot code sequence.
The TPS65982 boot code is loaded from OTP on POR, and begins initializing TPS65982 settings. This
initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values
to settle, and configuring the device I2C addresses.
The unique I2C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor
configuration on the I2C_ADDR pin.
Once initial device configuration is complete the boot code determines if the TPS65982 is booting under dead
battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65982 is booting under
dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS
power to the system.

VIN_3V3 or VBUS
Application

Initialize

Configure I2C

Dead Battery
Check

SPI_POCI High SPI_POCI Low

Load Appcode

Load from SPI Download from

Flash UART

Figure 9-54. Flow Diagram for Boot Code Sequence

9.4.2 Initialization
During initialization the TPS65982 enables device internal hardware and loads default configurations. The
48-MHz clock is enabled and the TPS65982 persistence counters begin monitoring VBUS and VIN_3V3. These
counters ensure the supply powering the TPS65982 is stable before continuing the initialization process. The

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initialization concludes by enabling the thermal monitoring blocks and thermal shutdown protection, along with
the ADC, CRC, GPIO and NVIC blocks.
9.4.3 I2C Configuration
The TPS65982 features dual I2C busses with configurable addresses. The I2C addresses are determined
according to the flow depicted in Figure 9-55. The address is configured by reading device GPIO states at boot
(refer to the I2C Pin Address Setting section for details). Once the I2C addresses are established the TPS65982
enables a limited host interface to allow for communication with the device during the boot process.
Initialization
Complete

Read state of
DEBUG_CTL1
DEBUG_CTL2
I2C_ADDR

Configure I2C
Address

Initialize Host
Interface

Figure 9-55. I2C Address Configuration

9.4.4 Dead-Battery Condition

After I2C configuration concludes the TPS65982 checks VIN_3V3 to determine the cause of device boot. If the
device is booting from a source other than VIN_3V3, the dead battery flow is followed to allow for the rest of the
system to receive power. The state of the BUSPOWERZ pin is read to determine power path configuration for
dead battery operation. After the power path is configured, the TPS65982 will continue through the boot process.
Figure 9-56 shows the full dead battery process.

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I2C Initiated

Yes
VIN_3V3 Valid

No

>2.4 V Check
BUSPOWERZ

≤2.4 V

No
VBUS Present

Yes

Configure for
VBUS Power

Check ≤0.8 V
BUSPOWERZ

> 0.8 V

Enable PP_HV as Enable PP_EXT as

SINK SINK

Load App Code

Figure 9-56. Dead-Battery Condition Flow Diagram

9.4.5 Application Code

The TPS65982 application code is stored in an external flash memory. The flash memory used for storing the
TPS65982 application code may be shared with other devices in the system. The flash memory organization
shown in Figure 9-57 supports the sharing of the flash as well as the TPS65982 using the flash without sharing.
The flash is divided into two separate regions, the Low Region and the High Region. The size of this region is
flexible and only depends on the size of the flash memory used. The two regions are used to allow updating
the application code in the memory without over-writing the previous code. This ensures that the new updated
code is valid before switching to the new code. For example, if a power loss occurred while writing new code, the
original code is still in place and used at the next boot.

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0x000000
Region Pointer (RPTR)
0x000004
Low Header
4 kB
0x000FFC
App Code Offset (AOFF)
0x001000
Region Pointer (RPTR)
0x001004
High Header
4 kB
0x001FFC
App Code Offset (AOFF)
0x002000

RPTR+AOFF

ID, Header, &

Configuration Data
(max. 4 kB)

RPTR+AOFF+CSIZE

Application Code
(max. 64 kB)

Figure 9-57. Flash Memory Organization

There are two 4 kB header blocks starting at address 0x000000h. The Low Header 4 kB block is at address
0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR)
that holds the address of the physical location in memory where the low region application code resides. Each
also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the
TPS65982 application code resides. The TPS65982 firmware physical location in memory is RPTR + AOFF. The
first sections of the TPS65982 application code contain device configuration settings where CSIZE is maximum
of 4 kB. This configuration determines the devices default behavior after power-up and can be customized using
the TPS65982 Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading
and determining whether a region is valid and contains good application code.
9.4.6 Flash Memory Read
The TPS65982 first attempts to load application code from the low region of the attached flash memory. If any
part of the read process yields invalid data, the TPS65982 will abort the low region read and attempt to read
from the high region. If both regions contain invalid data the device carries out the Invalid Memory flow. Figure
9-58 shows the flash memory read flow.

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Enter Flash Read

Read Low Header Read High Header

Region Pointer Region Pointer
and Application and Application
Code Offset Code Offset

Invalid
Config
Read Config Read Config
Area Area Invalid
Config

Valid Config

Invalid App
Code
Read App Read App
Code and Code and
Check CRC Check CRC
Valid App
Valid App Code
Code Invalid App
Code

Reset Core and Memory Invalid

Run App Code

Figure 9-58. Flash Read Flow

9.4.7 Invalid Flash Memory

If the flash memory read fails because of invalid data, the TPS65982 carries out the memory invalid flow and
presents the SWD interface on the USB Type-C SBU pins.
Figure 9-59 shows the invalid memory process.

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Memory Invalid

Enable VOUT_3V3
Release RESETZ

VBUS Invalid

Check VBUS

VBUS Good

Present
Rp/Rp

Rd/Rd Not
Attached
Check for
Rd/Rd

Rd/Rd Attached

Present SWD
Monitor VBUS

Figure 9-59. Memory Invalid Flow

9.4.8 UART Download

the secondary TPS65982 downloads the needed application code from the primary TPS65982 via UART. Figure
9-60 shows the UART download process.
Currently the TPS65982 firmware only supports 2 device (1 primary + 1 secondary) systems.

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SPI_POCI
App Code Loaded
Low

Send “Request Receive “Request

Data” Packet Data” Packet

Receive “Send
Block map Yes
Data” Packet &
complete
Save Data

No

Receive “Send Send “Send Data”

CRC” packet packet

No Saved Data Send “Send CRC”

valid Packet

Yes

Boot Fail Run App Code

Secondary Primary

Figure 9-60. UART Download Process

9.5 Programming
9.5.1 SPI Controller Interface
The TPS65982 loads flash memory during the Boot Code sequence. The SPI Controller electrical characteristics
are defined in SPI Controller Characteristics and timing characteristics are defined in Figure 8-5. The TPS65982
is designed to power the flash from LDO_3V3 to support dead-battery or no-battery conditions, and therefore
pullup resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support 12 MHz
SPI clock frequency. The size of the flash must be at least 1 Mbyte (equivalent to 8 Mbit) to hold the standard
application code outlined in Application Code. The SPI Controller of the TPS65982 supports SPI Mode 0. For
Mode 0, data delay is defined such that data is output on the same cycle as chip select (SPI_CSZ pin) becomes
active. The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_POCI and
SPI_PICO pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising
edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred
the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 kB. The
W25Q80 flash memory IC is recommended. Refer to TPS65982 I2C Host Interface Specification for instructions
for interacting with the attached flash memory over SPI using the host interface of the TPS65982.
9.5.2 I2C Slave Interface
The TPS65982 has three I2C interface ports. I2C Port 1 is comprised of the I2C_SDA1, I2C_SCL1, and
I2C_IRQ1Z pins. I2C Port 2 is comprised of the I2C_SDA2, I2C_SCL2, and I2C_IRQ2Z pins. These interfaces
provide general status information about the TPS65982, as well as the ability to control the TPS65982
behavior, as well as providing information about connections detected at the USB-C receptacle and supporting
communications to and from a connected device, cable supporting BMC USB-PD, or both. The third port is

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comprised of the DEBUG_CTL1 and DEBUG_CTL2 pins. This third port is a firmware emulated I2C master. The
pins are generic GPIO and do not contain any dedicated hardware for I2C such as detecting starts, stops, acks,
or other protocol normally associated with I2C. This third port is always a master and has no interrupt. This
port is intended to master another device that has simple control based on mode and multiplexer orientation.
DEBUG_CTL1 is the serial clock and DEBUG_CTL2 is serial data.
The first two ports can be a master or a slave, but the default behavior is to be a slave. Port 1 and Port 2 are
interchangeable. Each port operates the same way and has the same access in and out of the core. An interrupt
mask is set for each that determines what events are interrupted on that given port.
9.5.2.1 I2C Interface Description
The TPS65982 support Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the serial
clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data
transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high
initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred
during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period
as changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 9-61 shows the start and stop conditions of the transfer. Figure 9-62 shows the SDA and SCL signals for
transferring a bit. Figure 9-63 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

SDA

SCL

S P
Start Condition Stop Condition

Figure 9-61. I2C Definition of Start and Stop Conditions

SDA

SCL

Data Line Change

Figure 9-62. I2C Bit Transfer

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Data Output
by Transmitter

Nack
Data Output
by Receiver

SCL From Ack

Master
1 2 8 9
S
Start Clock Pulse for
Condition Acknowledgement

Figure 9-63. I2C Acknowledgment

9.5.2.2 I2C Clock Stretching

The TPS65982 features clock stretching for the I2C protocol. The TPS65982 slave I2C port may hold the clock
line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The
master communicating with the slave must not finish the transmission of the current bit and must wait until the
clock line actually goes high. When the slave is clock stretching, the clock line will remain low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100 kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
9.5.2.3 I2C Address Setting
The boot code sets the hardware configurable unique I2C address of the TPS65982 before the port is enabled
to respond to I2C transactions. The unique I2C address is determined by a combination of the digital level on the
DEBUG_CTL1/DEBUG_CTL2 pins (two bits) and the analog level set by the analog I2C_ADDR strap pin (three
bits) as shown in Table 9-9.
Table 9-9. I2C Default Unique Address
Default I2C Unique Address for Each Port
Port Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
I2C Port 1(1) 0 1 1 1 I2C_ADDR_DECODE[2:0] R/ W
I2C Port 2 0 1 DEBUG_CTL2 DEBUG_CTL1 I2C_ADDR_DECODE[2:0] R/ W

(1) I2C Port 1 ignores the hardware setting of the DEBUG_CTL1 and DEBUG_CTL2 pins and automatically sets these bits to 1 in Bit 4
and Bit 5 of the address

9.5.2.4 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65982.
The I 2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 9-64 and
Figure 9-65 show the write and read protocol for the I2C slave interface, and a key is included in Figure 9-66 to
explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated
here in part.
1 7 1 1 8 1 8 1 8 1

S Unique Address Wr A Register Number A Byte Count = N A Data Byte 1 A

8 1 8 1

Data Byte 2 A Data Byte N A P

Figure 9-64. I2C Unique Address Write Register Protocol

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1 7 1 1 8 1 1 7 1 1 8 1

S Unique Address Wr A Register Number A Sr Unique Address Rd A Byte Count = N A

8 1 8 1 8 1

Data Byte 1 A Data Byte 2 A Data Byte N A P

Figure 9-65. I2C Unique Address Read Register Protocol

1 7 1 1 8 1 1

S Slave Address Wr A Data Byte A P

x x
S Start Condition

SR Repeated Start Condition

Rd Read (bit value of 1)

Wr Write (bit value of 0)

x Field is required to have the value x

Acknowledge (this bit position may be 0 for an ACK or
A
1 for a NACK)
P Stop Condition

Master-to-Slave

Slave-to-Master

Continuation of protocol

Figure 9-66. I2C Read/Write Protocol Key

9.5.2.5 I2C Pin Address Setting

To enable the setting of multiple I2C addresses using a single TPS65982 pin, a resistance is placed externally
on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 9-67
shows the decoding. DEBUG_CTL1/2 are checked at the same time for the DC condition on this pin (high or
low) for setting other bits of the address described previously. Note, DEBUG_CTL1/2 are GPIO and the address
decoding is done by firmware in the digital core.

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5 µA

I2C_ADDR ADC

R_I2C

To Address
Decoder

DEBUG_CTL1

Tristate

DEBUG_CTL2

Debug Data

To Address
Decoder

Figure 9-67. I2C Address Decode

Table 9-10 lists the external resistance needed to set bits [3:1] of the I2C Unique Address. For the Primary
TPS65982 (UART Master), the I2C_ADDR pin is grounded and this TPS65982 is connected to the SPI Flash. In
a two Type-C port system sharing one SPI Flash, I2C_ADDR is left as an open-circuit (UART Slave 1) and this
TPS65982 is referred to as the Secondary.
Table 9-10. I2C Address Resistance
TPS65982 EXTERNAL I2C UNIQUE
DEVICE RESISTANCE (1%) ADDRESS [3:1]
SPI Owner, UART
0Ω 0x00
Master 0 (Primary)
UART Slave 7 38.3 kΩ 0x01
UART Slave 6 84.5 kΩ 0x02
UART Slave 5 140 kΩ 0x03
UART Slave 4 205 kΩ 0x04
UART Slave 3 280 kΩ 0x05
UART Slave 2 374 kΩ 0x06
UART Slave 1
Open 0x07
(Secondary)

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

The typical applications of the TPS65982 include chargers, notebooks, tablets, ultrabooks, docking systems,
dongles, and any other product supporting USB Type-C, USB-PD as a power source, power sink, data DFP,
data UFP, or dual-role port (DRP), or supporting both USB Type-C andUSB-PD. The typical applications outlined
in the following sections detail a Fully-Featured USB Type-C and PD Charger Application and a Dual-Port
Notebook Application Supporting USB PD Charging and DisplayPort.
10.2 Typical Applications
10.2.1 Fully-Featured USB Type-C and PD Charger Application
The TPS65982 controls three separate power paths making it a flexible option for Type C PD charger
applications. In addition, the TPS65982 supports VCONN power for e-marked cables which are required for
applications which require greater than 3 A of current on VBUS. Figure 10-1 below shows the high level block
diagram of a Type C PD charger that is capable of supporting 5 V at 3 A, 12 V at 3 A, and 20 V at 5 A. The 5
V and 12 V outputs are supported by the TPS65982 internal FETs and the 20-V output uses the external FET
path controlled by the TPS65982 NFET drive. This Type-C PD charger uses a receptacle for flexibility on cable
choice.

Supply 20 V, 5 A
HV_GATE1

SENSEN
HV_GATE2

SENSEP

Type C
Receptacle

VBUS VBUS

PP_HV Supply 12 V, 3 A
CC1/2 CC1/2
TPS65982
(Charger Application) PP_5V0 Supply 5 V, 3.5 A
USB2.0 USB2.0 PP_CABLE

SBU1/2 VIN_3V3 Supply 3.3 V, 50 mA

SSTX/RX

Copyright © 2016, Texas Instruments Incorporated

Figure 10-1. Type-C and PD Charger Application

10.2.1.1 Design Requirements

For a USB Type-C and PD Charger application, Table 10-1 lists the input voltage requirements and expected
current capabilities.
Table 10-1. Charging Application Design Parameters
DESIGN PARAMETER EXAMPLE VALUE DIRECTION OF CURRENT
PP_5V0 Input Voltage and Current 5 V, 3 A Sourcing to VBUS
Capabilities

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Table 10-1. Charging Application Design Parameters (continued)

DESIGN PARAMETER EXAMPLE VALUE DIRECTION OF CURRENT
PP_CABLE Input Voltage and Current 5 V, 500 mA Sourcing to VCONN
Capabilities
PP_HV Input Voltage and Current 12 V, 3 A Sourcing to VBUS
Capabilities
EXT FET Path Input Voltage and Current 20 V, 5 A Sourcing to VBUS
Capabilities
VIN_3V3 Voltage and Current Requirements 2.85 - 3.45 V, 50 mA Internal TPS65982 Circuitry

10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)

The external FET path allows for the maximum PD power profile (20 V at 5 A) and design considerations must
be taken into account for choosing the appropriate components to optimize performance.
Although a Type C PD charger will be providing power there could be a condition where a non-compliant device
can be connected to the charger and force voltage back into the charger. To protect against this the external FET
path detects reverse current in both directions of the current path. The TPS65982 uses two back-to-back NFETs
to protect both sides of the system. Another design consideration is to rate the external NFETs above the Type C
and PD specification maximum which is 20 V. In this specific design example, 30-V NFETs are used that have an
average RDS,ON of 5 mΩ to reduce losses.
The TPS65982 supports either a 10-mΩ or a 5-mΩ sense resistor on the external FET path. This RSENSE
resistor is used for current limiting and is used for the reverse current protection of the power path. A 5 mΩ
sense resistor is used in the design to minimize losses and I-R voltage drop. Recommended NFET Capabilities
summarizes the recommended parameters for the external NFET used. The total voltage drop seen across
RSENSE and the external NFET could be determined by Equation 5 below. It is important to consider the drop in
the entire system and regulate accordingly to ensure that the output voltage is within its specification. Equation 6
will calculate the power lost through the external FET path.
Table 10-2. Recommended NFET Capabilities
Voltage Rating Current Rating RDS,ON
30 V (minimum) 10 A (peak current) < 10 mΩ

Voltage Drop = DC Current × (RSENSE + NFET1 RDS,ON + NFET2 RDS,ON) (5)

Power Loss = Voltage Drop × DC Current (6)

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 TPS65982 External Flash
The external flash contains the TPS65982 application firmware and must be sized to 256kB minimum when the
flash is not shared with another IC, but a recommended minimum of 1 MB is needed when the flash memory of
the TPS65982 is shared with another IC. This size will allow for pointers and two copies of the firmware image to
reside on the flash along with the needed headers. The flash used is the W25Q80 which is a 3.3-V flash and is
powered from the LDO_3V3 output from the TPS65982.
10.2.1.2.2 I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors
I2C_ADDR, DEBUG_CTL1/2 pins must be tied to GND through a 0-Ω resistor tied to GND directly if needed
to reduce solution size. Pullups on the I2C_CLK, I2C_SDA, and I2C_IRQ are used for debugging purposes.
In most simple charger designs, I2C communication may not be needed. A 3.83-kΩ pullup resistor from
SWD_DATA to LDO_3V3 and a 100-kΩ pulldown resistor from SWD_CLK to GND must also be used for
debugging purposes.
10.2.1.2.3 Oscillator (R_OSC) Resistor
A 15-kΩ 0.1% resistor is needed for key PD BMC communication timing and the USB2.0 endpoint. A 1% 15-kΩ
resistor is not recommended to be used because the internal oscillators will not be controlled well enough by this
loose resistor tolerance.

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10.2.1.2.4 VBUS Capacitor and Ferrite Bead

A 1-µF ceramic capacitor is placed close to the TPS65982 VBUS pins. A 6 A ferrite bead is used in this design
along with four high frequency noise 10-nF capacitors placed close to the Type-C connector to minimize noise.
10.2.1.2.5 Soft Start (SS) Capacitor
The recommended 0.22 µF is placed on the TPS65982 SS pin.
10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
Although the charger is configured to be only a power source, SBU1/2, USB Top and Bottom must be routed to
the Type C connector. This allows for debugging or for any specific alternate modes for power to be configured if
needed. ESD protection is used in the design on all of these nets as good design practice.
10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
The design assumes that a DC-DC converter is connected to the paths where there is significant output
capacitance on the DC-DCs to provide the additional capacitance for load steps. TI recommends to for the
DC-DC converters for to be capable of supporting current spikes which can occur with certain PD configurations.
The PP_EXT path is capable of supporting up to 5 A which will require additional capacitance to support system
loading by the device connected to the charger. A ceramic 10-µF (X7R/X5R) capacitor is used in this design.
This capacitor must at least have a 25 V rating and it is recommended to have 30 V or greater rated capacitor.
The PP_HV path is capable of supporting up to 3 A which will require additional capacitance to support system
loading by the device connected to the charger. A ceramic 10-µF (X7R/X5R) capacitor coupled with a 0.1 µF
high frequency capacitor is placed close to the TPS65982.
The PP_5V0 and PP_CABLE supplies are connected together therefore a ceramic 22-µF (X7R/X5R) capacitor
coupled with a 0.1-µF high-frequency capacitor is placed close to the TPS65982. The PP_5V0 path can support
3 A and the PP_CABLE path supports 600 mA for active Type C PD cables.
The design assumes that a DC-DC converter is connected to the paths where there is significant output
capacitance on the DC-DCs to provide the additional capacitance. It is recommended to for the DC-DC
converters to be capable of supporting current spikes which can occur with certain PD configurations.
10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
This charger application is designed to only be a source of power and does not support Dead Battery. RPD_G1
and RPD_G2 must be tied to GND and not connected to the CC1 and CC2 respectively. For CC1 and CC2 lines,
they require a 220 pF capacitor to GND.
10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
For all capacitances it is important to factor in DC voltage de-rating of ceramic capacitors. Generally the effective
capacitance is halved with voltage applied.
VIN_3V3 is connected to VDDIO which ensures that the I/Os of the TPS65982’s will be configured to 3.3 V. A
1 µF capacitor is used and is shared between VDDIO and VIN_3V3. LDO_1V8D, LDO_1V8A, and LDO_BMC
each have their own 1 µF capacitor. In this design LDO_3V3 powers the TPS65982’s external flash and various
pull ups. A 10 µF capacitor was chosen to support these additional connections. VOUT_3V3 is not used in this
design and capacitor is not needed.

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10.2.1.3 Application Curve

1000
900
800

PP_EXT Power Loss (mW)

700
600
500
400
300
200
100
0
3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5
DC Current (A) D012

Figure 10-2. PP_EXT Power Loss (RNFETS + RSENSE = 30 mΩ)

10.2.2 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort

The TPS65982 features support for DisplayPort over Type-C alternate mode and manages sinking and sourcing
of power in Power Delivery. The block diagram, shown in Figure 10-3, shows a two port system that is capable
of charging from either Type C port over PD, DisplayPort Alternate Mode, and delivering Battery Power to a
bus-powered device. With the DisplayPort support, the TPS65982 controls an external SuperSpeed multiplexer,
HD3SS460, to route the appropriate super-speed signals to the Type-C connector. The HD3SS460 is controlled
through GPIOs configured by the TPS65982 application code and the HD3SS460 is designed to meet the timing
requirements defined by the DisplayPort over Type-C specification. A system controller is also necessary to
handle some of the dynamic aspects of Power Delivery such as reducing power capabilities when system battery
power is low. Audio accessory device is supported by the design as well. Although USB_RP_P and USB_RP_N
are not shown in the block diagram, they must be connected to the system-side IC that will receive and send
USB2.0 high-speed data through the integrated multiplexer of the TPS65982.

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DC Barrel Jack

PFET Control

HV_GATE1

SENSEN
HV_GATE2

SENSEP
Type C DC Barrel Jack Sense
Receptacle
VBUS VBUS

CC1/2 CC1/2 PP_HV Battery Voltage

PP_5V0 Supply 5 V, 3.5 A

USB2.0 USB2.0 TPS65982 PP_CABLE
(Notebook Application)
SBU1/2 SBU1/2 VIN_3V3 Supply 3.3 V, 50 mA

2
I C
DEBUG_2
SSTX/RX GPIO_0

GPIO_3
AUX_N/P

VIN BAT Battery Voltage

EN
AMSEL
POL

+
BQ Battery
Charger
HD3SS460 I2C
(SS MUX)
ML0 – ML3 DP Source
SSTX/RX
USB3 SSTX/RX USB3 Source
HV_GATE1

SENSEN
HV_GATE2

SENSEP

Type C
Receptacle I2C Master
VBUS VBUS
System
PP_HV Battery Voltage Controller
CC1/2 CC1/2
PP_5V0 Supply 5 V, 3.5 A
TPS65982
USB2.0 USB2.0 PP_CABLE
(Notebook Application)
SBU1/2 SBU1/2 VIN_3V3 Supply 3.3 V, 50 mA

I2C
DEBUG_2

SSTX/RX
GPIO_0

GPIO_3

AUX_N/P
EN
AMSEL
POL

HD3SS460
(SS MUX)
ML0 – ML3 DP Source
SSTX/RX
USB3 SSTX/RX USB3 Source

Copyright © 2016, Texas Instruments Incorporated

Figure 10-3. Dual-Port Notebook Application

10.2.2.1 Design Requirements

For a dual-port notebook application, Table 10-3 lists the input voltage requirements and expected current
capabilities.

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Table 10-3. Dual-Port Notebook Application Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE DIRECTION OF CURRENT
PP_5V0 Input Voltage and Current 5 V, 3 A Sourcing to VBUS
Capabilities
PP_CABLE Input Voltage and Current 5 V, 500 mA Sourcing to VCONN
Capabilities
PP_HV Input Voltage and Current 10-13 V, 3 A Sourcing to VBUS (directly from Battery)
Capabilities
EXT FET Path Voltage and Current 20 V, 3 A Sourcing to VBUS or Sinking from VBUS
Capabilities
VIN_3V3 Voltage and Current Requirements 2.85-3.45 V, 50 mA Internal TPS65982 Circuitry

10.2.2.1.1 Source Power Delivery Profiles for Type-C Ports

Table 10-4 lists the summary of the source PD profiles that are supported for this specific design. PDO 1 and
2 will always be present in the system and will be able to be negotiated without any other system interaction.
When DC barrel Jack voltage is sensed PDO 3 will become available for power delivery negotiation. The
external sense resistor, RSENSE, is configured to only measure the current being sourced by the system. When
operating as a sink of power the input current cannot be measured in this configuration.
Table 10-4. Source USB PD Profiles
EXTERNALLY
PDO POD TYPE VOLTAGE CURRENT OR POWER
DEPENDENT
PDO1 Fixed Supply 5V 3A No
PDO2 Battery Power 10 V - 13 V 30 W No
PDO3 Fixed Supply 20 V 3A Yes

10.2.2.1.2 Sink Power Delivery Profile for Type-C Ports

The two Type-C ports used in this design support Power Delivery and enable charging over a Type-C
connection. Table 10-5 shows the sink profile supported by both of the ports. The reverse current blocking
of the device allows both of the Type-C ports to negotiate a power contract, but it is good system practice for the
System Controller to change the sink profile when a power contract is established. When the DC barrel jack is
connected the TPS65982 is renegotiate the a PD contract to no longer charge of Type C and have the DC Barrel
Jack take precedence when connected.
Table 10-5. Sink USB PD Profile
EXTERNALLY
RDO RDO TYPE VOLTAGE
DEPENDENT
Fixed Supply 20 V 3A Yes

10.2.2.2 Detailed Design Procedure

The same passive components used in the Fully-Featured USB Type-C and PD Charger Application are also
applicable in this design to support all of the features of the TPS65982. Additional design information is provided
below to explain the connections between the TPS65982 and the system controller and the TPS65982 and the
HD3SS460 SuperSpeed multiplexer.
10.2.2.2.1 TPS65982 and System Controller Interaction
The TPS65982 features two I2C slave ports that can be used simultaneously, where the system controller has
the ability to write to either of the I2C slave ports. Each I2C port has an I2C interrupt that will inform the system
controller that a change has happened in the system. This allows the system controller to dynamically budget
power and reconfigures a port’s capabilities dependent on current state of the system. For example, if a battery
power contract is established and the system is running low on battery power the system controller could notify
the TPS65982 to re-negotiate a power contract. The system controller is also used for updating the TPS65982
firmware over I2C, where the Operating System loads the Firmware update to the system controller and then the
system controller updates the firmware stored in the SPI Flash memory via I2C writes to the TPS65982.

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10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration

The two Type-C ports in this design support DisplayPort simultaneously on both ports. When a system is not
capable of supporting video on both ports the system controller will disable DisplayPort on the second Type-C
port through I2C. Table 10-6 lists the DisplayPort configurations supported in the system. Table 10-7 lists the
summary of the TPS65982 GPIO signals control for the HD3SS460. Although the HD3SS460 is able to multiplex
the required AUX_N/P signals to the SBU_1/2 pins, they are connected through the TPS65982 for additional
support of custom alternate mode configurations.
Table 10-6. Supported DisplayPort Configurations
DisplayPort
CONFIGURATION DisplayPort ROLE DisplayPort LANES
PIN ASSIGNMENT
Configuration 1 DFP_D Pin Assignment C 4 Lane
Configuration 2 DFP_D Pin Assignment D 2 Lane and USB 3.1
Configuration 3 DFP_D Pin Assignment E 4 Lane (Dongle Support)

Table 10-7. TPS65982 and HD3SS460 GPIO Control

TPS65982 GPIO HD3SS460 CONTROL PIN DESCRIPTION
GPIO_0 AMSEL Alternate Mode Selection (DP/USB3)
GPIO_3 EN Super Speed Mux Enable
DEBUG2 POL Type-C Cable

10.2.2.2.3 9.3.2.3 DC Barrel Jack and Type-C PD Charging

The system is design to either charge over Type-C or from the DC barrel jack. The TPS65982 detects that the
DC barrel jack is connected to GPIOn. In the simplest form, a voltage divider could be set to the GPIO I/O level
when the DC Barrel jack voltage is present, as shown in Figure 10-4. A comparator circuit is recommend and
used in this design for design robustness, as shown in Figure 10-5.

20 V
DC Barrel Jack

100 kΩ

1.81 V Barrel Jack Detect

and PFET Enable

10 kΩ

Figure 10-4. DC Barrel Jack Voltage Divider

DC Barrel Jack Voltage

1.8 V

Barrel Jack Detect/ 100 kΩ

PFET Enable
+

10 kΩ

Figure 10-5. Barrel Jack Detect Comparator

This detect signal is used to determine if the barrel jack is present to support the 20 V PD power contracts and
to hand-off charging from barrel jack to Type-C or Type-C to barrel jack. When the DC barrel jack is detected
the TPS65982 at each Type-C port will not request 20 V for charging and the system will be able to support a

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20 V source power contract to another device. When the DC Barrel Jack is disconnected the TPS65982 will exit
any 20 V source power contract and re-negotiate a power contract. When the DC Barrel Jack is connected the
TPS65982 will send updated source capabilities and re-negotiate a power contract if needed.
The PFET enable will be controlled by the DC barrel jack detect comparator depicted in Figure 10-5. This will
allow the system to power up from dead battery through the barrel jack as well as the Type-C ports. Figure
10-7 shows the flow between changing from DC barrel jack charging and USB-PD charging. The example uses
back-to-back PFETs for disabling and enabling the power path for the DC Barrel Jack. It is important to use
PFETs that are rated above the specified parameters to ensure robustness of the system. The DC Barrel Jack
voltage in this design is assumed to be 20 V at 5 A, so the PFETs are recommended to be rated at a minimum of
30 V and 10 A of current.
The TPS65982 in this design also provides the GPIO control for the PFET gate drive that passes the DC Barrel
Jack Voltage to the system. Figure 10-7 shows the flow between changing from DC Barrel Jack charging and
Type-C PD charging.
10.2.2.2.4 Primary TPS65982 Flash Controller and Secondary Port
A single flash can be used for two TPS65982’s in a system where the primary TPS65982 is connected to the
flash and the seoncdary TPS65982 is connected to the primary through UART. UART data is used to pass the
firmware from the primary TPS65982 to the secondary TPS65982 in the system. Figure 10-6 shows a simplified
block diagram of how a primary and secondary TPS65982 are connected using a single flash. The primary
TPS65982 must have its I2C_ADDR pin tied to GND with a 0Ω to denote it as the primary TPS65982.

UART
TPS65982 TPS65982
(Primary) (Secondary)

SPI

SPI
Flash

Figure 10-6. Primary and Secondary TPS65982 Sharing a Single Flash

10.2.2.2.5 TPS65982 Dead Battery Support Primary and Secondary Port

The TP65982 supports dead battery functionality to be able to power up from the Type-C port. This design
supports dead battery using the PP_EXT path, where RPD_G1/2 and CC1/2 are connected respectively,
and BUSPOWERZ is connected to GND to path 5 V VBUS into the system through the PP_EXT path. The
TPS65982 will soft-start the PP_EXT (or PP_HV) path to comply with USB2.0 inrush current requirements.
To enable PD functionality the TPS65982 must boot the application firmware from the flash. For the primary
TPS65982, once VBUS is detected at 5 V it will automatically start to load the application firmware from the
flash. The TPS65982 will then be able communicate over PD and establish a power contract at the required 20
V. Figure 10-8 shows the boot up sequence of the primary TPS65982.
When the TPS65982 that is not connected to the flash is connected in dead battery it will pass the 5 V from
VBUS in to the battery charger where the battery would be able to generate the needed System 3.3 V rail to both
of the TPS65982s. Once the primary TPS65982 has a valid 3.3 V supply (VBUS = 0 V on Primary TPS65982) it
will load the application firmware from the flash and pass it to the secondary TPS65982 that is connected. Once
the secondary TPS65982 has loaded the application firmware over UART it will be able to negotiate a 20-V
power contract. Figure 10-9 shows the dead battery sequence of the secondary TPS65982.
10.2.2.2.6 Debugging Methods
The TPS65982 has methods of debugging a Type-C and PD system. In addition to the resistances
recommended in the I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD Resistors
section, additional series resistors are used for debugging. The two I2C channels allow a designer to check
the system state through the Host Interface Specification. By attaching 0-Ω series resistors between the I2C
master and the TPS65982 and additionally adding 0-Ω series resistors between the TPS65982 and test points,

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a multi-master scenario can be avoided. This allows breaking the connection between the I2C channels and the
system to allow I2C access to the TPS65982 from an external tool. A header is used to allow for connections
without soldering; however, SMT test pads can be used to provide a place to solder blue-wires for testing.
Exposing the SWD_DATA and SWD_CLK pins will allow for more advanced debugging if needed. A header or
SMT test point is also used for the SWD_DATA and SWD_CLK pins.
10.2.2.3 Application Curves
Barrel Jack Charging Barrel Jack Charging
Type-C Cable 20 V PD Power
Barrel Jack Barrel Jack Barrel Jack Connected Contract
Inserted Removed Inserted

20 V
DC Barrel Jack
Attached

DC Barrel Jack
Detect/PFET Enable

Type-C 5V
Charging

0V
Enter 20 V Type-C Exit 20 V Type-C VBUS
PD Contract PD Contract

PD Charging
Load
Figure 10-7. DC Barrel Jack and Type-C PD Application
FW Load
Charging Hand-Off
Active Boot Application
TPS65982 Code

Flash FW PD Comm.
Load Start Enabled
Figure 10-8. Primary TPS65982 Dead Battery
Sequence
Type-C Cable 20 V PD Power
Connected Contract

20 V

20 V

5V

Secondary 0V
VBUS
5V

Secondary 0V
PP_EXT
3.3 V
BQ Charger
0V
3.3 V Auxiliary
(VIN_3V 3)
Primary SPI LOAD
Application
FW Load

Secondary UART LOAD

Application
FW Load

Boot Application
Primary Active
TPS65982 Code

Secondary Active Boot Application

TPS65982 Code

Secondary
TPS65982 Loads
App. FW (UART)
Primary Secondary PD
TPS65982 Loads Communication
App. FW (SPI) Enabled

Figure 10-9. Secondary TPS65982 Dead Battery Sequence

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11 Power Supply Recommendations

11.1 3.3-V Power
11.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply to the TPS65982. The VIN_3V3 switch (S1 in Figure 9-40) is a
unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to
VIN_3V3. This switch is on when 3.3 V is available. See Table 11-1 for the recommended external capacitance
on the VIN_3V3 pin.
11.1.2 VOUT_3V3 Output Switch
The VOUT_3V3 output switch (S2 in Figure 9-40) enables a low-current auxiliary supply to an external element.
This switch is controlled by and is off by default. The VOUT_3V3 output has a supervisory circuit that drives
the RESETZ output as a POR signal to external elements. RESETZ is also asserted by the MRESET pin or a
host controller. See RESETZ and MRESET for more details on RESETZ. See Table 11-1 for the recommended
external capacitance on the VOUT_3V3 pin.
11.1.3 VBUS 3.3-V LDO
The 3.3-V LDO from VBUS steps down voltage from VBUS to LDO_3V3. This allows the TPS65982 to be
powered from VBUS when VIN_3V3 is not available. This LDO steps down any recommended voltage on the
VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65982 will operate
without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin may increase
temperature enough to trigger thermal shutdown. The VBUS 3.3-V LDO blocks reverse current from LDO_3V3
back to VBUS allowing VBUS to be unpowered when LDO_3V3 is driven from another source. See Table 11-1
for the recommended external capacitance on the VBUS and LDO_3V3 pins.
11.2 1.8 V Core Power
Internal circuitry is powered from 1.8 V. There are two LDOs that step the voltage down from LDO_3V3 to 1.8 V.
One LDO powers the internal digital circuits. The other LDO powers internal low voltage analog circuits.
11.2.1 1.8 V Digital LDO
The 1.8 V Digital LDO provides power to all internal low voltage digital circuits. This includes the digital core,
memory, and other digital circuits. See Table 11-1 for the recommended external capacitance on the LDO_1V8D
pin.
11.2.2 1.8 V Analog LDO
The 1.8 V Analog LDO provides power to all internal low voltage analog circuits. See Table 11-1 for the
recommended external capacitance on the LDO_1V8A pin.
11.3 VDDIO
The VDDIO pin provides a secondary input allowing some I/Os to be powered by a source other than LDO_3V3.
The default state is power from LDO_3V3. The memory stored in the flash will configure the I/O’s to use
LDO_3V3 or VDDIO as a source and application code will automatically scale the input and output voltage
thresholds of the I/O buffer accordingly. See I/O Buffers for more information on the I/O buffer circuitry. See Table
11-1 for the recommended external capacitance on the VDDIO pin.
11.3.1 Recommended Supply Load Capacitance
Table 11-1 lists the recommended board capacitances for the various supplies. The typical capacitance is the
nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum
capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum
capacitance allowing for tolerances and voltage de-rating ensuring proper operation.

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Table 11-1. Recommended Supply Load Capacitance

CAPACITANCE
VOLTAGE MIN TYP
PARAMETER DESCRIPTION MAX
RATING (ABS (TYP
(ABS MAX)
MIN) PLACED)
CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 µF 10 μF
CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 µF 10 µF 25 µF
CVOUT_3V3 Capacitance on VOUT_3V3 6.3 V 0.1 μF 1 μF 2.5 μF
CLDO_1V8D Capacitance on LDO_1V8D 4V 500 nF 2.2 µF 12 µF
CLDO_1V8A Capacitance on LDO_1V8A 4V 500 nF 2.2 µF 12 µF
CLDO_BMC Capacitance on LDO_BMC 4V 1 µF 2.2 µF 4 µF
CVDDIO Capacitance on VDDIO. When shorted to LDO_3V3, the CLDO_3V3 6.3 V 0.1 µF 1 µF
capacitance may be shared.
CVBUS Capacitance on VBUS 1 25 V 0.5 µF 1 µF 12 µF
CPP_5V0 Capacitance on PP_5V0 10 V 2.5 µF 4.7 µF
CPP_HV Capacitance on PP_HV (Source to VBUS) 25 V 2.5 µF 4.7 µF
Capacitance on PP_HV (Sink from VBUS) 25 V 47 µF 120 µF
CPP_CABLE Capacitance on PP_CABLE. When shorted to PP_5V0, the 10 V 2.5 µF 4.7 µF
CPP_5V0 capacitance may be shared.
CPP_HVEXT Capacitance on external high voltage source to VBUS 25 V 2.5 µF 4.7 µF
Capacitance on external high voltage sink from VBUS 25 V 47 µF 120 µF
CSS Capacitance on soft start pin 6.3 V 220 nF
CC_CC1 Capacitance on C_CC1 pin 25 V 220 pF 330 pF 470 pF
CC_CC2 Capacitance on C_CC2 pin 25 V 220 pF 330 pF 470 pF

11.3.2 Schottky for Current Surge Protection

To prevent the possibility of large ground currents into the TPS65982 during sudden disconnects because of
inductive effects in a cable, it is recommended that a Schottky be placed from VBUS to GND as shown in Figure
11-1. The NSR20F30NXT5G is recommended.
PP_EXT
HV_GATE1

HV_GATE2
SENSEN
SENSEP

PP_HV Gate Control

and Current Limit

PP_HV
HV Gate Control and Sense
Fast
current
limit

PP_5V0 Gate Control

and Current Limit

PP_5V0 VBUS
Fast
current
limit

AGND

Figure 11-1. Schottky on VBUS for Current Surge Protection

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12 Layout
12.1 Layout Guidelines
Proper routing and placement will maintain signal integrity for high-speed signals and improve the thermal
dissipation from the TPS65982 power path. The combination of power and high-speed data signals are easily
routed if the following guidelines are followed. It is a best practice to consult with a printed circuit board (PCB)
manufacturer to verify manufacturing capabilities.
12.1.1 TPS65982 Recommended Footprints
12.1.1.1 Standard TPS65982 Footprint (Circular Pads)
Figure 12-1 shows the TPS65982 footprint using a 0.25mm pad diameter. This footprint is applicable to boards
that will be using an HDI PCB process that uses smaller vias to fan-out into the inner layers of the PCB. This
footprint requires via fill and tenting and is recommended for size-constrained applications. The circular footprint
allows for easy fan-out into other layers of the PCB and better thermal dissipation into the GND planes. Figure
12-2 shows the recommended via sizing for use under the balls. The size is 5mil hole and 10mil diameter. This
via size will allow for approximately 1.5A current rating at 3 mΩ of DC resistance with 1.6nH of inductance. It is
recommended to verify these numbers with board manufacturing processes used in fabrication of the PCB. This
footprint is available for download on the TPS65982 product folder on the TPS65982 product folder.

Figure 12-1. Top View Standard TPS65982 Footprint (Circular Pads)

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Figure 12-2. Under Ball Recommended Via Size

12.1.2 Alternate TPS65982 Footprint (Oval Pads)

Figure 12-3 shows the TPS65982 footprint using oval-shaped pads in specific locations. This allows the PCB
designer to route the inner perimeter balls through the top layer. The balls around the perimeter have their
pads in an oval shape with the exception of the corner balls. Figure 12-4 shows the sizing for the oval pads,
0.25 mm by 0.17 mm. All of the other non-oval shaped pads will have a 0.25 mm diameter. This footprint is
recommended for MDI (Medium Density) PCB designs that are generally less expensive to build. The void under
the TPS65982 allows for vias to route the inner signals and connect to the GND and power planes. Figure 12-5
shows the recommended minimum via size (8mil hole and 16 mil diameter). The recommended 8mil vias will be
rated for approximately 1.8 A of DC current and 1.5 mΩ of resistance with 1.3 nH of inductance. Some board
manufactures may offer 6mil hole and 12 mil diameter vias with a mechanical drill. This footprint is available for
download on the TPS65982 product folder.

Figure 12-3. Top View Alternate TPS65982 Footprint (Oval Pads)

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Figure 12-4. Oval Pad Sizing

Figure 12-5. Recommended Minimum Via Sizing

12.1.3 Top TPS65982 Placement and Bottom Component Placement and Layout
When the TPS65982 is placed on top and its components on bottom the solution size will be at its smallest. For
systems that do not use the optional external FET path the solution size will average less than 64 mm2 (8 mm ×
8 mm). Systems that implement the optional external FET path will average a solution size of less than 100 mm2
(10 mm × 10 mm). These averages will vary with component selection (NFETs, Passives, etc.). Selection of the
oval pad TPS65982 footprint or standard TPS65982 footprint will allow for similar results.
12.1.4 Oval Pad Footprint Layout and Placement
The oval pad footprint layout is generally more difficult to route than the standard footprint because of the top
layer fan-out and void via placement needed; however, when the footprint with oval pads is used, Via on Pads,
laser-drilled vias, and HDI board processes are not required. Therefore, a footprint with oval pads is ideal for
cost-optimized applications and will be used for the following the layout example. This layout example follows the
charger application example (see Typical Applications) and includes all necessary passive components needed
for this application. This design uses both the internal and optional external FET paths for sourcing and sinking
power respectively. Follow the differential impedances for High Speed signals defined by their specifications
(DisplayPort - AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not
all designs will use all of the I/O on the TPS65982.
12.1.5 Component Placement
Placement of components on the top and bottom layers is used for this example to minimize solution size. The
TPS65982 is placed on the top layer of the board and the majority of its components are placed on the bottom
layer. When placing the components on the bottom layer, it is recommended that they are placed directly under
the TPS65982 in a manner where the pads of the components are not directly under the void on the top layer.
Figure 12-6 and Figure 12-7 show the placement in 2-D. Figure 12-8 and Figure 12-9 show the placement in
3-D.
12.1.6 Designs Rules and Guidance
When starting to route nets it is best to start with 4 mil clearance spacing. The designer may have to adjust the
4mil clearance to 3.5 mil when fanning out the top layer routes. With the routing of the top layer having a tight
clearance, it is recommended to have the layout grid snapped to 1 mil. For certain routes on the layout done in
this guide, the grid snap was set to 0.1 mil. For component spacing this design used 20 mil clearance between
components. The silk screen around certain passive components may be deleted to allow for closer placement
of components.
12.1.7 Routing PP_HV, PP_EXT, PP_5V0, and VBUS
On the top layer, create pours for PP_HV, PP_5V0 and VBUS to extend area to place 8 mil hole and 16 mil
diameter vias to connect to the bottom layer. A minimum of 4 vias is needed to connect between the top and
bottom layer. For the bottom layer, place pours that will connect the PP_HV, PP_5V0, and VBUS capacitors to
their respective vias. The external FETS must also be connected through pours and place vias for the external
FET gates. For 5 A systems, special consideration must be taken for ensuring enough copper is used to handle
the higher current. For 0.5 oz copper top or bottom pours with 0.5-oz plating will require approximately a 120-mil
pour width for 5-A support. When routing the 5 A through a 0.5 oz internal layer, more than 200 mil will be
required to carry the current. Figure 12-10 and Figure 12-11 show the pours used in this example.

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12.1.8 Routing Top and Bottom Passive Components

The next step is to route the connections to the passive components on the top and bottom layers. For the top
layer only CC1 and CC2 capacitors will be placed on top. Routing the CC1 and CC2 lines with a 8 mil trace will
facilitate the needed current for supporting powered Type C cables through VCONN. For more information on
VCONN please refer to the Type C specification. Figure 12-12 shows how to route to the CC1 and CC2 to their
respective capacitors. For capacitor GND pin use a 10 mil trace if possible. This particular system support Dead
Battery, which has RPD_G1/2 connected to CC1/2.
The top layer pads will have to be connected the bottom placed component through Vias (8 mil hole and 16
mil diameter recommended). For the VIN_3V3, VDDIO, LDO_3V3, LDO_1V8A, LDO1V8D, LDO_BMC, and
VOUT_3V3 use 6mil traces to route. For PP_CABLE route using an 8 mil trace and for all other routes 4 mil
traces may be used. To allow for additional space for routing, stagger the component vias to leave room for
routing other signal nets. Figure 12-13 and Figure 12-14 show the top and bottom routing. Table 12-1 provides a
summary of the trace widths.
Table 12-1. Routing Trace Widths
ROUTE WIDTH (mil)
CC1, CC2, PP_CABLE 8
LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3,
6
VOUT_3V3, VDDIO, HV_GATE1, HV_GATE2
Component GND 10

12.1.9 Void Via Placement

The void under the TPS65982 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be
used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the
device by the power path. Figure 12-15 shows the recommended placement of the vias. Note the areas under
the void where vias are not placed. This is done to allow the external FET gate drive and sense pins to route
under the TPS65982 through an inner layer. Figure 12-16 shows the top layer GND pour to connect the vias and
GND balls together.
12.1.10 Top Layer Routing
Once the components are routed, the rest of the area can be used to route all of the additional I/O. After all nets
have been routed place a polygonal pour under to connect the TPS65982 GND pins to the GND vias. Refer to
Figure 12-17 for the final top routing and GND pour.
12.1.11 Inner Signal Layer Routing
The inner signal layer is used to route the I/O from the internal balls of the TPS65982 and the external FET
control and sensing. Figure 12-18 shows how to route the internal layer.
12.1.12 Bottom Layer Routing
The bottom layer has most of the components placed and routed already. Place a polygon pour to connect all of
the GND nets and vias on the bottom layer, refer to Figure 12-19.

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12.2 Layout Example

Figure 12-6. Example Layout (Top View in 2-D)

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Figure 12-7. Example Layout (Bottom View in 2-D)

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Figure 12-8. Example Layout (Top View in 3-D)

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Figure 12-9. Example Layout (Bottom View in 3-D)

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Figure 12-10. Top Polygonal Pours

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Figure 12-11. Bottom Polygonal Pours

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Figure 12-12. CC1 and CC2 Capacitor Routing

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Figure 12-13. Top Layer Component Routing

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Figure 12-14. Bottom Layer Component Routing

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Figure 12-15. Void Via Placement

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Figure 12-16. Top Layer GND Pour

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Figure 12-17. Final Routing and GND Pour (Top Layer)

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Figure 12-18. Final Routing (Inner Signal Layer)

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Figure 12-19. Final Routing (Bottom Layer)

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13 Device and Documentation Support

13.1 Device Support
13.1.1 Development Support
For the IBIS Model, see TPS65982ZQZR IBIS Model (SLVMAY7)
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
• USB Power Delivery Specification, Revision 2.0, Version 1.2 (March 25th, 2016)
• USB Type-C Specification, Revision 1.2 (March 25th, 2016)
• USB Battery Charging Specification, Revision 1.2 (December 7th, 2010)
• TPS65981, TPS65982, and TPS65986 Firmware User’s Guide (SLVUAH7)
• TPS65981, TPS65982, and TPS65986 Host Interface Technical Reference Manual (SLVUAN1)
• W25Q80DV data sheet, 8M-Bit, 16M-Bit and 32M-Bit Serial Flash Memory With Dual and Quad SPI
• NSR20F30NXT5G data sheet, Schottky Barrier Diode
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
USB Type-C® is a registered trademark of USB Implementers Forum.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 1-Mar-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS65982ABZBHR NRND NFBGA ZBH 96 2500 RoHS & Green Call TI Level-3-260C-168 HR -10 to 85 TPS65982
AB

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65982ABZBHR NFBGA ZBH 96 2500 330.0 16.4 6.3 6.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65982ABZBHR NFBGA ZBH 96 2500 336.6 336.6 31.8

Pack Materials-Page 2
 PACKAGE OUTLINE
ZBH0096A SCALE 2.000
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY

6.1 B
A
5.9

BALL A1 CORNER
INDEX AREA

6.1
5.9

(0.65)

C
1 MAX
SEATING PLANE

BALL TYP 0.08 C

0.25
TYP
0.19

5 TYP
SYMM (0.5) TYP

K (0.5) TYP
J
H
G SYMM
5
TYP F
E
D 0.35
96X
0.25
C 0.15 C A B
B 0.05 C

A
0.5 TYP 1 2 3 4 5 6 7 8 9 10 11

0.5 TYP

4221754/B 09/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
ZBH0096A NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY

(0.5) TYP 96X ( 0.25)

1 2 3 4 5 6 7 8 9 10 11
A

(0.5) TYP
C

E
SYMM
F

SYMM

LAND PATTERN EXAMPLE

SCALE:15X

0.05 MAX 0.05 MIN METAL UNDER

( 0.25)
METAL SOLDER MASK

SOLDER MASK ( 0.25)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221754/B 09/2018

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com
 EXAMPLE STENCIL DESIGN
ZBH0096A NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY

96X ( 0.25)
(0.5) TYP (R0.05) TYP
1 2 3 4 5 6 7 8 9 10 11
A

(0.5) TYP
B

METAL
TYP E

SYMM
F

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:20X

4221754/B 09/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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