© 2020 JETIR April 2020, Volume 7, Issue 4 www.jetir.

org (ISSN-2349-5162)

Study of X-86 Family

Ayush Mishra
Student, Department of ETRX,
Shree L.R. Tiwari College of Engineering
Mira Road, Thane,
Mumbai, Maharashtra, India.

Shreya Shivalkar
Student, Department of ETRX,
Shree L.R. Tiwari College of Engineering,
Mira Road, Thane,
Mumbai, Maharashtra, India.

Shweta Yadav
Student, Department of ETRX,
Shree L.R. Tiwari College of Engineering,
Mira Road, Thane,
Mumbai, Maharashtra, India.

Anil Suthar
Student, Department of ETRX,
Shree L.R. Tiwari College of Engineering,
Mira Road, Thane,
Mumbai, Maharashtra, India.

Abstract-
The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with
memory segmentation as a solution for addressing more memory.
The term "X86" came into being because the names of several successors to Intel's 8086 processor end in
"86", including the 80186, 80286, 80386 and 80486 processors.This paper is an in detail study of X-86 family
consisting of its features, advantages, applications, instruction set and overview of other processors/extensions
in the X-86 family.Architecture,Programmer's model and Various addressing modes are also explained briefly.

Keywords- X-86 family, Registers, Pipelining, Modes of operation, clock speed, Core

I. INTRODUCTION Intel and has evolved over time by the addition of new
instructions as well as the expansion to 64-bits. As of
The 8086 was introduced in 1978 as a fully 16-bit 2009, x86 primarily refers to IA-32 (Intel Architecture,
extension of Intel's 8-bit 8080 microprocessor, with 32-bit) and/or X86-64,the extension to 64 bit .Versions of
memory segmentation as a solution for addressing more the x86 instruction set architecture have been implemented
memory.The X86 instruction set architecture originated by by Intel, AMD and several other vendors,with each
vendor having its own family of x86 processors.

II. FEATURES
● Wide Range of Clock Rates
● High Performance Processor (Up to 19
Times the 8086 Throughput)

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● Large Address Space 16 Megabytes

Physical/1 Gigabyte Virtual per Task
● Integrated Memory Management,
● Four-Level Memory Protection and
Support for Virtual Memory and Operating
● High Bandwidth Bus Interface (25
Megabyte/Sec)
● Can function in Protected Mode and Real
Mode[10]

Fig 2. General Purpose Registers

IV. PROGRAMMERS MODEL
8086 has 8 general purpose registers,labelled
AH,AL,BH,BL,CH,CL,DH and DL .The 32 bit
registers have four separately addressable parts and
the 16-bit registers have 16-bit AX, 8-bit AH and
AL,16-bit BX, 8-bit BH and BL, 16-bit CX, 8-bit
CH and CL, 16-bit DX, 8-bit DH and DL . These
registers can be used for arithmetic and logical
operations on data . Many have specialized
purposes.[3]

Register Size(in bits) Purpose

name

AL, 8/8/16 Known as

AH/AX accumulator. It
holds results of
Fig 1. Programmers model arithmetic
The programming model of the 8086 is considered operations and
function return
to be program visible because its registers are used
values.
during application programming and are specified
by the instructions.The programming model for a BL, 8/8/16 Used to store the
microprocessor shows the various internal registers BH/BX base address of the
that are accessible to the programmer. In the program.
programming model there are
CL, 8/8/16 Used for loop and
- 4 General Purpose registers( Data Registers)
CH/CX string operations.
- 4 Segment registers
- 2 Pointer registers
- 2 Index registers DL, 8/8/16 A general purpose
- 1 Instruction Pointer register DH/DX registers. Also
- 1 Flag register used for I/O
operations.

A.Basic Program execution registers. Table 1

b.) Segment Registers .

a.)General Purpose Registers

Fig 3. Segment Registers

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The four segment registers CS, DS, ES and SS are

the same as the segment registers found in Intel 8086
and Intel 286 processors and the FS and GS registers
were introduced into the Intel 32 bit
architecture.These registers are used to break up a
program into parts. As it executes, the segment
registers are assigned the base values of each
segment. From here, offset values are used to access
each command in the program.[4]

Fig 4. Flag Registers

Segment Size Purpose

Register (bits)

CS 16 Code segment register.Used Flag Bi Purpose

for fetching instructions. t

DS 16 Data segment register. Used CF Set if an arithmetic

for data accesses. (Carry 0 operation generates a carry
Flag) or a borrow out of the most
ES 16 Extra segment register. Used significant bit of the result,
during string operations. cleared otherwise.

SS 16 Stack segment register. Base PF 2 Set if the least-significant

location of the stack (Parity byte of the result contains an
segment. Flag) even number of 1 bit,
cleared otherwise.
FS 16 Extra segment register.
AF 4 Set if an arithmetic
GS 16 Extra segment register. (Adjust operation generates a carry
Flag) or a borrow out of bit 3 of the
Table 2 result, cleared otherwise.

ZF 6 Set if the result is zero,

c.) Instruction pointer register (Zero Flag) cleared otherwise

Instruction pointer register contains the offset in the SF 7 Set equal to the most-
current code segment for the next instruction to be (Sign Flag) significant bit of the result. 0
executed. It is advanced from one instruction indicates a positive value,
whereas 1 indicates a
boundary to the next one in straight line
negative value.
code.Instruction pointer register cannot be accessed
directly by software. It is controlled implicitly by AF 1 Set if the integer result is too
control-transfer instructions such as JMP, JCC, (Auxiliary large a positive number or
CALL, RET and IRET, interrupts and exceptions. carry Flag) too small a negative number,
cleared otherwise.
[6]

d.) Flag Registers TF 0 Set if processor enters

Flag is a flip-flop,which indicates some condition. (Trap single-step mode,cleared
Depending upon the value of result after any Flag) otherwise
Arithmetic and Logical operations, the flag bits IF 0 Set if CPU recognizes
become Set (1) or Reset (0).The 8086 has a 16-bit (Interrupt Maskable interrupt
flag register with 9-active flags.These flags are of Flag) requests,cleared otherwise.
two types: 6 Status flags namely carry flag, parity
flag, auxiliary carry flag, zero flag, sign flag and DF 0 Set if Instructions are
(Directio processed high address to
3 Control flags namely trap flag, interrupt flag
n flag) low address,cleared vice-
and direction flag.The Control flags are used to versa.
control certain operations. They are changed by the
programmer.[8] Table 3

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B. FPU Registers
There are Eight 80-bit floating point data
registers.They are named as
ST(0),ST(1),..ST(7).They are arranged in stacks and
are used for all floating-point arithmetic
operations.All floating-point instructions provide a
5-bit field that specifies which floating-point
Fig 7. XXM Registers
registers to use in the execution of the instruction.
All floating-point instructions other than loads are
performed on operands located in floating-point 5 ) Instruction Set of X-86 Microprocessors:
registers. Numbers are pushed onto the stack from
An instruction is a binary pattern designed inside a
memory, and are popped off the stack back to
microprocessor to perform a specific function. The
memory. There is no instruction allowing to transfer
entire group of instructions that a microprocessor
values directly to or from ALU registers. [5]
supports is called Instruction Set. 8086 has more
than 20,000 instructions.Instructions are classified
on the basis of functions they perform.The 8086
microprocessor supports 8 types of instructions −
● Data Transfer Instructions
● Arithmetic Instructions
● Bit Manipulation Instructions
● String Instructions
Fig 5. FPU Registers ● Program Execution Transfer Instructions
(Branch & Loop Instructions)
C.MMX Registers
● Processor Control Instructions
MMX defines eight registers, called MM0 through ● Iteration Control Instructions
MM7, and operations that operate on them. Each ● Interrupt Instructions
register is 64 bits wide and can be used to hold either
64-bit integers, or multiple smaller integers in a
"Packed" format. It provides arithmetic and logic
operations on 64-bit integer numbers.The extension a.) Data Transfer Instructions:
contains 16 data registers of 64-bits and eight
control registers of 32-bits.[2] The data transfer instructions are used to transfer
data from one location to another. This transfer of
data can be either from register to register, register
to memory or memory to register.It is important to
note here that the memory to memory transfer of
data directly is not possible.All the store, move,
load, exchange, input and output instructions belong
to this category. These instructions do not affect any
flags.[1]

Fig 6. MMX Registers For eg: MOV, PUSH, IN, OUT etc
D.XMM Registers
b.) Arithmetic Instructions:
These registers can be accessed directly using the
names XMM0 to XMM7; and they can be These instructions perform the arithmetic
accessed independently from the X87 FPU and operations, like addition, subtraction, multiplication
MMX registers and the General-purpose and division along with the respective ASCII and
registers.XMM registers can only be used to decimal adjust instructions. The increment and
perform calculations on data; they cannot be used decrement operations also belong to this type of
to address memory.Data can be loaded into or instructions. The arithmetic instructions affect all
written from the registers to memory in 32-bit, 64- the condition code flags.Unlike in 8085
bit, and 128-bit increments.[4] microprocessor, in 8086 microprocessor the
destination operand need not be the accumulator.[4]

For eg: ADD, SUB, MUL, DEC etc.

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c.)Logical Instructions: temporarily to a subroutine either within the

program or outside the program [9]
These instructions are used to perform operations
where data bits are involved, i.e. logical AND, OR, For eg: INT, INTO, IRET .[4]
XOR, NOT and TEST operations etc.. In an 8086
microprocessor, the destination operand need not be V. FAMILY OF X-86
the accumulator. For logical instruction ,the source
may be an immediate number, a register or a The term "x86" came into being because the
memory location. The destination may be a register names of several successors to Intel's 8086
or a memory location. The source and destination processor end in "86", including the 80186, 80286,
both cannot be memory locations in the same 80386 and 80486 processors.In the 1980s and early
instruction.[5] 1990s, when the 8088 and 80286 were still in
common use, the term x86 usually represented any
For eg: ROL, ROR, RCR, RCL etc. 8086-compatible CPU. Today, x86 usually implies
a binary compatibility also with the 32-bit
d.)String Instructions: instruction set of the 80386.
String is a series of data bytes or words available in
memory at consecutive locations. Their memory is
always allocated in a sequential order.. It is a series a.) 8086 Microprocessor
of the same type of data items in sequential memory
locations. They can move strings, compare strings, 8086 Microprocessor is an enhanced version of
search for a specific value within a string, initialize 8085Microprocessor that was designed by Intel in
a string to a fixed value, and do other primitive 1976. It is a 16-bit Microprocessor having 20
operations on strings. Using string instructions may address lines and16 data lines that provides up to
speed up your array manipulation code 1MB storage. It consists of a powerful instruction
considerably.[7] set, which provides operations like multiplication
and division easily.
For eg: REP, MOVS, INS, OUTS etc. It supports two modes of operation, i.e. Maximum
mode and Minimum mode. Maximum mode is
e.) Branch and loop Instructions: suitable for systems having multiple processors and
These instructions are used to execute the given Minimum mode is suitable for systems having a
instructions for a number of timesIt is also called single processor.
program execution transfer instruction. Instructions
of this group transfer program execution from the
normal sequence of instructions to the specified b.) 80186 Microprocessor
destination or target. When the instruction is
executed, the code segment (CS) and Instruction The 80186 series was generally intended for
pointer registers get loaded with new values of CS embedded systems, as microcontrollers with
and Ip corresponding to the Location to be external memory. Therefore, to reduce the number
transferred. [10] of integrated circuits required, it included features
such as clock generator, interrupt controller, timers,
For eg: LOOP, CALL, JMP, JC etc. wait state generator, DMA channels, and external
chip select lines.
f.) Processor Control Instructions: Multiply and divide also showed great
improvement being several times as fast as on the
These instructions are used to control the processor original 8086 and multi-bit shifts were done almost
action by setting/resetting the flag values They do four times as quickly as in the 8086.
not affect any other flag. They are responsible for
setting(1) or resetting(0) the values of flag
registers.[9]
c.) 80826 Microprocessor
For eg: STC, CLC, CMC, etc.
The 80286 is the first member of the family of
advanced microprocessors with memory
management and protection abilities. The 80286
g.) Interrupt Instructions:
CPU, with its 24-bit address bus is able to address
These instructions are used to call the interrupt
16 Mbytes of physical memory. Various versions of
during program execution. They are the instructions
80286 are available that runs on 12.5 MHz, 10 MHz
that interrupt the flow of a program and can cause
and 8 MHz clock frequencies. 80286 is upwardly
the program to either to end or to skip or to Go
compatible with 8086 in terms of instruction set.
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processor has a memory space of 4 GB (232 bytes)

and a separate I/O space with 64 KB of addressable
d.) 80386 Microprocessor locations. The memory space is organized as a
sequence of 64-bit quantities. Each 64-bit location
The Intel 80386, also known as i386 or just 386, has eight individually addressable bytes at
is a 32-bit microprocessor introduced in 1985. The consecutive memory addresses. The I/O space is
Internal Architecture of 80386 is divided into 3 organized as a sequence of 32-bit quantities. Each
sections. Central processing unit(CPU) , Memory 32-bit quantity has four individually addressable
management unit(MMU), Bus interface unit(BIU) bytes at consecutive memory addresses.
and Central processing unit. Further divided into
Execution unit(EU) and Instruction unit(IU). The
Memory management unit consists of a
Segmentation unit and Paging unit.
Segmentation unit allows the use of two address g.) Pentium Pro Microprocessor
components and viz. Segment and offset for
reliability and sharing of code and data. It allows It’s a sixth-generation x86 microprocessor
segments of size 4Gbytes at max. The Paging unit developed and manufactured by Intel introduced on
organizes the physical memory in terms of pages of November 1, 1995. The Pentium Pro
4kbytes size each. microprocessor belongs to the CISC (Complex
Instruction Set Computers) machines. Processors of
the Pentium Pro family are mostly present in
e.) 80486 Microprocessor majority of personal computers. The term ‘Pentium
processor’ refers to an Intel x86 family of
The Intel 80486, also known as the i486 or 486, microprocessors that share a common architecture
is the successor model of 32-bit x86 and instruction set. The Pentium Pro is capable of
microprocessor to the Intel 80386. Introduced in both dual- and quad-processor configurations.
1989, the 80486 improved on the performance of the
80386DX thanks to on-die L1 cache and floating- Pentium Pro clock speeds were 150, 166, 180 or
point unit, as well as an improved, five-stage tightly- 200 MHz with a 60 or 66 MHz external bus clock.
coupled pipelined design. Some users chose to overclock their Pentium Pro
One of the feature included in a 80486 is a built chips, with the 200 MHz version often being run at
in math coprocessor. This coprocessor is essentially 233 MHz, the 180 MHz version often being run at
the same as the 80387 processor used with a 80386, 200 MHz, and the 150 MHz version often being run
but being integrated on the chip allows it to execute at 166 MHz. The chip was popular in symmetric
math instructions about three times as fast as a multiprocessing configurations, with dual and quad
80386/387 combination. 80486 is an 8Kbyte code SMP server and workstation setups being
and data cache.To make room for the additional commonplace.
signals, the 80486 is packaged in a 168 pin, pin grid
array package instead of the. The 132 pin PGA used
for the 80386.

f.) Pentium Microprocessor h.) Core Microprocessor

Pentium, Family of microprocessors developed

by Intel Corp. Introduced in 1993 as the successor to Core is a brand encompassing a range of Intel's
Intel’s 80486 microprocessor, the Pentium consumer 64-bit x86-64 single, dual, and quad-core
contained two processors on a single chip and about microprocessors based on the Core
3.3 million transistors. Using a CISC (complex microarchitecture. Each contains two cores,
instruction set computer) architecture, its main packaged in a multi-chip module. The introduction
features were a 32-bit address bus, a 64-bit data bus, of Core relegated the Pentium brand to the mid-
built-in floating-point and memory-management range market, and reunified laptop and desktop CPU
units, and two 8KB caches. lines for marketing purposes under the same product
It was available with processor speeds ranging name. The Core 2 brand was introduced in mid-July
from 60 megahertz (MHz) to 200 MHz. The of 2006, comprising the Solo , Duo, Quad-core and
Pentium quickly became the processor of choice for in 2007, the Extreme sub brands. Intel Core
personal computers. It was superseded by ever faster processors with vPro technology which was
and more powerful processors, the Pentium Pro designed for businesses purposes include the dual-
(1995), the Pentium II (1997), the Pentium III core and quad-core branches.Although Woodcrest
(1999), and the Pentium 4 (2000). The Pentium

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processors are also based on the Core architecture, d) Indexed Addressing Mode :
they are available under the Xeon brand
In this mode, the effective address is calculated by
adding the unsigned 16-bit or sign-extended 8-bit
displacement and the contents of SI or DI.The
effective address is the sum of index register and
displacement.
VI. ADDRESSING MODES
For eg:MOV AX, [SI+2000]

The term addressing modes refers to the way in e.)Based-index addressing mode
which the operand of an instruction is specified. The
addressing mode specifies a rule for interpreting or The based indexed addressing modes are simply
modifying the address field of the instruction before combinations of the register indirect addressing
the operand is actually executed. modes. In this addressing mode, the offset address
The 8086 memory addressing modes provide of the operand is computed by summing the base
flexible access to memory, allowing you to easily register to the contents of an Index register.
access variables, arrays, records, pointers, and other
complex data types. The key to good assembly Example: ADD CX, [AX+SI]
language programming is the proper use of memory
addressing modes[8]
. f.)Based indexed with displacement mode
a.)Immediate addressing mode
In this addressing mode, the operands offset is
The addressing mode in which the data operand is a computed by adding the base register contents. An
part of the instruction itself is known as immediate Index registers contents and 8 or 16-bit
addressing mode.The 16-bit effective address (EA) displacement.These addressing modes are a slight
is taken directly from the displacement field of the modification of the base/indexed addressing modes
instruction. The displacement (unsigned 16-bit or with the addition of an eight bit or sixteen bit
sign-extended 8-bit number) is stored in the location constant.
following the instruction opcode.
Example:
For eg:ADD AL MOV AX, [BX+DI+08]

b.)Register Indirect Addressing Mode: g.)String addressing mode

This addressing mode allows data to be addressed at This addressing mode is related to string
any memory location through an offset address held instructions. In this the value of SI and DI are auto
in any of the following registers: BP, BX, DI & SI. incremented and decremented depending upon the
Indirect addressing is generally used for variables value of directional flag.[7]
containing several elements like arrays.
Example: MOVS B
For eg::MOV AX, [BX]

c.)Based addressing mode VI. MODES OF OPERATION

In this addressing mode, the offset address of the A. Protected Mode

operand is given by the sum of contents of the
BX/BP registers and 8-bit/16-bit displacement.The Protected mode was first added to the x86
physical memory address is calculated according to architecture in 1982 with the release of Intel's 80286
the base register.When the stack is accessed, the 20- processor, and later extended with the release of the
bit physical address is computed from BP and SS. 80386 in 1985. Due to the enhancements added by
protected mode, it has become widely adopted and
For eg: ADD AX, [BX+SI]. has become the foundation for all subsequent
enhancements to the x86 architecture. Protected
mode has a number of features designed to enhance
an operating system's control over application
software, in order to increase security and system
stability. These additions allow the operating system
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to function in a way that would be significantly more above.The microprocessor is one of the most
difficult or even impossible without proper significant inventions in the field of technology
hardware support.[] because of its effect on technologic engineering,
different aspects of life, and of course how it can
B.) Real Mode store data larger than the size of the actual chip. The
impacts the microprocessor had had on life and
Real mode programming involved manipulating whether it was for the better the invention was made
data between 0 and 1 MB. The memory there was is a controversy that still goes to this day.
accessible by any program running in memory. And
while, generally speaking, there weren’t multiple
programs running in memory at the same time, the
OS had to set up things called “interrupt handlers”
XI. REFERENCES
because the x86 architecture is interrupt driven. The
processor calculates the physical address of a
1. Kinnari Prakashan, TPS Computer Science
memory reference by shifting the value of a segment
- II, STD. XII.
register to the left by 4 binary digits and then adding
2. John Crisp, Introduction of Microprocessor
the offset address to this value. Thus, two 16-bit
and Microcontroller,
values (segment and offset) are combined to form a
3. R.D.Supekar, Vaishali Ghule, Taraka
single 20-bit physical address. There are no linear
Ghamande, Vilas Karmude, XIIth
addresses in real mode.[9]
Computer Science, Revised Ed.
4. www.eeeguide.com
VII. ADVANTAGES OF X-86 FAMILY 5. en.wikibooks.org
6. https://www.javatpoint.com/instruction-
set-of-8086
● It was the world's first general purpose
7. https://www.studytonight.com/computer-
microprocessor.
architecture/addressingmodes-
● Protected mode and Real mode were
instructioncycle
introduced.
8. www.javatpoint.com/instruction-set-of-
● Processors were highly pipelined.
8086
● Clock speed was increased.
9. www.tutorialspoint.com/microprocessor/
● Development of “NetBurst" architecture.
microprocessor_8086_instruction_sets.ht
● Notions like “Hyper-Threading”, and
m
“Multi-Core” chips were introduced.
10. www.google.com
● Due to X-86 microprocessors, “Multi-
core” desktop versions were
developed.[1]

IX. APPLICATION OF X-86 FAMILY

● It's used for small applications like for

calculators, scientific calculators & small
arithmetic operations.
● protected virtual-address mode enabled
Multitasking
● Used as an in-circuit emulator.
● Memory unit was subdivided into a
Segmentation unit and Paging unit.
● Faster math calculation due to 8Kbyte code
and data cache.
● Used in modems, telephone, digital telephone
sets, and also in air reservation systems and
railway reservation systems.[3]

X. CONCLUSION
In this article I have discussed briefly about all the
arithmetic and logical instructions of X-86
microprocessors and all the registers are shown in
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