Expt.

No:1 DESIGN OF HALF ADDER AND FULL ADDER

Date :

AIM:

To Design the Half adder & Full Adder using Verilog HDL. Simulate it using
Xilinx Software and implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:
i. Open Xilinx ISE software and create a project folder in a desired directory.

ii. Now, right click on project as new source add a Verilog HDL Module and name it
accordingly.
iii. Type the Verilog coding in the source page and save it to the directory.

iv. Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.

v. Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
vi. Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

vii. Assign package pins in user constraints view or add .ucf file for existing project.
viii. Run the implement design part to get the overall synthesis report.

ix. Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
x. Check the output by varying the corresponding switches.
1
Page
HALF ADDER:

LOGIC DIAGRAM:

TRUTH TABLE:

--------------------------------------------------

Input1 Input2 Sum C_out

---------------------------------------------------
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
----------------------------------------------------
SIMULATED WAVEFORM:

2
Page
 PROGRAM:

Half Adder:

module HalfAddr(sum, c_out, i1, i2);

output sum, c_out;
input i1; input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule

Full Adder:

module FullAddr(i1, i2, c_in, c_out, sum);

input i1, i2, c_in;
output c_out, sum; wire
s1,c1,c2; xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule

3
Page
FULL ADDER
LOGIC DIAGRAM:

TRUTH TABLE:

----------------------------------------------
Input1 Input2 C_in Sum C_out
--------------------------------------------------
0 0 0 0 0
0 0 1 1 0 \
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SIMULATED WAVEFORM:
4
Page
RESULT:
5

Thus, the simulation of Half adder & Full Adder using Verilog HDL was performed and output
Page

were verified using XILINX FPGA.

BLOCK DIAGRAM FOR 8 BIT ADDER

6
Page
Expt. No:2 DESIGN AN 8 BIT ADDER USING VERILOG HDL
Date :

AIM:

To Design the 8-bit adder using Verilog HDL. Simulate it using Xilinx Software
and implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:
i. Open Xilinx ISE software and create a project folder in a desired directory.

ii. Now, right click on project as New source add a Verilog HDL Module and name it
accordingly.
iii. Type the Verilog coding in the source page and save it to the directory.

iv. Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.

v. Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
vi. Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

vii. Assign package pins in user constraints view or add .ucf file for existing project.
viii. Run the implement design part to get the over all synthesis report.

ix. Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
x. Check the output by varying the corresponding switches.
7
Page
SIMULATED WAVEFORM FOR 8-BIT ADDER:

8
Page
PROGRAM:

8-bit adder Behavioral Modelling:

module adder(a,b, s,c);

input [7:0] a,b;
output [7:0] s,c;
assign {c,s} = a + b;
endmodule

8-bit adder Structural Modelling:

module ripple_adder(X, Y, S, Co);

input [7:0] X, Y;
output [7:0] S;
output Co;
wire c1, c2, c3,c4,c5,c6,c7;
fulladder u1(X[0], Y[0], 1'b0, S[0], c1);
fulladder u2(X[1], Y[1], c1, S[1], c2);
fulladder u3(X[2], Y[2], c2, S[2], c3);
fulladder u3(X[3], Y[3], c3, S[3], c4);
fulladder u3(X[4], Y[4], c4, S[4], c5);
fulladder u3(X[5], Y[5], c5, S[5], c6);
fulladder u3(X[6], Y[6], c6, S[6], c7);
fulladder u4(X[7], Y[7], c7, S[7], Co);
endmodule

module fulladder(X, Y, Ci, S, Co);

input X, Y, Ci;
output S, Co;
9
Page

wire w1,w2,w3;
Page 10
xor G1(w1, X, Y);
xor G2(S, w1, Ci);
and G3(w2, w1, Ci);
and G4(w3, X, Y);
or G5(Co, w2, w3);
endmodule

11
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Page 12
RESULT:

Thus, the simulation of 8 Bit adder using Verilog HDL was performed and output were verified
using XILINX FPGA.
13
Page
BLOCK DIAGRAM FOR 4 BIT MULTIPLIER

14
Page
Expt. No:3 DESIGN OF 4 BIT MULTIPLIER DESIGN
Date :

AIM:

To Design the 4-bit multiplier using Verilog HDL. Simulate it using Xilinx
Software and implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:
PROCEDURE:
xi. Open Xilinx ISE software and create a project folder in a desired directory.

xii. Now, right click on project as New source add a Verilog HDL Module and name it
accordingly.
xiii. Type the Verilog coding in the source page and save it to the directory.

xiv. Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.

xv. Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
xvi. Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

xvii. Assign package pins in user constraints view or add .ucf file for existing project.
xviii. Run the implement design part to get the over all synthesis report.

xix. Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
xx. Check the output by varying the corresponding switches.
15
Page
SIMULATED WAVEFORM FOR 4 BIT MULTIPLIER:

16
Page
 PROGRAM:
Behavioral Modelling

module multiply( x,y,z);

input [3:0] x;
input [3:0] y;
output [7:0]z ;
assign z = x * y;
endmodule

Structural Modelling

module array4x4(a,b,p);
//inputs
input [3:0]a,b;
//outputs
output [7:0]p;
//wires
wire [39:0]w;
//andgate instantiations
and a1(w[0],a[0],b[0]);
and a2(w[1],a[1],b[0]);
and a3(w[2],a[2],b[0]);
and a4(w[3],a[3],b[0]);
and a5(w[4],a[0],b[1]);
and a6(w[5],a[1],b[1]);
and a7(w[6],a[2],b[1]);
and a8(w[7],a[3],b[1]);
and a9(w[8],a[0],b[2]);
and a10(w[9],a[1],b[2]);
and a11(w[10],a[2],b[2]);
and a12(w[11],a[3],b[2]);
and a13(w[12],a[0],b[3]);
and a14(w[13],a[1],b[3]);
and a15(w[14],a[2],b[3]);
and a16(w[15],a[3],b[3]);
assign p[0]=w[0];
//full adders instatiations
fulladder a17(1'b0,w[1],w[4],w[16],w[17]);
fulladder a18(1'b0,w[2],w[5],w[18],w[19]);
fulladder a19(1'b0,w[3],w[6],w[20],w[21]);
17

fulladder a20(w[8],w[17],w[18],w[22],w[23]);
Page
Page 18
fulladder a21(w[9],w[19],w[20],w[24],w[25]);
fulladder a22(w[10],w[7],w[21],w[26],w[27]);
fulladder a23(w[12],w[23],w[24],w[28],w[29]);
fulladder a24(w[13],w[25],w[26],w[30],w[31]);
fulladder a25(w[14],w[11],w[27],w[32],w[33]);
fulladder a26(1'b0,w[29],w[30],w[34],w[35]);
fulladder a27(w[31],w[32],w[35],w[36],w[37]);
fulladder a28(w[15],w[33],w[37],w[38],w[39]);
//output assignments
assign p[1]=w[16];
assign p[2]=w[22];
assign p[3]=w[28];
assign p[4]=w[34];
assign p[5]=w[36];
assign p[6]=w[38];
assign p[7]=w[39];

endmodule

FULL ADDER
module fulladder(a,b,c,s,ca);
//inputs
input a,b,c;
//outputs
output s,ca;

//full adder assignments.

assign s=(a^b^c);
assign ca=((a&b)|(b&c)|(c&a));
endmodule

RESULT:

Thus, the simulation of 4 Bit multiplier using Verilog HDL was performed and output were
19

verified using XILINX FPGA.

Page
Block Diagram

20
Page
Expt. No:4 DESIGN OF 8 BIT ALU
Date :

AIM:

To Design the 8-bit ALU using Verilog HDL. Simulate it using Xilinx Software
and implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:
i. Open Xilinx ISE software and create a project folder in a desired directory.

ii. Now, right click on project as New source add a Verilog HDL Module and name it
accordingly.
iii. Type the Verilog coding in the source page and save it to the directory.

iv. Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.
v. Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
vi. Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

vii. Assign package pins in user constraints view or add .ucf file for existing project.
viii. Run the implement design part to get the over all synthesis report.

ix. Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
x. Check the output by varying the corresponding switches.
21
Page
Output Waveform

22
Page
Program

module alu(

input [7:0] A,B, // ALU 8-bit Inputs

input [3:0] ALU_Sel,// ALU Selection

output [7:0] ALU_Out, // ALU 8-bit Output

output CarryOut // Carry Out Flag

);

reg [7:0] ALU_Result;

wire [8:0] tmp;

assign ALU_Out = ALU_Result; // ALU out

assign tmp = {1'b0,A} + {1'b0,B};

assign CarryOut = tmp[8]; // Carryout flag

always @(*)

begin

case(ALU_Sel)

4'b0000: // Addition

ALU_Result = A + B ;

4'b0001: // Subtraction

ALU_Result = A - B ;

4'b0010: // Multiplication

ALU_Result = A * B;

4'b0011: // Division

ALU_Result = A/B;

4'b0100: // Logical shift left

ALU_Result = A<<1;
23

4'b0101: // Logical shift right

Page

ALU_Result = A>>1;
Page 24
 4'b0110: // Rotate left

ALU_Result = {A[6:0],A[7]};

4'b0111: // Rotate right

ALU_Result = {A[0],A[7:1]};

4'b1000: // Logical and

ALU_Result = A & B;

4'b1001: // Logical or

ALU_Result = A | B;

4'b1010: // Logical xor

ALU_Result = A ^ B;

4'b1011: // Logical nor

ALU_Result = ~(A | B);

4'b1100: // Logical nand

ALU_Result = ~(A & B);

4'b1101: // Logical xnor

ALU_Result = ~(A ^ B);

4'b1110: // Greater comparison

ALU_Result = (A>B)?8'd1:8'd0 ;

4'b1111: // Equal comparison

ALU_Result = (A==B)?8'd1:8'd0 ;

default: ALU_Result = A + B ;

endcase

end

endmodule
25
Page
Page 26
RESULT:

Thus, the simulation of 8-bit ALU using Verilog HDL was performed and output were verified
using XILINX FPGA.
27
Page
BLOCK DIAGRAM FOR UNIVERSAL SHIFT REGISTER:

Design Description

28
Page
Expt. No:5 UNIVERSAL SHIFT REGISTER DESIGN
Date :

AIM:

To Design the Universal shift register using Verilog HDL. Simulate it using Xilinx
Software and implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:

PROCEDURE:
i. Open Xilinx ISE software and create a project folder in a desired directory.

ii. Now, right click on project as New source add a Verilog HDL Module and name it
accordingly.
iii. Type the Verilog coding in the source page and save it to the directory.

iv. Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.

v. Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
vi. Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

vii. Assign package pins in user constraints view or add .ucf file for existing project.
viii. Run the implement design part to get the over all synthesis report.

ix. Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
x. Check the output by varying the corresponding switches.
29
Page
SIMULATED WAVEFORM FOR UNIVERSAL SHIFT REGISTER:

30
Page
 PROGRAM:

module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);

output reg [7:0] op;
input load;
input [1:0] sh_ro_lt_rt;
input [7:0] ip;
input clk, rst_a;

reg [7:0]temp;

always @(posedge clk or posedge rst_a)

begin
if (rst_a)
op = 0;
else
case(load)
1'b1:
begin //Load Input
temp = ip;
end
1'b0: //Operation
case (sh_ro_lt_rt)
2'b00: op = temp<<1; //Left Shift
2'b01: op = temp>>1; //Right Shift
2'b10: op = {temp[6:0],temp[7]}; //Rotate Left
2'b11: op = {temp[0], temp[7:1]}; //Rotate Right
default: $display("Invalid Shift Control Input");
endcase

default: $display("Invalid Load Control Input");

endcase
end
endmodule

RESULT:
31

Thus, the simulation of Universal Shift Register using Verilog HDL was performed and output
were verified using XILINX FPGA.
Page
MOORE STATE MACHINE STATE DIAGRAM

MEALY STATE MACHINE STATE DIAGRAM

32
Page
Expt. No:6 DESIGN OF FINITE STATE MACHINE
Date :

AIM:

To Design the finite state machine using Verilog HDL. Simulate it using Xilinx
Software and implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:

PROCEDURE:
i. Open Xilinx ISE software and create a project folder in a desired directory.

ii. Now, right click on project as New source add a Verilog HDL Module and name it
accordingly.
iii. Type the Verilog coding in the source page and save it to the directory.

iv. Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.

v. Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
vi. Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

vii. Assign package pins in user constraints view or add .ucf file for existing project.
viii. Run the implement design part to get the over all synthesis report.

ix. Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
x. Check the output by varying the corresponding switches.
33
Page
SIMULATED WAVEFORM FOR MOORE MACHINE

SIMULATED WAVEFORM FOR MOORE MACHINE

34
Page
PROGRAM

MOORE MACHINE:

module fsm_moore ( clk, rst, inp, outp);

input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
2'b10:
begin
35

if( inp ) state <= 2'b01;

Page
Page 36
else state <= 2'b11;
end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end
endmodule

37
Page
Page 38
PROGRAM

MEALY MACHINE:

module fsm_melay( clk, rst, inp, outp);

input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst ) begin
if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
end

2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end

end
2'b10: begin
39

if( inp ) begin

Page

state <= 2'b01;

Page 40
 outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;

end

end

default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule

RESULT:

Thus, the simulation of Moore and Mealy State Machine using Verilog HDL was performed
and output were verified using XILINX FPGA.
41
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Page 42
Expt. No:7 DESIGN OF MEMORY
Date :

AIM:

To Design the memory using Verilog HDL. Simulate it using Xilinx Software and
implement by Xilinx FPGA.

APPARATUS REQUIRED:

 Desktop Computer.
 XILINX Software.
 Spartan FPGA Trainer Kit

PROCEDURE:

PROCEDURE:
i) Open Xilinx ISE software and create a project folder in a desired directory.

ii) Now, right click on project as New source add a Verilog HDL Module and name it
accordingly.
iii) Type the Verilog coding in the source page and save it to the directory.

iv) Now, check the syntax in Xilinx ISE Simulator, and succeed with no errors, if any just
correct the errors and rerun the process.

v) Now, choose on views, simulation then simulate the behavioral model and force the
constant values to the inputs and run the signals or add a test bench file for existing project.
vi) Check the signals accordingly for the procedure written in verilog HDL coding and view
the RTL-Schematic in implementation type view for the functional coding achieved.

vii) Assign package pins in user constraints view or add .ucf file for existing project.
viii) Run the implement design part to get the over all synthesis report.

ix) Run the generate programming file. Add the bit file to the device by connecting PC to
trainer kit using JTAG.
x) Check the output by varying the corresponding switches.
43
Page
SIMULATED WAVEFORM OF MEMORY

44
Page
PROGRAM:

module memory_16x4_bi(data, clk, out_en, address, rd_en, wr_en );

inout [0:3] data;
input clk;
input out_en;
input rd_en, wr_en;
input [0:3] address;
reg [0:3] memory [0:15];
reg [0:3] data_out;

assign data = out_en ? data_out : 4'bZ;

always@(posedge clk)
begin
if(rd_en)
data_out = memory[address];
else if (wr_en)
memory[address] = data;
else data_out = 4'bx;

end

endmodule

45
Page
Page 46
RESULT:

Thus, the simulation of memory using Verilog HDL was performed and output were verified
using XILINX FPGA.
47
Page
INVERTER

Schematic:

Input Output Waveforms:

48
Page
Exp.8 Automatic Layout Generation of CMOS Inverter

Date :

Aim:

To design the CMOS inverter circuit using microwind and perform the automatic layout
generation.

Tools Required:

 Microwind DSCH
 Microwind 3.1

Procedure:

i) Open DSCH 2 and create a new file

ii) Using symbol library drag and drop the circuit elements on the workspace
iii) Make the circuit connections using “add a line”
iv) Use button as input for enable and light as output
v) Save and simulate the design, simulation control can be adjusted for operating speed
vi) View the timing diagram for functional verification
vii) From the file menu use “make verilog file” for the schematic and save the file, this is
used to generate the layout
viii) Open Microwind 3.1 and create a new file.
ix) From menucompilecompileverilog file and select the Verilog file created for the
designGenerate and back to editor, the layout will be created automatically
x) To perform parasitic extraction use “view electrical node” and select input and output
node in the layout.

49
Page
Layout Generation for CMOS Inverter

50
Page
RESULT:

Thus, the CMOS inverter circuit have designed using micro wind and performed the automatic
layout generation.
51
Page
CMOS NAND GATE

Schematic:

52
Page
Exp.9 Automatic Layout Generation of Gates and Flipflops

Date:

Aim:

To design the CMOS Gates and Flipflops using microwind and perform the automatic layout
generation.

Tools Required:

 Microwind DSCH
 Microwind 3.1

Procedure:

i. Open DSCH 2 and create a new file

ii. Using symbol library drag and drop the circuit elements on the workspace
iii. Make the circuit connections using “add a line”
iv. Use button as input for enable and light as output
v. Save and simulate the design, simulation control can be adjusted for operating speed
vi. View the timing diagram for functional verification
vii. From the file menu use “make verilog file” for the schematic and save the file, this is
used to generate the layout
viii. Open Microwind 3.1 and create a new file.
ix. From menucompilecompileverilog file and select the Verilog file created for the
designGenerate and back to editor, the layout will be created automatically
x. To perform parasitic extraction use “view electrical node” and select input and output
node in the layout.

53
Page
Input Output Waveforms:

54
Page
Page 55
Layout Generation for CMOS NAND

CMOS NOR GATE

Schematic:

56
Page
Page 57
Input Output Waveforms:

Layout Generation for CMOS NOR

58
Page
Page 59
D FLipflop

Schematic:

Input Output Waveforms:

60
Page
Page 61
Layout Generation for D FLipflop

62
Page
RESULT:

Thus, the gates and flipflops have designed using micro wind and performed the automatic
layout generation.
63
Page
4-bit Synchronous Counter Schematic:

64
Page
Exp.10 Automatic Layout Generation of 4-bit synchronous counter

Aim:

To design the 4-bit synchronous counter circuit using microwind and perform the automatic
layout generation.

Tools Required:

 Microwind DSCH
 Microwind 3.1

Procedure:

i. Open DSCH 2 and create a new file

ii. Using symbol library drag and drop the circuit elements on the workspace
iii. Make the circuit connections using “add a line”
iv. Use button as input for enable and light as output
v. Save and simulate the design, simulation control can be adjusted for operating speed
vi. View the timing diagram for functional verification
vii. From the file menu use “make verilog file” for the schematic and save the file, this is
used to generate the layout
viii. Open Microwind 3.1 and create a new file.
ix. From menucompilecompileverilog file and select the Verilog file created for the
designGenerate and back to editor, the layout will be created automatically
x. To perform parasitic extraction use “view electrical node” and select input and output
node in the layout.

65
Page
Input Output Waveforms:

Layout Generation for CMOS Inverter

66
Page
RESULT:

Thus, the 4-bit synchronous counter have designed using micro wind and performed the
automatic layout generation
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INVERTER

Schematic:

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Exp.11 SPICE SIMUALTION OF CMOS INVERTING AMPLIFIER

Aim:

To design the CMOS inverting amplifier using microwind and observe the DC,transisent
responses, calculate CMRR.

Tools Required:

 Microwind DSCH
 Microwind 3.1

Procedure:

i. Open DSCH 2 and create a new file

ii. Using symbol library drag and drop the circuit elements on the workspace
iii. Make the circuit connections using “add a line”
iv. Use button as input for enable and light as output
v. Save and simulate the design, simulation control can be adjusted for operating speed
vi. View the timing diagram for functional verification
vii. From the file menu use “make verilog file” for the schematic and save the file, this is
used to generate the layout
viii. Observe the DC, transient responses and calculate CMRR.

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RESULT:

Thus, the simple CMOS inverting amplifier was designed, DC and transient analysis were done,
and CMRR was obtained from the results.
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MOS Differential amplifier:

Circuit:

Input Output Waveforms:

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Exp.12 SPICE SIMUALTION OF MOS DIFFERENTIAL AMPLIFIER.

Aim:

To design the MOS Differential amplifier using microwind and observe the DC,transisent
responses, calculate CMRR.

Tools Required:

 Microwind DSCH
 Microwind 3.1

Procedure:

i. Open DSCH 2 and create a new file

ii. Using symbol library drag and drop the circuit elements on the workspace
iii. Make the circuit connections using “add a line”
iv. Use button as input for enable and light as output
v. Save and simulate the design, simulation control can be adjusted for operating speed
vi. View the timing diagram for functional verification
vii. From the file menu use “make verilog file” for the schematic and save the file, this is
used to generate the layout
viii. Observe the DC, transient responses and calculate CMRR.

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Frequency response :

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RESULT:

Thus, the simple MOS Differential amplifier was designed, DC and transient analysis were done,
and CMRR was obtained from the results.
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RING OSCILLATOR SCHEMTIC AND TIMING DIAGRAM:

LAYOUT OF RING OSCILLATOR:

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Exp.13 SIMULATION AND AUTOMATIC LAYOUT GENERATION OF
OSCILLATOR

Aim:

To design ring oscillator, simulate, generate layout and extract the parasitic elements.

Tools Required:

 Microwind DSCH
 Microwind 3.1

Procedure:

i. Open DSCH 2 and create a new file

ii. Using symbol library drag and drop the circuit elements on the workspace
iii. Make the circuit connections using “add a line”
iv. Use button as input for enable and light as output
v. Save and simulate the design, simulation control can be adjusted for operating speed
vi. View the timing diagram for functional verification
vii. From the file menu use “make verilog file” for the schematic and save the file, this is
used to generate the layout
viii. Open Microwind 3.1 and create a new file.
ix. From menucompilecompileverilog file and select the Verilog file created for the
designGenerate and back to editor, the layout will be created automatically
x. To perform parasitic extraction use “view electrical node” and select input and output
node in the layout.

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PARASTIC EXTRACTION:

Input node

Output node:

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Result:

Thus ring oscillator was designed and verified in DSCH, layout was generated automatically and
parasitic extraction was done.
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