Bee Kid

Câu 1: Given 8-bit floating point format:

1 (sign) + 3 (exponent) + 4 (mantissa)
Convert the 8-bit floating point number 57 (in hex) to decimal.
5716 = 0101 0111
Sign: 0
Exponent: 1012 = 510
Bias: 23−1 − 1 = 3
E=5–3=2
7
Mantisa: 01112 = 2−2 + 2−3 + 2−4 =
16
7
Value: (−1)0 (1 + 16) 22 = 5,75

Câu 2: A system programmer needs to divide ­6247 by 300 (decimal). Instruct him
to code in debug (number must be in hex) and the result should be?
MOV AX, E799
CWD
MOV BX, 012C
IDIV BX
Result: AX = FFEC; DX = FF09

Câu 3: Write mask byte (in hex) to clear the lower 4 bit of a byte value with AND
instruction.
1111 00002 = 𝐹016

Câu 4: To isolate one or more bits in a byte value, use AND instruction.

Câu 5: EAX now stored a 32-bit IP address of a host. The network ID (netID) is 20 bit
and can be extracted from IP byte anding with a 32-bit mask. Write correct
instruction to extract netID from EAX register.
MOV EAX, FFFFF000

Câu 6: The following sequence of instructions are executed. What is the correct
values at watch point?
MOV AX, 67FE
MOV BX, AX BH = 6716 BL = FE16
MOV CL, BH CL: 6716
MOV CH, BL CH: FE16
Result: CX = FE67; BX = 67FE
 Bee Kid

Câu 7: The following sequence of instructions are executed. What is the correct
value of flag bits at watch point?
MOV EAX, 12AE
SUB EAX, 12AF 12AE – 12AF = FFFF16 = -110
Sign flag: set
Zero flag: reset
Carry flag: set
0001 0010 1010 1110
-
0001 0010 1010 1111
1 1111 1111 1111 1111

Câu 8: Physical address of the stack pointer is 2DA82, stack segment located at
1DAE. Computer the value of SP register?
1𝐷𝐴𝐸16 = 759810
2𝐷𝐴8216 = 18701010
Address = 16 * segment + offset = 16 * SS + SP
Value of SP: 187010 − 16 ∗ 7598 = 6544210 = 𝐹𝐹𝐴216

Câu 9: Match the following hexadecimal numbers to octal.

𝐸716 = 3478
6𝐸16 = 1568
𝐴916 = 2518

Câu 10: Enter debug command to fill 256 bytes in data segment starting from 100
with value 0D
f 100 1FF 0D
1𝐹𝐹16 = 10016 + 10016 − 1

Câu 11: Given 8-bit floating point format:

1 (sign) + 3 (exponent) + 4 (mantissa)
Convert the 8-bit floating point number E7 (in hex) to decimal.
𝐸716 = 1110 01112
Sign: 1
Exponent: 1102 = 610
Bias: 23−1 − 1 = 3
E=6–3=3
7
Mantisa: 01112 = 2−2 + 2−3 + 2−4 = 16
7
Value: (−1)1 ∗ (1 + 16) ∗ 23 = −11,5

Câu 12: Match the correct answer for binary operations on the left
1111111 ­ 111 = 1111000
 Bee Kid

1100111 ­ 111 = 1100000

1010101 + 10101 = 1101010
1010110 ­ 101 = 1010001
1110011 + 11001 = 10001100
1111111 + 11111 = 10011110

Câu 13: Convert the following binary numbers to hexadecimal

101010012 = 𝐴916
011011102 = 6𝐸16
111001012 = 𝐸516
111001112 = 𝐸716

Câu 14: The following sequence of instructions are executed. What is the correct
value of CF and OF at watch point?
MOV AX, 140h
MOV CX, 8h
MUL CX AH = 0A; AL = 00h
Result: CF = Reset; OF = Reset
0001 0100 0000
*
0000 0000 1000
0 1010 0000 0000

Câu 15: To test one bit in a byte value without destructing the byte, use TEST
instruction.

Câu 16: Given a row of memory image in debug

0AE8:0120 13 96 D0 E0 D0 E0 A2 1E ­ 99 80 3E 20 99 00 75 24
Initially, AX = BX = CX = DX = 0, SI = 121
What are value of CX, DX after execution of the following instructions?
MOV DX, [SI]
MOV CX, [SI+2]
Result: CX = D0E0; DX = D096

Câu 17: Select correct match for register values at watch points:
MOV AX, 152D
ADD AX, 003F AX = 156C
watch point #1:
ADD AH, 10 AX = 256C
watch point #2:
.....
Watch point #1: AH = 15 AL = 6C
Watch point #2: AH = 25 AL = 6C
 Bee Kid

Câu 18: A memory location located in extra segment which now has value of 564F.
This memory managed by ES:SI register­pair. SI now points to 905F. Compute the
physical address of this memory
location
Address = 16 * segment + offset = 16 * SS + SP = 16 * 564F + 905F = 5F54F

Câu 19: Select correct match for AL and carry flag at watch point #1:
MOV BL, 8C BL = 8C
MOV AL, 7E AL = 7E
ADD AL, BL AX = 010A AH = 01 AL = 0A
watch point #1:
Result: AL = 0A CF = set
1000 1100
+
0111 1110
1 0000 1010

Câu 20: Convert the 32-bit floating-point number C4361000 (in hex) to decimal.
𝐶436100016 = 1100 0100 0011 0110 0001 0000 0000 00002
32-bit: 1-bit sign + 8-bit exponent + 23-bit mantissa
Sign: 1
Exponent: 100 0100 02 = 13610
Bias: 28−1 − 1 = 127
E = 136 – 127 = 9
865
Mantissa: 011 0110 0001 0000 0000 0000 = 2−2 + 2−3 + 2−5 + 2−6 + 2−11 = 2048
865
Result: (−1)1 (1 + 2048) 29 = −728,25

Câu 21: Which of the following instructions are not legal addressing?
Select one or more:
MOV AX, [DI]
MOV AX, [BX + SP]
MOV AX, [SP + 1]
MOV CX, [SI]

Câu 22: Compute the physical address of stack top if stack pointer is FFAE and stack
segment located at 1DAE
Address: 16 * SS + SP = 16 * segment + offset = 1016 ∗ 1𝐷𝐴𝐸 + 𝐹𝐹𝐴𝐸 = 2𝐷𝐴8𝐸

Câu 23: Sign­extend number 1011 0101 (8­bit binary) to 16­bit

1111 1111 1011 0100
 Bee Kid

Câu 24: The following sequence of instructions are executed. What is the correct
value of AX, CX, DX at watch point?
MOV AX, 30 AX = 001E
MOV CX, FFFF CX = FFFF
MUL CX AX = FFE2; DX = 001D
watch point:
Result: AX = FFE2 CX = FFFF DX = 001D

Câu 25: Write mask byte (in hex) to set bit 6th, 4th of a byte value with OR
instruction (LSB is the 1st bit).
0010 1000 = 2812

Câu 26: Consider the following assembly instruction sequence

XOR BX, BX BX = 0
CMP DL, 5 DL = 10 = 0Ah; BX = 10h + 1h = 11h
JLE a_label DL = 17h (a_label); BX = 0h + 1h = 1h
CMP DL,17h DL = 0FFh (a_label) BX = 0h + 1h = 1h
JGE a_label
MOV BX, 10h
a_label:
INC BX
watch point:
...
Choose correct value of BX register at watch point for different value of DL
DL = 10 → BX = 11h
DL = 17h → BX = 1h
DL = 0FFh → BX = 1h
DL = 0Ah → BX = 11h

Câu 27: Choose correct features for SRAM and DRAM

DRAM: Slower access time, cheaper cost per bit, can manufacture with large size
SRAM: Faster access time, cost more per bit, smaller size

Câu 28: Consider a 16-bit microprocessor, with a 16-bit external data bus, driven
by an 10-MHz input clock. Assume that this microprocessor has a bus cycle whose
minimum duration equals four input clock cycles. What is the maximum data
transfer rate across the bus that this microprocessor can sustain?
1
Cycle clock = seconds
10𝑀
1
1 bus cycle has 4 input clock cycles → 1 bus cycle = 4. 10𝑀 seconds
16-bit → 2 Bytes
1
Maximum data: 2/ (4. 10𝑀) = 5.106 𝑏𝑦𝑡𝑒𝑠/𝑠𝑒𝑐𝑜𝑛𝑑 = 5𝑀𝐵/𝑠
 Bee Kid

Câu 29: The memory stack area of a program shown in figure. The value of SP
register is 1D50. What is the value of SP follows the execution of PUSH SI

Address 1D50 1D51 1D52 1D53

Value AF 90 71 DA
SP = 1D50 – 2 = 1D4E

Câu 30: A benchmark program is run on a 40Mhz processor. The executed program
consists of 100000 instructions executions, with the following instructions mix and
clock cycle count:
Calculate MIPS rate for this program

Instruction Type Instruction Count Cycles per Instruction

Integer airthmetic 45000 1

Data transfer 32000 2

Floating point 15000 2

Control transfer 8000 2

45000.1 + 32000.2 + 15000.2 + 8000.2
𝐶𝑃𝐼 = = 1,55
100000
𝐼𝑐 𝑓 40.106 800
𝑀𝐼𝑃𝑆 = 6
= 6
= 6
= = 25,80645161
𝑇. 10 𝐶𝑃𝐼. 10 1,55.10 31

Câu 31: Choose the correct structure of memory chip as shown

below

𝐴0 → 𝐴10 = 11 𝑏𝑢𝑠 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 → 211

𝐷1 → 𝐷8 = 8 𝑏𝑢𝑠 𝑑𝑎𝑡𝑎 → 8
Structure: 2K x 8-bit
 Bee Kid

Câu 32: What is the correct value of SI, AL (in hex) at watch point:
01: MOV SI, 300h
02: MOV AL, 10h AX = 0010
03: MOV CX, 7 CX = 0007
04: Loop_label:
05: MOV [SI], AL
06: ADD AL, 10h
07: INC SI
08: LOOP Loop_label
watch point:
Result: SI = 307h AL = 70h

Câu 33: The principle of cache memory relies on key features: locality of reference
which involves spatial and temporal locality. Match the definition to keywords on
the left
Temporal locality
- The tendency for a processor to access memory locations that have been used recently
- Be exploited by keeping recently used instruction and data in cache memory and by exploiting
a cache hierarchy
Spatial locality:
- The tendency of execution to involve a number of memory locations the are clustered. The
tendency to use large cache and prefetch mechanism
- be exploited by using larger cache blocks and by incorporating prefetching mechanisms into
the cache control logic

Câu 34: For memory hierarchy below, which relationship hold when moving
downward
Increasing access time
Decreasing cost per bit
Decreasing frequency of access by the processor
Increasing capacity

Câu 35: Given 8-bit floating-point binary format:

1 (sign) + 3 (exponent) + 4 (mantissa)
Convert the 8-bit floating point number 68 (in hex) to decimal.
6816 = 0110 10002
Sign: 0
Exponent: 1102 = 6
Bias: 23−1 − 1 = 3
E=6–3=3
1
Mantissa: 10002 = 2−1 =
2
 Bee Kid

1
Result: (−1)0 (1 + ) 23 = 12
2

Câu 36: In computer organization, the CPU transfer rate is much higher than that
of memory. It is easy to match performance of these components by:
Select one:
increase the bus speed
increase I/O speed
producing faster memory module
Introducing cache memory

Câu 37: The instruction that loads the AH register with the lower byte of the flag
register is LAHF
LAHF = load AH from flag
SAHF = store AH to flag
PUSHF = push flag to stack

Câu 38: Which are correct about 32-bit index registers of IA-32 processors:
Select one or more:
☐ESH, EDH: 16-bit pointers to higher memory above 1M
☒SI: 16-bit pointer to source memory in data movement instructions
☒ESI: 32-bit pointer to source memory in data movement instructions
☒EDI: 32-bit pointer to destination memory in data movement instructions
☒DI: 16-bit pointer to destination memory in data movement instructions

Câu 39: The following sequence of instructions are executed. What is the correct
value of flag bits at watch point?
MOV AL, 0F AL = 0000 1111
ADD AL, F1 AL (8-bit) = 0000 1111 + 1111 0001 = 1 0000 0000
Result: ZF = set; CF = set;

Câu 40: What is the correct sequence of instruction cycle?

Step 1: Fetch opcode (Fetch instruction) (aka – pre – fetch)
Step 2: Decode
Step 3: Calculate operand address (evaluate address) (address generation)
Step 4: Fetch operand (read memory data)
Step 5: Execution (ALU access)
Step 6: Store result (write back memory data)
 Bee Kid

Câu 41: To encrypt a byte value, use XOR instruction.

Câu 42: Which of the following instructions are not valid?

Select one or more: for segment registers only these types of MOV are supported:
SS:SP; SS:BP
☐MOV AX, SI
MOV SREG, memory MOV memory, SREG
☐MOV AX, [BP + 2]
MOV REG, SREG MOV SREG, REG
☒MOV DS, B800h
SREG: DS, ES, SS, and only as second operand: CS.
☒MOV SP, SS : [SI + 2] REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
Không thể gắn địa chỉ cho memory: [BX], [BX+SI+7], variable
thanh ghi segment

Câu 43: 8088 is 16-bit processor, the maximum addressable memory is: 1MB =
1024KB
8088 has 8-bits datas and 20-bits addresses

Câu 44: Select correct definition of seek time, rotational delay, access time,
transfer time for hard drives with moveable-head system:
Access time: transfer time
Rotational delay: time for the sector in the request track to reach the head
Seek time: time for the head to settle at the request track

Câu 45: Which of the following instructions are not legal addressing?
Select one or more:
☒MOV AX, [SP + 1]
☐MOV AX, [DI]
☐MOV CX, [SI]
☒MOV AX, [BX + SP]
Chỉ lấy giá trị của SP, không thể lấy địa chỉ của SP

Câu 46: A memory chip has 12 address pins, determine the maximum memory
words of this chip?
212 = 4096

Câu 47: Convert 0.1015625 to IEEE 32-bit floating point format (1 sign + 8 exponent
+ 23 mantissa)
Convert to Binary: 0,0001101 = 1,101.10−4
Mantissa: 101 0000 0000 0000 0000 0000
Exponent: −4 + 28−1 − 1 = 12310 = 0111 10112
Sign: 0
Result: 0011 1101 1101 0000 0000 0000 0000 00002 = 3𝐷𝐷0000016
 Bee Kid

Câu 48: Structural components of computer include:

Select one or more:
☒Memory
☒Central processing unit
☒I/O
☐DMA
☐Interrupt
☒System interconnection

Câu 49: Select the correct sequence of instructions to compute -1024/128 (all
values are in hex).
MOV AX, FC00 AX = FC00
CWD Convert Word to DoubleWord
MOV CX, 80h CX = 0080h
IDIV CX AX = FFF8 DX = 0000

Câu 50: Sign-extend number 1011 0101 (8-bit binary) to 16-bit

1111 1111 1011 01012 = 𝐹𝐹𝐵516

Câu 51: Part of computer memory is shown in figure. What is the value of AX
register after instruction MOV AX, [1D4B] execute

Address 1D48 1D49 1D4A 1D4B 1D4C 1D4D 1D4E 1D4F

Value 03 7F F5 2D 5A 12 7B C0
AX = 5A2D

Câu 52: Choose correct RAID volume definitions for a request 2T storage.
RAID 0 Striped volume: 2 x 1T HDDs are needed, enhance data transfer, no fault tolerance,
data lost when one HDD fails
RAID 1 Mirror volume: 2 x 2T HDDs are needed, no data lost when the primary storage fails
Spanned Volume: 2T HDD + more HDDs to extend storage, no fault tolerance, data lost
when one HDD fails
RAID5 Volume: At least 3 x 2T HDDs, fault-tolerance, no data lost, no down-time

Câu 53: Select correct level for contemporary computer multilevel machine
Level 0: Digital logic level
Level 1: Microarchitecture level
Level 2: Instruction set level
Level 3: Operating system level
Level 4: Assembly Language level
 Bee Kid

Level 5: High level programming language

Level 6: Applications

Câu 54: the instruction, CMP to compare source and destination operands by
Subtracting

Câu 55: Write mask byte (in hex) to clear bit 2nd, 3rd, 5th of a byte value with AND
instruction (LSB is 1st bit).
1110 1001 = 𝐸916

Câu 56: To evaluate processor performance, the following indicators and formulas
are used:
∑𝒏
𝒊=𝟏 𝑪𝑷𝑰𝒊 ∗𝑰𝒊
Cycles in Instruction 𝑪𝑷𝑰 = 𝑰𝒄
Time to execute program 𝑻 = 𝑰𝒄 ∗ 𝑪𝑷𝑰 ∗ 𝝉
Or 𝑻 = 𝑰𝒄 ∗ [𝒑 + (𝒎 ∗ 𝒌)] ∗ 𝝉
In which:
𝒑: the number of processor cycles needed to decode and execute the instruction
𝒎: the number of memory references needed
𝒌: the ratio between memory cycle time and processor cycle time
𝝉: cycle time = 1/f
𝐼𝑐 𝑝 𝑚 𝑘 𝜏
Instruction set architecture x x
Complier technology x x x
Processor implementation x x
Cache and memory hirearchy x x

Câu 57: Which is correct about dual-layer DVD?

Select one:
contains layers on both sides of the disk for writing data to
the same as double-sided DVD
contains two layers on a single side for writing data to
DVD drives has double laser head for reading from or writing to this disk

Câu 58: The following sequence of instructions are executed. What is the correct
value of AX, CX, DX at watch point?
MOV AX, 0020
MOV CX, 0010
MUL CL DX = 0000 AX = 0200
watch point:
Result: AX = 0200 CX = 0010 DX = 0000
 Bee Kid

Câu 59: In multiplication instruction, the upper half of the result is nonzero implies
which state of Carry flag and Overflow flag?
Select one or more:
☐CF=0
☒OF=1
☐OF=0
☒CF=1

Câu 60: Which statements are correct for HDDs?

Select one or more:
☒Head, Track, Sector are key parameters for access data on hard disk
☐Head, Track, Cylinder are key parameters for access data on hard disk
☒Bits are stored on tracks
☐Bits are store randomly on disk surfaces

Câu 61: Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and
64 sectors per track. Sector size is 1 kB. What is the disk capacity
Disk capacity: 1 ∗ 64 ∗ 512 ∗ 8 ∗ 1 = 262144𝐾𝐵 = 256𝑀𝐵
Disk capacity = (bytes/sector) * (avg. sectors/ track) * (tracks/ surface) * (surfaces/ platter) * (platters/
disk)

Câu 62: Which are the correct inputs for XLAT instruction
Select one or more:
☒look-up index must be loaded into AL
☐look-up index must be loaded into DL
☒DS : [BX] pointed to look-up table
☐DS : [SI] pointed to look-up table

Câu 63: A benchmark program is run on a 40MHz processor. The execute program
consists of 100000 instructions executions, with the following instructions mix and
clock cycle count. Calculate the execution time for this program

Instruction Type Instruction Count Cycles per Instruction

Integer airthmetic 45000 1

Data transfer 32000 2

Floating point 15000 2

Control transfer 8000 2

45000.1 + 32000.2 + 15000.2 + 8000.2
𝐶𝑃𝐼 = = 1,55
100000
 Bee Kid

𝐼𝑐 ∗ 𝐶𝑃𝐼 100000.1,55 31
𝐶𝑃𝑈 𝑡𝑖𝑚𝑒 = 𝐼𝑐 ∗ 𝐶𝑃𝐼 ∗ 𝜏 = = 6
= = 3,875.10−3
𝑓 40.10 8000

Câu 64: In multiplication instruction, when the source operand is 8 bit, _________ will
be multiplied with source.
Select one:
BX
AL
AX
Whatever general purpose register

Câu 65: Which are the correct actions for LODSW string operation if DF is reset (=0).
Select one or more:
☒Load 16-bit value at memory location pointed by DS : [SI] into AX
☐decrease DI by 2
☐Load 16-bit value at memory location pointed by ES : [DI] into AX
☒increase SI by 2
LODSB: AL ← [DS:SI]
Nếu DF=0 thì : SI ← SI + 1
ngược lại thì : SI ← SI - 1
LODSW: AX ← [DS:SI+1,DS:SI]
Nếu DF=0 thì : SI ← SI + 2
ngược lại thì : SI ← SI – 2

Câu 66: A system programmer needs to compute 449/2+358/4 (decimal). Instruct

him to code in debug (number must be in hex) with the least number of instruction
counts.
MOV AX, 166h
MOV CL, 2
SHR AX, CL AX = 259h
MOV BX, 1C1h
SHR BX, 1 BX = 1E0h
ADD AX, BX

Câu 67: The instruction that loads the AH register with the lower byte of the flag
register is
Select one:
LAHF
PUSHF
AH
SAHF
 Bee Kid

Câu 68: For better speed, in CPU design, engineers make use of the following
techniques:
Select one or more:
☒Speculative execution
☒Branch prediction
☒Pipelining
☐Faster CPU internal bus

Câu 69: Which ones are not correct for static RAM?
Select one or more:
☒Cheaper than dynamic RAM because simpler chip controller
☒Cost per bit is lower than dynamic RAM
☒faster than dynamic RAM because they are made from capacitor
☐Cost per bit is higher than dynamic RAM

Câu 70: Match the correct definition of flag bits in PSW.

indicates the result of an arithmetic or comparison operation ZF
contains the carry from bit 3 to bit 4 following an arithmetic operation AF
indicates the overflow of leftmost bit of data after an arithmetic operation OF
shows the sign of the result of an arithmetic operation SF

Câu 71: A system programmer needs to compute 163250 % 32767 + 257 (decimal).
Instruct him to code in debug (number must be in hex) and the result should be?
MOV EAX, 27DB2
MOV BX, 7FFF
DIV BX EDX =00007DB6 EAX = 00000004
ADD EDX, 101h EDX = 7EB7
Cộng vào phần dư

Câu 72: Convert the 32-bit floating point number 3E580000 (in hex) to decimal.
3𝐸58000016 = 0011 1110 0101 1000 0000 0000 0000 00002
Sign: 0
Exponent: 011 1110 02 = 12410
Bias: 28−1 − 1 = 127
E = 124 – 127 = – 3
11
Mantissa: 101 1000 0000 0000 0000 00002 = 2−1 + 2−3 + 2−4 = 16
11
Result: (−1)0 (1 + 16) 2−3 = 0,2109375

Câu 73: Major structural components of the CPU include:

Select one or more:
☐Instruction Pointer (PC)
 Bee Kid

☒Arithmetic and Logic Unit

☒Interconnections
☒Registers
☐Instruction Register
☒Control Unit

Câu 74: Convert the 32-bit floating point number 44363800 (in hex) to decimal.
4436380016 = 0100 0100 0011 0110 0011 1000 0000 00002
Sign: 0
Exponent: 100 0100 02 = 13610
Bias: 28−1 − 1 = 127
E = 136 – 127 = 9
1735
Mantissa: 011 0110 0011 1000 0000 00002 = 2−2 + 2−3 + 2−5 + 2−6 + 2−10 + 2−11 + 2−12 = 4096
1735
Result: (−1)0 (1 + 4096) 29 = 728,875

Câu 75: Select correct match for register values at watch points:
MOV AX, 4FCA AH = 4F AL = CA
ADD AX, DDA9 AX = 2D73
watch point #1:
ADD AH, F3 AX = 2073
watch point #2:
......
watch point #1: AH = 2D AL = 73
watch point #2: AH = 20 AL = 73

Câu 76: Which statement is correct about interrupt vector table?

Select one or more:
☒Store in the beginning area of the main memory
☐Store in the ending area of 1024K of the main memory
☒Take up 1024 bytes in the main memory
☐Store on disk
 Bee Kid

Câu 77: Given an assembly code copying the memory buffer Buff1 to Buff2:
PUSH DS
POP ES
LEA SI, Buff1
LEA DI, Buff2
MOV CX,20
;--- Start of block
Tăng SI, DI nên đang xét theo chiều
cp_loop:
tăng địa chỉ
MOV AL, Byte Ptr [SI]
đang thực hiện việc chuyển địa chỉ
MOV Byte Ptr ES:[DI], AL
SI sang DI
INC SI
INC DI
STD bien DF thanh 1 -> xu ly giam
LOOP cp_loop dia chi
; ---End of block
CLD bien DF thanh 0 -> xu ly tang
Choose equivalent string operations in place of block
dia chi
Select one or more:
☐STD
cp_loop:
MOVSB
LOOP cp_loop
☒CLD REP giong nhu LOOP lap lai neu
𝐶𝑋 ! = 0
cp_loop:
MOVSB MOVSB la chep ESI sang EDI
LOOP cp_loop
☒CLD
REP MOVSB
☒CLD
cp_loop:
REP MOVSB
LOOP cp_loop

Câu 78: Given a code snippet:

int n = 10;
do {
n--;
} while (n > 0);
Which ones are the equivalent logic sequence of instructions in Assembly
Select one or more:
mov cx, 10 mov cx, 10 mov cx, 10 mov cx, 10
a_label: a_label: a_label: a_label:
..... ..... dec cx .....
dec cx dec cx cmp cx, 0 loop a_label
loop a_label jz e_label
 Bee Kid

cmp cx, 0 Lệnh LOOP tự giảm cx jmp a_label

jz a_label e_label:

Câu 79: Make use of string operations, write a sequence of instructions to locate
the last space character on the 10th line of screen by peeking at the display
memory starting from B800. The result is read from the SI register.
MOV BX, 0B800h ; Load base address of display memory
MOV AX, 80 ; Load number of characters per line
MUL 9 ; Multiply by line number (10th line - 1)
ADD BX, AX ; Add result to base address
SUB BX, 2 ; Move to the last character position in the 10th line
FIND_SPACE:
CMP BX, 0 ; Check if we reached the beginning of the display memory
JL NO_SPACE ; If yes, space not found
CMP BYTE PTR [BX], ' ' ; Compare character with space
JE SPACE_FOUND ; Jump if space is found
DEC BX ; Decrement address to check previous character
JMP FIND_SPACE ; Repeat loop
SPACE_FOUND:
MOV SI, BX ; Store address of space character in SI register
JMP AFTER_SEARCH
NO_SPACE:
MOV SI, -1 ; Set SI to a special value (-1) to indicate space not found
AFTER_SEARCH:
; Continue your code here...

Câu 80: Memory dump at 1D20:0200 as below:

1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Given value of registers: DS = 1D20, SI = 200, BX = 202, AX = 0103
Identify correct value of AX register after XLAT instruction is executed.
XLAT instruction is
MOV AH, 0
MOV SI, AX SI = 103
MOV AL, [BX + SI] AL = [205]
Result: AH = 00h (unchanged) AL = 47h AX = 0047h
 Bee Kid

Câu 81: The result of an IMUL instruction is 0060, what is the correct state of Carry
flag and Overflow flag? Select one or more: 1111 0000 0000 0110 0000
☐OF=1
☐CF=1
☒OF=0
☒CF=0

Câu 82: The instruction that enables subtraction with borrow is

Select one:
☐DEC
☐SUB
☐None of the choices are correct
☒SBB
SBB subtract have carry flag
SBB (Subtract Borrow)

Câu 83: After executing PUSH EAX instruction, the stack pointer
Select one:
increment by 1
increment by 2
decrements by 4
decrement by 1

Câu 84: Given 8-bit floating point format:

1 (sign) + 3 (exponent) + 4 (mantissa)
Convert the 8-bit floating point number E8 (in hex) to decimal.
5716 = 1110 10002
Sign: 1
Exponent: 1102 = 610
Bias: 23−1 − 1 = 3
E=6–3=3
1
Mantisa: 10002 = 2−1 =
2
1
Value: (−1)1 (1 + 2) 23 = −12

Câu 85: The following sequence of instructions are executed. What is the correct
value of flag bits at watch point?
MOV DL, FF DL = -110
MOV AL, F6 F6 = -1010
IMUL DL AX = 1010 = 000A16 = 0000 0000 0000 10102
watch point:
Result: CF = reset; OF = reset
 Bee Kid

Câu 86: A SRAM memory chip labeled 32K x 8bit. Which of the following is correct
pinout regarding address and data lines?
Select one:
15 address pins, 8 data pins
32 address pins, 3 data pins
5 address pins, 3 data pins
32 address pins, 4 data pins

Câu 87: In multiplication instruction, the result is taken from AX means the source
operand is 8 bit

Câu 88: Part of memory as shown in figure. The value of BX register follows the
execution of MOV BX, [1D49] is F57F. What is the endian type of this computer
system

Address 1D48 1D49 1D4A 1D4B 1D4C 1D4D 1D4E 1D4F

Value 03 7F F5 2D 5A 12 7B C0
big-endian
level-endian
little-endian
non-endian

Câu 89: The memory stack area of a program shown in figure. The value of SP
register is 1D48. What is the value of SP follows the execution of POP SI
1𝐷48 + 2 = 1𝐷4𝐴

Câu 90: Bus is a shared transmission medium, multiple devices connect to it but
only one at a time can successfully transmit. Which component in computer
facilitates this operation?
Select one:
Bus Arbiter
Direct Memory Access (DMA)
Bus master
Programmed I/O

Câu 91: Which set of registers are valid for addressing a memory location?
Select one or more:
☐SS:DI
☒DS:BX
☒DS:SI
☒CS:IP
 Bee Kid

Câu 92: A processor with 16-bit instruction set. The instruction composed of 2
fields: the first byte contains the opcode and the remainder the operand or an
operand address. What is the maximum directly addressable memory capacity?
The maximum directly addressable memory capacity for this processor is 65,536 bytes
the processor can directly access 256 bytes of memory. → 256

Câu 93: Convert -89.2345 to IEEE 32-bit floating point format (1 sign+ 8 exponent +
23 mantissa) in hex
89,234510 = 0101 1001,0011 1100 0000 1000 0011 0001 0010 0110 1110 1001
= 1,01 1001 0011 1100 0000 1000 0011 0001 0010 0110 1110 1001.106
Mantissa: 01 1001 0011 1100 0000 1000 0
Exponent: 6 + 28−1 − 1 = 133 = 1000 0101
Sign: 1
Result: 1100 0010 1011 0010 0111 1000 0001 00002 = 𝐶2𝐵2781016

Câu 94: Write a sequence of instructions to sum up 10 values of word in memory

starting from 200h. The result must be stored at memory location 300h.
01: MOV [SI] 200h
02: MOV AL, 0
03: MOV CX, 10
04: Loop_label:
05: CWD
06: ADD AX, [SI]
07: INC SI
08: LOOP Loop_label
09: MOV [300h], AX
 Bee Kid

Câu 95: Consider the following assembly instruction sequence

CMP DL, 0 DL = 10 = Ah (a_label) → AL = 0Ah + 37h = 41h
JB x_label DL = 8 = 8h → AL = 8h + 30h = 38h
CMP DL, 9 DL = 55h → AL = 55h
JA a_label DL = FFh → AL = FFh
ADD DL, 30h
JMP x_label
a_label:
CMP DL, 0Fh
JA x_label
ADD DL, 37h
x_label:
MOV AL, DL
watch point:
...
Choose correct value of AL register at watch point for different value of DL?
DL = 10 AL = 41h
DL = 8 AL = 38h
DL = 55h AL = 55h
DL = 0FFh AL = FFh

Câu 96: The following sequence of instructions are executed. What is the correct
value of CF and OF at watch point?
MOV AX, FFF6h 1111 1111 1111 0110 = -10
MOV CX, 1000h 0001 0000 0000 0000 = 4096
IMUL CX DX:AX = FFFF6000
watch point:
Result: CF = set; OF = set

Câu 97: Which could be correct ones for the destination operand in a data
movement instruction?
Select one or more:
☒register
☐immediate data
☒memory location

Câu 98: Given a row of memory image in debug

0AE8:0120 13 96 D0 E0 D0 E0 A2 1E - 99 80 3E 20 99 00 75 24
Initially, AX = BX = CX = DX = 0, SI = 128
What are value of EAX, EDX after execution of the following instructions?
MOV EDX, [SI]
MOV EAX, [SI + 4]
Result: EDX = 203E8099 EAX = 24750099
 Bee Kid

Câu 99: Part of memory shown in figure

What is the value of AH follow the execution of this code:
MOV BX, 1D4D
MOV AX, [BX]

Address 1D48 1D49 1D4A 1D4B 1D4C 1D4D 1D4E 1D4F

Value 03 7F F5 2D 5A 12 7B C0

Result: AX = 7B12 AH = 7B AL = 12

Câu 100: Which are valid based indexed addressing?

Select one or more:
☐[SP][SI]
☒[BX][SI]
☒[BP][SI]
☐[DX][DI]

Câu 101: Part of computer memory are shown in figure.

What is the value of AX register after instruction execut MOV AX, 1D49 executed

Address 1D48 1D49 1D4A 1D4B 1D4C 1D4D 1D4E 1D4F

Value 03 7F F5 2D 5A 12 7B C0
AX = F57F
 Bee Kid

Câu 102: Given a code snippet:

if (a>=0 && a <=9)
x = a + 30h;
else if (a >=10 && a <=15)
x = a + 55;
The logic of the above code snippet in assembly is (with missing lines):
01: CMP DL, 0
02: ------------ ; possibly missing code
03: CMP DL, 9
04: ------------ ; possibly missing code
05: ADD DL, 30h
06: ------------ ; possibly missing code
a_label:
08: CMP DL, 0Fh
09: ------------ ; possibly missing code
10: ADD DL, 55
x_label:
12: MOV AL, DL
...
Choose correct missing instructions in the above sequence of instructions
02: JL x_label
04: JG a_label
06: JMP x_label
09: JG x_label

Câu 103: Given a row of memory image in debug

072C:FFF0 00 00 00 01 00 00 2C 07 - 07 01 2C 07 17 72 00 00
SS=072C, SP=FFF8, DS = 072C
Assume the stack now stores two (2) 16-bit parameters and one (1) 16-bit return
address in following order: stack top (return address) >> parameter #1 >>
parameter #2.
The following sequence of instructions are executed. What is the correct values at
watch points?
MOV BP, SP BP = SP = FFF8
watch point #1 (BP):
MOV AX, [BP+2] AX = [FFF8 + 2] = [FFFA] = 072C
watch point #2 (AX):
ADD AX, [BP+4] AX = 072C + [FFF8 + 4] = 072C + [FFFC] = 072C + 7217 = 7943
watch point #3 (AX):
MOV DI, 120 DI = 120
MOV [DI], AX [DI] = 7943
Watch point #1: BP = FFF8
 Bee Kid

Watch point #2: AX = 072C

Watch point #3: AX = 7943

Câu 104: Given a code snippet to look for a value (from AL) in memory buffer Buff

Buff DB 11,22,33,44,55
................
01: LEA DI, Buff
02: ------------ ; possibly missing code
03: MOV AL,33
04: MOV CX,5
a_label:
05: ------------ ; possibly missing code
06: CMP Byte Ptr [DI],AL
07: ------------ ; possibly missing code
08: LOOPNZ a_label
...
Choose correct missing instructions in the above sequence of instructions
02: Empty
05: INC DI
07: JE exit_label

Câu 105: In multiplication instruction, when the value of source operand is 12

(decimal), the other operand is loaded in AX. Which registers can be used to load
source operand?
Select one or more:
☒DX
☒BX
☐CL
☐AX
☐DL

Câu 106: The following sequence of instructions are executed. What is the correct
value of AX and DX (in hex) at watch point?
MOV AX, FFF6h 1111 1111 1111 0110 = -10
MOV CX, 1000h 0001 0000 0000 0000 = 4096
IMUL CX DX:AX = FFFFF000
watch point:
Result: DX = FFFF AX = 6000
 Bee Kid

Câu 107: To test one bit in a byte value which can be destructive. use AND
instruction.

Câu 108: The following sequence of instructions are executed. What is the correct
value of AX, DX at watch point?
MOV DL, FF DL = FF = -1 DX = 00FF
MOV AL, 42 AL = 2Ah
IMUL DL AX = FFD6
watch point:
Result: AX = FFD6 DX = 00FF

Câu 109: In multiplication instruction, when the source operand is 16 bit, how can
the result be taken?
Select one:
from DX:AX pair
from EAX
from AX:DX pair
from AX

Câu 110: Here after is instruction sequence to compute the sum of 8 bytes starting
at memory address 200. Two lines of code are possibly missing. Choose correct one
to fill in?
01: _____________; possibly missing code
02: MOV AL, 0
03: MOV CX, 8
04: Loop_label:
05: _____________; possibly missing code
06: ADD AX, [SI];
07: INC SI
08: LOOP Loop_label
01: MOV [SI], 200h
05: CWD

Câu 111: Which are valid based index addressing?

Select one or more:
☒[BX + DI]
☐[DX + SI]
☐[SP + DI]
☒[BX + SI]
 Bee Kid

Câu 112: Given a flowchart of an algorithm. Select the correct instruction

sequence:

mov dl,10 x = 10 mov dl,10 mov dl,10 mov dl,10

cmp al, bl cmp al, bl cmp al, bl
cmp al, bl jz n_label jnz n_label jnz n_label
jnz n_label mov cl,1 add dl,10 add dl,10
add dl,10 x = x + 10 shl dl, cl jmp e_label mov dh, dl y = dl
jmp e_label jmp e_label n_label: jmp e_label
n_label: n_label: mov cl,1 n_label:
mov cl,1 cl = 1 add dl,10 shr dl, cl mov cl,1
shl dl, cl dl = x * 21 e_label: e_label: shl dl, cl
e_label: mov dh, dl mov dh, dl e_label:
mov dh,dl dh = dl = mov dh, dl
y

Câu 113: Which set of registers are valid for addressing a stack memory location?

Select one or more:

☐DS:SI
☒SS:SP
☒SS:BP
☐SS:BX

Câu 114: In computer, how does the processor serve multiple interrupt request from
devices?
Select one:
Each device are assigned an interrupt priority, the device with lower priority will be
served.
Device with higher priority will use interrupt enable flag
Each device are assigned an interrupt priority, the device with higher priority will be served.
The processor can not process multiple interrupt requests
 Bee Kid

Câu 115: Given a row of memory image in debug

0AE8:0120 13 96 D0 E0 D0 E0 A2 1E - 99 80 3E 20 99 00 75 24
Initially, AX = BX = CX = DX = 0, SI = 128
What are value of AX, DX after execution of the following instructions?
MOV EDX, [SI] EDX = 203E8099 DX = 8099
MOV EAX, [SI + 4] EAX = 24750099 AX = 0099
Result: DX = 8099 AX = 0099

Câu 116: Basic functions that a computer can perform including:

Select one or more:
☒Data movement
☒Control
☐Interrupt
☒Data processing
☒Data storage
☐Direct memory access

Câu 117: The instruction, MOV AX, 0005h belongs to which addressing mode?
Select one:
Register
Direct
Index
Immediate

Câu 118: Which are correct about the data registers of IA-32 processors:
Select one or more:
☒Lower halves of the 16-registers an be used as 8-bit data registers: AH, AL, BH, BL, CH, CL, DH,
DL
☒Lower halves of the 32-registers an be used as 4 16-bit data registers: AX, BX, CX, DX
☐Higher halves of the 32-bit registers can be used as 16-bit registers: EAH, EAL, EBH, EBL, ECH,
ECL, EDH, EDL
☒complete 32-bit registers: EAX, EBX, ECX, EDX

Câu 119: What are components of Von Neumann, namely IAS computer?
Select one or more:
☐Monitor
☒Memory
☒I/O Equipments
☐Punched card reader
☒Bus
☒CPU
 Bee Kid

Câu 120: The following sequence of instructions are executed. What is the correct
value of flag bits at watch point?
MOV AL, -5
SUB AL, 124 AL = - 129 = 7F
watch point:
Result: OF = set; CF = set; ZF = reset; SF = set

Câu 121: Which are correct action for STOSB string operation if DF is reset (=0)
Select one or more:
☐decrease DI by 1
☒Store 8-bit value from AL into memory location pointed by ES:[DI]
☒increase DI by 1
☐Store 8-bit value from AL into memory location pointed by DS:[SI]

Câu 122: Which are correct action for SCASW string operation if DF is set (=1)
Select one or more:
☒decrease DI by 2
☒compare value in AL register with memory location pointed by ES:[DI]
☐compare value in AL register with memory location pointed by DS:[SI]
☐increase DI by 2

Câu 123: The instruction that subtracts 1 from the contents of the specified
register/memory location is
Select one:
SUB
DEC
SBB
INC

Câu 124: Memory dump at 1D20:0200 as below:

1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Given value of registers:
DS = 1D20, ES = 1D20,
DI = 20A, SI = 208,
BX = 202, AX = 0103, CX = 0003
and flag bit DF = 1
What is the correct value of AX, SI, DI registers after the instruction REP LODSW is
executed?
Result: DI = 20Ah AX = 5D10 SI = 202h

Câu 125: Which are correct action for SCASW string operation if DF is reset (=0)
Select one or more:
☐compare value in AL register with memory location pointed by DS:[SI]
 Bee Kid

☐decrease DI by 2
☒increase DI by 2
☒compare value in AL register with memory location pointed by ES:[DI]

Câu 126: Which are correct about the Pointer registers of IA-32 processors:
Select one or more:
☐Base Pointer (BP): The 16 bit pointer refers to stack memory
☐Stack Pointer (SP): the 16 bit pointer to the top of stack
☐Instruction Pointer (IP): the 16 bit register points to the next instruction to be execute
☒Base Pointer (EBP): The 32 bit pointer refers to stack memory
☒Stack Pointer (ESP): the 32 bit pointer to the top of stack
☒Instruction Pointer (EIP): the 32 bit register points to the next instruction to be execute

Câu 127: The instruction that loads effective address is

LAHF
LDS
LEA
LES

Câu 128: Enter debug command to fill 250 bytes in the memory segment FED5 in
computer memory
starting from 100 with value AD
f 100 1F9 AD
1𝐹916 = 𝐹𝐴16 + 10016 − 1

Câu 129: The following sequence of instructions are executed. What is the correct
value of EAX, EBX, EDX at watch point?
MOV EAX, 00002000
MOV EBX, 00100000
MUL EBX EDX = 00000002 EAX = 00000000
watch point:
Result: EAX = 00000000 EBX = 00100000 EDX = 00000002

Câu 130: Convert 39887.5625 to IEEE 32-bit floating point format (1 sign + 8
exponent + 23 mantissa) in hex
39887,5625 = 1001 1011 1100 1111,10012 = 1,001 1011 1100 1111 1001.1015
Mantissa: 001 1011 1100 1111 1001 0000
Exponent: 15 + 28−1 − 1 = 14210 = 1000 11102
Sign: 0
Result: 0100 0111 0001 1011 1100 1111 1001 00002 = 471𝐵𝐶𝐹9016
 Bee Kid

Câu 131: The instruction, MOV AX, 1234h is an example of

Select one:
Immediate addressing mode
based index addressing mode
direct addressing mode
register addressing mode

Câu 132: The following sequence of instructions are executed. What is the correct
value of flag bits at watch point?
MOV AL, 78
MOV BL, 2
MUL BL AL = 156
watch point:
Result: CF = reset OF = reset

Câu 133: The following sequence of instructions are executed. What is the correct
value of flag bits at watch point?
MOV AL, -5
ADD AL, 132
ADD AL, 1
watch point:
Result: ZF = reset OF = reset CF = reset SF = reset

Câu 134: the instruction, JMP C008:2000h is an example of

Select one or more:
☒intersegment jump
☒far jump
☐near jump
☐intrasegment mode
 Bee Kid

Câu 135: Memory dump at 1D20:0200 shown as below:

1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Given value of registers:
DS = 1D20, ES = 1D20, DI = 20A
The following sequence of instructions is being executed:
MOV SI, 208h SI = 208h
MOV AX, 0040h AX = 0040h
MOV CX, 000Ah CX = 000Ah = 10d
CLD Clear direction flag → DF = 0 → DI increase
REPNZ SCASB Next 10 bytes
watch point:
.....
What is the correct value of AX, SI, DI registers at watch point?
Result : SI = 208h AX = 0040h DI = 21Ah

Câu 136: Physical address of a memory location is 5FE2E. This memory address
located by DI register which now has value of 993E. Compute the memory address
of data segment register
Address = 16 * segment + offset = 16 * SS + SP
5𝐹𝐸2𝐸16 −993𝐸16
The memory address of data segment register: 1610
= 564𝐹16

Câu 137: Given a code snippet:

int ax, bx;
...
if (ax >= bx)
ax -= bx;
else
bx -= ax;
What is the equivalent logic sequence of instructions in Assembly
Select one:
cmp ax, bx cmp ax, bx cmp ax, bx cmp ax, bx
jbe a_label jge a_label ja a_label jl a_label
sub ax, bx sub ax, bx sub ax, bx sub ax, bx
jmp x_label jmp x_label jmp x_label jmp x_label
a_label: a_label: a_label: a_label:
sub bx, ax sub bx, ax sub bx, ax sub bx, ax
x_label: x_label: x_label: x_label:

Câu 138: After each execution of POP instruction, the stack pointer is
Select one:
increment by 1
increment by 2
 Bee Kid

decrement by 2
decrement by 1

Câu 139: Which are the correct actions for LODSB string operation if DF is reset (=0)

Select one or more:

☒Load 8-bit value at memory location pointed by DS : [SI] into AL
☐decrease DI by 1
☐Load 8-bit value at memory location pointed by ES : [DI] into AL
☒increase SI by 1

Câu 140: The following sequence of instructions are executed. What is the correct
value of AX, DX at watch point?
MOV AL, 80 AL = 50h
MOV BL, 2 BL = 2h
MUL BL AL = A0h
watch point:
Result: CF = reset OF = reset

Câu 141: The instruction that supports addition when carry exists is ADC

Câu 142: Given a row of memory image in debug

0AE8:0120 13 96 D0 E0 D0 E0 A2 1E - 99 80 3E 20 99 00 75 24
SI = 120, DI = 128
Select correct sequence of instructions to subtract words at [DI] from [SI] then
store the result at memory location 12A
Step 1: MOV AX, [SI]
Step 2: SUB AX, [DI]
Step 3: SUB AX, [SI]
Step 4: MOV [12A], AX

Câu 143: What is the meaning of Amdahl's law in processor performance

evaluation?
Select one:
the cost reduce when moving from single­core to multicore processor
the potential speedup of a program using multiple processor compared to a single
processor
the speedup of a multicore processor when increasing system bus speed
the maximum speedup of a multicore processor
 Bee Kid

Câu 144: To balance the super speed of CPU with the slow response of memory,
which of the following measures have been made by engineers in system design?

Select one or more:

☐To move data directly by DMA
☒Make wider data bus path
☒Make use of both on­chip and off­chip cache memory
☒Using higher­speed bus and us hierarchy

Câu 145: Which one best describe cache hit and cache miss?
Cache miss ratio: the number of memory accesses that CPU must retrieve from the main
memory per the total number of memory accesses
Cache hit ratio: the number of memory accesses that the CPU can retrieve from the cache per
the total number of memory accesses

Câu 146: For cache write policies, which are often used for write­hit and write­miss
Write­hit: Write­back
Write­miss: Write­allocate

Câu 147: Identify the correct sequence to update a page onto a flash memory?
Step 1: the entire block is being read from flash into RAM then request data in page is update
Step 2: The entire block of flash memory are erased
Step 3: The entire block from RAM then is written back to the flash memory

Câu 148: Choose correct set of registers for x86 processor

Data pointer to source memory in extra segment ES:SI
Pointer to variable in stack SS:BP
Instruction pointer CS:IP
Data pointer in data segment: DS:BX

Câu 149: Match the definition of flag bits in PSW

contains the carry of 0 or 1 from the leftmost bit after an arithmetic operation CF
determine the direction for moving or comparing data between memory areas DF
determine whether an external interrupts are to be ignored or processed IF
the processor switches to single­step mode TF

Câu 150: Which is not correct about MOORE law?

Select one or more:
☐The number of transistors that could be put on a single chip was doubling every year
☒The number of transistors that could be put on a single chip was triple every year nowadays.
☒Likely triple after 2000
 Bee Kid

☐The number of transistors that could be put on a single chip was doubling every year except
1970s

Câu 151: What are the processor's instruction categories

Select one or more:
☒Data processing
☒Control
☐Processor ­ Cache memory
☒Processor ­ I/O
☒Processor ­ Memory
☐Memory ­ Memory (DMA)

Câu 152: When many devices of different transmission speed connect to the same
bus, the overall system performance suffers. How did the design engineers
resolved this:
PCI Express bus
PCI bus
Split system bus into local bus and memory bus
Multiple­Bus hierarchies

Câu 153: What are the features of direct­mapping cache organization?

Select one or more:
☒Thrash ­­> low hit ratio
☐faster
☒Simple and inexpensive
☐small cache memory

Câu 154: Which one is not correct?

Select one or more:
☒EEPROM is erasable by exposing under UV
☐PROM is non­volatile memory
☒EPROM is erasable electrically
☒Flash memory can only be erased electrically byte by byte

Câu 155: What is correct about the function of TRIM command in SSD?
Select one:
Allow SSD to allocate memory pages in blocks properly for faster access
Allow SSD to defragment scattered data stored in separate pages
Allow OS to notify SSD the presence of occupied blocks of data which are no longer in use
and can be erased internally
Allow SSD to manage occupied pages and remove them automatically for later use
 Bee Kid

Câu 156: Select correct items to describe best about CISC

Number of clocks per instruction multi­clock
code size of program small code size
Assembly code simpler
Instruction set Complex
Bytes per instruction different for variety of instructions

Câu 157: What can be concluded from the following chart of processor trends:

The multi­core processors and level off clock speed help to make heat dissipation of CPU
chip less
The number of transistors in chips produce more heat dissipation
Heat dissipation in processor chip is increasing year after year since 1970
The processor speed keeps increasing after 2003

Câu 158: Key parameters to consider when evaluating processor hardware include:

Select one or more:

☒reliability
☒performance
☒power consumption
☐databus size
☒size
☐Address bus size
☒cost
 Bee Kid

Câu 159: Which of the following best describe the memory chip with pinout as
shown below:
𝐴0 → 𝐴7 = 8 ∗ 2 = 16 𝑏𝑢𝑠 𝑎𝑑𝑑𝑟𝑒𝑠𝑠(𝑅𝐴𝑆, 𝐶𝐴𝑆) → 216
𝐷1 → 𝐷4 = 4 𝑏𝑢𝑠 𝑑𝑎𝑡𝑎 → 4
Structure: 64K x 4bit

Câu 160: The three key characteristics of memory are: capacity, access time and
cost. Which of the following relationships hold for a variety of memory
technologies?
Select one or more:
☒Faster access time, greater cost per bit
☐Higher capacity, higher access time
☒Greater capacity, smaller cost per bit
☒Greater capacity, slower access time

Câu 161: A SRAM memory chip labeled 32x8bit. Which of the following is correct
pinout regarding address and data lines?
Select one:
☐32 address pins, 3 data pins
☐32 address pins, 4 data pins
☐5 address pins, 3 data pins
☒15 address pins, 8 data pins

Câu 162: In the interconnection system, the number of address lines are governs
by
Select one:
I/O Module
CPU
data bus line
Memory size

Câu 163: Identified correct addressing mode of the following instructions?

MOV AX, BX Register
MOV BP, [BX+SI] Base plus index
MOV AX, ARRAY [BX+SI] Base relative plus index
MOV AX, [BX] Register indirect
MOV AX, [1234h] Direct
 Bee Kid

MOV AX, 3540h Immediate

Câu 164: In the RCR instruction, the contents of the destination operand
undergoes function as
Select one:
carry flag is pushed into LSB then MSB is pushed into carry flag
overflow flag is pushed into MSB then LSB is pushed into carry flag
carry flag is pushed into MSB then LSB is pushed into carry flag
auxiliary flag is pushed into LSB then MSB is pushed into carry flag

Câu 165: Which of the following is not a data copy/transfer instruction?

Select one or more:
☒ADC
☐MOV
☐LEA
☒DAS

Câu 166: When CPU is executing a Program that is part of the operating system, it
is said to be in
Simplex mode
Half mode
Interrupt mode
System mode

Câu 167: Von Neumann architecture is

MISD
SISD
SIMD
MIMD

Câu 168: Cache memory works on the principle of

A. Locality of data
B. Locality of memory
C. Locality of reference and memory
Locality of reference
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Câu 169: A computer System has an L1 and L2 cache, and a main memory unit
connected as shown below. The block size in L1 cache is 4 words. The block size in
L2 cache is 16 words. The memory access times are 2 nanoseconds, 20
nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unity
respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is
transferred from L2 cache to L1 cache. What is the time taken for this transfer?

L1 Cache Data bus L2 Cache Data bus Main

4 words memory
4 words

The block size in L1 cache is 4 words.

Total time is = time to access L2 + time to place in L1 = 20 + 2 = 22 ns

Câu 170: The device which used to connect a peripheral to bus is called
Communication protocol
None
Interface
Control register

Câu 171: In a virtual memory system the address space specified by the address
lines of the CPU must be _______ than the physical memory size and _________than the
secondary storage size
larger, larger
smaller, smaller
larger, smaller
smaller, larger

Câu 172: The ALU of a computer normally contains a number of high-speed storage
elements called
Registers
IC
Semi-conductor memory
Hard disk

Câu 173: Compared to RISC processors, CISC processors contains ________

More registers and smaller instruction set.
larger instruction set and less registers.
Less registers and smaller instruction set.
More transistor elements

Câu 174: Disadvantage of dynamic RAM over static RAM is

Lower Packing density
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Variable speed
Need to refresh the capacitor charge every once in two milliseconds.
Higher power consumption

Câu 175: Desirable characteristic(s) of a memory system is(are)

Speed and reliability
Low power consumption
Durability and compactness
All

Câu 176: Four memory chips of 16 x 4 size have their address bases connected
together. The system will be of size.
Final memory is 16 X 4(4) = 16 X 16

Câu 177: Consider a single-level paging system with 12-bit virtual addresses, 24-bit
physical addresses, and a 256 (𝟐𝟖 ) byte page size. A process P1 has the following
page table. Frame numbers are given in hexadecimal notation (recall that each
hexadecimal digit represents 4 bits). Convert physical address: 0x1100A0 into
virtual address.
Page Number Frame Number
0 0x1010
1 0x2034
2 0x43AC
3 0x1100
4 0xAC11
5 0x8000
Page Size = Frame Size = 256 = 28 → offset # = 8 bit
Virtual Addresses = 12 bit = Page # + offset # → page # = 4 bit
Physical Addresses = 24 bit = Frame # + offset # → Frame # = 16 bit
0x1100A0 = 0001 0001 0000 0000 1010 00002
Frame # = 0001 0001 0000 00002 = 0x1100 → Page # = 310 = 00112
Offset # = 1010 00002
Vitural Address of 0x1100A0 is 0011 1010 00002 (0x3A0)

Câu 178: Let us consider a memory hierarchy (main memory + cache) given by
- Memory size 1 Giga words of 16 bit (word addressed)
- Cache size 1 Mega words of 16 bit (word addressed)
- Cache block size 256 words of 16 bit
Main Memory = 1GigaBytes = 230 Bytes → kích thước địa chỉ 30 bit
Block = 256 words = 28 → b = 8 bit
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Cache Size = 1MegaBytes = 220 Bytes

220
Line Size = 28
= 212
Direct Mapping
Index Size (Set size) = Line size = 212 → s = 12 bit
Tag (t) = 30 – (8 + 12) = 10 bit
Cấu trúc địa chỉ:
t 10 s 12 b 8
Associate Mapping
Tag (t) = 30 – 8 = 22 bit
Cấu trúc địa chỉ
t 10 b 22
Set Associate Mapping (2 - way) → k = 2
212
Index Size (Set size) = 2
= 211 → s = 11
Tag (t) = 30 – (11 + 8) = 11 bit
Cấu trúc địa chỉ:
t 11 s 11 b 8
Set Associate Mapping (4 - way) → k = 4
212
Index Size (Set size) = 4
= 210 → s = 10
Tag (t) = 30 – (10 + 8) = 12 bit
Cấu trúc địa chỉ:
t 12 s 10 b 8

Câu 179: Consider the following paging memory system: There are 4 page table
entries (with values of 0xC, 0x2, 0x8, 0x5 for entries 0…3, respectively). The physical
memory is 128 bytes, with frames of 8 bytes each.
a. How large (the number of bits) is the physical address?
b. How large is the virtual address?
c. What is the physical address (in hex) that corresponds to virtual address 0x1D
d. What is the physical address (in hex) that corresponds to virtual address 0x03?
Page Number Frame Number
0 0xC
1 0x2
2 0x8
3 0x5
a. Physical memory = 128 bytes = 27 bytes → Physical address = 7 bit
b. Page Size = Frame Size = 8 bytes = 23 bytes → Offset # = 3 bit
Page number = 4 = 22 → Page # = 2 bit
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Virtual Address = Page # + offset # = 2 + 3 = 5 bit

c. 0x1D = 0001 11012
Page # = 112 = 310 → Frame # = 0x5 = 01012
Offset # = 1012
Physical Address of 0x1D is 0010 11012 (0x2D)
d. 0x03 = 0000 00112
Page # = 0 → Frame # = 0xC = 11002
Offset # = 0112
Physical Address of 0x03 is 0110 00112 (0x63)

Câu 180: If processor A has a higher clock rate than processor B, and processor A
also has a higher MIPS rating than processor B, explain whether processor A will
always execute faster than processor B. Suppose that there are two
implementations of the same instruction set architecture. Machine A has a clock
cycle time of 20ns and an effective CPI of 1.5 for some program, and machine B has
a clock cycle time of 15 ns and an effective CPI of 1.0 for the same program. Which
machine is faster for this program, and for how much?
For Some program → 𝐼𝐶𝐴 = 𝐼𝐶𝐵
𝑀𝐼𝑃𝐴 𝐼𝐶𝐴 𝐶𝑃𝑈𝑡𝑖𝑚𝑒𝐵 . 106 𝐶𝑃𝑈𝑡𝑖𝑚𝑒𝐵 𝐼𝐶𝐵 ∗ 𝐶𝑃𝐼𝐵 ∗ 𝜏𝐵 1 ∗ 15 1
= . = = = = = 0,5
𝑀𝐼𝑃𝐵 𝐶𝑃𝑈𝑡𝑖𝑚𝑒𝐴 . 106 𝐼𝐶𝐵 𝐶𝑃𝑈𝑡𝑖𝑚𝑒𝐴 𝐼𝐶𝐴 ∗ 𝐶𝑃𝐼𝐴 ∗ 𝜏𝐴 1,5 ∗ 20 2
𝑀𝐼𝑃𝐴 = 0,5𝑀𝐼𝑃𝐵 → Machine A slower Machine B → Machine B faster Machine A

Câu 181: Memory units have low access time?

Disk > Main memory > Cache > Registers

Câu 182: In the CPU

Control Unit: To decode program instruction
Register: To store program instruction
ALU: To perform logic operations
Program Counter: CPU fetches the instruction from memory (Instruction Pointer)

Câu 183: A group of bits that tell the computer to perform a specific operation is
known as
Micro-operation
Accumulator
Instruction code
Register

Câu 184: hrough which technique, the speed imbalance between memory access
and CPU operation can be reduced?
Cache memory
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Reducing the size of memory

Memory interleaving and Cache memory
Memory interleaving

Câu 185: The memory unit that communicates directly with the CPU is called the
auxiliary memory
Secondary memory
main memory
shared memory

Câu 186: In comparison with static RAM memory, the dynamic RAM memory has
Lower bit density and higher power consumption
Higher bit density and low power consumption
Lower bit density and lower power consumption

Câu 187: A dynamic RAM consists of 1 transistor and 1 tiny capacitor

Câu 188: The communication between the components in a microcomputer takes

place via the address and
I/O bus
Address bus
Data bus
Control lines

Câu 189: Cache memory acts between CPU and RAM

Câu 190: the following is the address generated by CPU: logical address

Câu 191: An n-bit microprocessor has

n-bit instruction register
n-bit program counter
n-bit ALU
n-bit address register

Câu 192: The flag that the instruction SBB uses is

Borrow flag
Direction Flag
Overflow Flag
Carry flag

Câu 193: If the offset of the operand is stored in one of the index registers, then it
is
based indexed addressing mode
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relative based indexed addressing mode

indexed addressing mode
none of the mentioned

Câu 194: If the data is present in a register and it is referred using the particular
register, then it is
direct addressing mode
register addressing mode
indexed addressing mode
immediate addressing mode

Câu 195: in an even parity coding system, transmitted data is 8-bit width comprise
1 parity bit (msb) and 7 data bits. Assuming that the byte to be parity-encoded is
in the AL register and the sum of 1 now is an odd number. The parity bit now needs
to be set with a mask byte without altering the remaining 7 bits. Write the correct
value of the mask byte
The value of the mask byte is: 1000 00002 = 12810 = 0x80