On Pulse Position Modulation and its

Application to PLLs for Spur Reduction

A THESIS

submitted by

CHEMBIYAN THAMBIDURAI

for the award of the degree

of

MASTER OF SCIENCE
(by Research)

Department Of Electrical Engineering

Indian Institute of Technology Madras, India

October 2011
 CERTIFICATE

This is to certify that the thesis titled On Pulse Position Modulation and

its Application to PLLs for Spur Reduction, submitted by Chembiyan

Thambidurai, to the Indian Institute of Technology Madras, for the award of
the degree of Master of Science, is a bona fide record of the work done by him
under my supervision. The contents of this thesis, in full or in parts, have not

been submitted to any other Institute or University for the award of any degree
or diploma.

Dr. Nagendra Krishnapura

Research Advisor,
Associate Professor,

Dept. of Electrical Engineering,

IIT Madras, 600 036

Place: Chennai

Date: October 2011

ACKNOWLEDGEMENTS

‘Live like you are going to die tomorrow’, theme of the movie Mr.Magorium’s
Wonder Emporium, inspired me as an young adult when I first watched it. I
believe in searching and pursuing what you are passionate about. As someone
who had interests in fields as diverse as choreography, mathematics, literature

and physics, I was at crossroads many a times in life unsure of what to choose.
Sometimes some decisions I made backfired, some took off well. But through all
these experiences I have learnt one thing, that failures are a part of life, avoiding it
is like missing a roller coaster ride. Though fearful when you are at it, a remarkable
experience to remember later than the successes. After many failed attempts, I

finally decided to do research in Circuit design at IIT Madras. This work would
not have been possible without the factors that helped me in accomplishing it.
First and foremost I would like to express my gratitude to my research adviser,
Dr. Nagendra Krishnapura for his constant guidance and support he gave me in

finishing my MS at IIT Madras. The freedom he gives to his students in pursuing

research is exemplary. His drive for perfection in presentation taught me a lot in
writing a good technical document. I would also like to thank Dr. Shanthi Pavan
for his ‘never boring’ classes on filter design.

Through my last two years of work at IIT Madras I owe profoundly to the empty
sun heated electric trains of Chennai where many ideas struck me on my journey
from home to the institute (and vice versa). Next in line are the beaches of chennai
which I frequently visited. Walking on the long and lonely beach of the Triplicane
in the afternoons is an experience I can never forget. I felt a connection with it,

where the land and water met, I could see the logic and imagination meet in the
deep thoughts on research and writing.
Man is a social being, the purpose of his creation is not to ‘live and die’ but
to experience it, share some of its wonderful moments with his fellow men. I
m infinitely blessed to have a very few but lifelong friends. First I would like to
thank Kiran. We have been friends through the merrier and difficult times, helping

each other when we were met with failures. The long trips we had as childhood
friends climbing tall mountains and catching fishes in ponds, to the recent frequent
trips (12 years later) we had to the ‘pizza hut and sanjeevanam’ and him putting
up with my obsessions of being choosy about food are the experiences I can never
forget. I hope he finds the ‘girl of his dreams’ that he keeps trying and failing at

many times.
Good friends stay with us when in times of need. There cannot be a better example
than my friends from BITS-Pilani kana (karthik) and state (Srinivasa raghavan), in
my case. Without them I would have missed something in life. Each of them well

accomplished (kana a Stanford grad, state a cricket player and an ‘IBM stalwart’)
by themselves are people with good hearts. Through all the difficult times, they
have kept my spirits up by emails and chats. The treats we had in the biting
cold winters at Connaught place where kana ate his favorite mix veg oothappam

and state devoured ‘anything’ that came his way, where we discussed each of our
dreams and my dreams of studying at Berkeley are experiences we often recollect
to tear filled eyes.
Being a first born child at home, I never had an elder brother to advice me or to
whom I could confide my mistakes. Arun and Srini filled that gap in my life. Their

matured stance in life was something very inspiring to me. They have always been
great friends to me who had shared interests, with whom I had some memorable
discussions on topics as diverse as ‘artificial intelligence’ to ‘the lives of bohemian
artists’.

I would also like to thank Dr. V. Kamakoti for serving on my graduate committee.
Everyone in TI lab are indebted to Shankar for providing us the best computing
facility in the lab. The discussions I had on art and creativity with Mrinmay and

iii
Shankar are memorable. I thank everyone else (inclusive of the alumni) in the TI
lab for making the lab a great place to work.
Finally, my special thanks to my parents who put up with all my idiosyncrasies and
patiently waiting for me complete my degree even when they needed my financial

assistance. I would like to dedicate this thesis to all the independent minds who
produced truly independent work and whose legacy has enabled the sustenance of
such a race in this otherwise boring world.

iv
ABSTRACT

Phase lock loops (PLLs) are used in frequency synthesis for modulation and de-
modulation of base band data in wireless communications and to generate clocks
for accurate timing in digital systems like microprocessors. One class of PLLs
called the charge pump PLLs has gained wide popularity due to its relative ease

of implementation. However due to the discrete time nature of the phase frequency
detector and nonidealities in the charge pump, a periodic charge pump current is
injected into system in the steady state. This results in spurs in the output spec-
trum of the PLL. The bandwidth of the PLL is reduced to have low spur levels.
A lower PLL bandwidth increases the settling time of the PLL and reduces the

frequency range of rejection of the VCO phase noise.

The central idea of this work is to break the periodicity and convert the energy in
the spurs into a wideband noise, which enables the PLL to have larger bandwidth
and maintain low spur levels. Randomizing the positions of charge pump current

pulses in a PLL breaks their periodicity and redistributes the reference spurs into
broadband noise. In this work closed form expressions for the spectrum of pulse
position modulated (PPM) signals are derived and intuitive explanations for the
results are given. The redistributed noise has a highpass shape and does not affect

the close in phase noise of the PLL. PPM using a uniformly distributed uncorre-
lated sequence completely removes the spurs and provides a first order shaping of
redistributed noise. Higher order shaping and reduction of redistributed noise at
intermediate offset frequencies are possible using PPM with a correlated modulat-
ing sequence and pulse repetition. Circuit implementations of these techniques are

given and their nonidealities are discussed. The implementation ideas proposed
in this work leads to a compact implementation of the techniques and is more
insensitive to delay mismatch. A detailed analysis of the delay line nonidealities
is also presented to study their effect on the PLL output phase noise.
Simulation results confirm the results of the analysis and viability of the proposed
techniques. In the presence of nonidealities spurs can be reduced by at least 13 dB

without any trimming of the delays in the PPM circuits and by 25 dB after trim-
ming the delays within 5% of the nominal value.
A 1 GHz PLL operating from a reference frequency of 20 MHz and a bandwidth
of 1 MHz is implemented in 0.18 µm CMOS technology to test the proposed ideas.
The spur at -20 MHz offset from the carrier (980 MHz) was measured to be 64 dBc.

Enabling the PPM and PR reduces the magnitude of the spur by 8 dB and 9 dB
respectively.

vi
 TABLE OF CONTENTS

ACKNOWLEDGEMENTS ii

ABSTRACT v

LIST OF TABLES xii

LIST OF FIGURES xiii

ABBREVIATIONS xx

1 Introduction 1

1.1 Charge pump PLL basics . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Discrete-time behaviour of the PLL . . . . . . . . . . . . 2

1.1.2 Continuous time model of the PLL . . . . . . . . . . . . 4

1.2 Problem of reference spurs . . . . . . . . . . . . . . . . . . . . . 5

1.3 Overview of the thesis . . . . . . . . . . . . . . . . . . . . . . . 11

2 Spur Reduction Techniques 12

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Mathematical formulation . . . . . . . . . . . . . . . . . . . . . 12

2.2.1 Power lost and power redistributed . . . . . . . . . . . . 14

2.3 PPM by an uniformly distributed iid sequence . . . . . . . . . . 15

vii
 2.3.1 Shape of the redistributed noise . . . . . . . . . . . . . . 18

2.3.2 Sensitivity to delay variations . . . . . . . . . . . . . . . 18

2.4 Spur reduction techniques . . . . . . . . . . . . . . . . . . . . . 20

2.4.1 Random pulse position modulation (PPM) . . . . . . . . 22

2.4.2 Pulse repetition (PR) . . . . . . . . . . . . . . . . . . . . 22

2.4.3 Pulse position modulation with pulse repetition (PPM+PR) 24

2.4.4 Shaped PPM+PR . . . . . . . . . . . . . . . . . . . . . 26

2.5 Delaying narrow UP/DN pulses . . . . . . . . . . . . . . . . . . 29

2.6 Modulating sequence generation . . . . . . . . . . . . . . . . . . 33

2.6.1 Practical considerations for PRBS generation . . . . . . 34

2.6.2 Shaped data generation . . . . . . . . . . . . . . . . . . 35

2.7 Effects of delay line nonidealities . . . . . . . . . . . . . . . . . 36

2.7.1 Effect of mismatch . . . . . . . . . . . . . . . . . . . . . 36

2.7.2 Effect of noise . . . . . . . . . . . . . . . . . . . . . . . . 41

3 Implementation Details 44

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2 Phase frequency detector . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.3.1 Charge pump implementation . . . . . . . . . . . . . . . 46

3.3.2 Charge pump bias generation . . . . . . . . . . . . . . . 49

3.4 Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.5 Pulse position randomizer and pulse repetition circuit . . . . . . 51

viii
 3.5.1 Randomization . . . . . . . . . . . . . . . . . . . . . . . 51

3.5.2 Delay cell . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.3 8:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.4 Pulse repeating circuit . . . . . . . . . . . . . . . . . . . 53

3.6 Modulating sequence generation . . . . . . . . . . . . . . . . . . 54

3.7 Timing analysis for clocking the modulating signal . . . . . . . . 55

3.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . 56

3.8.1 Delay cell . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.8.2 Tuning circuit . . . . . . . . . . . . . . . . . . . . . . . . 58

3.9 Frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.9.1 Multi-modulus dividers . . . . . . . . . . . . . . . . . . . 61

3.9.2 Programmable divide value . . . . . . . . . . . . . . . . 65

3.10 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.10.1 Control voltage buffer . . . . . . . . . . . . . . . . . . . 67

3.10.2 VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.11 Lock detector circuit . . . . . . . . . . . . . . . . . . . . . . . . 70

4 Delay tuning PLL 73

4.1 Delay tuning PLL dynamics . . . . . . . . . . . . . . . . . . . . 74

4.1.1 Feedback compensation . . . . . . . . . . . . . . . . . . . 76

4.1.2 Feedforward compensation . . . . . . . . . . . . . . . . . 77

4.1.3 Choice of input frequency . . . . . . . . . . . . . . . . . 81

4.1.4 Inverter chain based VCO . . . . . . . . . . . . . . . . . 81

ix
 4.1.5 Schematic of the PFD and charge pump . . . . . . . . . 82

4.1.6 DLL buffer . . . . . . . . . . . . . . . . . . . . . . . . . 83

5 Simulation Results 86

5.1 Block level simulations . . . . . . . . . . . . . . . . . . . . . . . 86

5.1.1 Transient simulation . . . . . . . . . . . . . . . . . . . . 89

5.2 Noise computations . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.2.1 Power consumption . . . . . . . . . . . . . . . . . . . . . 93

6 Testing 94

6.1 Floor plan of test chip . . . . . . . . . . . . . . . . . . . . . . . 94

6.2 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.3 Measured results . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.4 Discussions on measured results . . . . . . . . . . . . . . . . . . 101

6.4.1 Spurs at ±4fr . . . . . . . . . . . . . . . . . . . . . . . . 101

6.4.2 Higher even order harmonics in PPM . . . . . . . . . . . 101

6.4.3 Asymmetric spurs at fvco ±kfr . . . . . . . . . . . . . . . 102

7 Conclusion and Future Work 104

A Spectral Analysis of PPM signals 106

A.1 Autocorrelation function of the PPM signals . . . . . . . . . . . 106

A.1.1 PPM by an iid sequence . . . . . . . . . . . . . . . . . . 108

A.1.2 PPM by a pseudo random sequence . . . . . . . . . . . . 110

x
 A.1.3 PPM by a binary correlated sequence . . . . . . . . . . . 110

A.1.4 PPM by a two bit correlated sequence . . . . . . . . . . 113

A.1.5 PPM by a finitely correlated sequence . . . . . . . . . . 114

A.1.6 PPM by a correlated periodic sequence . . . . . . . . . . 115

A.2 Practical considerations for the choice of PRBS length . . . . . 116

B Ring Oscillator Basics 118

B.1 Sinusoidal ring oscillators . . . . . . . . . . . . . . . . . . . . . . 119

B.2 Oscillators with non-linear gain elements . . . . . . . . . . . . . 120

B.2.1 Conventional inverter based ring oscillator . . . . . . . . 124

B.2.2 Effect of impedance scaling . . . . . . . . . . . . . . . . 125

B.2.3 Noise as a function of n . . . . . . . . . . . . . . . . . . 126

C Asymmetric Sidebands in the Presence of both Amplitude and

Phase Modulation 129

C.1 Amplitude modulation . . . . . . . . . . . . . . . . . . . . . . . 129

C.2 Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . 130

C.3 Both AM and FM . . . . . . . . . . . . . . . . . . . . . . . . . . 131

D Pin Details of the Fabricated Test Chip 133

xi
 LIST OF TABLES

1.1 PLL parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Implemented PLL parameters. . . . . . . . . . . . . . . . . . . . 45

4.1 Delay tuning PLL parameters . . . . . . . . . . . . . . . . . . . 80

5.1 PLL power consumption . . . . . . . . . . . . . . . . . . . . . . 93

6.1 Areas of individual blocks. . . . . . . . . . . . . . . . . . . . . . 96

6.2 Measured spur levels for different techniques . . . . . . . . . . . 101

D.1 Functionality of each pin. . . . . . . . . . . . . . . . . . . . . . 133

xii
 LIST OF FIGURES

1.1 Standard charge pump PLL architecture. . . . . . . . . . . . . . 1

1.2 (a) Continuous-time PLL model, (b)Discrete-time PLL model. . 2

1.3 Closed-loop PLL magnitude response from the continuous and dis-
crete time models. . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 Response of the control voltage to a frequency step. The response of

an actual PLL matches the response obtained from a linear model
in an average sense. . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5 Linear model of the PLL. . . . . . . . . . . . . . . . . . . . . . . 4

1.6 (a) Standard charge pump PLL architecture showing the periodic
nature of the charge pump current, (b) the spectrum of the steady
state charge pump current and (c) the PLL output spectrum show-
ing the up conversion of the charge pump spurs. . . . . . . . . . 6

1.7 Charge pump nonidealities . . . . . . . . . . . . . . . . . . . . . 7

1.8 Illustrative pulse shapes of the charge pump current injected into
the loop filter every reference cycle in steady state . . . . . . . . 8

1.9 Periodic disturbance on the control voltage in steady state . . . 8

1.10 Spurs at PLL output at harmonics of reference frequency offset from

the carrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.11 The modified PLL architecture with pulse position modulator/pulse

repeater shown at block level. . . . . . . . . . . . . . . . . . . . 10

xiii
2.1 (a) PAM with sequence xk , (b) Pulse position modulating sequence
ak , (c) PPAM with sequences ak and xk for N = 8. . . . . . . . . 13

2.2 The spectrum of the unmodulated impulse train and the spectrum
of the 8-PPM signal (PSD computed with a resolution bin width of
fr /512). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 The spectrum of the PPM signal modulated by a uniformly dis-

tributed sequence overlaid with the associated pseudo filter for
N = 8 (PSD computed with a resolution bin width of fr /512). . 17

2.4 Redistributed noise for different values of N (shown in a log scale

for better comparison). . . . . . . . . . . . . . . . . . . . . . . . 18

2.5 Sensitivity to delay variations. . . . . . . . . . . . . . . . . . . . 19

2.6 i) The modified PLL architecture with pulse position modulator/pulse

repeater shown at block level. ii) Illustrative waveforms of charge

pump current before and after applying the techniques (a) Standard
PLL, (b) PPM, (c) Pulse Repetition (PR), (d) PPM+PR. . . . . 21

2.7 Implementation of PPM. . . . . . . . . . . . . . . . . . . . . . . 22

2.8 (a) Pulse repeater circuit, (b) Charge delivered per reference cy-
cle vs phase error δt by the standard PFD+charge pump and N-

PR+scaled charge pump. . . . . . . . . . . . . . . . . . . . . . . 23

2.9 The spectrum of the 8-PPM signal overlaid with the 4-PPM+2-PR

signal (PSD computed with a resolution binwidth of fr /512). . . 25

2.10 (a) The UP pulse before and after applying the technique, (b) Im-
plementation details of combined 4-PPM+2-PR technique. . . . 25

2.11 The spectrum of the 8-PPM signal overlaid with noise shaped 4-
SPPM+2-PR signal shown on a log scale for noise comparisons (PSD

computed with a resolution binwidth of fr /512). . . . . . . . . . 27

xiv
2.12 Implementation of the technique to tackle the narrow pulse problem. 30

2.13 Alternative implementation with delay lines placed before the PFD: (a)

PPM, (b) PR, (c) PPM+PR. . . . . . . . . . . . . . . . . . . . 32

2.14 The spectra of the 8-PPM signal modulated by an uncorrelated (white)

data and correlated (lowpass) data shown on log scale for noise com-

parisons (PSD computed with a resolution binwidth of fr /512). . 35

2.15 The UP/DN pulse waveforms and the charge pump current in the

presence of delay variations corresponding to a delay of iT /N. . 37

2.16 Spur rejection vs random delay mismatch. . . . . . . . . . . . . 39

2.17 PLL output phase noise due to the delay line noise when delay line
is placed after and before PFD. . . . . . . . . . . . . . . . . . . 42

3.1 Block diagram of the implemented PLL. . . . . . . . . . . . . . 44

3.2 Tri-state PFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3 DFF used in the PFD. . . . . . . . . . . . . . . . . . . . . . . . 46

3.4 Charge pump switch arrangements. . . . . . . . . . . . . . . . . 46

3.5 Charge pump implementation. . . . . . . . . . . . . . . . . . . . 47

3.6 Amplifier used in the charge pump. . . . . . . . . . . . . . . . . 48

3.7 Magnitude and phase response of the unity gain amplifier used in
the charge pump. . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.8 Transient simulation showing the wide swing operation of the am-

plifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.9 Charge pump bias generation circuit. . . . . . . . . . . . . . . . 50

3.10 Loop filter architecture. . . . . . . . . . . . . . . . . . . . . . . 51

xv
3.11 Pulse position randomizer. . . . . . . . . . . . . . . . . . . . . . 51

3.12 Delay cell implementation. . . . . . . . . . . . . . . . . . . . . . 52

3.13 8:1 Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.14 Pulse repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.15 8-input OR gate schematic. . . . . . . . . . . . . . . . . . . . . 54

3.16 3-bit random number generation. . . . . . . . . . . . . . . . . . 55

3.17 Figure showing the timing for the PRBS and the PLL. . . . . . 55

3.18 Basic VCO cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.19 (a) VCO tuning circuit, (b) I-V characteristics of the V-I converter,
(c) The resulting f-V characteristics of the VCO. . . . . . . . . . 58

3.20 Stagger tuned VCO. Transconductance cells active in the range (a)
0.3 - 0.7 V, (b) 0.7 - 1.1 V, (c) 1.1 - 1.5 V, (d) Staggered transcon-
ductor I-V characteristics. . . . . . . . . . . . . . . . . . . . . . 59

3.21 Tuning current vs input voltage. . . . . . . . . . . . . . . . . . . 60

3.22 VCO characteristics measured at the nominal corner. . . . . . . 61

3.23 A multi-modulus divider formed using 2/3 modulus dividers. . . 62

3.24 Divider architecture. . . . . . . . . . . . . . . . . . . . . . . . . 63

3.25 Divide by 2/3 section shown at gate level . . . . . . . . . . . . . 63

3.26 CMOS latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.27 CMOS latch with AND functionality combined. . . . . . . . . . 64

3.28 (a) Pseudo NMOS latch and (b) ANDed pseudo NMOS latch shown

at a transistor level. . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.29 Divider encoder logic. . . . . . . . . . . . . . . . . . . . . . . . . 65

xvi
3.30 Divider waveforms overlaid with the VCO waveform. . . . . . . 67

3.31 Control voltage buffer schematic. . . . . . . . . . . . . . . . . . 68

3.32 Transient response of the control voltage buffer. . . . . . . . . . 68

3.33 Buffered VCO output driving the bond pad, pin and a 50 Ω resistor. 69

3.34 VCO buffer schematic. . . . . . . . . . . . . . . . . . . . . . . . 70

3.35 (a) Idea behind the ‘Phase lock’ detector implementation, (b) Fig-
ure showing the sampling instants Te and Tl w.r to the rising edge
of the reference clock. . . . . . . . . . . . . . . . . . . . . . . . . 71

3.36 ‘Phase lock’ detector schematic. . . . . . . . . . . . . . . . . . . 72

3.37 ‘Phase lock’ detector characteristics. . . . . . . . . . . . . . . . 72

4.1 Supply regulated PLL for Delay tuning . . . . . . . . . . . . . . 74

4.2 Transconductor with Current Assistance . . . . . . . . . . . . . 75

4.3 The proposed idea to make the Gm independent of the VCO load
by feedback replica current injection. . . . . . . . . . . . . . . . 76

4.4 Feedforward replica current injection . . . . . . . . . . . . . . . 77

4.5 Supply noise rejection of the two techniques when applied to the
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.6 Step response of the PLL with the VCO impedance modeled as
resistor overlaid with the actual VCO timevarying load. . . . . . 80

4.7 VCO schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.8 VCO tuning characteristics. . . . . . . . . . . . . . . . . . . . . 82

4.9 Delay cell schematic showing the cascade of inverter chains used in
the VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

xvii
4.10 Delay cell buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.11 Buffer step response. . . . . . . . . . . . . . . . . . . . . . . . . 84

5.1 Transistor level charge pump schematic showing the source of mis-
match added for simulations. . . . . . . . . . . . . . . . . . . . . 86

5.2 Phase noise of the PLL output comparing the the performance of
the 8-PPM and 8-PR techniques with the standard PLL (The reso-
lution bandwidth used for PSD computation is 78.125 kHz). . . 87

5.3 Phase noise at the PLL output due to the resistor, VCO and charge
pump compared with the redistributed noise added by 8-PPM and
4-PPM+2-PR techniques. . . . . . . . . . . . . . . . . . . . . . 88

5.4 The phase noise contribution of the 8-PPM overlaid with the phase
noise due to 4-SPPM+2-PR technique. . . . . . . . . . . . . . . 89

5.5 Settling behavior of the PLL for different techniques for a frequency
step of 80 MHz (from 1 GHz to 1.08 GHz). . . . . . . . . . . . . 89

5.6 Linear PLL model showing the various noise sources contributing
to the output phase noise. . . . . . . . . . . . . . . . . . . . . . 90

5.7 VCO phase noise measured at 1.18 GHz. . . . . . . . . . . . . . 91

5.8 Charge pump noise current density. . . . . . . . . . . . . . . . . 92

5.9 Total PLL output noise. . . . . . . . . . . . . . . . . . . . . . . 92

5.10 Total PLL output noise overlaid with the noise added by the ran-
domization techniques. . . . . . . . . . . . . . . . . . . . . . . . 93

6.1 Floor plan of the designed PLL. . . . . . . . . . . . . . . . . . . 94

6.2 Snapshot of the layout of the designed PLL . . . . . . . . . . . 95

6.3 Test setup for measuring the phase noise of the PLL chip. . . . 96

xviii
6.4 Measured results showing the PLL output spectrum. . . . . . . 97

6.5 Measured results showing the PLL output spectrum when PR is

turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.6 Measured results showing the PLL output spectrum when PPM is
turned on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.7 Measured results showing the PLL output noise. The measured in
band noise spectrum of the PPM, PR and normal PLL are shown

in blue, green and black colors. . . . . . . . . . . . . . . . . . . 100

6.8 AM due to the modulation on the bias current. . . . . . . . . . 103

B.1 n-stage ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . 118

B.2 Nonlinear oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 121

B.3 Delay with gain in the feedforward path. . . . . . . . . . . . . . 123

B.4 n-stage inverter based ring oscillator shown with device sizes. . . 124

B.5 Model of the inverter as a current charging and discharging a ca-

pacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

C.1 Asymmetric sideband in the presence of AM and FM. (a) Spectrum

of an AM signal, (b) Spectrum of an FM signal and (c) Spectrum

of the combined AM and FM signal . . . . . . . . . . . . . . . . 131

D.1 Pin diagram of the PLL. . . . . . . . . . . . . . . . . . . . . . . 133

xix
ABBREVIATIONS

PLL Phase Lock Loop

CMRR Common Mode Rejection Ratio
CT Continuous Time
UGB Unity Gain Bandwidth

DSM ∆Σ Modulator
DT Discrete Time
NTF Noise Transfer Function
PSD Power Spectral Density
PPM Pulse Position Modulation

PPAM Pulse Position and Amplitude Modulation

PR Pulse Repetition
SPPM Shaped Pulse Position Modulation
 CHAPTER 1

Introduction

1.1 Charge pump PLL basics

Vdd

VCO
fr
ref UP fout
fdiv
div DN R
Cp
Cz

ND

Figure 1.1: Standard charge pump PLL architecture.

Charge pump PLLs are widely used for frequency synthesis in transceivers and

clock generation in microprocessors. A large body of work can be found in the

literature that deals with the analysis of charge pump PLLs [1], [2], [3]. So a brief
introduction of its details is presented in this chapter.
The widely used architecture of a charge pump PLL is shown in Fig. 1.5. A PLL

is a feedback system that forces the output signal frequency (phase) to track the
input frequency (phase) or a multiple of the input frequency. It consists of a phase
frequency detector (PFD) that measures the phase error between the input refer-
ence clock and the feedback (divide) clock. The PFD produces two digital signals

called UP and DN, which are converted into current pulses (whose pulse widths
are proportional to the phase error) by the charge pump. The current pulses are
fed into the loop filter generating a voltage that is a linear function of the phase
error. The generated voltage is used to control the frequency of the voltage con-
trolled oscillator (VCO). The PFD, charge pump and the loop filter convert the
phase-error information to control voltage of the VCO. In the steady state the
net output of the charge pump current is zero and the divided output frequency

equals the input frequency.

1.1.1 Discrete-time behaviour of the PLL

φin(s) Ts φout(s) φin(z) φout(z)

+ +
H(s) H(z)
- -

N N

(a) (b)

Figure 1.2: (a) Continuous-time PLL model, (b)Discrete-time PLL model.

The PFD measures the phase error every reference cycle and the charge pump
outputs current pulses proportional to the phase error. Close to the steady state,

the phase error between the reference and divide signals is much smaller than 2π.
That is when the time difference between the rising edges of the reference and
divide signals is much smaller compared to the reference clock period T and the
charge pump outputs very narrow current pulses. The narrow current pulses oc-

curring every reference period can be modeled as impulses with amplitudes equal
to area under the pulses (the phase error). Thus the PFD and the charge pump be-
haviour can be modeled as a discrete time system, sampled at the input reference
frequency fr = 1/T [2]. But the loop filter and the VCO operate in a continuous

time fashion. This hybrid nature of the PLL makes it hard to analyze the sys-
tem. However when the bandwidth of the PLL is much smaller than the reference
frequency one can conveniently represent the PLL as a linear continuous-time sys-
tem.
Due to the discrete nature of the PFD and charge pump, it is more accurate

2
to analyze the PLL as a sampled data system with the phase errors sampled at
fr = 1/T [2]. The discrete time model of the PLL will reveal if there are any insta-
bility problems due to the sampling delay incurred by the discrete nature of the
PFD that may not be seen in a continuous-time model [1]. As shown in Fig. 1.2

40

35

30
Magnitude (dB)

25

20

15

10
Discrete time
Continuous time
5 2 3 4 5 6 7
10 10 10 10 10 10
frequency (Hz)

Figure 1.3: Closed-loop PLL magnitude response from the continuous and discrete
time models.

the continuous-time model can be transformed into its sampled equivalent by re-
placing the open loop continuous time filter H(s) with the sampled equivalent
H(z) using an impulse invariance transformation. Fig. 1.3 shows the magnitude

response of the PLL obtained from the discrete model overlaid with the response
of the continuous time linear model. The two responses are identical over most of
the frequency range except for a small peaking of 0.2 dB in the discrete-time model
near the 3 dB bandwidth of the PLL. Hence the continuous time approximation

can be used without any additional stability concerns for bandwidths smaller than
fr /10.
To see how the settling behaviour of the actual PLL is approximated by the
continuous-time linear model, we simulated the PLL behaviourally and then used

a continuous-time model to compare the time domain responses to a small step

in the frequency. Fig. 1.4 shows the LTI response overlaid with the actual step

3
 1080
actual
linear model
1070

1060

frequency (MHz)
1050

1040

1030

1020

1010

1000
0 1 2 3 4 5 6
time (us)

Figure 1.4: Response of the control voltage to a frequency step. The response of
an actual PLL matches the response obtained from a linear model in
an average sense.

response of the PLL for a certain step in the frequency. The PLLs step response
matches the linear model in an average sense. Hence it is common to use LTI
analysis to characterize the PLL loop dynamics.

1.1.2 Continuous time model of the PLL

φin(s) φout(s)
Icp/2π Hlp(s) 2πKvco/s

1/ND

Figure 1.5: Linear model of the PLL.

The input of the system is the reference phase φin (s) and the output of the system
is the phase of the VCO output φout (s). The open loop transfer function H(s) of

4
the linear phase domain model of the PLL is given by

 
φout (s) Icp Kvco 1 RCz 1
H(s) = = 2
+ s (1.1)
φin (s) (Cz + Cp )ND s s (1 + )
ωp

where Icp is the charge pump current, Kvco is the VCO gain in Hz/V, ND is the
divide value and ωp = 1/(RCz ||Cp ).

The unity gain bandwidth (UGB) of the PLL is given by

Icp Kvco R
ωu ≈ (1.2)
ND

Table 3.1 shows the parameters of the example1 PLL used to demonstrate the

Table 1.1: PLL parameters.

Parameters
Input frequency 20 MHz
PFD Tri-state PFD
Charge pump current Icp = 56 µA
Loop filter R = 21.7 kΩ, Cz = 37.25 pF, Cp = 1.99 pF
VCO fvco = 1 GHz, Kvco = 300 MHz/V
Divider ND = 50
unity gain bandwidth fu = 1 MHz
closed-loop 3dB bandwidth f3dB = 1.9 MHz
Phase margin PM= 52.550

operation and problems associated with the charge pump PLLs.

1.2 Problem of reference spurs

A major drawback of the charge pump PLL is the presence of reference spur in the

output spectrum. In the steady state of a charge pump PLL, the reference and
divide edges are aligned by the feedback action of the PLL. The phase error is zero
and thus the output of the PLL does not have any spur at the reference frequency.
1
The same specifications given in the example is used for the PLL designed in this work.

5
 icp(t)
Vdd
0 T 2T
VCO
fr
ref UP icp(t) fout
fdiv
div DN R
Cp
Cz

ND

(a) fout

Icp(f) Sφ(f)

-2fr -fr 0 fr 2fr fr fr

(b) (c)
Figure 1.6: (a) Standard charge pump PLL architecture showing the periodic na-
ture of the charge pump current, (b) the spectrum of the steady state
charge pump current and (c) the PLL output spectrum showing the
up conversion of the charge pump spurs.

6
However in the presence of nonidealities in the PFD and charge pump, a periodic
non-zero error current with zero average value flows into the loop filter as shown
in Fig. 1.6. This results in a periodic disturbance of the control voltage, which
frequency modulates the VCO and results in a spurs at the reference frequency

and its harmonics2 .

The nonidealities in the PFD, charge pump and loop filter that cause reference
Vdd

Iup=Icp
UP
Iftp icp(t)

DN R
-Iftn Cp Ileak
Idn=Icp+ Imis Cz

Figure 1.7: Charge pump nonidealities

spurs are

• mismatch in the UP and DN signal paths of the PFD

• mismatch in the UP and DN currents of the charge pump

• feed through of the charge pump switches

• leakage current in the loop filter capacitors

The charge pump current injected into the loop filter every reference cycle (T )
is a pair of impulses (narrow triangular pulses) spaced reset delay (Trst ) apart in
the presence of the feed through (Ift ) of charge pump switches and a pulse in
presence of charge pump current mismatch (Imis ) or loop filter leakage (Ileak ). The

illustrative pulse shapes of the charge pump current are shown in the Fig. 1.8(a),
1.8(b) and 1.8(c) respectively. This non-zero periodic current generates a periodic
2
In time domain this appears as jitter in the output and in frequency domain as discrete
components at integer multiples of reference frequency away from the output frequency.

7
icp(t) icp(t) icp(t)

Ift Icp Icp

Trst

{
T
T -Imis T -Ileak

{
-Ift
Trst
(a) (b) (c)
Figure 1.8: Illustrative pulse shapes of the charge pump current injected into the
loop filter every reference cycle in steady state

disturbance on the control voltage and manifests itself as a reference spur at the
PLL output. The magnitude of the spur at a frequency offset fr from the carrier

1.3

1.25

1.2
control voltage

1.15

1.1
1.1005
1.05

1 1.1

0.95 1.0995
5 5.05 5.1 5.15
0.9
0 1 2 3 4 5 6
time (us)

Figure 1.9: Periodic disturbance on the control voltage in steady state

at the PLL output can be expressed in dBc as [4]

!
2
Z(f ) Kvco
Sφ (f ) = 10 log Scp (f ) (1.3)
f

Where Scp (f ) is the spectral density of icp (t). When icp (t) is periodic at fr ,
Scp (f ) (and hence Sφ (f )) consists of impulses, or spurs, at integer multiples of
fr . A PLL was simulated with the PFD and charge pump at schematic level and
the remaining blocks at behavioural level. Fig. 1.9 shows the periodic disturbance

on the control voltage once the PLL has settled. Fig. 1.10 shows the phase noise of

8
 −60

−70

Phase Noise (dBc)

−80

−90

−100

−110

−120 1 2
10 10
frequency (MHz)

Figure 1.10: Spurs at PLL output at harmonics of reference frequency offset from
the carrier.

the PLL output in the presence of the periodic disturbances on the control voltage.
The presence of reference spurs at multiples of the reference frequency (20 MHz in
the above example) can be clearly seen from the figure.

Eq. (1.3) implies that a low spur level at the output is achieved by having a low
VCO gain (Kvco ) or a low loop filter impedance (Z(fr )). But reducing these two
parameters reduces the bandwidth of the PLL, leading to longer settling time and
lower noise filtering of the VCO. Therefore, there is a trade-off between settling

time and tolerable reference spur levels.

Several techniques have been proposed to minimize the spurs while maintaining a
higher bandwidth. [5] addresses the issue based on the technique of delay-sampling
the control voltage. This converts the periodic disturbances to dc, but it is not
effective in the presence of loop filter capacitor leakage. [6] minimizes the charge

pump mismatch thereby reducing the spur, at the cost of increased settling time.
[7] uses distributed charge pump and PFD with pulse position randomization to
reduce the spur. Using distributed PFD and charge pumps can cause the total
size of the charge pump switches to be larger, increasing the net feed through error

besides increasing the implementation complexity.

9
The central work of the thesis is to eliminate the spurs by spreading the energy
present in the spurs to all frequencies. To accomplish this, the charge pump current
pulse positions are modulated within a single reference period by modulating the
pulse positions of the UP and DN pulses as shown in Fig. 1.11. Random positioning
Vdd

fr UPr VCO
ref UP PPM/PR icp(t) fout
fdiv DNr
R
div DN PPM/PR
Cp
Cz

ND

Figure 1.11: The modified PLL architecture with pulse position modulator/pulse
repeater shown at block level.

of the charge pump current pulses icp (t) within the reference period T ( [7],[8]), in

other words, pulse position modulation (PPM) by a random sequence, breaks the
periodicity and distributes the energy in the reference spurs into wideband phase
noise. In order to quantify this effect, the spectral density of the charge pump
current (Scp (f ) in Eq. 1.3) after applying the random PPM has to be determined.
In this work, we present a general analysis of pulse trains whose amplitude and

pulse positions are modulated by independent stationary sequences with arbitrary

probability distributions and give closed form expressions for the spectral density.
This analysis is simpler and more intuitively understood compared to previously
published results [9]. We also analyze the effects of pulse repetition (PR) within a

reference period [7], and a combination of PPM and PR.

The proposed spur reduction techniques can be implemented in a more compact
manner compared to previously published ones because they involve delaying UP
and DN signals which control icp (t) by random amounts, which can be accom-

plished using digital delay lines and a MUX controlled by a random sequence [8].

10
A similar approach also results in a simpler implementation of PR compared to [7].
The proposed implementation is less sensitive to delay line mismatch than when
the delay lines are placed before the PFD [7]. Unlike the latter, it requires delaying
narrow pulses with a minimum width equal to the reset delay of the PFD. Design

trade offs due to these constraints are analyzed. Modifications to the implemen-
tation are suggested for cases when the reset delay is very small.

1.3 Overview of the thesis

The rest of the thesis is organized as follows

• Chapter 2 discusses the spectral analysis of PPM signals and ways to reduce
reference spurs at a system level. The performance of the proposed tech-
niques in the presence if delay line nonidealities is also discussed in detail.

• Chapter 3 explains the details of the circuits of the implemented PLL.

• Chapter 4 explains the implementation details of the supply regulated PLL

used for delay tuning.

• Chapter 5 shows the circuit level simulation results of the PLL.

• Chapter 6 presents the measured results taken from an actual silicon imple-
mentation.

• Chapter 7 concludes the thesis and suggests future work to be carrier out.

• Appendix A discusses the unified spectral analysis of digitally modulated

signals in the presence of nonidealities.

• Appendix B discusses the basics of linear and non-linear ring oscillators.

• Appendix C discusses the asymmetric sidebands in the presence of both AM

and FM.

11
 CHAPTER 2

Spur Reduction Techniques

2.1 Introduction

As discussed in the previous chapter, the periodicity in the steady state charge
pump current is the cause of the spurs at the output. The central idea of this

work is to break the periodicity in the charge pump current pulses by applying
pulse position modulation based techniques. In theory this randomizing effect
redistributes the energy of the current pulses concentrated at the harmonics of
reference frequency to all the frequencies making it appear as wideband noise. The

resulting “redistributed noise” is further filtered by the loop-filter and the VCO.
Ideally this approach can eliminate spurs completely. To quantify the effects of
the redistributed noise on the PLL output phase noise, spectra of different pulse
position modulation schemes are analyzed and optimum schemes are derived to
tackle the reference spurs based on the analysis.

2.2 Mathematical formulation

Let xk and ak be two stationary sequences. Then

∞
X
xp (t) = xk δ(t − kT ) (2.1)
k=−∞

is a pulse amplitude modulated (PAM) signal [10] of period T , and

∞
X
rp (t) = xk δ(t − kT − ak Td ) (2.2)
k=−∞
is a pulse position and amplitude modulated (PPAM) signal whose pulse positions
ak Td are modulated by the sequence ak ∈ [0, N − 1] and pulse amplitudes are
modulated by xk . The pulse shape p(t) is assumed to be an impulse for simplicity of
expressions. Fig. 2.1 illustrates PAM and PPAM signals for N = 8 and Td = T /N.

The signals xp (t) and rp (t) are cyclostationary random processes [10] when the
x0
(a) x2
xp(t) x1

0 T 2T

a1=5

(b) ak a =2
0
a2=0

0 T 2T

x0
x2
(c)
rp(t) x1
{

0 T 2T
Td
2Td T+5Td 2T+0Td
Figure 2.1: (a) PAM with sequence xk , (b) Pulse position modulating sequence
ak , (c) PPAM with sequences ak and xk for N = 8.

modulating sequences xk and ak are stationary. The power spectral density (PSD)
Sxp (f ) of the PAM signal in Eq. (2.1) is given by [10]

1
Sxp (f ) = Sx (f ) (2.3)
T

where Sx (f ) is the PSD of the stationary sequence xk (with an autocorrelation

P
function Rx (k)) given by Sx (f ) = k Rx (k)e−j2πf kT . If the samples of the se-
quence ak are iid, the PSD Srp (f ) of PPAM signal is given by (Appendix A.1)

1 Rx (0)
Srp (f ) = Sx (f )|C(f )|2 + [1 − |C(f )|2 ] (2.4)
T T

13
where
N
X −1
C(f ) = PA (a = m)e−j2πf mTd (2.5)
m=0

PA (a) is the probability mass function of the sequence ak . C(f ) is what we call the
“Pseudo filter1 ”. It is the characteristic function [10] of the modulating sequence’s
probability mass function. For any arbitrary pulse shape p(t), the PSD of the PAM
and PPAM signals is obtained by multiplying the above expressions by |P (f )|2 ,

where P (f ) is the Fourier transform of the pulse p(t). When p(t) represents the
charge pump current, the pulses are much narrower than the reference period T
and have an average value of zero.

2.2.1 Power lost and power redistributed

The spectrum of the PPAM signal can be written as

Sx (f ) Rx (0)
Srp (f ) = |C(f )|2 + [1 − |C(f )|2 ] (2.6)
| T {z } | T {z }
Power filtered Power redistributed

Eq. (2.6) shows that the PPAM is equivalent to passing the PAM signal (with a
PSD Sx (f )/T ) through a filter C(f ) and adding a component that corresponds to

redistributing the power that is filtered out (lost) as continuous wideband noise.
The characteristics of the filter and the noise are completely determined by the
probability distribution of the randomizing sequence ak . Since PA (a = m) is
P
positive for all m and m PA (a = m) = 1, C(f ) is a lowpass filter with unity dc

gain and the redistributed power has a highpass shape.

One can intuitively see that, on an average over a large number of clock cycles, the
samples of xp (t) would have occupied the positions mTd within the single interval
T , with weights PA (a = m). A scaled summation of the delayed versions of the
signal xp (t) is nothing but lowpass filtering of the signal.
1
Since it is not an actual filter.

14
2.3 PPM by an uniformly distributed iid sequence

P
Let xi (t) be a periodic impulse train of period T , xi (t) = k δ(t − kT ). xi (t) is
a PAM signal with xk always equal to 1, hence Rx (k) = 1. Using Eq. (2.3), the
PSD Sxi (f ) of xi (t) is given by

1 X −j2πf kT 1 X
Sxi (f ) = e = 2 δ(f − kfr ) (2.7)
T k T k

By virtue of its periodicity, the power of the signal is concentrated only at the
harmonics of the fundamental frequency (fr = 1/T ). Let ak be of uniform dis-
tribution ∈ [0, N − 1] and Td = T /N. Using Eq. (2.4), the PSD Sr (f ) of the
resulting N-PPM (N represents the number of pulse positions of the PPM signal)

signal r(t) can be computed to be

∞
1 X 1 
Sr (f ) = 2 δ(f − kfr )|CN (f )|2 + 1 − |CN (f )|2 (2.8)
T k=−∞ T

Since P (ak ) = 1/N, the squared magnitude of the associated pseudo filter CN (f )
from Eq. (2.5) is given by

N −1 2  2
2 1 X −j2πf lT /N sin(πf T )
|CN (f )| = e = (2.9)
N l=0 N sin(πf T /N)

CN (f ) is a moving average filter of length N with nulls at kfr where k ∈ ([1, N −

1], [N + 1, 2N − 1], · · · ). Thus the spectrum of N-PPM reduces to

∞
1 X 1 
Sr (f ) = 2 δ(f − kNfr ) + 1 − |CN (f )|2 (2.10)
T k=−∞ T

Comparing Eq. (2.10) to Eq. (2.7) we can see that the N-PPM signal contains
spurs at the harmonics of Nfr and the harmonics in [fr , (N − 1)fr ] are absent.

15
The second term in Eq. (2.10) is the ‘redistributed noise’ Ssn (f )

1 
Ssn (f ) = 1 − |CN (f )|2 (2.11)
T

The power lost Plost (power in the absent spurs) in the frequency band [0, Nfr ] is

Z N fr N −1
1 X (N − 1)
Plost = 2
δ(f − kfr ) df =
0 T k=1 T2

The power redistributed Psn in the same band is

Z N fr Z N fr
1  (N − 1)
Psn = Ssn (f ) df = 1 − |CN (f )|2 df =
0 0 T T2

Thus power filtered out Plost is equal to the power redistributed Psn . Random-
izing the impulse positions by a uniformly distributed sequence ak is equivalent

to passing it through a moving average filter and the harmonics in the inter-
val [fr , (N − 1)fr ] are eliminated and spread as ‘redistributed noise’ Ssn (f ). As
N → ∞, all the harmonics of fr are eliminated and converted to noise. The pseudo
filter in the limiting case can be shown to be a sinc filter2 |C∞ (f )| = |sinc(f T )| =

|sin(πf T )/πf T | and the spectrum of the ∞-PPM signal is given by

!
2
1 sin(πf T )
Sr (f ) = 1−
T πf T

Fig. 2.2 shows the simulated spectrum of the periodic signal and an 8-PPM signal.
From the figure we can see that the harmonics in [fr , 7fr ] are absent and spread as

noise. The simulated spectral density is coincident with the shape of redistributed
noise given by Eq. (2.10). To show the filtering nature of the PPM, Fig. 2.3 shows
the spectrum of the 8-PPM signal overlaid with the associated Pseudo filter. We
can clearly see the absence of harmonics occurring at the zeroes of the Pseudo
2
This might seem intuitively correct as we can see that the impulse response of pseudo filter
is the pmf of ak with the samples spaced T /N seconds apart. As N increases the samples come
closer and eventually become a continuous pulse of width T and magnitude 1/T (as the impulse
response is now a continuous probability distribution). The Fourier transform of a pulse is the
’sinc’ function.

16
 20
Unmodulated signal PSD

magnitude (dB)
0

−20

−40

−60
0 1 2 3 4 5 6 7 8
20
8−PPM PSD
magnitude (dB)
0

−20

−40

−60
0 1 2 3 4 5 6 7 8
frequency (f/fr)

Figure 2.2: The spectrum of the unmodulated impulse train and the spectrum
of the 8-PPM signal (PSD computed with a resolution bin width of
fr /512).

20
8−PPM PSD
Pseudo filter
10

0
magnitude (dB)

−10

−20

−30

−40

−50

−60
0 1 2 3 4 5 6 7 8
frequency (f/fr)

Figure 2.3: The spectrum of the PPM signal modulated by a uniformly distributed
sequence overlaid with the associated pseudo filter for N = 8 (PSD
computed with a resolution bin width of fr /512).

17
filter.

2.3.1 Shape of the redistributed noise

CN (f ) is a moving average lowpass filter. A moving average filter is a first order

shaped low pass filter and hence the redistributed noise has a first order high pass

characteristic. We can easily verify that for (N = 2), Ssn (f ) = (1/T )·sin2 (πf T /2),
which is a first order highpass filter. Thus the PPM technique when applied to a
PLL does not affect the close-in phase noise or long term jitter of the PLL. Fig. 2.4
shows the redistributed noise on a log scale for different values of N. The shape

is similar at low frequencies independent of the value of N.

−20
N=2
N=4
−30 N=8
N=16

−40
Magnitude (dB)

−50 1st order noise shaping

for different N

−60

−70

−80 −2 −1 0
10 10 10
frequency (f/fr)

Figure 2.4: Redistributed noise for different values of N (shown in a log scale for
better comparison).

2.3.2 Sensitivity to delay variations

The analysis above revealed that increasing N does not increase the noise shaping
at low frequencies but eliminates reference spurs up to Nfr . But increasing N
increases the implementation complexity of the PLL with randomization. Usually

eliminating the spurs from the first few harmonics of reference frequency is suffi-

18
cient as the spurs far away are well rejected by the lowpass characteristic of the
PLL loop filter itself. So in order to choose N, we consider the sensitivity to delay
variations as a measure of performance.
The charge pump current pulses are pulse position modulated by modulating the

UP/DN pulse positions3 . The delays Td in the implementation of PPM are re-
alized using inverters and are thus prone to systematic variations due to process
and temperature. In that case Td 6=T /N and the pseudo filter is given by

 2
2 sin(Nπf Td )
|CN (f )| = (2.12)
N sin(πf Td )

From Eq. (2.12) we can see that the filtering action introduces zeroes at frequencies

−5

N=2
−10
N=4
spur rejection (dB)

N=8

−15
N=16 & N=32

−20

−25
−40 −30 −20 −10 0 10 20 30 40 50
percentage variation in delay (Td)

Figure 2.5: Sensitivity to delay variations.

fz = k/NTd where k is an integer and k 6= 0, N, 2N · · · . When Td = T /N, the

zeroes occur exactly at the multiples of fr and the reference spurs up to Nfr are

completely eliminated. When Td 6=T /N, the zeroes of the filter do not occur at
multiples of fr and reference spurs appear at the output. Fig. 2.5 shows the spur
rejection when the delay Td varies from the nominal value of T /N. As N increases,
the sensitivity to delay variations improves up to N = 8 (improvement clearly seen
3
The UP/DN pulses are delayed by multiples of Td and one of them is chosen at random to
implement the PPM.

19
for positive % delay variations). Beyond that the improvement becomes marginal
and therefore N = 8 was chosen for implementation.
In the absence of any delay tuning mechanisms, the delays are prone to large
variations (±40%), hence the spur rejection degrades severely especially for lower

values of delays Td < T /N as seen from the figure (6 dB for -40 % variation). So to
avoid this problem one can choose a skewed nominal delay such that Td ≈ 1.3T /N.
As seen from the figure, even for ±40% variations in the skewed delay the spur
rejection is at least 13 dB as opposed to 6 dB for the nominal delay. Addition
of delay trimming mechanisms for process and temperature variations can reduce

the systematic delay variations to ±5% resulting in at least 25 dB spur rejection.

2.4 Spur reduction techniques

The previous section dealt with the analytical study of PPM, where it was shown
that PPM by an uniformly distributed iid sequence is equivalent to passing the
signal through an N-tap moving average filter and the energy in the reference har-

monics were removed and redistributed as wideband noise. In a charge pump PLL,
a periodic current is injected into the loop filter in the presence of nonidealities
which leads to reference spurs at the PLL output as explained in chapter 1. In
the current work, the periodicity in the charge pump current pulses is broken by
pulse position modulating the current pulses thereby redistributing the reference

spurs as noise. Other spur elimination techniques such as pulse repetition (PR)
which involves passing the current pulses through a moving average filter thereby
removing the spurs completely without redistributing them as noise are also dis-
cussed in detail. Variants of PPM and a combination of PPM and PR that have

advantage over a simple uniform PPM is also presented and their advantages are
discussed in detail in the remainder of this section.
Fig. 2.6 shows the modified PLL architecture employing the PPM based tech-
niques at a block level, with the illustrative charge pump current pulses before

20
 Vdd

fr UPr VCO
i) ref UP PPM/PR icp(t) fout
fdiv DNr
R
div DN PPM/PR
Cp
Cz

ND

ii)
icp(t) icp(t)

T T

(a) (b)

icp(t) icp(t)

T T
(c) (d)
Figure 2.6: i) The modified PLL architecture with pulse position modulator/pulse
repeater shown at block level. ii) Illustrative waveforms of charge
pump current before and after applying the techniques (a) Standard
PLL, (b) PPM, (c) Pulse Repetition (PR), (d) PPM+PR.

21
and after applying the techniques.

2.4.1 Random pulse position modulation (PPM)

sel [2:0]
Td=T/8

}
UP/DN

8:1 UPr/DNr
MUX

Figure 2.7: Implementation of PPM.

As explained in section 2.3, PPM of charge pump current pulses removes spurs
up to Nfr and converts them to wideband noise. To implement the technique
the pulse position of the UP/DN signals is modulated based on a random control
signal sel[2 : 0]. Modulating the pulse position can be accomplished by delaying
the pulses and choosing one of the 8 delayed versions using a 8 : 1 MUX based on

the control signal as shown in Fig. 3.11.

2.4.2 Pulse repetition (PR)

Instead of randomizing the pulse positions, we can repeat the pulse N times at

intervals of T /N within a single period, making it appear as a high frequency (Nfr )

signal. The charge pump current is reduced by a factor of N to ensure that the
charge delivered by the charge pump per reference cycle remains the same. This
is same as passing the current pulse through a N-tap moving average filter CN (f ).

The PSD Spr (f ) of the N-PR (N here refers to the number of the repeated pulse
positions) signal is

1 2
X 1 X
Spr (f ) = |C N (f )| δ(f − kfr ) = δ(f − kNfr ) (2.13)
T2 k
T2 k

22
In N-PR, the harmonics in [fr , (N − 1)fr ] are filtered out and unlike in N-PPM
there is no additional redistributed noise.
N-PR is implemented in [7] using N scaled charge pumps driven by delayed
UP/DN pulses generated by a distributed phase frequency detector (PFD). This

method of implementation increases the complexity as the number of charge pump

cells and PFDs increase with N. A much simpler implementation would be to drive
a single scaled charge pump with a repeated UP/DN pulse, generated by passing
N delayed versions of the UP/DN pulses through an N-input OR gate as shown in
Fig. 3.14 (a). For input phase errors smaller than T /N, the proposed implementa-

Td=T/N
(a) }
UP/DN
UPr/DNr

(b)
Qav Qav

-T -T/N -T/N
T/N T δt T/N δt

Standard PLL N-PR

Figure 2.8: (a) Pulse repeater circuit, (b) Charge delivered per reference cycle vs
phase error δt by the standard PFD+charge pump and N-PR+scaled
charge pump.

tion of the N-PR technique behaves similar to a standard PLL (charge delivered

per reference cycle is same for both the cases). For phase errors greater than
T /N, the delayed UP/DN pulses overlap and the output of the OR-gate is always
held high leading to gain saturation (charge delivered remains constant for errors
> T /N) as shown in Fig. 3.14 (b), which increases the settling time of the PLL. In
order not to affect the settling behaviour of the PLL, pulse repetition needs to be

deactivated and the charge pump current scaled up by a factor N when the PLL
is out of lock. This requires additional circuitry in the implementation.

23
2.4.3 Pulse position modulation with pulse repetition (PPM+PR)

Since PR removes the reference harmonics without redistributing it as noise, it

may seem more attractive than random PPM. However, when the charge pump
current is small (of the order of few micro amperes), dividing the current further
by N may not be possible due to the restrictions imposed by the charge pump

mismatch and leakage currents. Also charge pump switch sizes and mismatch
may not scale with charge pump currents, leading to an increase in the net error
current injected into the loop filter due to nonidealities. In that case as both PR
and PPM offer the same spur rejection, the PR technique can perform poorly
when compared to PPM in the presence of delay variations, since the magnitude

of the inherent spur is larger.

A combination of PR and PPM results in a better performance. To achieve the
same spur rejection of 8-PPM and 8-PR, we apply 4-PPM in conjunction with
2-PR, by passing the pulse through a 2-tap moving average filter C2 (f ) given by

C2 (f ) = (1 + e−jπf T )/2 and then randomizing the filtered pulse positions to four
values spaced T /8 seconds apart (this ensures that all the 8 pulse positions are
occupied). Fig. 2.10 (a) shows the UP/DN pulses before randomization and the
possible positions occupied after applying the technique. The spectrum of the

resulting signal is4

1 X 2 2 1
δ(f − kfr )|C(f )| |C 2 (f )| + (1 − |C(f )|2 )|C2(f )|2
T2 k T

P3 −jπf kT /4
where C(f ) is the pseudo filter associated with the 4-PPM, C(f ) = 0.25 k=0 e .
C2 (f ) has zeroes at odd harmonics of fr and C(f ) has zeroes at even harmonics
of fr except at multiples of 8fr . We can easily verify that

7
1 X −jπf kT /4
C(f )·C2 (f ) = e = C8 (f ) (2.14)
8
k=0
4
The spectrum can be obtained by first deriving the spectrum of the signal for 4-PPM with
2
Td = T /8 using Eq. (2.10) and then multiplying the resulting spectrum by |C2 (f )| (since 2-PR
is equivalent to passing the signal through the filter C2 (f )).

24
which is equivalent to an 8-tap moving average filter. The spectrum of the signal
reduces to
1 X 1
2
δ(f − 8kfr ) + (1 − |C(f )|2 )|C2(f )|2 (2.15)
T T
k

Eq. (2.15) shows that the spur rejection equals that of 8-PPM and 8-PR. The

0
8−PPM
4−PPM+2−PR
−10

−20
magnitude (dB)

−30

−40

−50

−60
0 1 2 3 4 5 6 7 8
frequency (f/fr)

Figure 2.9: The spectrum of the 8-PPM signal overlaid with the 4-PPM+2-PR
signal (PSD computed with a resolution binwidth of fr /512).

(a)
UP UPr

t 0
{
{

0 T/2 T T/2 T t
Td Td
sel [1:0]
(b)
Td=T/8
UP/DN
}

4:1 UPr/DNr
MUX

Figure 2.10: (a) The UP pulse before and after applying the technique, (b) Imple-
mentation details of combined 4-PPM+2-PR technique.

redistributed noise is lower compared to 8-PPM as it gets filtered by C2 (f ). One

can intuitively see that the current pulse is passed through a 2-tap moving av-
erage filter (2-PR), which eliminates the odd harmonics of fr and when 4-PPM

25
is applied, the power concentrated in the remaining even harmonics (other than
harmonics of 8fr ) are redistributed as noise. Since the total power in the reference
harmonics is reduced after 2-PR, the redistributed noise in the 4-PPM+2-PR is
smaller compared to 8-PPM.

Fig. 2.9 shows the simulated spectrum of the 4-PPM+2-PR signal overlaid with
the spectrum of 8-PPM signal. We can see from the figure that the noise with
the combined technique is lower than 8-PPM technique as expected. Fig. 2.10 (b)
shows the implementation details of the 4-PPM+2-PR technique. The repeated
UP/DN pulse is generated by first passing the pulse and a half cycle delayed ver-

sion of the pulse to a two input OR gate and then pulse positions of the repeated
pulse are randomly selected using a 4 : 1 MUX based on a two bit control word
sel[1 : 0]. The implementation complexity is also reduced compared to 8-PPM as
the complexity of multiplexer and the logic generating the select signals is now

reduced.

2.4.4 Shaped PPM+PR

When the magnitude of the spur is high, the redistributed noise floor is corre-
spondingly high. The noise is then passed through the PLL transfer function
which provides high gain for ‘midband’ frequencies (fr /100 to fr /10) inside the
bandwidth of the PLL. In cases where the PLL has very low phase noise require-

ments the redistributed noise may form a lower bound on the noise floor in this
region. To resolve this problem we can increase the order of noise shaping of the
redistributed noise5 .
The PSD of the PPM signal modulated by an iid sequence ai depends only on

the probability distribution of ai . When the samples of ai are correlated, the re-
sulting spectrum not only depends on its probability distribution but also on its
correlation properties. The correlation properties of ai can be exploited to control
5
A similar approach albeit for a different purpose is proposed in [11].

26
the shape of the redistributed noise. The spectrum of PPM becomes too complex
to compute analytically when ai is correlated for the general case (for any N).
Fortunately it is very easily tractable for N = 2. The spectrum Src (f ) of the
shaped PPM (SPPM) signal when ai takes on binary values (0 and 1) with equal

probability (p = 0.5), is given by (Appendix A.1.3)

1 2
X 4 sin2 (πf T /2)
Src (f ) = |C 2 (f )| δ(f − kfr ) + Sa (f ) (2.16)
T2 k
T

where Sa (f ) is the PSD of ak and C2 (f ) is the associated 2-tap pseudo moving

average filter. Eq. (2.16) shows that the redistributed noise depends upon the

PSD Sa (f ) of ai . Thus the redistributed noise can be tailored to shape the noise
further to higher frequencies by controlling the PSD of ai . If the sequence ai has
a high-pass spectrum, from Eq. (2.16) the order of the high pass shaped redis-
tributed noise is G + 1, where G is the high-pass order of Sa (f ).
One can realize an N-SPPM using an m-bit shaped sequence (N = 2m ) generated

using m independent one bit shaped sequences6 .

0 8−PPM
4−SPPM+2−PR
−10
Noise peaking @ 2fr
−20

−30
magnitude (dB)

−40

−50

−60 27 dB
−70

−80

−90

−100 −2 −1 0
10 10 10
frequency (f/f )
r

Figure 2.11: The spectrum of the 8-PPM signal overlaid with noise shaped 4-
SPPM+2-PR signal shown on a log scale for noise comparisons (PSD
computed with a resolution binwidth of fr /512).

27
The shaped PPM will increase the high frequency noise floor and hence it has to be
used in conjunction with PR technique to reduce high frequency noise. For N = 8,
the two possible combinations are one bit SPPM with 4-PR (2-SPPM+4-PR) and
two bit SPPM with 2-PR (4-SPPM+2-PR). Though using a 4-PR technique re-

sults in a lower high frequency noise, it suffers from the aforementioned problems
of gain saturation and net increase in spur magnitude in the presence of nonide-
alities like 8-PR. Hence we go for 4-SPPM+2-PR technique.
A 4-SPPM+2-PR technique is the same as 4-PPM+2-PR except that the modu-
lating sequence is a two bit higher order shaped sequence. In the current work we

chose a third order shaped sequence to achieve low midband noise. The two bit
shaped sequence was generated by combining two independent third order shaped
one bit sequences (generated as described in later sections). The two bit sequence
can be represented as ac [k] = 2a1 + a0 where a1 and a0 are two one bit sequences

with PSD given by Sa (f ) = | sin(πf T ) sin(2πf T ) sin(4πf T )|2 . The PSD of the
two bit sequence is

Sac (f ) = 5| sin(πf T ) sin(2πf T ) sin(4πf T )|2

The PSD7 of the 4-SPPM+2-PR signal is given by (Appendix A.1.4)

1 X 2 2 2 2 2


δ(f − kfr )|C(f )C 2 (f )| + |C 2 (f )| S a (f ) sin (πf Td ) + sin (3πf Td )
T2 k T

4

+ |C2 (f )|2 Sa2 (f ) 2 sin2 (2πf Td ) + sin2 (πf Td ) − sin2 (3πf Td )
T
P
where Sa2 (f ) = k (Ra (k))2 e−j2πf kT The pseudo filter and the 2-tap moving aver-
age filter associated with this technique are similar to those in the 4-PPM+2-PR
6
Extending the results presented in Appendix A.1.3, we can readily show that the redis-
tributed noise depends up to mth power of the autocorrelation function for m-bit case. This
results in the noise not truly being (G + 1)th order shaped due to the additional terms in the
redistributed noise.
7
The spectrum is derived in a similar manner as the 4-PPM+2-PR signal. First the spectrum
of 4-SPPM is computed (Appendix A.1.4) and the resulting spectrum is passed through the filter
|C2 (f )|2

28
technique. This ensures that the reference spurs up to 8fr are absent. The redis-
tributed noise however depends on the PSD Sa (f ) of the one bit sequences ai and
the Fourier transform of its squared autocorrelation (Ra (i))2 (proof given in Ap-
pendix A.1.4). Thus the noise is not truly third order shaped due to the additional

component in the redistributed noise. Nevertheless it leads to a significant reduc-

tion in the noise in the midband frequency range. Fig. 2.11 shows the spectrum of
the 4-SPPM+2-PR overlaid with 8-PPM. The high frequency noise is lower than
the 8-PPM technique for most of the frequencies and peaks at some points which
is expected in a shaped PPM. The midband noise is orders of magnitude less due

to aggressive noise shaping of the SPPM technique.

The implementation of the 4-SPPM+2-PR is similar to the 4-PPM+2-PR tech-
nique as shown in Fig. 2.10, where the two bit control signal is the shaped two bit
random sequence.

2.5 Delaying narrow UP/DN pulses

To obtain a delay of Td , we need an infinite bandwidth system with transfer

function e−sTd . An inverter is a delaying system with a finite bandwidth, which
depends upon the device length and the technology. This restricts the minimum
pulse width that a chain of inverters can delay reliably without attenuating it be-
low the switching threshold. In a given technology, a maximum bandwidth digital

delay line can be realised using a long chain of minimum length inverters. In a
0.18 µm CMOS process with a 1.8 V supply to realize a maximum bandwidth de-
lay line of delay 6.25 ns (Td ), the number of minimum length inverters necessary is
close to 100 and the average current consumption is 31 µA. At the slowest process

and temperature corners this chain can pass pulses of width > 200 ps without
significant attenuation. This minimum delayable pulse width (MPW) reduces as
technology scales down.
In a practical charge pump PLL, to improve the linearity of the PFD/CP and thus

29
avoid the problem of dead zone, a non-zero reset delay of Trst seconds is introduced
in the PFD reset path depending upon the size of the charge pump switches and
tolerable spur level. This ensures that the UP/DN pulses are ‘on’ for at-least Trst
seconds even when the PLL is in lock condition. The value of Trst can be close

to a few hundred picoseconds ([6, 12]), well above the minimum delayable pulse
width. Based on the value of Trst , the delay line is designed by varying the length
and supply voltage of the inverters used in the delay chain to obtain the desired
delay.
In cases where the desired Trst is close to the minimum delayable pulse width,

the delay line needs to have a very high bandwidth. Hence a large number of

Min. pulse width=Trst+Tx Min. pulse width=Trst

UP(DN) UPnew(DNnew)

Tx
UPnew(DNnew)
UP(DN) To CP
PPM/PR
UPr(DNr)

Figure 2.12: Implementation of the technique to tackle the narrow pulse problem.

minimum sized inverters are necessary to realize the desired delay. A straightfor-
ward approach to reduce the delay line bandwidth (hence its area and power) is

to increase the reset delay more than the desired value (thus making the UP/DN
pulses wider). But it leads to a proportional increase in spur level and noise con-
tribution from the CP, when fed to the charge pump in the presence of charge
pump nonidealities [6].

To resolve this problem, the width of the UP/DN pulses is first increased by Tx
before feeding it to the delay line and then reduced by the same amount once it
is out of the randomizing blocks, before being fed to the charge pump. Thus the
delay line sees wider UP/DN pulses and the charge pump sees narrower pulses,

relaxing the delay line bandwidth without compromising the spur level and noise.

30
Increasing the UP/DN pulse width by Tx can be accomplished by increasing the
PFD reset delay to Trst + Tx and decreasing the pulse width at the output of the
randomizing block can be accomplished using a two input AND gate and a delay
Tx as shown in Fig. 2.12. Thus the minimum UP/DN pulse width seen by the

delay line is Trst + Tx and the reset delay pulse width seen by the charge pump is
Trst . Even if Trst is small, Tx can be adjusted such that Trst + Tx is wide enough for
it to be transmitted through the delay line without increasing its area and power.
For a Trst of 500 ps, to realize a delay of 6.25 ns in a 0.18 µm technology, the num-
ber of inverters necessary is close to 60, with their length equal to 0.25 µm and

an average current consumption of 18 µA. Using the aforementioned technique,

with Tx =2.5 ns, the number of inverters necessary to realize the same delay across
process and temperature variations is 6, with their length equal to 1.25 µm and
an average current consumption of 4.3 µA. Hence the implementation of the de-

lay cell is made simpler and independent of Trst . The implementation techniques
presented in section 2.4 can be used with this minor addition of an AND gate and
delay Tx . In case of PR, the minimum time difference between two pulses is Td
seconds and hence the delayed pulse should not overlap with the next pulse. This

restricts Tx to be less than Td /2.

Another approach to implement the PPM/PR techniques is to place the delay
line before the PFD [7], where the delay lines are driven by the ref and div signals
instead of the UP/DN signals. Circuits for PPM, PR and PPM+PR with this
modified architecture are shown in Fig. 2.13. In this method the width of the

pulses is not a concern as the ref/div signals are much wider than the UP/DN
signals and the bandwidth of the delay line can be lower (two inverters with their
length equal to 3.3 µm is sufficient to realize a delay of 6.25 ns). Though placing
the delay line before PFD might seem attractive due to their small area and power

dissipation, a detailed comparison between the two methods (discussed in section

2.7) shows that the delay line after PFD has advantages like better delay mismatch
insensitivity, reduced implementation complexity and relatively smaller delay line

31
 fr
(a) UPr
8:1 ref

sel[2:0] PFD

8:1 div DNr

fdiv

UP0
ref
UP0
(b) PFD1 UPr
DN0
div
UPN

DN0
DNr
fr UPN
ref
PFDN DNN
fdiv DNN
div

fr ref3
(c)
UP0
4:1 ref

sel[1:0] PFD1
DN0
4:1 div
UP0 UPr
fdiv div3 UP1

DN0
DNr
ref3 DN1
UP1
4:1 ref

sel[1:0] PFD2
DN1
4:1 div

div3

Figure 2.13: Alternative implementation with delay lines placed before the
PFD: (a) PPM, (b) PR, (c) PPM+PR.

32
area (and current consumption) for the same jitter specification, compared to the
former method.

2.6 Modulating sequence generation

In practice the modulating sequence ak is generated using a pseudo random bit

sequence (PRBS) generator. Sequences produced by the PRBS generator are de-
terministic and periodic [13]. Let ak be a uniformly distributed periodic sequence

with a period M. Since the modulating signal is periodic, the PPM signal also
exhibits a periodic behaviour with a period Tp = MT . The PSD Sr,per (f ) of the
periodic PPM signal is given by (derived in Appendix A.1.2)

1 X (1 − |CN (f )|2 ) X kfr

Sr,per (f ) = 2
δ(f − kNfr ) + 2
δ(f − )
T k MT k
M

The above equation shows that, in a periodic PPM, the noise shaping and the fil-

tering nature of the random PPM are still preserved. But the redistributed noise
has only discrete ‘frequency slots’ (or impulses) over which the noise is spread due
to the modulating signal’s periodicity (unlike the random case where the noise is
spread continuously). This might seem intuitive since the PPM signal is periodic

with a period Tp , its spectrum should have energy concentrated only at the har-
monics of 1/Tp . The harmonics of fr are also the harmonics of 1/Tp = fr /M,
hence the redistributed noise contains spur at kfr , but reduced in magnitude.
Since CN (kfr ) = 0 for k ∈ [1, N − 1], for a N-tap moving average filter, we can
compute the strength of the reference spurs kfr to be

1
Sr,per (kfr ) = δ(f − kfr ) (2.17)
MT 2

Comparing the above equation to the spectrum of an unmodulated impulse train,

we can see that the strength of the reference harmonics is reduced by a factor

33
M. So increasing the periodicity reduces the redistributed noise level (by 3 dB for
two fold increase in M). One can intuitively see that increasing the time period
increases the number of frequency slots over which the redistributed power can be
spread and hence the noise level goes down.

2.6.1 Practical considerations for PRBS generation

Linear feedback shift register (LFSR) is used to generate a PRBS. A sequence a[i]

constructed using the taps of a LFSR will tend to have a uniform distribution if
sufficiently long lengths8 are used (as frequency of ones and zeros in the PRBS se-
quence will approach 0.5). For a LFSR of length L, the periodicity of the sequence
generated is M = 2L − 1. Increasing L increases the period and hence reduces the

noise level. Thus a long LFSR length not only ensures uniform distribution but
also a lower redistributed noise floor. For an LFSR of length 15 (M = 215 − 1),
the spur is reduced by 10 log(M) = 45.2 dB.
A three bit (N = 8) modulating sequence a[i] can be generated using three taps

of a single LFSR or by taking each bit from three LFSRs with different feed-
back configurations. In the latter case the sequence generated will have a ‘white’
spectrum as the samples of the sequence appear uncorrelated to each other. But
the implementation complexity is increased as we will need three LFSRs. When
the sequence is generated from a single LFSR, the samples of the sequence are

correlated as the tap outputs (z[i]) of the single LFSR are just shifted versions
of each other. For example taking the three consecutive tap outputs of a LFSR,
P
the modulating sequence is given by ac [i] = 2s=0 2s z[i − s]. The sequence ac [i]
possesses a low pass spectrum. For a low pass spectrum of the modulating se-

quence, the PPM signal will have higher noise at low frequencies than in the case
when the modulating sequence is uncorrelated. Fig. 2.14 shows the 8-PPM spec-
trum when modulated by an uncorrelated sequence generated by combining three
8
LFSR length refers to the number of shift registers.

34
 −10
PPM with uncorrelated data
−15 PPM with lowpass data

−20 −42

−25 −44

magnitude (dB)
−46 4 dB
−30
−48
−35 −50
−1.6 −1.1
10 10
−40

−45

−50

−55

−60 −2 −1 0
10 10 10
frequency (f/fr)

Figure 2.14: The spectra of the 8-PPM signal modulated by an uncorre-

lated (white) data and correlated (lowpass) data shown on log scale
for noise comparisons (PSD computed with a resolution binwidth of
fr /512).

uncorrelated one bit data, overlaid with the 8-PPM spectrum when modulated
by the correlated low pass sequence ac [i] in the above example. We can see that
the spurs are absent in the correlated case as well, but the low frequency noise
floor (fr /100 < f < fr /10) increases by 4 dB. Since the increase is marginal, it is

not critical as the low frequency noise is dominated by the PFD and charge pump
noise. Hence we can generate the three bit sequence from a single LFSR itself to
reduce the implementation complexity.

2.6.2 Shaped data generation

One method of generating shaped binary data for SPPM is by feeding a uniformly

distributed dither at the input of the quantizer of a one bit sigma delta modu-
lator (SDM). This ensures that the output bits generated will have an uniform
distribution (equal number of ones and zeroes) but the spectrum is high pass
shaped by the noise transfer function (NTF [14]) of the SDM.

35
Another way of generating shaped binary random numbers with equal number
of zeroes and ones is to use the Manchester encoding given in [15]. Manchester
encoding maps a bit 1 to [10] and bit 0 to [01] from a random binary data stream,
which provides a first order shaping [15]. Hence a third order shaped sequence can

be generated by repeating the procedure three times. After the repeated encoding
process, bit 1 is mapped to [10010110] and bit 0 is mapped to [01101001]. The
magnitude spectrum of the shaped random binary stream (after removing the dc
component) can be shown to be |sin(πf T )sin(2πf T )sin(4πf T )|. This method of
generating shaped binary random numbers is very simple to implement because it

requires a single LFSR running at fr /8 and a few additional registers. Therefore

we choose this method for generating the shaped sequence.

2.7 Effects of delay line nonidealities

The delays are implemented using CMOS inverters and are prone to process vari-
ations, random mismatch and device noise (thermal and flicker). The effect of

process variations is discussed in section 2.3.2. The mismatch in the delay lines
leads to a reference spur and the noise in the delay lines increases the noise floor
at the VCO output. The detailed analysis is discussed in the remainder of the
section.

2.7.1 Effect of mismatch

In the presence of mismatch, a delay of iT /N in the UP and DN signal paths,

becomes iT /N + ∆Tui and iT /N + ∆Tdi respectively as shown in Fig. 2.15. To

analyze its effect on the PLL performance, we split the delay variation into common
mode and differential components. When these pulses are fed to a charge pump,
the common mode component in the delay iT /N + (∆Tui + ∆Tdi )/2 leads to an

additional time shift in the current pulse from its ideal position and the differential

36
component in the delay ∆Tdi − ∆Tui produces a zero average current pulse whose
width is equal to ∆Tdi − ∆Tui as shown in Fig. 2.15. The narrow charge pump
current pulses can be modeled as impulses spaced Trst seconds apart9 with weights
given by the area under the pulses and delayed by the common mode component.

Let ∆T be variation (due to device mismatch or random device noise) in the delay
of single delay cell of value T /N (where ∆T is a zero mean gaussian random
variable with variance σ∆T 2 ). A delay of iT /N is obtained by passing the pulse
through i identical delay cells of value T /N. Assuming that the variations in
the delay cells are independent of each other, the variance associated with the

delay iT /N is iσ∆T 2 . Thus the variance of random variables ∆Tui and ∆Tdi is
iσ∆T 2 . Let ∆Tcmi = (∆Tui + ∆Tdi )/2 and ∆Ti = ∆Tdi − ∆Tui be the common
p
mode and differential variations in the delay iT /N. Then σ∆Tcmi = i/2σ∆T
√
and σ∆Ti = 2iσ∆T . In the presence of common mode mismatch, the phase

Delay line after PFD Delay line before PFD

Ideal pulse Ideal pulse

position (iT/N) position (iT/N)

UP ref

∆Tui ∆Tui

DN div

∆Tdi ∆Tdi
icp(t) Icp icp(t) Icp
∆Ti
}

{
{

∆Ti ∆Ti
-Icp ∆Ti=(∆Tdi-∆Tui)
Icp∆Ti Icp∆Ti
∆Tcmi=(∆Tui+∆Tdi)/2
icp(t) Trst icp(t)

∆Tcmi -Icp∆Ti ∆Tcmi

Figure 2.15: The UP/DN pulse waveforms and the charge pump current in the
presence of delay variations corresponding to a delay of iT /N.
9
In the analysis it is assumed that only the delay cell is the source of noise and hence the
width of UP/DN pulses is equal to Trst (the reset delay seen by the charge pump).

37
shift iT /N becomes iT /N + ∆Tcmi , which leads to a change in the delays of the
pseudo filter. When the delays vary, the location of the zeroes of the pseudo
filter change (fz 6=k/T ) leading to a degradation in spur rejection. The maximum
degradation occurs when there is maximum variation in the delays. Since ∆Tcmi

is a gaussian random variable, the maximum variation in in the delay iT /N is

considered to be ≈ 3σ∆Tcmi . The pseudo filter C(f ) for a worst case scenario can
be written as
1 X −j2πf (iT /N +3√i/2σ∆T )
N −1
|C(f )| = e
N i=0

Fig. 2.16 shows the degradation in spur rejection in the presence of random mis-
match. A point to note is that, in the absence of any delay trimming mechanisms
the effect of these random mismatch errors will be dominated by the large system-
atic errors in the delay caused by temperature and process variations as explained

in section 2.3.2. The degradation due to systematic errors (±10 %) is overlaid with
the random mismatch case in Fig. 2.16 to show its dominance.
The differential mismatch produces a zero average current pulse whose amplitude
depends upon the delay value selected. The effect of differential mismatch on the

PLL output spectrum can be easily understood in case of PR. When a delay of
iT /N is selected, the error pulse injected can be expressed as (Icp ∆Ti /N)pd (t −
iT /N), where pd (t) = δ(t) − δ(t − Trst ). In PR, N delayed versions of the UP/DN
signals appear per reference cycle, hence we have N mismatch current waveforms

corresponding to the N delayed versions. So a periodic current is injected into the

loop filter every reference cycle in the presence of differential mismatch between
the delay lines. Thus differential mismatch is an additional source of reference
spur. The worst case scenario occurs when the mismatches between the delays in
√
the UP/DN delay lines add up in the same polarity and ∆Ti = 3 2iσ∆T . The
periodic charge pump current injected per reference cycle due to the differential

38
 −20

−25
Systematic error
−30

spur rejection (dB)

−35

−40

−45 Random mismatch

−50

−55
−0.1 −0.05 0 0.05 0.1
mismatch (3σ/Td)

Figure 2.16: Spur rejection vs random delay mismatch.

mismatch can be expressed as

√ N −1
2Icp 3σ∆T X √
incp (t) = ipd (t − iT /N) (2.18)
N i=0

The magnitude of the spur (dBc) using Eq. (1.3) is given by

√ N −1
Z(fr ) Kvco 2Icp 3σ∆T X √ −j2πifr T /N
20 log Pd (fr ) ie
fr NT i=0

Pd (f ) = 1 − e−j2πf Trst is the Fourier transform of the pulse pd (t) which is first
order highpass shaped. In case of the PPM based techniques, on an average over

a large number of reference cycles, all the error waveforms appear equal number
of times (since ai is uniformly distributed) within a reference cycle. Hence the
average current waveform per reference cycle is the same as in PR and so is the
magnitude of the reference spur. Thus all the techniques produce spurs of the

same magnitude. The PPM based techniques additionally add redistributed noise
at the PLL output. For a Trst of 780 ps and a 5 % mismatch in a single delay
cell (3σ∆T = 0.05T /N), the reference spur introduced is -61.6 dBc. To remove this

39
component of spur, the UP and DN delay lines can be randomly interchanged
based on an additional random signal. The noise added by this randomization
will have insignificant contribution at dc due to the highpass nature of the pulse
pd (t). However it adds to the implementation complexity of the logic.

When the delay lines are placed before the PFD, only the positive half of the error
current (in Fig. 2.15) is injected into the loop filter in the presence of mismatch.
The PLL responds in a way such that the average current injected into the loop
filter every reference cycle is zero. Thus the per cycle error current waveform in
case of PR can be represented as

√ N −1
2Icp 3σ∆T X √
incp (t) = ( i − α)δ(t − iT /N) (2.19)
N i=0

P √
where α = (1/N) i i. The magnitude of the spur for the same mismatch as

before can be computed to be -41.25 dBc. The magnitude of the spur is 20 dB

higher than the former case, where there is a significant reduction in spur due to
the highpass nature of the pulse pd (t). Randomizing the mismatch in this case
will directly affect the inband noise as well due to the absence of pulse shaping.
This is one major disadvantage of placing the delay line before PFD. Results from

behavioral transient simulations show that the spur reduction when the delay lines
were placed after PFD was 19.1 dB more than when they were placed before the
PFD (close to the value predicted by analysis).
When the pulse narrowing circuits (Fig. 2.12) are used in the UP and DN paths,

there will be mismatch between Tx values used in the two paths. This mismatch
appears as a dc phase offset (as every pulse is passed through the circuit) and gets
corrected by the PLL. Thus no additional spur is created due to the mismatch
between the delays in the pulse narrowing circuits.

40
2.7.2 Effect of noise

In the presence of delay line noise, the rising and falling edges of the UP/DN pulses
are corrupted by jitter at the output of the delay line. This leads to an injection
of noise current at both these edges spaced Trst seconds apart into the loop filter.
The noise analysis can also be carried in a similar manner by splitting the error

as common mode and differential components. Unlike the case of delay mismatch,
the variations in the rising and falling edge are not the same due to uncorrelated
nature of the noise. The common mode component of the delay line noise can
be treated as a random variation in the delays of the pseudo filter. This leads to
degradation in the spur rejection. But this effect will be negligible compared to

the effect of mismatch due to its small magnitude and hence it can be ignored.
The differential component of the delay noise however is an additive noise at the
charge pump output and hence degrades the output phase noise. The jitter in the
rising and falling edges can be treated as uncorrelated and identical noise sources.

If Sn (f ) is the noise current density due to the rising edge jitter, then the total
noise current density is 2Sn (f ) (the sum of two uncorrelated noise PSDs).
When the delay lines are placed before the PFD [7], the jitter of the delay line acts
as an input phase error to the PLL and the PFD measures the phase difference

between the rising edge of the ref and div signals. So only the error current
corresponding to the rising edge is injected into the loop filter and the noise current
spectral density is given by Sn (f ). Thus the noise added due to delay line jitter
is 3 dB lower compared to the former case.
Fig. 2.17 shows the PLL output phase noise when the delay line is placed before

and after the PFD. For the computations, each delay cell (of delay 6.25 ns) was
modeled to have an rms jitter of 2.8 ps10 . The inband noise as shown in the figure
is -107 dBc/Hz and -104 dBc/Hz when the delay lines are placed before and after
10
The jitter was computed using the phase noise analysis in ‘spectre’ on a delay line built
using six CMOS inverters in 0.18 µm technology with an MPW > 3 ns (Trst + Tx = 3 ns and
Trst = 780 ps) and their supply held at 1.8 V. Also the same delay line is used before and after
PFD.

41
PFD in case of PR. Thus with the same delay line jitter before and after PFD,
the output phase noise is 3 dB more for the latter.
Also the figure shows that the PR technique adds the least noise among all the
proposed techniques. In PR the amplitude of each pulse is 1/N of that in PPM,

resulting in a 1/N 2 times noise power per pulse. Since there are N pulses per
period in PR as opposed to a single pulse in PPM, the total noise power due to
the delay line jitter in PR is N/N 2 = 1/N of that of PPM (9 dB less for N = 8).
Thus making PR desirable due to the low noise levels associated with it.
When the delay lines are placed before the PFD, fewer inverters of lower bandwidth

can be used to realize a given delay compared to when the delay lines are placed
after PFD. But to a first order, for a given delay and jitter specification, the

−70 −70
Delay line before PFD Delay line after PFD
−80 −80
−90 −90 9 dB
9 dB
−100 −100
Phase noise (dBc/Hz)

−110 PPM −110 PPM

−120 −120 −104 dBc/Hz
−107 dBc/Hz
−130 −130
−140 −140
−150 PPM+PR −150 PPM+PR

−160 −160 PR
PR
−170 −170
−180 0 2−180 0 2
10 10 10 10
frequency (MHz) frequency (MHz)
Figure 2.17: PLL output phase noise due to the delay line noise when delay line
is placed after and before PFD.

power consumed by a short chain of low bandwidth inverters is the same as the
long chain of high bandwidth inverters. Also simulations show that the gate
area increases gradually as the delay line bandwidth reduces (or as device length

increases). Therefore no significant benefit is gained in placing the delay line

42
before PFD, besides the 3 dB difference in noise mentioned above. This advantage
has to be weighed against the significantly large spur due to mismatch between
UP/DN delay lines as shown before, and, in case of PR, increased implementation
complexity (multiple PFDs). In the author’s opinion, it is preferable to place the

delay line after the PFD and use the technique shown in Fig. 2.12 to increase the
pulse width to a value that results in convenient bandwidth and the number of
inverters in the delay line.
When the pulse narrowing circuits (Fig. 2.12) are used in the UP and DN paths,
the jitter in the delay Tx directly contributes to the inband noise. But since the

delay Tx is much smaller compared to the large delays of the delay lines in the
randomizing blocks, its effect on the output phase noise is negligible compared
to that of the latter. A detailed analysis of PPM was performed and several
techniques based on the analysis were proposed to mitigate reference spurs. Owing

to a strict time constraint we could only implement PPM and PR technique in

the current work. The rest of the thesis explains the circuit details employed in
implementing the techniques and present the simulation and measured results.

43
 CHAPTER 3

Implementation Details

3.1 Introduction

The block diagram of the implemented PLL to test the proposed ideas of spur
reduction is shown in Fig. 3.1. The parameters of the implemented PLL is shown

UP
PRBS CP1

sel[2:0] DN PLL_SEL
VCO
fr
ref UP UP UPr

fdiv PFD PPM/PR

div DN DN DNr
PLL_SEL
LPF
DN
CP2
UP

ND

Figure 3.1: Block diagram of the implemented PLL.

in Table. 3.1. The UGB of the PLL was chosen to be fr /20 = 1 MHz. The
circuit level implementation of the individual blocks are discussed in detail in the
reminder of the chapter.

3.2 Phase frequency detector

A PLL is a feedback system that forces the divide phase to equal the reference
phase. Any phase difference between the reference and divide signals is measured
 Table 3.1: Implemented PLL parameters.

Parameter
Input frequency 20 MHz
PFD Tri-state PFD
Charge pump current Icp = 56 µA
Loop filter R = 21.7 kΩ, Cz = 37.25 pF, Cp = 1.99 pF
VCO fvco = 1 GHz, Kvco = 300 MHz/V
Divider ND = 50
unity gain bandwidth fu = 1 MHz
closed-loop 3dB bandwidth f3dB = 1.9 MHz
Phase margin PM= 52.550

as an error signal by a phase frequency detector (PFD). Charge pump PLLs employ
the classic tri-state PFD for its linear phase to voltage characteristics and zero

static power dissipation in the steady state [1].

The schematic of the tri-state PFD used in the design is shown in Fig. 3.2. The
reset path shown here has an ‘AND’ gate and a buffer which introduces a delay
of 1.2 ns (in the nominal case) to address the problem of dead zone [1]. The D-flip

Vdd

UP
D Q
Ref
R

Div R

D Q
DN
Vdd
Figure 3.2: Tri-state PFD.

flop used in the design is a standard architecture built using high speed master and
slave latches. The schematic of the D-flip flop is shown in Fig. 3.3. The flip-flop
also has an asynchronous reset incorporated into it. The reset is performed by the
MOS devices Mnr and Mpr as shown in the figure.

45
 Vdd Vdd Vdd Vdd Vdd

R
Mpr

CLK CLKb
D Q Q
CLKb CLK

R R
Mnr Mnr

Figure 3.3: DFF used in the PFD.

3.3 Charge pump

Charge pump is the interface between the PFD and the loop filter. The UP/DN
pulses contain the phase error information between the reference and divide signals

in their pulse widths. Since the VCO needs a voltage for its control, a simple way
to convert the error information in pulse widths to a voltage is to generate current
pulses whose widths are proportional to the phase error and inject it into an
impedance with lowpass characteristic.

3.3.1 Charge pump implementation

Vdd Vdd Vdd

UP

UP UP UP
To LPF To LPF To LPF
DN
DN DN
DN

Figure 3.4: Charge pump switch arrangements.

To convert the phase error information in UP/DN signals to current pulses, the
UP/DN pulses turn two current sources on and off as shown in Fig. 3.4. When
both the UP and DN signals are high, the output current is zero. That is the

charge pump does not respond to common mode changes in the UP/DN signals.

46
For positive phase errors the UP pulse goes high and a positive current pulse is
generated by the charge pump. For negative phase errors the DN pulse goes high
and a negative current pulse is injected into the loop filter.
The current pulses can be generated in in three ways as shown in Fig. 3.4. In the

first two ways shown in Fig. 3.4(a) & (b), the current source is fully turned off when
the UP/DN signals are zero. When any of the signals goes high, the current has
to fully turn on to produce a current pulse proportional to the phase error. Thus
the current pulses produced by the first two methods contain large current spikes
in the current output as the current source has to fully turn on from an off state.

The architecture shown in Fig. 3.4 c) ‘steers’ the current when the UP/DN signals
are zero into a different path. Thus the current source is never fully turned off
leading to a low feed through current injection into the loop filter when the UP/DN
changes their levels. The charge pump implemented in our design is illustrated

Vdd
Vbiasp
Mp Vdd

Vcascp Icp
Mp

UP UP UP UP
P P

DN DN DN DN
N N
Vcascn
Mn
Icp
Vbiasn
Mn

(a) (b)

Figure 3.5: Charge pump implementation.

in the Fig. 3.5.(a), showing the bias devices and the switch configuration. The
devices Mp , Mn are the bias devices that generate the desired UP and DN currents.

The bias voltages that set the currents are derived using a bias generation circuit
explained in the following section. Dummy devices are added to the switches

47
as shown in Fig. 3.5.(b) to reduce the feed through current injected during the
transitions in the UP/DN signals. The unity gain follower shown in the Fig. 3.5
is used to maintain the same drain voltages of the switching NMOS and PMOS
devices used for current steering. This reduces the errors injected due to drain

voltage mismatch of the current steering devices. The schematic of the unity gain
follower amplifier implemented as a two stage amplifier with miller compensation
is shown in Fig. 3.6. The open loop gain and phase response of the amplifier is
Vdd

Ibias

im ip

out

Figure 3.6: Amplifier used in the charge pump.

shown in Fig. 3.7. The UGB of the amplifier is 13.7 MHz and the phase margin
is 84 degrees. The wide swing operation of the amplifier is tested by applying a

60
magnitude (dB)

40

20 UGB=13.7 MHz

−20 −3 −2 −1 0 1 2
10 10 10 10 10 10

200
Phase (degree)

150
84 degree
100

50

0 −3 −2 −1 0 1 2
10 10 10 10 10 10
frequency (MHz)

Figure 3.7: Magnitude and phase response of the unity gain amplifier used in the
charge pump.

voltage ramp of slope 1.8 V/10 µs. As shown in the Fig. 3.8, the amplifier tracks

the input for a range of 0 to 1.4 V. The saturation in the gain at high input voltages

48
occurs due to the PMOS input pair of the amplifier entering into the cut-off region.
An important point to note is that the input pair enters cutoff region as the input
voltage increases above Vdd −|VD,sat | −|VT p | and this results in the devices entering
sub threshold region and for further increase in the input voltage to cutoff region1 .

From simulations without any mismatch in the input pair it was found that the
input voltage tracks for a voltage range of 0 - 1.4 V as shown in Fig. 3.8.

1.8

1.6

1.4
Amplitude (V)

1.2

0.8

0.6

0.4

0.2 input
output
0
0 5 10 15 20
time (µs)

Figure 3.8: Transient simulation showing the wide swing operation of the ampli-
fier.

3.3.2 Charge pump bias generation

An external voltage source (Vr = 0.9) is used to generate the UP current by us-
ing an amplifier in feedback as shown in Fig. 3.9. The generated UP current is
Iup = Vr /R = 56µA. The UP current source, is then used to generate the DN

current by a replica feedback mechanism as shown in Fig. 3.9, thus ensuring that
the UP and DN currents are equal. The amplifiers used in the bias generation
circuit are single stage differential to single ended converters with PMOS inputs.
The bias devices are sized with large lengths and hence proportionally larger
width for a given Gm (W = L = 2µ for PMOS and W = L = 4µ for NMOS) to
1
Though the gain and bandwidth reduce with increasing voltage level, the follower functional-
ity does not have a significant impact on the PLL performance for such small variations between
the input and output voltage.

49
 Reference current generation Replica feedback Bias filtering

Vdd Vdd Vdd

Vref_cp
−
Vgp Vgp Vgp_cp
+ Vdd
vcascp

R_cp vcascp vcascp_cp

Vr

vcascn vcascn_cp
Vdd

−
Vdd
Vgp

vcascn vcascp vcascn Vfb Vfb_cp

Vfb

Figure 3.9: Charge pump bias generation circuit.

achieve the following benefits. Large area devices reduce the flicker noise contri-

bution of the individual devices of the charge pump and also leads to a smaller VT
and Vds (λ) mismatch. Additionally it adds to the supply bypass capacitor that
filters the supply noise and the noise from current mirroring devices.

3.4 Loop filter

The loop filter used in the PLL is the standard architecture with a proportional and
integral path provided by a resistor (R) and capacitor (Cz ) as shown in Fig. 3.10.

The capacitor Cp is to reduce the fluctuations on the control voltage or to reduce

the magnitude of the reference spur at the PLL output. The values of the resistor
and capacitors are chosen based on the loop dynamics as explained in Chapter 1.

50
 Icp

R R = 21.23 kΩ
Cz= 39.25 pF
Cp
Cp= 3.925 pF
Cz

Figure 3.10: Loop filter architecture.

3.5 Pulse position randomizer and pulse repeti-

tion circuit

3.5.1 Randomization

The charge pump pulse position is randomized to spread the energy in the reference

harmonics to all frequencies as described in Chapter 2. This randomization can

be achieved by randomizing the UP/DN pulses that are fed as an input to the
charge pump. The pulse position randomization is done in two steps.

• First the different delayed versions of the UP/DN pulses are generated using
a chain of delay cells
• Next one of the delayed versions is chosen using a 8:1 multiplexer based on
a 3-bit control word

sel [2:0]
Td=T/8
}

UP/DN

8:1 UPr/DNr
MUX

Figure 3.11: Pulse position randomizer.

Fig. 3.11 shows the pulse position randomizing circuit at a block level.

51
3.5.2 Delay cell

The delay cell is implemented as a chain of CMOS inverters. The desired delay is
controlled by varying the supply voltage of the CMOS inverter. Fig. 3.12 shows

Vc Vdd Vdd
Vdd
in out
in out

Vc Vdd Vc Vdd

in out

13 inverters 13 inverters

Figure 3.12: Delay cell implementation.

the schematic of the delay cell. The delay cells should be able to delay very narrow

pulses of width ≈ 1 ns, which is the reset delay of the PFD. So the lengths of the
delaying inverters should be chosen to ensure not only that the desired delay is
met but also the narrow pulses should pass through them without being filtered
out by the low pass nature of the delay cells. In the current work the length and

widths were chosen through simulations such that they were able to allow narrow
pulses of worst case width close to 0.8 ns. High speed buffers are inserted after the
13 cells to restore the pulses to a nearly rectangular shape.

3.5.3 8:1 Multiplexer

The 8:1 MUX is implemented by using 2:1 MUXs as shown in Fig. 3.13. Each
2:1 MUX is a set of switches with a driving inverter. The pass switches are

implemented as transmission gate switches. The 2:1 MUX output is driven by an

inverter, to reduce the load seen by the input to the 2:1 MUX.

52
 sel[0] sel[1] sel[2]

i0
2:1
i1
2:1
i2
2:1
i3 out
2:1
i4
2:1 S
i5 A
2:1
i6 O=AS+BS
2:1 S
i7
B

Figure 3.13: 8:1 Multiplexer.

3.5.4 Pulse repeating circuit

The pulse repetition is accomplished by passing delayed versions of the UP/DN

signals through an 8-input OR gate as discussed in Chapter 2. The conceptual

Td=T/N
}

UP/DN
UPr/DNr

Figure 3.14: Pulse repeater.

schematic of the idea is shown in Fig. 3.14 for N = 8. To implement the 8-input
OR gate for the pulse repetition technique, a pseudo NMOS logic is chosen over
CMOS logic. In a CMOS implementation the PMOS devices form a series stack
for the OR gate implementation and the NMOS devices are connected in parallel.

Hence the discharging path of the output node is same for the different delayed
pulses but the charging times are different for the different delayed versions. This
generates a varying output pulse width for different delayed versions, introducing
a periodic behaviour in the repeated pulse every reference cycle. Hence reference

spurs appear at the output. A pseudo NMOS implementation ensures that the

53
charging and discharging paths are identical for all the delayed versions of the
pulses and hence leads to a perfect pulse repetition. The schematic of the 8-input
OR gate is shown in Fig. 3.15.
Vdd

out

ip1 ip2 ip8

Figure 3.15: 8-input OR gate schematic.

3.6 Modulating sequence generation

For N = 8 we need a three bit random number to control the 8:1 MUX. For a
PRBS of length L with an Linear feedback shift register (LFSR) structure, maxi-
mum length sequences can be generated by many combinations of taps which are
summed and fed back to the first stage [13]. Once the length of the PRBS is chosen,
the number of possible configurations (the taps whose outputs are summed and fed

back to the first stage), varies with the length and all these configurations leads to
a maximum length sequence. Simulations showed that the sequences generated by
these different configurations were uncorrelated to each other and hence a binary
summing of the output of three such maximum length sequence implementations

produces three bit binary stream with a white spectrum. The different configu-
rations of LFSR of length 15 used for the three bit random number is shown in
Fig. 3.16. The PRBS is custom designed using CMOS logic.

54
 z3[i]
1 14 15 4

z2[i] a[i]=zl[i]+2z2[i]+4z3[i]
1 11 15 2

z1[i]
1 8 15 1

Figure 3.16: 3-bit random number generation.

3.7 Timing analysis for clocking the modulating

signal

T1= UP/DN pulse span

T2= UP/DN pulse span

of previous cycle
T3= Time window for changing
the modulating sequence

T2 T3 T1

(k-1)T kT-T/N kT

Reference
edge position

Figure 3.17: Figure showing the timing for the PRBS and the PLL.

The modulating sequence is changed every reference cycle and needs to be clocked

appropriately to avoid any timing clashes with the UP/DN signals. In the steady
state the UP/DN pulses appear close to the reference edge. If the divider edge
leads the reference edge, the DN pulse appears before the reference edge and vice
versa. The span of the UP/DN pulses is shown as T1 in Fig. 3.17. In the previous

cycle when a delay of 7T /N is selected, the UP/DN pulse can appear at kT −T /N

55
in the previous cycle. The span of the UP/DN pulses around kT − T /N is shown
as T2 in the figure. Hence the modulating signal for the k th reference cycle has to
be changed in the time window between kT and kT − T /N as shown in Fig. 3.17.
This ensures that the change in the select signal for the k th cycle does not conflict

with the timing of the UP/DN pulses of the current and previous cycle. So the
reference clock is fed to the PRBS first and a delayed version (delayed by 2.5 ns)
is fed to the PFD in the PLL.

3.8 Voltage controlled oscillator

Ring oscillators are known for their easy integration and wide tuning range in
CMOS processes. LC oscillators are known for very good phase noise performance,

but the inductors occupy very large area and need extensive additional work to
model, design and layout them. Thus a ring oscillator based VCO is chosen for
implementation in the current work.
A n-stage ring oscillator is formed by a cascade of n single pole amplifiers with

the final output negatively fed back to the input of the first stage amplifier. For
a given frequency of oscillation and a phase noise specification, the area and the
power dissipated is independent of the number of stages in the oscillator (explained
in Appendix B). A three stage ring oscillator is chosen in the current work for
implementation for simplicity.

3.8.1 Delay cell

A fully differential three stage ring oscillator is chosen as the VCO for the PLL
due to its immunity to common mode noise sources like the supply noise. The
differential delay cell has NMOS inputs and a diode connected PMOS load as
shown in Fig. 3.18. The minimum supply voltage necessary for the operation of

56
 Vdd

Vb Vb Vb
om op

ip im Vc Vc Vc

Vb Vc

Figure 3.18: Basic VCO cell.

the delay cell is

Vdd,min = Vovp + Vovn + VT n + |VT p | + Vovt

where Vovp , Vovn and Vovt are the overdrive voltages of the PMOS load, NMOS
input and the NMOS tail transistors of the delay cell. The lengths of the devices
are chosen to meet the desired range of frequency of oscillation.

Having a large overdrive improves the phase noise performance of the VCO as it
reduces the noise contributed by the individual devices. To achieve a good phase
noise, the overdrives of the devices used in the delay cell and the tail current
sources needs to be higher but it demands a large supply voltage. In order to

resolve this we can go for a delay cell with linear region MOS resistor loads, where
the drop across the device can be reduced significantly as it operates in linear
region. But this method would need an additional bias generation circuit to set
the desired gate voltage for the linear region MOS load, which adds additional
phase noise to the VCO. Hence we traded the linear region load with a diode

connected load operating at a supply voltage of 2.2 V, to reduce the phase noise
and the implementation complexity of the delay cell.

57
3.8.2 Tuning circuit

The tuning of the VCO is accomplished by changing the current Ivco of the delay
cell proportional to the control voltage of the VCO. The functional diagram of
the tuning circuit is shown in Fig. 3.19. The VCO current of a single delay cell is

Ivco=Ibias+Itune(Vin)

Vin
Itune(Vin) Ibias

(a)

Itune(Vin)

Imax fmax

Inom fnom

Imin fmin
vmin vop vmax Vin vmin vop vmax Vin

(b) (c)

Figure 3.19: (a) VCO tuning circuit, (b) I-V characteristics of the V-I converter,
(c) The resulting f-V characteristics of the VCO.

given by
Ivco = Ibias + Itune (Vin )

The tuning current and the bias current are selected to get the desired VCO

characteristics. The tuning current is given by

Itune (Vin ) = Gm Vin

Since we need to generate a tuning current proportional to the control voltage, the
tuning circuit is nothing but a trans-conductor. To achieve a wide tuning range, we
need a linear transconductor operating over a wide input range. The VCO needs to

have a tuning range of 0.3 - 1.5 V, which implies that the transconductors should
have an operating range of 1.2 V (symmetric about 0.9 V). Assuming a simple
NMOS or PMOS differential pair the linear range (range over which the current

58
fully switches to another pair) is approximately
Vdd
Vdd

IT/3
Ivco2
Vin VCM1 Ivco1 VCM2 Vin

IT/3

(a) (b)

Vdd Combined tuning curve

IT

Ivco3
VCM3 Vin
IT/3

IT/3 0
Vin
Vcm1 Vcm2 Vcm3
(c) Ivco=Ivco1+Ivco2+Ivco3 (d)

Figure 3.20: Stagger tuned VCO. Transconductance cells active in the range (a)
0.3 - 0.7 V, (b) 0.7 - 1.1 V, (c) 1.1 - 1.5 V, (d) Staggered transconduc-
tor I-V characteristics.

√
Vrg = 2 2(Vgs − VT )

where Vgs − VT is the overdrive of the input pair in the quiescent condition. Since
the linear range requirement is 1.2 V, we have

(Vgs − VT ) ≥ 0.43V

So to have a wide tuning range, a single transconductor should have an overdrive

of at least 0.43 V for the input pair and hence a Vgs of approximately 0.85 volts (for
a worst case VT of 400 mV in 0.18 µm CMOS process). Since we want the char-
acteristics to be symmetric around 0.9 V, the transconductor will not be able to

provide a wide tuning range and linearity due to voltage headroom problems.
To resolve this we use a staggered transconductor whose I-V characteristic is shown
in Fig. 3.20 (d). The three transconductors are staggered at 0.5 V, 0.9 V and 1.3 V,
with a range of 0.4 V per transconductor cell. The overdrives per stage of the stag-

gered transconductors are reduced to 0.141 V, relaxing the headroom requirement

59
of the transconductors. Thus it covers the entire VCO tuning range of 0.3 V to
1.5 V and provides high linearity. The first transconductor with a 0.5 V com-
mon mode uses a PMOS input pair for voltage headroom reasons and the other
two transconductors have NMOS inputs with common mode voltages of 0.9 V and

1.3 V as shown in Fig. 3.20.(a), (b), (c). The simulated tuning characteristic of the
staggered Gm cell is shown across corners at a temperature of 270 C in Fig. 3.21.
The VCO does not have any amplitude control loop, as the amplitude variation

1.5

1
Current (mA)

0.5
ss
tt
ff
snfp
fnsp
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
voltage (V)

Figure 3.21: Tuning current vs input voltage.

across corners was less than 20 %. The nominal value of the maximum tuning
current IT per cell is 1.44 mA and the bias current for a nominal setting is 1.2 mA.

The VCO is simulated at a transistor level with extracted layout parasitics in the
nominal corner. Figure 3.22 shows the VCO tuning characteristics. The gain of
the VCO is ≈ 300 MHz/V.

60
 1.3

1.2

frequency (GHz)
1.1

0.9

0.8

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

control voltage (V)

Figure 3.22: VCO characteristics measured at the nominal corner.

3.9 Frequency divider

3.9.1 Multi-modulus dividers

Multi-modulus dividers form the basic building block for the frequency synthe-

sizers which require programmable divide value. A promising architecture for

implementing multi-modulus dividers is to use a cascade of 2/3 modulus dividers
as shown in Fig. 3.23. This type of dividers built using 2/3 modulus dividers
are known for their modular nature and wide-range programmability without any
feedback loops around large chain of flip-flops [16]. Owing to their asynchronous

nature they are also more power efficient. Thus they have become the de-facto
choice for programmable frequency division in PLLs and frequency synthesizers.
The programmable divide value is selected using the l-bit select signal [P0 : Pl−1 ].
The 2/3 dual modulus dividers divide the input signal frequency by two or three

based on the select signal and the mod signal fed to every stage from the preceding
stage as shown in Fig. 3.23. The cascaded 2/3 architecture generates a mod signal
which propagates from the last stage to the first stage as shown in Fig. 3.23. For

61
every output clock cycle of the divider, the mod signals of all the stages goes high
once. The ON-time of the mod pulse of the ith stage in the divider is equal to
the time period of the ith divider’s output. For instance the ON-time of the last
stage mod signal is one divider output clock cycle (hence it is always ON every

cycle), the stage before that has a mod value of 1 for half the output clock cycle
and so on till the first stage which has an ON time for the mod0 signal to be 1
clock cycle of its output (which is VCO output divided by 2, 2Tvco ). When both
the select signal Pi and the mod signal are simultaneously high, the 2/3 modulus
divider counts three cycles of the input signal, otherwise it counts two cycles of

the input signal. Thus when all the Pi are logic high, all the 2/3 cells count three
input cycles once per divider output period. The final divide value (total number
of counted cycles) at the output is given by

fvco
fvco/N
2/3 2/3 2/3
Vdd
mod0 mod1 modl-1

p0 p1 pl-1

Figure 3.23: A multi-modulus divider formed using 2/3 modulus dividers.

N = 2l + [P0 + 2P1 + ... + 2l−1 Pl−1 ] (3.1)

l−1
X
l
N =2 + 2 i Pi (3.2)
i=0

Thus for a l stage dual modulus divider the divide value is in the range [2l , 2l+1 −
1]. The nominal VCO output frequency is 1 GHz and the reference frequency is
20 MHz. Thus the nominal divide value is 50. To achieve this we need at least five
2/3 modulus divider stages. With five stages, the division ratio lies in the range

[32, 63].
The 2/3 modulus divider architecture used in the divider is shown in Fig. 3.24.
The input to the divider is the VCO output running at a frequency of 1 GHz. It is

62
 CMOS
Pseudo NMOS

{
fin fout
2/3 2/3 2/3 2/3 2/3 Vdd

p0 p1 p2 p3 p3

Figure 3.24: Divider architecture.

well known that in a given CMOS technology pseudo NMOS logic is always faster
than CMOS logic. Thus we opted to use pseudo NMOS logic for the first two
stages that operate at 1-1.5 GHz even if it is not power optimal (A current mode
logic (CML) could have been used for the initial stages to save power, however the

CML logic has a large number of devices stacked from supply to ground demanding
a large supply voltage for a low input sensitivity2 or wide output swing. Hence
we chose pseudo NMOS for the initial stages). The rest of the logic in the divide
chain is CMOS. The divide by 2/3 section of the multi-modulus divider is shown

A1 Latch1 Latch2
D Q D Q
clk clk Q Fout

Fin
modout
A2
A3
Q D modin
Q D
Q clk clk

Latch4 Latch3
Pi

Figure 3.25: Divide by 2/3 section shown at gate level

at a gate level in Fig. 3.25. When either modin or Pi signal is low, one of the input
to the AND gate A1 is always high and hence the 2/3 section behaves as a divide
2
A low input sensitivity here means the smallest input signal that can be applied to the
divider. A smaller input signal demands a larger gain for the sampling stage in the divider,
which in turn implies a larger Gm or load resistor. In order not to increase the noise, to increase
the gain, the Gm is increased fixing the resistor which leads to an increased drop across the
resistor and demands a larger supply voltage

63
by 2 circuit. When both modin and Pi signals are high, the 2/3 section behaves
as a divide by 3 circuit [16].
The latches in the 2/3 section are implemented in a fully differential pseudo

Vdd

D clkb Db

clk clk

Qb Q

clkb clkb

D clk Db

Figure 3.26: CMOS latch.

NMOS logic for the first two stages as they operate at the highest frequency in
the divide chain. The 2/3 section consists of D-latches and ‘AND’ gates. The
latch is implemented as a positive level triggered latch which samples on clkb and
holds (latches) it on clk. The latches which have an ANDed input can be combined
Vdd

B A clkb Bb

Ab

clk clk

Qb Q

clkb clkb

A clk Bb Ab

Figure 3.27: CMOS latch with AND functionality combined.

into a single stage latch with AND functionality merged into it. Fig. 3.26 shows the

64
architecture of the differential CMOS latch used in the design. The CMOS Latch
combined with the AND gate functionality is shown in Fig. 3.27. The architecture
of the pseudo NMOS logic latch of the first two stages is also similar to the CMOS
latch except the complementary PMOS load is replaced by a simple PMOS linear

region load. The schematic of the pseudo NMOS latch and the ANDed pseudo
NMOS latch are shown in Fig. 3.28.
Vdd
Vdd

clkb clkb
Qb Q Qb Q

clkb clkb
B

D clk Db A clk Ab Bb

(a) (b)

Figure 3.28: (a) Pseudo NMOS latch and (b) ANDed pseudo NMOS latch shown
at a transistor level.

3.9.2 Programmable divide value

1010 32
x[n] 4 5 Div= 42 - 57 b3b2b1b0
1010
0 - 15 10 - 25 O4O3O2O1O0
(a)
b0 O0

b1 O1

O2
b2

b3 O3

b1
b2 O4

b3
b3

Figure 3.29: Divider encoder logic.

65
The VCO has a tuning range of 1.2 V, which corresponds to a frequency range
of 1.2Kvco = 360 MHz = 18fr . Since it is an integer N PLL, to cover the entire
range of the VCO we need a divide value that is programmable up to 18 values
in steps of one. Though the implemented divider provides a five bit control (32

values), only 18 values is necessary to get the desired divide value. Using a five bit
control results in a large division range being unused, hence the programmability
range was reduced to 16 values and a four bit control was used3 . Maintaining the
divide value of 50 corresponding to the nominal output frequency of 1 GHz as the
center, the desired division ratio is in the range 42 - 57.

To obtain the desired divide value, the 5-stage dual modulus divider needs a five
bit control signal in the range 10 - 25. To the external four bit control word, 1010
is added using a four bit full adder with carry. This results in a five bit control
word between 10 and 25, necessary to control the programmable divider.

Since the one of inputs to the adder is always constant (1010 in our case), we
use this to minimize the complexity of the adder. Let b3 b2 b1 b0 be the input data
stream and O4 O3 O2 O1 O0 be the five bit output of the adder as shown in Fig. 3.29.
Then with some simple Boolean algebra we arrive at

O0 = b0

O1 = b1

O2 = b1 ⊕b2

O3 = b3 ⊕(b1 b2 )

O4 = b3 + b1 b2 b3

The encoder used for the division ration selection is given in Fig. 3.29.
Simulations were carried out on the extracted view of the divider in the slow

corner4 . The simulated waveforms of the divider for an input of 1 GHz (1 ns time
3
This results in a reduction of the VCO output frequency range by (18 − 16)fr = 2·fr =
40 M Hz.
4
The simulations are performed in slow corner, since the divider is prone to malfunction at
this corner due to slower speeds of the initial stage dividers. Ensuring an accurate operation at

66
period) of peak-to-peak amplitude 200 mV and a select value for the divider to be
b0 b1 d2 b3 = 1111 (which corresponds to a divide value of 57) are shown in Fig. 3.30.

input signal
divided signal
2

1.5
Amplitude (V)

1 57 ns

1 ns period signal
0.5

0 10 20 30 40 50 60 70
time (ns)

Figure 3.30: Divider waveforms overlaid with the VCO waveform.

3.10 Buffers

3.10.1 Control voltage buffer

The control voltage output is probed to study the settling performance of the

PLL. To minimize the noise introduced on the control voltage by the probing
path, we use a unity gain follower to buffer and shield the control voltage from the
external noise sources. The buffer needs to have wide input operating range from
0.3 V to 1.5 V and unity gain bandwidth > 1 MHz. A simple way to accomplish
a wide swing operation is to connect a differential to single ended amplifier with

PMOS input pair in parallel with a differential to single ended amplifier with
NMOS inputs as shown in Fig. 3.31. For lower input voltages (vin < 0.5 V ) the
this corner would automatically ensure the correct operations at other corners as well.

67
 Vdd

out

in out
Vdd

out

Figure 3.31: Control voltage buffer schematic.

output
2 input

1.5
Amplitude (V)

0.5

0
0 2 4 6 8 10
time (µs)

Figure 3.32: Transient response of the control voltage buffer.

68
amplifier with PMOS inputs is active and for input voltages greater than 1.2 V
the amplifier with the NMOS input pair is active. For voltages near the common
mode voltage (0.9 V), both the amplifiers are active and the gain is maximum as
devices in both the amplifiers are in the active region of operation. The transient

response of the amplifier for a slow voltage ramp with a slope of 1.8 V/µs.

3.10.2 VCO buffer

VCO
Buffer Cp Cpi 50 Ω

Lb

Cp Cpi 50 Ω

Figure 3.33: Buffered VCO output driving the bond pad, pin and a 50 Ω resistor.

The VCO buffer serves as an interface to bring the VCO output on chip to the
external world for phase noise measurements. The circuit model of the VCO buffer

being taken out for measurement to a 50 Ω resistor load is shown in Fig. 3.33. The
figure shows the VCO buffer driving the bond pad modeled as a capacitor Cp ,
bond wire modeled as an inductor Lb , the output pin modeled as a capacitor
Cpi. The output pin is capacitively coupled to a measuring device (Spectrum

analyzer) modeled as a 50 Ω load resistor. The VCO buffer is implemented in

current mode logic (CML) with resistive loads as a tapered buffer architecture
shown in Fig. 3.34. The total power consumed by the VCO buffer is 10.8 mA. For
a bond pad capacitor value of 1.5 pF, bond wire inductance of 2 nH and a pin
capacitor of 3 pF, the simulated peak to peak differential output voltage delivered

to the 50 Ω load resistor is 450 mV.

69
 Vdd

R=12.8 kΩ

x(w/l) x(w/l)=20(0.5µ/0.18µ)

Ix=200 µA

Vb=1.2 V

VCO
Bondpads

X 3X 10X 40X

Vb=1.2 V

Figure 3.34: VCO buffer schematic.

3.11 Lock detector circuit

A lock detector is implemented to detect and disable5 the randomization logic

when the phase errors exceed δT > T /N = 6.25 ns. The phase lock detection

circuit was implemented by exploiting the fact that the inverters behave as a low
pass filter. The phase error is first generated by feeding the UP and DN signal to
an XOR gate. This produces a pulse whose width is proportional to the magnitude
of the phase error between the reference and divide clocks. The resulting error
pulse is passed through a series of inverters with long device lengths followed by a

high speed inverter. This is equivalent to passing the pulse through a lowpass filter
followed by a slicer as shown in Fig. 3.35.(a). So when the pulse widths are larger
than a threshold value, the pulse is passed through the inverters and it appears
at the slicer output, and for small pulse widths the lowpass filter attenuates its

amplitude and the slicer detects it as a zero. The inverter lengths are chosen such
that they allow pulses of width greater than 9 ns (in the nominal corner) which is
a condition indicating the PLL is out of lock.
5
Though not implemented in the current design, the lock detector can also be used to disable
the PR technique when the phase errors are large enough to affect the PLL dynamics.

70
When the pulse appears at the slicer output we set the ‘lock det’ signal high.

(a) Slicer threshold

in out
DFF

LPF SLICER
fr
Laging ref edge Leading ref edge
(b)

Te T Tl
Figure 3.35: (a) Idea behind the ‘Phase lock’ detector implementation, (b) Figure
showing the sampling instants Te and Tl w.r to the rising edge of the
reference clock.

This can be accomplished by sampling the output of the slicer using the reference

clock signal. If the reference clock leads the divide clock, the pulse would appear
after the reference edge and when the divide edge leads the reference edge, the
pulse would appear before the reference edge. So to sample the pulse we use an
‘early-late sampling’. We use a delayed version of the reference clock to sample

the pulse when the reference clock leads the divide clock and an advanced (early)
version of the reference clock when it lags the divide clock. The sampling instants
of the delayed (Tl ) and the early (Te ) clocks are shown in Fig. 3.35.(b) along with
the possible error pulses.
The gate level schematic of the lock detector is shown in Fig. 3.36 with the di-

mensions of the inverters used for lowpass filtering and slicer operations. The
D-Flip flops are implemented in a master and slave configuration using level trig-
gered CMOS latches. The transfer characteristics of the implemented lock detec-
tor (simulated on the extracted view) is shown in Fig. 3.37.

71
 Lowpass Inverter Slicer buffer
Vdd Vdd Vdd

4(0.5/3) 5(0.24/0.18) 5(0.72/0.18)

0.5/3 2(0.24/0.18) 2(0.48/0.18)

Early sampling
fre
DFF
UP lock_det

DN
DFF
frd
Delay sampling

Figure 3.36: ‘Phase lock’ detector schematic.

1.8

1.6
Lock detector output (V)

1.4

1.2

0.8

0.6

0.4

0.2

0
−30 −20 −10 0 10 20 30
time (ns)

Figure 3.37: ‘Phase lock’ detector characteristics.

72
 CHAPTER 4

Delay tuning PLL

The delays are implemented using CMOS inverters and are prone to process and
temperature variations. One straightforward approach to counter the delay varia-
tions is to use a replica delay locked loop (DLL), where a voltage controlled delay

line is used in a feedback loop which ensures that the delay is equal to one refer-
ence clock period. However there are two problems associated with this approach.
First, in the presence of nonidealities like charge pump feedthrough and mismatch,
the DLL will finally settle such that there is a finite phase offset between the DLL
output and the input clock, which implies that the delay attained is not exactly

one reference period. Second, the DLL has the problem of locking to integer mul-
tiples of reference period in the steady state.
An alternative is to configure (one half of) the delay line as a voltage controlled
ring oscillator and tune its oscillating frequency to a fixed reference frequency us-

ing a PLL. Though there may be finite phase offsets between the VCO output
and the input reference clock, the frequency is perfectly tracked. Hence the time
period of the VCO is exactly equal to the reference clock period, Tvco = Ti . Ti
is the time period of the input reference clock. When the inverter chain in the

ring oscillator is used a delay line, the delay value generated is exactly tuned to
the desired value without the afore-mentioned problems associated with the DLL
based tuning. Therefore a PLL based delay tuning is chosen for delay tracking
across process and temperature corners.
4.1 Delay tuning PLL dynamics

Fig. 4.1 shows the schematic of the PLL used for delay tuning. The PLL employs a
dual path for phase error, the first proportional path [1] is provided by the resistor
R and charge pump CP1 with current Icp1 and the second proportional path is

provided by charge pump CP2 with current Icp2 as shown in the figure. The

CP2

fi Rvco
ref UP
CP1
Gm
div DN R
Cvco fout
C1

Figure 4.1: Supply regulated PLL for Delay tuning

integral path for the error is provided by the capacitor C1 . The PLL employs a

ring oscillator as its VCO and in the steady state the VCO time period will be
equal to the input reference period and the delay cells used in the VCO behave as
a delay line with delay equal to Ti /2. These delay cells are replicated and used in
the design to get the desired delays required for spur elimination. The loop gain
LG(s) of the PLL is given by

s
Icp1Kgm Kvco (1 + )
ωz
LG(s) = s (4.1)
s2 C1 (1 + )
ωp

Gm
ωz =
(a1 + Gm R)C1
Gm + Gvco
ωp =
Cvco

74
 Gm Rvco
where Kgm = , a1 = Icp2/Icp1 . The transconductance amplifier Gm has
1 + Gm Rvco
to drive the ring oscillator and hence needs to provide the current required by the
oscillator. The bias current of the transconductor has to be much higher than the
current drawn by the ring oscillator and hence a simple differential to single ended
amplifier cannot be used a transconductor due to voltage headroom requirements

despite its good supply rejection characteristics [17]. This mandates a two stage
amplifier which needs to be miller compensated for stability requirements as the
second stage sees a large load capacitor Cvco chosen for better supply noise rejec-
tion. Adding a two stage amplifier for the transconductor introduces additional

pole within the PLL loop and thereby affects the stability margin. We can also
see from the above equations of loop dynamics, that the Gm of the transconductor
not only determines the pole location, but also the loop gain (Kgm ). In order to
decouple the dual functions of providing the DC gain and the VCO current, we
use the technique of current assistance for the transconductor.

The conceptual schematic of the current assisted transconductor is shown in

Fig. 4.2. A pre-estimated current (Ivco ) is injected into the VCO as shown in

vi Ivco
I=0 Ivco
vo
Gm

Figure 4.2: Transconductor with Current Assistance

the figure. This relaxes the transconductor current specifications as it has to sup-

ply zero current to the VCO and thus only maintain vi = vo by its feedback action.
The current can be estimated and pumped into the VCO in two different ways.
The first method is named as the feedback method and the second as the feedfor-
ward method.

75
4.1.1 Feedback compensation

Illustrated in the figure 4.3 is the feedback method. A replica VCO (main VCO
scaled down by n) is separately driven by an amplifier and the current that is fed
by the PMOS pass transistor is multiplied by n and mirrored to the VCO. The
advantage can be seen by the fact that the current estimating loop sees a lower

capacitor at its second stage due to the load scaling operation. The equations that
Vdd

n(W/L)

vi Ivco
I=0 Vdd
vo
Gm
W/L

Ivco/n
VCO scaled down
by n
VCO

Figure 4.3: The proposed idea to make the Gm independent of the VCO load by
feedback replica current injection.

represent the dynamics in the feedback compensation are

dvo (t)
Gm .vi (t) = Gm .vo (t) + vo (t)[Gvco (t) − Gf b (t)] + Cvco (4.2)
dt

Since the VCO draws a time varying periodic current, the load offered by the VCO

is modeled as a time varying transconductance Gvco (t). Gf b (t) is the estimated

time varying feedback current injected into the VCO. When Gf b (t) = Gvco (t), we
have
Cvco dvo (t)
vi (t) = vo (t) + (4.3)
Gm dt

Applying the Laplace transform to Eq. 4.3, we get

Vo (s) 1
=
Vi (s) sCvco
1+
Gm

76
The above equation shows that the DC gain is 1 (independent of Gm ) and the pole
is located at Gm /Cvco .

4.1.2 Feedforward compensation

Another method is to use a feed forward current injection as shown in Fig. 4.4.
The VCO current is estimated in a similar manner by using the input voltage as
shown in the figure. The equation for the dynamics of the PLL in the feed-forward

Vdd

W/L n(W/L)

Ivco/n

vi

Ivco
I=0
vo
Gm

Figure 4.4: Feedforward replica current injection

current injection case is given by

dvo
vi (t)[Gm + Gf f (t)] = vo (t)[Gm + Gvco (t)] + Cvco (4.4)
dt

when Gf f (t) = Gvco (t)

Cvco dvo
vi (t) = vo (t) + (4.5)
Gm + Gvco (t) dt

The VCO current can be seen as a dc current plus a zero average periodic current

riding over it. As the number of stages increase the current drawn from the VCO

77
control voltage will tend to a DC current1 . In the current design to meet the
requirement of delaying narrow UP/DN pulses, the replica ring oscillator chain
consists of a large number of high speed inverters. Thus the DC current is much
larger than the transient variations in the current and its effect can be ignored.

Hence the time varying load Gvco (t) can be approximated to its average value Gvco .
Applying the Laplace transform to Eq. 4.5, we get

Vo (s) 1
=
Vi (s) sCvco
1+
Gm + Gvco

The above equation shows that the DC gain is 1 (independent of Gm ) and the pole
is located at (Gm + Gvco )/Cvco .
It can be inferred from the preceding analysis that the two techniques ensure a
unity DC gain and are identical complexity wise. Even the supply noise rejection2

of the PLL remains same for both the techniques as shown in Fig. 4.5.
However the positive feedback method has a drawback when there is a mismatch
between the actual VCO load and the replica load. If

Gf b > Gvco

then at the DC we have

vo 1
= (4.6)
vi 1 − ∆G
Gm

1
As the number of stages increase for a given frequency of oscillation, the rise and fall times
of the oscillator output will reduce and the output will tend to be nearly rectangular in shape.
The high frequency current drawn from the supply will have frequency of nfvco , where n is the
number of stages. This is because the n-stages in a VCO draw current from the supply when
they are undergoing transitions in a single VCO period offset in phase by π/n. As n increases
the phase difference between the successive outputs of the inverters in the oscillator chain will
become smaller and the current drawn from the supply will appear like a DC when n tends to
∞.
2
The supply noise rejection of the PLL is measured by injecting noise at the supply voltage of
the buffer driving the VCO and computing the phase noise at the VCO output. In the current
analysis the PLL was replaced with its linear model with the buffer driving the VCO alone at
schematic level. The noise was injected at the supply of the buffers and the phase noise was
computed at the linear VCO phase-domain model.

78
 Feedforward
0
Feedback

−10

Supply noise rejection (dB)

−20

−30

−40

−50

−60 4 6 8 10
10 10 10 10
frequency (Hz)

Figure 4.5: Supply noise rejection of the two techniques when applied to the PLL.

where ∆G = Gf b − Gvco Here we can see that when ∆G > Gm the gain is negative
and the loop becomes unstable. This might be true in cases where Gvco ≫Gm .
In the feedforward method of providing the load current, the gain at dc is given
by
vo ∆G
=1+ (4.7)
vi Gm + Gvco

And it is less sensitive to variations in Gf f . So the feedforward method is chosen

for implementation. The loop gain LG(s) of the PLL after applying the technique
is given by
s
Icp1 Kvco (1 + )
ωz
LG(s) = s (4.8)
s2 C1 (1 + )
ωp
where

Gm + Gvco
ωz =
(a1 + (Gm + Gvco )R)C1
Gm + Gvco
ωp =
Cvco

The VCO load is modeled as a linear load Rvco = 1/Gvco for loop dynamics
simulations. Fig. 4.6 shows the step response of the PLL for a control voltage step

79
of 0.1 V. Also shown in the figure is the step response of the PLL when the VCO
load is time varying. The linear resistive model of the VCO is replaced by the
VCO running at the desired frequency of oscillation. The close match between
the two step response validates the assumption made in modeling the load of the

VCO as a resistor Rvco . The parameters of the delay tuning PLL are listed in 4.1.

1.25
linear model
actual

1.2
control voltage

1.15

1.1
0 1 2 3 4 5
time (us)

Figure 4.6: Step response of the PLL with the VCO impedance modeled as resistor
overlaid with the actual VCO timevarying load.

Table 4.1: Delay tuning PLL parameters

Parameters
Input frequency 160 MHz
PFD Tri-state PFD
charge pump currents Icp1 = 5 µA, Icp2 = 50 µA
Resistor and capacitors R = 5.2 K Ω, C1 = 41.4 pF, Cvco = 9.1 pF
VCO fvco = 160 MHz, Kvco = 344.25 MHz/V
unity gain bandwidth fu = 4 MHz
closed-loop 3dB bandwidth f3dB = 5.9 MHz
Phase margin PM≈ 72 degree

80
4.1.3 Choice of input frequency

The inverter chain used in the VCO (in the steady state) provides a delay of Ti /2
and is used as delay cell in the randomization logic of the actual PLL. If the input
frequency of the delay tuning PLL is 20 MHz, the control voltage of the PLL will
have spurs at 20 MHz and when it is used to drive the replicated delay cell in

the actual PLL with randomization it introduces noise at fr degrading the spur
performance. To overcome this problem we use an input frequency of Nfr and
thus the spurs introduced by the delay tuning PLL occur at Nfr . Thus the input
frequency of the DPLL is chosen to be 8fr = 160 MHz.

4.1.4 Inverter chain based VCO

Vc
Vdd Vdd
Vdd

in out in out

Vc Vdd

13 inverters

Figure 4.7: VCO schematic.

The VCO of the delay tuning PLL is a chain of inverters with a slicer buffer as
shown in the Fig. 4.7. The slicer buffer is added keeping in mind the fact that

the chain of inverters would be replicated in the delay cell of the actual PLL

81
and a long chain would narrow the UP/DN pulses as they propagate through
the chain. Thus repeater buffers should be added in between the inverter chains
to restore the rise and fall times of the propagating pulse. The added repeater
buffers will introduce additional delay in the delay line which leads to degradation

in the spur performance (due to the increase in the delay of the individual cell). So
the repeater buffer is included in the VCO itself and the delay of the chain with
the buffer is tuned to T /2 in the steady state. The tuning characteristics of the
inverter chain VCO is shown in Fig. 4.8. The inverter chain of the VCO provides

300

250
VCO ouput frequency (MHz)

200

150

100

50

0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6

VCO input voltage (V)

Figure 4.8: VCO tuning characteristics.

a delay of T /2N and a cascade of two such invert chains provides a delay of T /N.
Thus a cascade of two such VCO inverter chains is used a single unit delay cell of
delay T /N in the randomization logic of the PLL. The schematic of the unit delay

cell is shown in Fig. 4.9.

4.1.5 Schematic of the PFD and charge pump

The schematics of the PFD and two charge pumps are similar to the ones used in
the actual PLL explained in chapter 3.

82
 Vc Vdd Vc Vdd

in out

in out

0 t T/N t

Figure 4.9: Delay cell schematic showing the cascade of inverter chains used in the
VCO.

4.1.6 DLL buffer

First stage Second stage

vi Vdd
A1
A1

Cc
vo

Delay CL
A2 chain

Figure 4.10: Delay cell buffer.

The control voltage of the delay tuning PLL has to drive a low impedance load (the
replicated delay cells with supply voltage control) which draws switching current.

The VCO control node cannot be directly used to drive the delay chain as the
load will affect the stability of the delay tuning PLL. Hence a buffer is necessary
to isolate the load from the control voltage node. The buffer is divided into two
stages, the first stage is a low capacitance input stage with a very low bandwidth

to filter out all the high frequency noise on the control voltage. The second stage
is the driver stage which drives the load of the delay cell. The delay cell offers
a low resistive impedance3 ≈ Rvco /14 and a large load capacitor CL is connected
3
A cascade of two identical VCO chains form a single delay cell and hence if Rvco is the

83
at the output node for better supply noise rejection and to minimize the voltage
fluctuations at that node due to switching currents drawn by the inverters. The
low impedance output node demands a two stage amplifier for the second stage
buffer to meet the gain requirements. But it leads to two closely spaced poles

for a two stage amplifier (due a large resistance and small capacitance at the high
gain first stage). To compensate this a large compensating capacitor is needed,
which results in a low bandwidth for the buffer. So a feedforward compensation
path is used from the input to the output that bypasses the two stage amplifier
at high frequencies as shown in Fig. 4.10. This simultaneously provides the high

gain (gain of a two stage amplifier) at DC and a large bandwidth (equivalent to an

uncompensated single stage amplifier).
The amplifiers A1 and A2 are single stage differential to single ended amplifiers

1.5
Buffered Voltage (V)

1
1.1
1.5 mV
1.099

0.5 1.098

1.097
6 6.2 6.4

0
0 2 4 6 8 10
time (us)

Figure 4.11: Buffer step response.

with NMOS inputs and PMOS current mirror load. A1 is a low bandwidth ampli-
fier with a current consumption of 10 µA and A2 is the high bandwidth amplifier
with a current consumption of 400 µA. The amplifiers are chosen with NMOS
impedance looking into the supply voltage of the VCO chain, then Rvco /2 is the impedance of
a single delay cell. Since 7 such delay cells are needed for the entire delay generating block, the
impedance looking into the supply of the entire delay chain is Rvco /14.

84
input pairs since the variation of the control voltage is always above 0.9 V across
process and temperature variations.
A transient simulation is performed to test the performance of the buffer feeding
the bias to the delay line. The buffer is made to drive a time varying load which is

simulated by exciting the delay cell with a periodic signal of time period T = 50 ns
and a pulse width of 1 ns4 . The buffer delivers a voltage of 1.1 V to the simulated
time varying load. The step response of the buffer simulated at a schematic level
is shown in Fig. 4.11.

4
This is done to emulate the actual load in the lock condition where the pulse widths of the
UP/DN signals is of the order of 1 ns.

85
 CHAPTER 5

Simulation Results

5.1 Block level simulations

Vdd

vb1
Icp Imis=0.05Icp
vb2

UP UP
To LPF

DN DN

vb3
Icp
vb4

Figure 5.1: Transistor level charge pump schematic showing the source of mis-
match added for simulations.

Reference spurs arise due to nonidealities in the PFD, charge pump and loop-
filter. To reduce the simulation time, the VCO, divider and the digital logic for
randomization are modeled behaviorally as they have no effect on the generation of
reference spur. The PFD, charge pump and loop filter are simulated at transistor

level. The VCO, divider and the randomization logic are noiseless and the source
of noise is only deterministic, contributed by the charge pump and PFD. To model
the effect of charge pump mismatch, a constant current source of value 0.05Icp (5
% mismatch) is connected in parallel with the upper current source as shown in
Fig. 5.1. The feed through is inherent with the circuit of the implemented charge
pump.
The simulated1 phase noise of the 8-PPM and 8-PR techniques overlaid with the

−60
Standard PLL
8−PPM
−70 8−PR

−80
−87 dBc
Phase Noise (dBc)
−90

−100
−70
−110
−80
21.8 dB
−90
−120
−100
19.9 20 20.1
−130 −1 0 1 2
10 10 10 10
Frequency Offset from Carrier (MHz)

Figure 5.2: Phase noise of the PLL output comparing the the performance of the
8-PPM and 8-PR techniques with the standard PLL (The resolution
bandwidth used for PSD computation is 78.125 kHz).

standard PLL is shown in Fig. 5.2. The figure shows the absence of reference spur
in both the 8-PPM and 8-PR techniques. The spur is converted to noise in 8-

PPM technique and the noise level is 21.8 dB below the reference spur (measured
at a resolution bin-width of 78.125 kHz). The 8-PR technique has only spurs at
8fr without adding any redistributed noise as expected. Additionally it can be
observed that the spur at 8fr in case of 8-PR is higher than the PPM. This is

attributed to the net increase in the injected spur current into the loop filter as
the feed through current does not exactly scale with the scaled switch sizes.
The randomization techniques (8-PPM and 4-PPM+2-PR) spread the energy in
the harmonics to all the frequencies and hence raise the noise floor at the PLL
output. To study the effect of the techniques on the output phase noise we compare

the phase noise contribution of the VCO, loop filter resistor and charge pump to
1
The phase noise of the PLL is obtained by computing the PSD of the output VCO phase,
which is obtained by running a transient simulationR of the PLL and integrating the zero mean
control voltage (vc (t)) after settling, φout = 2πKvco vc (t)dt.

87
the noise introduced by 8-PPM and 4-PPM+2-PR techniques. Fig. 5.3 shows
the phase noise due to the randomization overlaid with the PLL noise at the
output. (The phase noise model of the open loop VCO assumes a phase noise
specification of -120 dBc/Hz at 1 MHz offset and a 1/f 3 corner of 200 kHz as

shown in Fig. 5.32 ). The phase noise contributed to the PLL output by the VCO

−90
8−PPM
−100 4−PPM+2−PR
VCO Noise
−110
Total PLL Noise
−120
Phase Noise (dBc/Hz)

−130 20 dB Spur @ 8fr

−140

−150

−160

−170

−180

−190

−200 −1 0 1 2
10 10 10 10
Frequency Offset from Carrier (MHz)

Figure 5.3: Phase noise at the PLL output due to the resistor, VCO and charge
pump compared with the redistributed noise added by 8-PPM and
4-PPM+2-PR techniques.

and resistor is dominant near the bandwidth of the PLL and at high frequencies.
The plot shows that the noise added by the randomization techniques is 40 dB

lower than these two contributions at frequencies close to the bandwidth of the
PLL and it becomes dominant only at frequencies greater than fr (20 MHz in the
simulated PLL). We can also see from Fig. 5.3 that the combined 4-PPM+2-PR
technique has lower redistributed noise due to the additional filtering offered by
2-PR as explained before.

Fig. 5.4 shows the spectrum of the 4-SPPM+2-PR technique when applied to
the implemented PLL and compared with the 8-PPM technique. We can clearly
see the shaping of the noise for low frequencies, leading to orders of magnitude
2
A point to note is that the actual VCO implemented in the PLL is not as stringent. The
purpose here is to emphasize that the noise introduced by these techniques are smaller compared
to such a stringent VCO specification.

88
 −90
4−SPPM+2PR
−100 8−PPM
−110

−120
Nearly 3rd order shaped

Phase Noise (dBc/Hz)

−130

−140

−150
27 dB
−160

−170

−180

−190

−200 −1 0 1 2
10 10 10 10
Frequency Offset from Carrier (MHz)

Figure 5.4: The phase noise contribution of the 8-PPM overlaid with the phase
noise due to 4-SPPM+2-PR technique.

reduction in the ‘midband’ region. The simulated PLL shows a reduction in the
noise level by 27 dB near the PLL bandwidth (fr /20) compared to the 8-PPM

technique.

5.1.1 Transient simulation

Standard PLL 8−PPM

Frequency (GHz)

1.1 1.1

1.05 1.05

1 1
0 5 10 0 5 10

8−PR 4−PPM+2−PR
Frequency (GHz)

1.1 1.1

1.05 1.05

1 1
0 5 10 0 5 10
time (us) time (us)

Figure 5.5: Settling behavior of the PLL for different techniques for a frequency
step of 80 MHz (from 1 GHz to 1.08 GHz).

As mentioned earlier in Section 2.4.2, the 8-PR technique has the problem of

89
gain saturation for large phase/frequency errors which leads to an increased set-
tling time. So to compare the large-signal settling of the PLL when the different
techniques are applied, we give a step of 4 in the divide value (50 to 54) which cor-
responds to an output frequency step of 4fr = 80 MHz from 1 GHz to 1.08 GHz.

Fig. 5.5 shows the simulated response of the PLL to a frequency step when differ-
ent techniques were applied. The figure shows that the settling behavior of 8-PPM
and 4-PPM+2-PR techniques is similar to the standard PLL. The PR technique
shows a slewing behavior due to the gain saturation for nearly 4.5 µs and then
settles to the desired value after 8 µs (approximately twice as much as in the other

techniques).

5.2 Noise computations

Incp(s) φvco(s)

φin(s) φout(s)
Icp Kvco
2π s
Cz
Cp
φdiv(s)
R

Vnr(s) +
−

1/ND

Figure 5.6: Linear PLL model showing the various noise sources contributing to
the output phase noise.

The phase noise of the VCO simulated at 1.18 GHz is shown in Fig. 5.7. The phase
noise is close to -98.5 dBc/Hz @ 1 MHz offset from the carrier. The simulated

noise current density of the charge pump output current is shown in Fig. 5.8. To

90
 −20

−40

Phase noise (dBc/Hz)

−60

−80 −98.5 dBc/Hz @ 1MHz

−100

−120

−140

−160
−2 0 2
10 10 10
frequency (MHz)

Figure 5.7: VCO phase noise measured at 1.18 GHz.

obtain the current noise spectral density, the output node of the charge pump
is connected to a constant DC voltage source (0.9 V in the nominal case) and the
noise current is measured through the voltage source after performing an AC noise

analysis. In the steady state, the UP/DN pulses are on for at least Trst seconds.
Assuming a white current noise spectral density, the total noise current power
injected into the loop filter reduces by a factor of Trst /T . Hence we scale the noise
current density obtained from the noise analysis by a factor Trst /T to obtain the

actual noise current density injected into the loop filter [18]. For a worst case noise
analysis Trst is chosen to be 2 ns3 . The total PLL output noise overlaid with the
individual contributions is shown in Fig. 5.9. The total PLL noise is overlaid with
the noise added by the randomization techniques to compare their performance.
The randomization noise is significantly lower than the noise contribution of the

PLL. The VCO noise used for noise computations is the noise of the implemented
VCO and not the ideal VCO noise profile assumed previously in Fig. 5.3.
3
The nominal value is 1.2 ns.

91
 −225
Charge pump noise
−226

Current Noise density (log(A2/Hz))

−227

−228

−229

−230

−231

−232

−233

−234 −2 0 2
10 10 10
frequency (MHz)

Figure 5.8: Charge pump noise current density.

−80

Total noise
−100

−120
Phase noise (dBc/Hz)

−140 Resistor noise

−160
VCO noise
−180 Charge pump noise

−200

−220 −2 0 2
10 10 10
frequency (MHz)

Figure 5.9: Total PLL output noise.

92
 −90
−100

−110 PPM+PR Total PLL noise

>40 dB
−120

Phase Noise (dBc/Hz)

PPM
−130

−140

−150

−160 SPPM+PR
−170

−180

−190

−200 −1 0 1 2
10 10 10 10
Frequency Offset from Carrier (MHz)

Figure 5.10: Total PLL output noise overlaid with the noise added by the ran-
domization techniques.

5.2.1 Power consumption

The total current consumption of the PLL is listed in Table. 5.1.

Table 5.1: PLL power consumption

Block Current consumption

PFD 0.462 mA
Charge pump 0.18 mA
Randomization Logic 0.5 mA
VCO (nominal setting) 6.7 mA
Divider 8.7 mA
Delay tuning PLL 1.32 mA
Total 16.54 mA (without Delay tuning PLL)
Total 17.86 mA (with Delay tuning PLL)

93
 CHAPTER 6

Testing

6.1 Floor plan of test chip

The layout floor plan of the test chip fabricated to verify the ideas presented in
the previous chapters is shown in Fig. 6.1. Empty area is filled up with supply

bypass capacitors.

DePLL

PRBS

PFD

Delay selection
logic 2.5 mm

Charge pump

Divider VCO

BUF

1 mm

Figure 6.1: Floor plan of the designed PLL.

The snapshot of the layout of the chip is shown in Fig. 6.2. The area of the
individual blocks are given in Table 6.1
Figure 6.2: Snapshot of the layout of the designed PLL

95
 Table 6.1: Areas of individual blocks.

Block Area (mm2 )

PFD 0.00075
Charge 0.1524
pump (both
PPM and PR,
including by
pass caps)
LPF 0.084
VCO 0.055
Divider 0.03
Delay selection 0.048
logic
PRBS 0.1125
Delay tuning 0.245
PLL

6.2 Measurement setup

The test setup for measuring the phase noise of the PLL is shown in Fig. 6.3. A
Rhode and Schwarz spectrum analyzer with a measurement frequency range of
200 kHz to 13 GHz was used for measuring the phase noise. The PLL output from
the chip is differential and the spectrum analyzer is single ended. Hence a Balun

was used to convert the differential signal to a single ended output before feeding
it to the spectrum analyzer as shown in Fig. 6.3.

R&S FSP
Spectrum
Test Board Analyzer
Balun
PLLoutp
Refclk DUT

PLL
Signal Source PLLoutn
Agilent 33250A

Figure 6.3: Test setup for measuring the phase noise of the PLL chip.

96
6.3 Measured results

The phase noise of the measured PLL is shown in Fig. 6.4. The measured spur
at fvco + fr is -65 dBc and fvco − fr is -64 dBc below the carrier power. Fig. 6.5

Figure 6.4: Measured results showing the PLL output spectrum.

shows the measured phase noise of the PLL when PR is enabled. The reduction
in the spur level at fvco ±fr can be clearly seen. The spur level at fvco − fr is
-73 dBc (9 dB reduction in spur). Fig. 6.6 shows the phase noise of the PLL when
PPM is enabled. Even in this case the reduction in the spurs can be clearly seen.

The spur level at fvco − fr is -72 dBc (8 dB reduction in spur). Fig. 6.7 shows the
phase noise of the PLL when different techniques are applied. It can be seen that
the in band noise of the PLL remains unaffected when PR is tuned on. This is due
the fact that the in band delay line noise which is dominated by the flicker noise

of the delay line, gets first order shaped as discussed in Chapter 2. Hence the in

97
Figure 6.5: Measured results showing the PLL output spectrum when PR is turned
on.

98
Figure 6.6: Measured results showing the PLL output spectrum when PPM is
turned on.

99
band noise addition due to PR is insignificant. The noise of the PLL when PPM is
enabled increases significantly due to the high gain provided by the PLL loop filter
at low frequencies for the redistributed noise. The result is a clear indication that
PPM with a iid sequence is not an attractive solution from a noise perspective.

Though not implemented in the current work, one can use a noise shaped PPM
and apply PR (SPPM+PR) in conjunction with it to reduce the in band noise
contribution as suggested in Chapter 2.

Figure 6.7: Measured results showing the PLL output noise. The measured in
band noise spectrum of the PPM, PR and normal PLL are shown in
blue, green and black colors.

The spur levels in the output spectrum of the measured PLL are listed in Table. 6.2.

100
 Table 6.2: Measured spur levels for different techniques

Spur (offset Spur level in Spur level in Spur level in

from carrier) dBc (Normal) dBc (PR) dBc (PPM)
+fr -65 -69 -79
+2fr -68 -81 -69
+3fr -66 -69 -73
+4fr -64.6 -65.15 -59.6
+5fr -85 -76 -84.4
+6fr -75 -75 -65
+7fr -74.6 -77.5 -81.5
+8fr -75 -76 -76
−fr -64 -73 -72
−2fr -70 -81 -69
−3fr -71 -76.5 -83
−4fr -70.6 -72 -64.5
−5fr -81 -82.5 -89
−6fr -78 -70.2 -81
−7fr -78 -86 -83
−8fr -77 -78 -76

6.4 Discussions on measured results

6.4.1 Spurs at ±4fr

Large spurs at fvco ±4fr were observed in the measured results in all the cases.
The magnitude of these spurs did not change with the changes in the delay values
or by changing the switch voltage levels of the charge pump. This is an indication

that the source of the these spurs are not due to nonidealities in delay cells, PFD
and charge pump. Though the exact source of these spurs could not be traced due
to time constraints of the work, it is clear that it is due to external sources like
coupling from the switching currents in the divider and on board coupling.

6.4.2 Higher even order harmonics in PPM

When the PPM is enabled higher even order harmonics were observed (harmonics

at 2fr and 4fr were larger in magnitude compared to PR). This is attributed to

101
the switching noise induced by the PRBS operation. This hypothesis was verified
by turning on the PRBS alone and enabling the PR technique. Ideally this should
have no effect on the PR technique as the multiplexer in the PPM is bypassed in
this mode. When the PR technique was enabled without enabling the PRBS, the

second harmonic spurs were lower in magnitude and when the PRBS was turned
ON the second harmonic terms increased to the levels as seen in PPM.

6.4.3 Asymmetric spurs at fvco ±kfr

The spurs measured at the PLL output exhibit asymmetry about the center fre-
quency. That is the spurs at fvco + kfr and fvco − kfr are unequal in magnitude.
The spurs are an effect of frequency modulation of the VCO output due to a

periodic charge injection at the control voltage every reference cycle. If it was
purely frequency modulation then the spurs about the VCO frequency should be
identical in magnitude (explained in Appendix C). Similarly in case of a sinusoidal
amplitude modulation, the spectrum of the amplitude modulated signal contains

equal magnitude spurs at ±fr offset from the carrier. The only difference between
an AM signal and narrow band FM signal is that the phase of the sidebands are
of opposite polarity in case of narrow band FM and same polarity in case of AM.
Thus when an AM signal is added to an FM signal (both modulated with the
same base band signal with different amplitudes), the resulting signal will have

asymmetric tones at the modulating frequency (shown in Appendix C). Thus in

the author’s opinion the possible source of the asymmetric spurs is due to the
amplitude modulation of the VCO output (which is already frequency modulated
at fr ) at fr .

The VCO output is taken to the pads through a CML buffer and then passed
through a Balun on board before being fed to the spectrum analyzer. The bias
current of the CML buffer is externally supplied through a pin. The source of
amplitude modulation is the modulation of the bias current (at the reference fre-

102
quency) due to stray coupling on board. It is well known [19] that modulating
the bias current of a CML buffer is nothing but mixing (multiplying) the input
signal with the bias current modulating signal. This is nothing but an amplitude
modulation of the input fed to the buffer. Fig. 6.8 illustrates the source of the

amplitude modulating noise in the CML buffer. Thus the output of the buffer is
a combination of AM and FM and hence the output sidebands are asymmetric.
The signal at the output of the buffer can be modeled as

Vdd

R R

out(t)

invco(t)

mcos(2πfrt)

Figure 6.8: AM due to the modulation on the bias current.

xout (t) = A cos(2πfvco t + m2 sin(2πfr t))(1 + m1 cos(2πfr t))

Using the results in Appendix C, it can be readily shown that the above signal
will indeed have asymmetric spurs at fvco ±fr .

103
 CHAPTER 7

Conclusion and Future Work

A major contribution of this thesis is the spectral analysis and interpretation of

PPM signals. A detailed analytical study of PPM was presented and noise shap-

ing characteristics of several PPM based techniques were analyzed and discussed.
PPM of charge pump current pulses by a uniformly distributed sequence behaves
as a moving average filter and converts the filtered out harmonics to first order
shaped wideband noise. The noise added is insignificant at frequencies close to

dc. Therefore it does not affect the long term jitter of the PLL. Another spur
reduction technique called pulse repetition (PR) (proposed in [7]) eliminates the
spurs completely without redistributing it as noise. This technique is analysed
and compared to PPM.

Different spur reduction techniques based on PPM and PR are discussed. Sim-
pler implementation ideas are proposed to implement the techniques. Methods
of increasing the order of noise shaping in PPM to further reduce the midband
noise contributed by random PPM are discussed. The performance degradation of
the techniques in the presence of delay variations, random mismatch in the delays

and modulating sequence periodicity are discussed in detail. Simulation results

confirm the correctness of the derived results, reduction in spur levels and low
noise levels added by the PPM techniques.
The divider used in the design consumes high power due to the use of pseudo

NMOS logic for the initial stages. Better power optimization techniques like using
CML for the initial stages could be explored to reduce the power consumed by the
divider.
Since the major focus of the work is on the analysis of PPM based techniques, the

PLL was not optimized for random noise. The noise specification for which the
PLL was designed can be further tightened. For a given bandwidth, the charge
pump current can be increased and the loop filter resistor can be reduced to im-
prove the inband noise performance. The choice of ring oscillator for the VCO was
made due to the lack of better models of the inductors in the current technology

and time constraint to complete the work. However with an accurate inductor
model the VCO noise can be further reduced employing LC oscillators.
A replica delay tuning PLL was used to tune the delay across process and tem-
perature corners. This method however leads to an increased implementation
complexity. Better circuit design techniques can be explored to reduce the delay

variations in the delay line without increasing the implementation complexity.

105
 APPENDIX A

Spectral Analysis of PPM signals

A.1 Autocorrelation function of the PPM sig-

nals

The pulse position and amplitude modulated signal rp (t) is given by

X
rp (t) = xk p(t − kT − ak Td )
k

It can be expressed as rp (t) = r(t) ∗ p(t) where

∞
X
r(t) = xk δ(t − kT − ak Td ) (A.1)
k=−∞

r(t) is an impulse train whose amplitude is modulated by the sequence xk , and

the impulse positions are modulated by ak . Let xk and ak be stationary random

processes1 , such that ak is a integer valued sequence ∈ [0, N − 1]. Let Rx (k)
be the autocorrelation function of xk and Sx (f ) its power spectral density given
P
by Sx (f ) = k Rx (k)e−j2πf kT . For a cyclostationary random process [20] of pe-

riod T , the autocorrelation can be computed as a time average of the ensemble

autocorrelation function.

Z LT /2
1
Rr (τ ) = lim E[r(t)r(t − τ )] dt (A.2)
L→∞ LT −LT /2

1
Though we have assumed xk and ak to be stationary, wide sense stationarity [20] is sufficient
for the derivations given in this work.
E[r(t)r(t − τ )] = Rr (t, τ ) is the ensemble autocorrelation function given by

" #
XX
Rr (t, τ ) = E xi xj δ(t − iT − ai Td )δ(t − τ − jT − aj Td )
i j

Since xk and ak are independent, and f (t)δ(t − t0 ) = f (t0 )δ(t − t0 ), and E[xi xj ] =
Rx (i − j), making the substitution i − j = k, we get

XX
Rr (t, τ ) = Rx (k)E [δ(t − iT − ai Td )δ(τ − kT − (ai − ai−k )Td )]
k i

The above equation shows that the ensemble autocorrelation is a function of time.
It can be easily verified that it is also periodic, with a period T . Thus r(t) is a
cyclostationary random process [10]. Using Eq. (A.2) we get

L/2
X 1 X
Rr (τ ) = Rx (k) lim
L→∞ LT
k i=−L/2

Z iT +T
E [δ(t − iT − ai Td )δ(τ − kT − (ai − ai−k )Td )] dt (A.3)
iT

we define bk = ai − ai−k , as a new sequence. since the sequence ak is stationary,

the statistics of bk is independent of time origin i and depends only on time

difference k. Taking the integration inside the expectation operator and after
some manipulations we obtain

1X
Rr (τ ) = Rx (k)E [δ(τ − kT − bk Td )] (A.4)
T k

Let PA (a) be the probability mass function of the random variable a, and PBk (b)
be the probability mass function of the random variable bk . Then

 
X τ − kT
E [δ(τ − kT − bk Td )] = PBk (b) [δ(τ − kT − bTd )] = PBk
b∈B
Td

107
Using the above result in Eq. (A.4) we have

 
1X τ − kT
Rr (τ ) = Rx (k)PBk (A.5)
T k Td

 
τ − kT
PBk is a set of impulses spaced Td apart centered around kT . The
Td
amplitude of the impulses is the probability mass function2 of bk . Eq. (A.5) can
be re-written as

1X τ
Rr (τ ) = Rx (k)δ(τ − kT ) ∗ PBk ( ) (A.6)
T k Td

Then the spectrum of the PPAM signal is obtained by taking the Fourier transform
of Eq. (A.6). To compute the autocorrelation function we need to compute PBk (b)
for all k. The expressions of the spectrum is derived for different cases of the
modulating sequence by computing PBk (b) for all these cases, in the reminder of
the section.

A.1.1 PPM by an iid sequence

If the sample values of the sequence ak are iid, then ai and ai−k are independent.
The probability mass function PBk (b) of bk is the same for all non-zero values of
k and is given by the convolution of the PA (a) and PA (−a) [10].


 PA (a) ∗ PA (−a) = PB (b) for k 6= 0
PBk (b) = (A.7)

 δ(b) for k = 0

where PB (b) is the time independent probability distribution of the sequence bk .

Using the above conditions we obtain the expression for Rr (τ ) from Eq. (A.6) to
2
Though we have assumed ak to have discrete probability distribution, the expressions
 are

τ − kT
same even for continuous distributions. If bk is a continuous random variable then PBk
Td
is a continuous symmetric pulse centered at kT , whose area is 1 (since it is a pdf).

108
be !
1X τ Rx (0) τ
Rx (k)δ(τ − kT ) ∗ PB ( )+ [δ(τ ) − PB ( )]
T k Td T Td

The PSD Sr (f ) of the signal r(t) is obtained by taking the Fourier transform of the
above result. Since PA (τ /Td ) is real. If C(f ) is the Fourier transform of PA (τ /Td ),
then the Fourier transform of PA (−τ /Td ) is C ∗ (f ). Using Eq. (A.7) the Fourier
transform Cb (f ) of PB (τ /Td ) is given by

Cb (f ) = C(f )·C ∗ (f ) = |C(f )|2 (A.8)

Using these results we obtain the spectrum of PPAM signal r(t) modulated by an
iid sequence as

1 Rx (0)
Sr (f ) = Sx (f )|C(f )|2 + (1 − |C(f )|2 ) (A.9)
T T

For any arbitrary pulse shape rp (t) = r(t) ∗ p(t). The power spectral density
(Srp (f )) of of the PPAM signal rp (t) is given by Srp (f ) = Sr (f )|P (f )|2 , where

P (f ) is the Fourier transform of the pulse p(t). The spectrum Sxp (f ) of the PAM
signal xp (t) is well known [10] and given by Sxp (f ) = |P (f )|2 Sx (f )/T . Using this
we can reduce the spectrum of PPAM to

Rx (0)
Srp (f ) = Sxp (f )|C(f )|2 + (1 − |C(f )|2 )|P (f )|2 (A.10)
T

One can readily show that for a deterministic sequence xk , we obtain the same
results as derived above. An important point to observe is that the spectrum of

a PAM signal is completely determined by the autocorrelation of the samples of

the amplitude modulating sequence alone, but in a PPAM signal, the spectrum
depends on the probability distribution of the modulating signal ak as well.

109
A.1.2 PPM by a pseudo random sequence

In practice the modulating sequence ak is generated using a PRBS generator.

PRBS sequences are pseudo random and the sequence repeats itself with a period
M, ai = ai+M . The sequence bk = ai − ai+k is also periodic with a period M and
bk = 0 for k = · · · − M, 0, M, 2M · · · . For all other values of k, the sequence is the

same as the uncorrelated case.



 PA (a) ∗ PA (−a) = PB (b) for |k| =
6 0, M, 2M · · ·
PBk (b) =

 δ(b) for |k| = 0, M, 2M · · ·

Using these constraints in Eq. (A.6) and taking its Fourier transform we obtain the
spectrum Sr,per (f ) of the PPAM signal modulated by a pseudo random sequence

with period M as

1 2 (1 − |C(f )|2 ) f
Sr,per (f ) = Sx (f )|C(f )| + Sx ( ) (A.11)
T T M

P
where Sx (f /M) = k Rx (kM)e−j2πf kM T . When the impulse amplitudes are not
modulated Rx (k) = 1, the spectrum reduces to

1 2
X (1 − |C(f )|2 ) X kfr
2
|C(f )| δ(f − kfr ) + 2
δ(f − ) (A.12)
T MT M
k k

A.1.3 PPM by a binary correlated sequence

When the samples of ak are not iid PBk (b) is not constant and the spectrum of
the PPAM signal cannot be expressed in terms of the probability distribution of
sequence ak alone. We need to compute PBk (b) for all k, which depends on the
joint statistics of the sequence ai and ai+k . The spectrum can be computed by

modeling the source as a Markov source and the probabilities are computed as a
relative frequency of the samples of the signal. The statistics of the sequence bk
can also be computed analytically from the higher order moments of ak . Since

110
the probability distribution of bk depends upon the higher order moments of the
modulating sequence, N-PPM is a high non-linear modulation as the sequence
length increases.
However when ak takes on two values the spectrum of PPM as shown later is a

filtered version of the spectrum of the modulating sequence.

Let A be a two valued random variable which takes values a1 and a2 with prob-
abilities PA (a = a1 ) = p and PA (a = a2 ) = 1 − p. The autocorrelation of the
sequence ai is given by

Ra (k) = E[ai ai+k ] − µ2 6= 0 for k 6= 0 (A.13)

where µ = E[A] = p is the mean and µ2 is subtracted from E[ai ai+k ] to remove

the dc offset. Since the random variable A can take only two values (a1 and a2 ),
the sequence bk takes three values −(a1 − a2 ), 0 and a1 − a2 . To compute the
probability distribution of the sequence bk we need three equations, since we have
three unknowns.

We use the moments of the random variable bk to get the three equations

E[bk 0 ] = PBk (a2 − a1 ) + PBk (0) + PBk (a1 − a2 ) = 1

E[bk 1 ] = PBk (a2 − a1 ) − PBk (a1 − a2 ) = 0

E[bk 2 ] = (a1 − a2 )2 .[PBk (a1 − a2 )+

PBk (a2 − a1 )] = 2(Ra (0) − Ra (k))

Solving the above equations, we get


1 − 2·(Ra (0) − Ra (k))/(a1 − a2 )2 b = 0





PBk (b) = (Ra (0) − Ra (k))/(a1 − a2 )2 b = ±(a1 − a2 ) (A.14)




 0 otherwise

111
Thus the probability distribution PBk (b) of the sequence bk is completely deter-
mined by the probability distribution of the sequence ai and its autocorrelation
function Ra (k) when the random variable a takes only two values. Now that we
know PBk (b) for all k, we can substitute it in Eq. (A.6) and obtain the spectrum

of the PPAM signal Src (f ) modulated by a correlated binary random variable.

1 4sin2 (πf Td (a1 − a2 ))

Src (f ) = |C(f )|2 Sx (f ) + (Sa (f ) ∗ Sx (f )) (A.15)
T T

The PSD can be further reduced to

1 1 Sa (f ) ∗ Sx (f )
Sx (f )|C(f )|2 + (1 − |C(f )|2 )
T T Ra (0)

P
where Sa (f ) = Ra (k)e−j2πf kT is the PSD of the sequence ak , Sa (f )∗Sx (f ) is the
k
P
convolution of the two power spectra given by Sa (f )∗Sx (f ) = k Ra (k)Rx (k)e−j2πf kT
2
and |C(f )|2 = pe−j2πf a1 Td + (1 − p)e−j2πf a2 Td = 1 − 4p(1 − p)sin2 (πf Td (a1 − a2 ))

and Ra (0) = (a1 − a2 )2 p(1 − p). When the amplitude of the impulses are not
modulated Rx (k) = 1, we have

1 X 1 Sa (f )
Src (f ) = |C(f )|2 δ(f − kfr ) + · (1 − |C(f )|2 )
T T Ra (0)
k

An interesting point to note is that binary PPM is a linear modulation with

respect to the input modulating sequence. As the number of values taken by the

modulating sequence increases the probability distribution of bk depends upon

higher order moments of the modulating sequence ak . Thus the PSD of the N-
PPM signal for N > 2 depends on the higher order moments of the modulating
sequence. Hence N-PPM is a nonlinear modulation for N > 2.

112
A.1.4 PPM by a two bit correlated sequence

Let ac [i] be a two bit sequence formed by combining two independently generated
one bit sequences a1 [i] and a2 [i] with uniformly distributed ones and zeroes. Let
P
Ra (k) and Sa (f ) = k Ra (k)e−j2πf kT be the autocorrelation function and the PSD
of the two one bit sequences. The sequence bk = ac [i] − ac [i − k] can take values

∈ [−3, 3]. The probability distribution PBk (b) of the sequence bk for all k is given
by 


 P0 2 for b = 0



P1 2 + P1 P0



 for b = ±1

PBk (b) = P1 P0 for b = ±2 (A.16)






 P1 2 for b = ±3




0 otherwise

where P0 = p2 + (1 − p)2 + 2Ra (k) and P1 = p(1 − p) − Ra (k). Now that we know

PBk (b) for all k, we can substitute it in Eq. (A.6) and obtain the spectrum of the
PPAM signal Src (f ) modulated by a correlated two bit random variable

1 2

Sx (f )|C4 (f )|2 + Sa (f ) ∗ Sx (f ) sin2 (πf Td ) + sin2 (3πf Td )
T T

4

+ Sa (f ) ∗ Sx (f ) 2 sin2 (2πf Td ) + sin2 (πf Td ) − sin2 (3πf Td )
T
P P
where Sx (f )∗Sa2 (f ) = k Rx (k)(Ra (k))2 e−j2πf kT , Sa (f )∗Sx (f ) = k Rx (k)Ra (k)e−j2πf kT .
Though the PSD of the two bit correlated PPM depends only on its autocorre-
lation function, it is not a linear modulation as its spectrum depends upon the
squared auto correlation function as well. When the impulse amplitudes are not

modulated (Rx (k) = 1), the PSD of the PPM signal is given by

1 X 2 2 2 2


δ(f − kfr )|C 4 (f )| + S a (f ) sin (πf Td ) + sin (3πf Td )
T2 k T

4

+ Sa2 (f ) 2 sin2 (2πf Td ) + sin2 (πf Td ) − sin2 (3πf Td )
T

113
 P
where Sa2 (f ) = k (Ra (k))2 e−j2πf kT

A.1.5 PPM by a finitely correlated sequence

When the pulse amplitudes are not modulated Rx (k) = 1, the PSD Src (f ) of
the correlated PPM signal is obtain by taking the Fourier transform of the above
equation Eq. (A.6)
1X
Src (f ) = Cbk (f )e−j2πf kT (A.17)
T k

where Cbk (f ) is the characteristic function of the random variable bk for all k. Let
P
a[i] = 2s=0 2s z[i − s], be a three bit uniformly distributed sequence generated by
three shifted versions of the one bit iid sequence z[i]. Then a[i] and a[i − k] are
correlated for |k| = 0, 1 & 2 and for any |k| ≥ 3 the sequences are independent of
each other. When the total number of shifts k for which the sequence is correlated
is finite, we can express the power spectrum of the PPM signal modulated by a

correlated sequence as

1 X
Src (f ) = δ(t − kNfr ) + Cc (f ) (A.18)
T2 k

1 X 
Cc (f ) = CBl (f ) − |C(f )|2 e−jl2πf T (A.19)
T
l∈L

where L is the set of all the values of the time shifts for which the sequence a[i] and
a[i − k] are correlated. For the example sequence a[i], the set L is −2, −1, 0, 1, 2.

It can be seen from Eq. (A.18), the spectrum of the PPM signal is still filtered
by the pseudo moving average filter (CN (f )). But the redistributed noise is now
dependent on Cc (f ) which is a function of the joint distribution of a[i] & a[i − l]
for all the values of l for which the sequence is correlated. The first term of
Eq. (A.18) has no spurs at kfr for k ∈ [1, N − 1]. For the spurs to be absent in

Src (f ), Cc (f ) should be finite at these frequencies. |CN (kfr )| = 0 for a uniformly

distributed sequence ak . CBk (f ) is the Fourier transform of PBk (τ /T ), which is

114
real and non-negative and has an unit area. We have

Z ∞
|CBk (f )| < PBk (τ /T )dτ = 1 (A.20)
−∞

Using these conditions, we can readily show a crude upper bound on the noise
level to be
N1
Src (kfr ) ≤ (A.21)
T

where N1 is the cardinality3 of the set L. If N1 is finite, then Src (kfr ) converges
to a finite value which implies there is no harmonic at kfr . So for finitely corre-
lated sequences, uniform distribution of the modulating sequence ak is a sufficient

condition for spur elimination.

A.1.6 PPM by a correlated periodic sequence

If the samples of the sequence ak , in addition to being correlated, are also periodic
with a period M then the spectrum of the PPAM signal depends not only on
the correlation properties of the sequence ak but also the redistributed noise is
concentrated only on the harmonics of the modulating signal’s periodicity. The

spectrum of the PPAM signal whose pulse positions are modulated by a sequence
that is periodic and correlated can be expressed as

1
Srcp (f ) = Sx (f )|C(f )|2 + Cc (f ) (A.22)
T

where

1 XX 
Cc (f ) = CBl (f ) − |C(f )|2 Rx (kM + l)e−jl2πf (kM +l)T
T k l∈L
3
number of elements in L

115
Assuming only the pulse positions are modulated (Rx (k) = 1), the spectrum of
the PPM signal is given by

1 X
Srcp (f ) = 2
δ(f − kfr )|C(f )|2 + Cc (f ) (A.23)
T k

where
1 X 2  −j2πf lT
X kfr
Cc (f ) = 2
C Bl (f ) − |C(f )| e δ(f − )
MT l∈L k
M

A similar analysis can be performed like in the correlated case to find the ‘reference
harmonic strength bound’ when the sequence ak is uniformly distributed. It can
be shown that
N1
Src (kfr ) ≤ δ(f − kfr )
MT 2

A.2 Practical considerations for the choice of PRBS

length

Let a[i] be a m-bit sequence formed by m single bit sequences {zs [i]}. Generally
such pseudo random sequence are implemented using a LFSR. A maximum length
LFSR of length L is a state machine that goes through 2L − 1 states. That is it

undergoes all the states except the all zero state. In such a sequence, the number
of 1’s is equal to 2L−1 and the number of zeroes is (2L−1 − 1). One can then
compute the relative frequency of the occurrence of ones (p) and zeroes(1 − p) to
2L−1 2L−1 − 1
be p = P (zs [i] = 1) = L and 1 − p = P (zs [i] = 0) = L . It is clear
2 −1 2 −1
from these expressions that p & 1 − p are not equal and they approach 0.5 as L
increases. So increasing the length of the LFSR ensures that the random binary
data generated is of uniform distribution.
Pm−1 s
If a[i] = s=0 2 zs [i], the probability distribution of a[i] is given by

PA (q) = pq (1 − p)m−q

116
where q is the number of 1′ s in the m-bit number a[i]. we can readily see that
if p = 1/2, then a[i] has an uniform distribution. For a PRBS of length 7, p =
0.5034 (which is very close to 0.5). For a 3-bit sequence generated by taking three
consecutive tap outputs, we can easily compute PA (0) = 0.128, PA (7) = 0.122,

PA (1) = PA (2) = PA (4) = 0.124 and PA (3) = PA (5) = PA (6) = 0.126 which are
all close to 0.125.

117
 APPENDIX B

Ring Oscillator Basics

An n-stage ring oscillator is formed by a cascade of n single pole amplifiers with

the final output negatively fed back to the input of the first stage amplifier as
shown in Fig. B.1. A cascade of such n-stages ideally should produce sinusoidal

output if the Barkhausen criterion is exactly met. However the amplifier gain is
prone to process variations and when it’s value is smaller than the nominal value,
the oscillations will die out with time. Thus in practice the gain is chosen higher
than the nominal value to ensure that the system produce sustained oscillations.
However when the gain is chosen greater than the nominal value, the output of the

oscillator grows unbounded and in practice the amplifiers saturate resulting in a

clipped sinusoidal waveform. The following sections analyze the oscillators under
such conditions, first assuming that the gain is just sufficient for oscillation and
then assuming highly nonlinear amplifiers (saturating non-linearity) and compare

their performance in the presence of noise as a function of the number of stages

n.

-1

Gm Gm Gm
R C R C

Figure B.1: n-stage ring oscillator

B.1 Sinusoidal ring oscillators

The loop gain the n- stage ring oscillator shown in Fig. B.1 is given by

A0 n
A(s) = s n (B.1)
(1 + )
ωp

The closed loop poles of the feedback system are the solutions of

A0 n
1+ s n =0 (B.2)
(1 + )
ωp

Solving this we obtain the closed loop poles as

sk jkπ
= −1 + A0 exp (B.3)
ωp n

sk kπ kπ
= A0 cos − 1 + jA0 sin (B.4)
ωp n n

where k = 1, 3, ....2n − 1. From the Barkhausen criteria for oscillation we have

|A(jω)| = 1 and ∠A(jω) = π. For these conditions to be met, since all the stages

are identical each stage must introduce a phase shift of π/n. Using this result, we
get

π 1 π
= tan−1 (ωosc RC)fosc = tan( )
n 2πRC n

Additionally from the gain constraint (|A(jω)| = 1) we have

r
π 1
A0 = 1 + tan2 = π (B.5)
n cos
n

using the value of A0 from Eq. (B.5), and substituting it in Eq. (B.4)

Sk cos(kπ/n) sin (kπ/n)

= −1+j
ωp cos(π/n) cos (π/n)

119
since cos(kπ/n)/cos(π/n)≤1, the real part of all the poles are negative except for
two cases when k = 1 and k = 2n − 1, where the real part vanishes and the poles
are purely imaginary (±jωp tan(π/n)). This implies that out of the n poles only
two poles contribute to the oscillation and the transients due to the other poles die

out over time. From a frequency domain perspective, placing n first order poles in
a feedback loop results in a single resonant frequency with an infinite Q and the
remaining resonant points have finite Q and hence their natural response die out
in the steady state. Hence such an oscillator generates sinusoidal oscillations.If the
gain of the amplifier is made larger than the nominal value, then the poles move

to the right half s-plane. Thus ideally the system will produce an exponentially
growing sinusoid. In reality the amplifiers saturate once the voltage reach the
supply voltage level. Thus the amplitude of the sinusoid that is fed back remains
same (without increasing exponentially) and the oscillator’s output is no longer a

sinusoidal signal, but a clipped sinusoid. Section B.2 analyzes such a system and
shows the existence of multiple harmonics in the presence of high gain saturating
nonlinearities.

B.2 Oscillators with non-linear gain elements

A non-linear oscillator is one that employs high gain non-linear blocks with mem-
ory (in this case a delay element) to obtain sustained oscillation. A class of such

non-linear oscillator that is of interest to the discussion is shown in Fig. B.2.

CMOS based ring oscillators are classic examples of such non-linear oscillators. A
CMOS inverter can be modeled as a high gain saturating amplifier with a delay,
the delays of n such stages can be combined as a single delay of value Td and the

high gain blocks can be combined to a single slicer as shown in Fig. B.2. One can
readily see that feeding an impulse input to the system will produce a sustained os-
cillation as the impulse is fed back every Td seconds with opposite polarity. When

120
an impulse input is fed to the system, the output of the system is given by

X
y(t) = δ(t − 2kTd ) − δ(t − (2k + 1)Td )
k

It can be easily shown that such an output has harmonics at odd multiples of
fosc = 1/(2Td).
The above result can be intuitively seen from a frequency domain analysis as well.

The reminder of the section discusses the result using a linear analysis.
Consider a system with a delay in the feedback path and a memory less unity

x y

e-sTd

Figure B.2: Nonlinear oscillator

gain in the forward path. The loop gain of such a system is L(s) = e−sTd . The

characteristic equation of the system is given by

1 + e−sTd

The frequencies at which the system oscillates is determined by the frequencies at

which the loop gain becomes -11 . The magnitude of the loop gain is unity for all
frequencies but the phase of the loop gain reaches π at odd multiples of 1/(2Td ).

The magnitude of the closed loop transfer function of the system is given by

1
cos(πf Td )
1
In the frequency domain, these are the points at which the close loop transfer function blows
up on the jω axis.

121
The magnitude of the closed loop transfer function blows up when cos(πf Td ) = 0.
That is, when πf Td = kπ/2, k is an odd integer. Thus the system has multiple
oscillation frequencies that are odd harmonics of 1/(2Td ).
A point to note is that in an all pole system free of delays, when the Barkhausen

criterion is met, only a single pair of poles can exist on the jω axis and hence
only a single frequency of oscillation is possible. However in a system with linear
phase delay as discussed above, traditional root locus analysis cannot be used and
one has to resort to Nyquist plot for it stability. The Nyquist plot for the system
with the linear phase delay is a circle on the imaginary plane. As one increases

the frequency, the Nyquist diagram intersects the real axis at -1 infinite number
of times indicating the presence of infinite number of poles on the jω axis.
Considering the system again with a gain A in the forward path as shown in
Fig. B.3. To analyze the general stability of a system, bode plot alone would

be insufficient. A bode plot provides the value of the loop gain as a function of
frequency and thus is helpful in finding any singularities on the jω axis only. If
the pole is either in the right half or left half s-plane, bode analysis would not
reveal any singularities in the closed loop transfer function. In such a case one

has to vary the real part of s and find the appropriate jω line where the loop
gain exhibits a singularity2 . In the above example When an impulse is applied to
the system, a delayed and amplified version is fed back after Td seconds and the
process repeats indefinitely. If A < 1, the magnitude of the fed back impulses dies
down exponentially and when A > 1, the output grows indefinitely. Thus when

A > 1, the system is unstable3 . The closed loop transfer function of the system is
given by
A
H(s) =
1 + Ae−sTd

The inverse Laplace transform is obtained by the series expansion of the above
2
It can be easily verified that for a transfer function with a right half plane pole, the value
on the jω axis is finite.
3
For a bounded input, it produces unbounded output.

122
 x y
A

e-sTd

Figure B.3: Delay with gain in the feedforward path.

transfer function
i
A X (−Ae−sTd )
= A ·
1 + Ae−sTd i
i!

The inverse Laplace transform of the above series is

∞
X
A· (−A)i δ(t − iTd )
i=0

For A > 1 the output grows exponentially as expected.

Now consider the system with a saturating gain as shown in Fig. B.2. The sat-
urating gain assumes an infinite gain for signal levels around zero amplitude and

a zero gain for values greater than or less than zero. The behavior of the system
is very similar to the systems considered above with finite gain. But the ampli-
tude of oscillation is decided by the saturating amplifier shown in Fig. B.2. One
can readily see that feeding an impulse input to the system, the output would be

very similar to the system with A = 1. However as the amplitude of the input is
increased, the steady state output amplitude increases proportionately in case of
an unity gain amplifier. In case of non-linear oscillator, the amplitude of oscilla-
tion is determined by the forward slicer’s saturating amplitude (hence it remains
constant) and the frequency of oscillation is determined by the delay element in

the loop.

123
B.2.1 Conventional inverter based ring oscillator

In a given technology, the maximum obtainable frequency of oscillation (fmax ) is

the oscillation frequency of the three stage ring oscillator with minimum length
devices. Changing the width of the devices increases the current drawn from
the supply and also the load capacitance at each stage. Thus the frequency of

oscillation which depends upon the rise and fall times of the inverter remains
unchanged (since both current and capacitance scale by the same factor). However
increasing the length of the devices increases the load capacitance but reduces the
current drawn and hence lowers the frequency of oscillation. For an n-stage ring
Vdd

x(µW/Ln)
in out µn
µ=
µp
x(W/Ln)

Figure B.4: n-stage inverter based ring oscillator shown with device sizes.

oscillator there is a unique length Ln of the inverter corresponding to a given

frequency of oscillation fosc and supply voltage Vdd . Since increasing the number
of stages demands that the per-stage delay be reduced for the same frequency of
oscillation, the value of Ln decreases for increasing n.

Li > Lj for i < j

The problem is now to decide the number of stages given a target frequency of
oscillation.
For a given frequency of the oscillation, the maximum length Lmax of the inverter
used in the ring oscillator corresponds to the one when n = 3. That is Lmax = L3 .

The frequency of oscillation is inversely proportional to the per stage delay Td of

124
the inverter chain. The delay is further proportional to rise (tr ) and fall times (tf )
of the inverter. Assuming symmetric rise and fall times (tr = tf ), the rise and fall
times is proportional to the current provided by the device to charge the output
node capacitance. Let I be the current drawn from the supply and C be the

output node capacitance, then

1 1 In 1
fosc ∝ ∝ ∝ ∝ (B.6)
nTd ntr nC nLn 2

In in
In α (W/Ln)

in2 α (W/Ln)

C
C α (WLn)

Figure B.5: Model of the inverter as a current charging and discharging a capaci-
tor.

B.2.2 Effect of impedance scaling

For any ring oscillator, as the width of the devices is doubled, the signal current and
the output node capacitance doubles (frequency of oscillation remains same). The
noise power doubles (3 dB increase). Thus there is a 6 dB increase in the signal
power whereas a 3 dB increase in the noise power and the signal to noise ratio

improves by 3 dB. So once the number of stages n and the corresponding length
Ln is fixed, increasing the width of the devices increases the power consumption
and improves the phase noise of the VCO (For every 6 dB increase in signal power,
the signal to noise ratio improves by 3 dB).

125
B.2.3 Noise as a function of n

Let fosc be the desired oscillation frequency such that fosc < fmax 4 . The minimum
number of stages necessary to obtain the desired frequency of oscillation is 3, and
the corresponding length is L3 which is larger than the minimum possible length
in a given technology. In practice there exists a maximum number of stages nmax

that can oscillate at fosc 5 . Thus for a given frequency of oscillation fosc , there are
many possible number of stages n (with different lengths), such that 3 < n < nmax .
Fig. B.5 shows the model of the inverter in a ring oscillator as a current source
I charging (discharging) a capacitor with an additive noise current source In . As
shown in the figure, the signal current is proportional to the device width to

length ratio W/Ln and the power of the noise current is also proportional to the
width to length ratio (channel transconductance of the devices). The total power6
consumed in the ring oscillator is In Vdd . In every cycle of oscillation, the capacitor
is charged and discharged by the signal current In and the additive noise current

in . The phase of the VCO output is determined by the signal and noise current
as they charge and discharge the output capacitance.
The phase of the signal gets corrupted only when it is transitioning from 0 to Vdd .
For simplicity of analysis this time is taken to be equal to the rise time of the

inverter. The output voltage in the interval [0, tr ] can be written as

Z t
In in (t)
vout (t) = t + dt
C 0 C
4
fmax refers to the maximum frequency of oscillation of a three stage ring oscillator with
minimum lengths.
5
The maximum number of stages nmax can be found by maintaining the lengths of the devices
at a minimum and increasing the number of stages till the desired frequency of oscillation is
obtained.
6
In a n-stage ring oscillator the current drawn from the supply is switching between a max
and minimum value. The average value of the current is proportional to per stage current In
and the high frequency zero average current switches at a frequency nfosc . Thus the average
power dissipated by a n-stage ring oscillator is given by In Vdd

126
When t = tr , the signal should ideally reach Vdd . That is Vdd = In tr /C.

Z tr
In in (t)
vout (tr ) = tr + dt
C 0 C

 Z tr 
In in (t)
= tr + dt
C 0 In

From the above expression the rise time in the presence of noise can be written as

Z tr
in (t)
tr1 = tr + dt (B.7)
0 In

The amount by which the rise time deviates from its ideal value depends upon the
noise current and the signal current injected into the capacitor. This deviation is
nothing but the per stage jitter added by the inverter. Let σdt 2 be the per stage
jitter variance, then tr1 = tr + σdt . Assuming the noise current to be a zero mean

Gaussian noise process with variance σi 2 . in (t) is a stationary random process and
the integral version of the gaussian process is a Wiener process [20]. The variance
of the integral in Eq. (B.7) is proportional to the integration interval[20] tr

kσi 2
σdt 2 = tr
In 2

where k is a proportionality constant. The variance of the noise current is pro-

portional to transconductance of the devices, which in turn is proportional to the

per stage current In for a fixed gate over drive voltage. Thus we have

k1 In k1 tr
σdt 2 = 2 tr =
In In

The total jitter at the ring oscillator output is the sum of the jitter of the n stages.
Let σtot 2 be the total jitter of the n-stage ring oscillator, then

k1 tr
σtot 2 = nσdt 2 = n·
In

127
The figure of merit (FOM) of the n-stage ring oscillator is given by

1 1
F OM = =
jitter·Pd nk1 tr Vdd

From Eq. (B.6) we have that fosc ∝1/(ntr ). Thus the FOM can be further reduced
to
k3 fosc
F OM =
Vdd

An interesting observation to make is that the FOM is independent of n. Thus

for a given frequency of oscillation and supply voltage, the FOM is independent
of the number stages in the ring oscillator. As the number of the stages increase

the pulse shape also changes. But in case of sinusoidal oscillators, as the number
stages increases the per stage delay reduces but the shape of the sinusoidal signal
remains the same and there is no advantage due to faster rise/ fall times. Hence
for a large n, as the number of stages are increased the signal amplitude does not
change, but the noise power changes. Another point to observe is that the FOM

is proportional to the oscillation frequency in case of saturating ring oscillators,

but inversely proportional to the frequency of oscillation in case of the sinusoidal
oscillators.

128
 APPENDIX C

Asymmetric Sidebands in the Presence of both

Amplitude and Phase Modulation

C.1 Amplitude modulation

Amplitude modulation (AM) refers to the modulation of the amplitude of the

carrier signal proportional to a low frequency modulating signal. The amplitude

modulated signal is represented as

xAM (t) = A1 (1 + m(t)) cos(2πfc t)

The spectrum of the signal contains impulses at the carrier frequency and a fre-
quency translated version of the low frequency modulating signal. For a sinusoidal

modulation m(t) = m1 cos(2πfm t), the time domain signal can be represented as

A1 m1 A1 m1
xAM (t) = A1 cos(2πfc t) + cos(2π(fc + fm )t) + cos(2π(fc − fm )t)
2 2

The spectrum of the AM signal modulated by a sinusoidal signal is given by

A1 A1 m1 A1 m1
SAM (f ) = δ(f − fc ) + δ(f − fc − fm ) + δ(f − fc + fm )
2 4 4

A1 A1 m1 A1 m1
+ δ(f + fc ) + δ(f + fc + fm ) + δ(f + fc − fm )
2 4 4

In case of AM the magnitude of both the sidebands are same and the sidebands

are in phase.
C.2 Frequency modulation

In Frequency modulation (FM), the frequency of the carrier signal is modulated

proportional to a low frequency modulating signal. The time domain representa-
tion of such a signal is given by

Z t
xF M (t) = A2 cos(2πfc t + 2π m(τ )dτ )
−∞

For an arbitrary modulating signal m(t), it is not possible to write a general ex-
pression for the spectrum of xF M (t) in terms of the spectrum of m(t). However
when the modulating signal is sinusoid, the spectrum of the signal is completely
known [10].

For the purposes of the discussion carried out here, we consider an even sim-
pler version of sinusoidal FM called narrow-band FM, where the amplitude of
the modulating signal is much smaller than 11 . Let the modulating signal be
m1 cos(2πfm t). The time domain representation of an FM signal modulated by a
sinusoid is given by

xF M (t) = A2 cos(2πfc t + m2 sin(2πfm t))

where m2 = m1 /fm . In case of a narrow band FM, the time domain signal can
expressed as

xF M (t)≈A2 cos(2πfc t) + A2 m2 sin(2πfc t) sin(2πfm t)

A2 m2 A2 m2
= A2 cos(2πfc t) + cos(2π(fc + fm )t) − cos(2π(fc − fm )t)
2 2

The spectrum of the resulting signal is given by

A2 A2 m2 A2 m2
SF M (f ) = δ(f − fc ) + δ(f − fc − fm ) − δ(f − fc + fm )
2 4 4
1
The same conclusions can be drawn even if it were wide band FM. But the complex analysis
is avoided for the sake of brevity.

130
 A2 A2 m2 A2 m2
+ δ(f + fc ) + δ(f + fc + fm ) − δ(f + fc − fm )
2 4 4

A few points to note here are

• The modulating signals in case of AM and FM are in quadrature2

• The sidebands in the narrow band FM signal have opposite polarity.

C.3 Both AM and FM

A1/2
(a)
m1A1/4 m1A1/4 (A1+A2)/2
(c)
(m2A2+m1A1)/4
fc-fm fc fc+fm (m1A1-m2A2)/4

A2/2 fc-fm fc fc+fm

(b)
m2A2/4
fc-fm
fc fc+fm
-m2A2/4
Figure C.1: Asymmetric sideband in the presence of AM and FM. (a) Spectrum
of an AM signal, (b) Spectrum of an FM signal and (c) Spectrum of
the combined AM and FM signal

Adding the AM signal with an FM signal generates a signal with asymmetric

sidebands. Let x(t) be the resulting signal, then the time domain representation

is given by

A1 + A2 A1 m1 + A2 m2
x(t) = xAM (t) + xF M (t) = cos(2πfc t) + cos(2π(fc + fm )t)
2 2

A1 m1 − A2 m2
+ cos(2π(fc − fm )t)
2
2
This is due to the integration of the modulating signal in case of FM.

131
The spectrum of the AM and FM signal and the resultant signal obtained by
adding the two signals is shown graphically for positive frequencies in Fig. C.1.
The spectrum of the signal (for positive frequencies) is given by

A1 + A2 A1 m1 + A2 m2 A1 m1 − A2 m2
Sx (f ) = δ(f −fc )+ δ(f −fc −fm )+ δ(f −fc +fm )
2 4 4

132
 APPENDIX D

Pin Details of the Fabricated Test Chip

1 48 47 46 45 44 43 42 41 40 39 38 37
2 36
3 35
4 34
5 33
6 32
7
PLL_180nm 31
8 30
9 29
10 28
11 27
12 26
13 14 15 16 17 18 19 20 21 22 23 2425

Figure D.1: Pin diagram of the PLL.

Table D.1: Functionality of each pin.

Pin Name Functionality

1, 6, 12, gnd Ground
21, 25, 44
2 VDD PRBS 1.8 V Supply voltage of the PRBS
3 PRBS EN Enable signal for the PRBS (Enables PRBS
when it is high)
4 REF CLK Reference clock signal for the PLL
5 VDD PFD 1.8 V Suppy voltage for the PFD and delay
cells
7, 8, 9, 10 BW CP0, Control bits for charge pump current and
BW CP1, loop filter capacitor tuning
BW LPF1,
BW LPF2
11 VDD DIV 1.8 V Supply voltage for the divider block
13, 14, 15, DIV3, DIV2, DIV1, Control bits for changing the divide
16 DIV0 value (nominal value is ‘1000’)
17 PLL SEL Enables one of the two techniques in the PLL
18 VB VCO BUF 20 µA current bias input for the VCO buffer
Pin Name Functionality
19 VDD VCO BUF 2.4 V supply of the VCO output buffer
20, 22 PLL OUTN, Differential output signals of the VCO buffer
PLL OUTP
23 VDD VCO 2.2 V supply voltage for the VCO
24 VCM BUF 1.2 V common mode bias signal for the VCO
buffer
26 and 28 IBIAS VCO and 1.2 mA and 240 µA current bias inputs for
ITUNE VCO the VCO
27 VDD REF 1.8 V reference signal for the VCO tuning cir-
cuit
29 PLL VCONT OUT Buffered control voltage output of the PLL
30, 31, 32 Vr cp, VDD CP, 0.9 V, 1.8 V,0.9 V bias and supply signals for
VCM the charge pump
33, 34 VTOP, VBOT 1.4 V and 0.4 V signals for the inverters driv-
ing charge pump switches
35 BW MEAS EN when ‘high’ connects the buffered control
voltage output to the PLL VCONT OUT
pin
36 RST PRBS Reset signal for the PRBS
37 VD EXT External supply voltage for the delay cells
38 LCK DET EN Enable high signal for the lock detector
39 VCONT DLL Buffered control voltage of the DLL
40 DLL DISABLE Disable ‘high’ signal for the DLL
41, 42 VDD DLL, 1.8 V and 0.9 V supply and bias voltages for
VCM DLL the DLL
43 VBIAS DLL current input bias signal for the DLL
45 DLL REF CLK Reference clock for the DLL
46, 47, 48 PRBS EXT0, External PRBS signals for the PLL (Enabled
PRBS EXT1, when PRBS EN=0)
PRBS EXT2

134
List of Publications Based on the Thesis

• Chembiyan Thambidurai and Nagendra Krishnapura, “Spur Reduction in

Wide band PLLs by Random Positioning of Charge pump Current Pulses,”
in Proc. 2010 IEEE Int. Symposium on Circuits and Systems (ISCAS), June
2010.

• Chembiyan Thambidurai and Nagendra Krishnapura, “On Pulse Position

Modulation and its Application to PLLs for Spur Reduction,” IEEE Trans-
action on Circuits and Systems I : Regular Papers, July 2011.

135
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