CMR INSTITUTE OF TECHNOLOGY

Affiliated to VTU, Approved by AICTE, Accredited by NBA and

NAAC with “A++” Grade
ITPL MAIN ROAD, BROOKFIELD, BENGALURU-560037,
KARNATAKA, INDIA

Department of Artificial Intelligence and Data Science

LAB MANUAL

DIGITAL DESIGN AND COMPUTER

ORGANIZATION LABORATORY
(Effective from the academic year 2023 -2024)

Course Code: BCS302

Course objectives:

● To demonstrate the functionalities of binary logic system

● To explain the working of combinational and sequential logic system

● To realize the basic structure of computer system

● To illustrate the working of I/O operations and processing unit

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:

CO1: Apply the K–Map techniques to simplify various Boolean expressions.

CO2: Design different types of combinational and sequential circuits along with Verilog
programs.

CO3: Describe the fundamentals of machine instructions, addressing modes and Processor
performance.

CO4: Explain the approaches involved in achieving communication between processor and
I/O devices.

CO5:Analyze internal Organization of Memory and Impact of cache/Pipelining on Processor

Performance.
 TABLE OF CONTENTS

S. No Experiments Page

Simulation packages preferred: Isim

1. Write HDL code to realize all logic gates.

2. Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder,
Half and Full Subtractor.

3. Design Verilog program to implement Different types of multiplexer like 2:1, 4:1
and 8:1

4. Design Verilog program to implement types of De-Multiplexer.

5. Design Verilog HDL to implement Decimal adder.

6. Design Verilog program for implementing various types of Flip-Flops such as SR,
JK and D.

7. Given a 4-variable logic expression, simplify it using appropriate technique and

simulate the same using basic gates.

8. Design a 4 bit full adder and subtractor and simulate the same using basic gates.

9. Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
 OVERVIEW OF HDL LAB

In electronics, a hardware description language or HDL is any language from a class of Computer
languages for formal description of electronic circuits. It can describe the circuit's operation, its
design and organization, and tests to verify its operation by means of simulation HDLs are
standard text-based expressions of the spatial, temporal structure and behavior of electronic
systems. In contrast to a software programming language, HDL syntax, semantics include explicit
notations for expressing time and concurrency, which are the attributes of hardware. Languages
whose only characteristic is to express circuit connectivity between a hierarchies of blocks are
properly classified as netlist languages.HDLs are used to write executable specifications of some
piece of hardware. A
simulation program, designed to implement the underlying semantics of the language statements,c
oupled with simulating the progress of time, provides the hardware designer with the
ability to model a piece of hardware before it is created physically. It is this execute ability that
gives HDLs the illusion of being programming languages. Simulators capable of supporting
discrete-event and continuous-time (analog) modeling exist, and HDLs targeted for each are
available.It is certainly possible to represent hardware semantics using traditional programming
languages such as C++, although to function such programs must be augmented with extensive
and unwieldy class libraries. Primarily, however, software programming languages function as a
hardware description language Using the proper subset of virtually any language, a software
program called a synthesizer can infer hardware logic operations from the language statements
and produce an equivalent net list of generic hardware primitives to implement the specified
behavior. This typically requires the synthesizer to ignore the expression of any timing constructs
in the text.The two most widely-used and well-supported HDL varieties used in industry are

Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The
language supports the design, verification, and implementation of analog, digital, and mixed -
signal circuits at various levels of abstraction The designers of Verilog wanted a language with
syntax similar to the C programming language so that it would be familiar to engineers and
readily accepted. The language is case-
sensitive, has a preprocessor like C, and the major control flow keywords, such as "if"and "while",
are similar. The formatting mechanism in the printing routines and languageoperators and their
precedence are also similarThe language differs in some fundamental ways. Verilog uses
Begin/End instead of curly bracesto define a block of code. The concept of time, so important to a
HDL won't be found in C The language differs from a conventional programming language in
that the execution of
statementsis not strictly sequential. A Verilog design consists of a hierarchy of modules are define
d with a set of input, output, and bidirectional ports. Internally, a module contains a list of
wiresand registers. Concurrent and sequential statements define the behavior of the module by
defining the relationships between the ports, wires, and registers Sequential statements
are placed inside a begin/end block and executed in sequential order within the block. But all
concurrent statements and all begin/end blocks in the design are executed in parallel,qualifying V
erilog as a Data flow language. A module can also contain one or more instances of another
module to define sub-behavior A subset of statements in the language is synthesizable. If the
modules in a design contains a netlist that describes the basic components and connections to be
implemented in hardware only synthesizable statements, software can be used to transform or
synthesize the design into the netlist may then be transformed into, for example, a form
describing the standard cells of an integrated circuit (e.g. ASIC) or a bit stream for a
programmable logic device (e.g. FPGA).
 EXPERIMENT 1

Aim: Write HDL code to realize all logic gates.

Theory:

A logic gate performs a logical operation on one or more logic inputs and produces a
single logic output. The logic normally performed is Boolean logic
and is most commonly found in digital circuits.

Verilog Code:

module allgate ( a, b, yand,yor,ynot,ynand,ynor,yxor,yxnor );

input a,b;
output yand, yor, ynot, ynand, ynor, yxor, yxnor);
assign yand = a & b; //AND Operation
assign yor = a | b; //OR Operation
assign ynot = ~a ; //NOT Operation
assign ynand = ~(a & b); //NAND Operation
assign ynor = ~(a | b); //NOR Operation
assign yxor = a ^ b; //XOR Operation
assign yxnor =~(a^b); //XNOR Operation
endmodule // END of the module
 EXPERIMENT-2

Aim: Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half
and Full Subtractor.

Theory:

Half Adder -A Half-adder is an arithmetic circuit that needs two binary inputs and two binary
outputs to perform the addition of two single bits.

The input variable determines the augend and addend bits whereas the output variable generates
the sum and carry. The Half-Adder is a basic building block for adding two numbers (two inputs)
and produce two outputs. The function of a half-adder with the block diagram, Logical
circuit, and truth table of a half-adder as shown below:

The adder is used to perform OR operation of two single bit binary numbers and generates an
output as follows:

The logical expression for half adder:

Sum= AB + AB = AB
Carry = AB
 Verilog Code:

Program: Half Adder

module HalfAdder(a,b,sum,carry);
input a,b;
output sum, carry;
assign sum=a^b;
assign carry=a&b;
endmodule

Testbench code –

initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
// Wait 100 ns for global reset to finish
end

Full Adder- The half adder can be used to add two numbers only. To overcome this issue, the full
adder was designed. The full adder is employed to add three 1-bit binary numbers (consider the
inputs as A, B, and C) and generates the output as SUM and CARRY. The block diagram of Full
adder, truth table and K-map implementation are presented below:
 Sum = Ā B Cin + A B Cin + A B Cin + A B Cin = A B Cin

Carry = AB + BCin + CinA

Verilog Code:

Program: Full Adder:

module FullAdder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

Testbench code –

initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;

// Wait 100 ns for global reset to finish

end

Half Subtractor - A half-subtractor is a combinational logic circuit that have two inputs and
two outputs (i.e. difference and borrow).

Truth Table for Half Subtractor

Inputs Outputs
A B d b
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 K- Map for half subtractor

Equation of Half Subtractor:

Difference (d) = A XOR B = A^B

Borrow (b) = A&B

Verilog Code:

Program: Half Subtractor

module Halfsubtractor(a,b,diff,borrow);
input a,b;
output diff,borrow;
assign diff=a^b;
assign borrow=(~a)&b;

endmodule

Testbench Code:

initial begin
// Initialize Inputs

a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;

// Wait 100 ns for global reset to finish

// Add stimulus here

end
Full Subtractor- A full subtractor is designed to accommodate the extra borrow bit from the
previous stage. Thus it has three single-bit inputs and produces two single-bit outputs.

Block diagram

A
Full
B Subtractor
.
C

Truth table

A B C Difference(d) Borrow(b)

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Equation of full subtractor

D = A ^ B ^ Bin
Bout = A’ · B + (A ^ B)’ · Bin

Program: FullSubtractor

Verilog Code:

module fullsubtractor(a,b,c,diff,borrow);

input a, b, c;
output diff, borrow;
assign diff=a^b^c;
assign borrow=((~a)&b)|((~a)&c)|(b&c);

endmodule
Testbench Code:

initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;

// Add stimulus here

end
 EXPERIMENT 3

Aim: Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and
8:1.

Theory:

A multiplexer (MUX) is a combinational circuit that connects any one input line (out of
multiple N lines) to the single output line based on its control input signal (or selection lines).
Usually, for ‘n’ selection lines, there are N = 2^n input lines. Nomenclature: N:1 denotes it has
‘N’ input lines and one output line.

2:1 Multiplexer:
2:1 MUX has 2 input lines and one select line.

Block diagram

I0

2:1
Multiplexer Y

I1

S
Truth Table

S Outputs
0 I0
1 I1

Program : Mux 2x1

Verilog Code:

module mux_2_1(I0,I1,S,Y );
input I0,I1,S;
output reg Y;
always @ (*)
begin
case(S)
1'b0: Y<=I0;
1'b1: Y<=I1;
endcase
end
endmodule
 Testbench code-

initial begin
// Initialize Inputs
I0 = 1'b0; #100;
I1 = 1'b0; #100;
S = 1'b0; #100;

I0 = 1'b1; #100;
I1 = 1'b1; #100;
S = 1'b1; #100;

// Wait 100 ns for global reset to finish

end

4:1 Multiplexer

4:1 has 4 input lines and two select lines.

Block Diagram

i0

i1 4:1
Multiplexer
i2 Y

i3

S0 s1

Truth Table

S0 S1 y
0 0 i0
0 1 i1
1 0 i2
1 1 i3

4:1 Multiplexer equation

Y = s0ʹ . s1ʹ .i0 + s0ʹ. s1. i1 + s0. s1ʹ. i2 + s0. s1. i3

Program : Mux 4x1

Verilog Code

module MUX_4_1(Y,S,I);
input [3:0]I;
input [1:0]S;
output reg Y;
always@(I or S)
begin
case(S)
2'b00:Y<=I[0];
2'b01:Y<=I[1];
2'b10:Y<=I[2];
2'b11:Y<=I[3];
endcase
end
endmodule

Testbench code -

initial begin
// Initialize Inputs
I=4'b1001;S=2'b00;#100;
I=4'b0110;S=2'b01;#100;
I=4'b1100;S=2'b10;#100;
I=4'b0110;S=2'b11;#100;

// Wait 100 ns for global reset to finish

end

8:1 Multiplexer:

8:1 multiplexer has 8 input lines and 3 select lines.

Block diagram:

Enable (E)

I0
I1
I2
I3 8:1
I4 Multiplexer Y
I5
I6
I7

s0 s1 s2
Truth Table

S0 S1 S2 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Program : Mux 8x1

Verilog Code:

module MUX_8_1(Y,S,I);
input [7:0]I;
input [2:0]S;
output reg Y;
always@(*)
begin
case(S)
3'b000:Y<=I[0];
3'b001:Y<=I[1];
3'b010:Y<=I[2];
3'b011:Y<=I[3];
3'b100:Y<=I[4];
3'b101:Y<=I[5];
3'b110:Y<=I[6];
3'b111:Y<=I[7];
endcase
end
endmodule

Testbench Code –

initial begin
// Initialize Inputs
I=8'b00101010;S=3'b000;#100;
I=8'b01101010;S=3'b001;#100;
I=8'b10001110;S=3'b010;#100;
I=8'b01101011;S=3'b011;#100;
I=8'b00101010;S=3'b100;#100;
I=8'b01111010;S=3'b101;#100;
I=8'b01011010;S=3'b110;#100;
I=8'b00111111;S=3'b111;#100;
// Wait 100 ns for global reset to finish

end
 EXPERIMENT 4

Aim: Design Verilog program to implement types of De-Multiplexer.

Theory: A demultiplexer (DEMUX) is a combinational circuit that works exactly opposite to a

multiplexer. A DEMUX has a single input line that connects to any one of the output lines
based on its control input signal (or selection lines). Usually, for ‘n’ selection lines, there are N
= 2^n output lines. Nomenclature: 1:N denotes one input line and ‘N’ output lines.

1:2 Demultiplexer

1:2 DEMUX has one select line and 2 output lines.

Block diagram

Y0
1:2
I Demultiplexer

Y1

S1
Truth Table

S1 Y0 Y1
0 I 0
1 0 I

Veriog Code:

Program : Demux1x2

module DEMUX_1_2(Y,S,I);
input I,S;
output reg [1:0]Y;
always@(*)
case(S)
0:begin Y[0]<=I; Y[1]<=0;end
1:begin Y[1]<=I; Y[0]<=0;end
endcase
endmodule
Testbench Code –

initial begin
// Initialize Inputs
i = 1; s = 0; #100;
i = 1; s = 1; #100;

end

1:4 Demultiplexer

1:4 DEMUX has one select line and 4 output lines.

Block diagram:

Y0

i 1:4 Y1
DEMUX
Y2

Y3

s0 s1

Truth Table

S0 S1 Y0 Y1 Y2 Y3
0 0 i 0 0 0
0 1 0 i 0 0
1 0 0 0 i 0
1 1 0 0 0 i

Program : Demux1x4
module rk_demux_1_4(i,s,y);
input i;
input [1:0]s;
output reg [3:0]y;
always @ (*)
begin
case (s)
2'b00: begin y[0]<=i; y[3:1]<=0; end
2'b01: begin y[1]<=i; y[0]<=0; end
2'b10: begin y[2]<=i; y[1]<=0; end
2'b11: begin y[3]<=i; y[2]<=0; end
endcase
end
endmodule
Testbench code:

initial begin
// Initialize Inputs
i = 1;s = 2'b00;#100;
i = 1;s = 2'b01;#100;
i = 1;s = 2'b10;#100;
i = 1;s = 2'b11;#100;
// Wait 100 ns for global reset to finish
end

1:8 DEMUX:

1:8 DEMUX has one input, three select lines and eight outputs.

Block diagram
Y0

Y1
Y2
i Y3

Y4
Y5
Y6
Y7

s0 s1 s2

Truth Table

i S0 S1 S2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1

Equation of 1:8 DEMUX

Boolean Expression for 1:8 Demultiplexer

Y0 = A (S2)'(S1)'(S0)’
Y1 = A (S2)'(S1)'(S0)
Y2 = A (S2)'(S1)(S0)’
Y3 = A (S2)'(S1)(S0)
Y4 = A (S2)(S1)'(S0)’
Y5 = A (S2)(S1)'(S0)
Y6 = A (S2)(S1)(S0)’
Y7 = A (S2)(S1)(S0)

Program : Demux1x8

Verilog Code

module rk_demux_1_8(i,s,y);
input [2:0]s;
input i;
output reg [7:0]y;

always @ (*)
begin

case (s)
3'b000: begin y[0]<=i; y[7:1]<=0; end
3'b001: begin y[1]<=i; y[0]<=0; end
3'b010: begin y[2]<=i; y[1]<=0; end
3'b011: begin y[3]<=i; y[2]<=0; end
3'b100: begin y[4]<=i; y[3]<=0; end
3'b101: begin y[5]<=i; y[4]<=0; end
3'b110: begin y[6]<=i; y[5]<=0; end
3'b111: begin y[7]<=i; y[6]<=0; end
endcase
end
endmodule

Testbench Code -

initial begin
// Initialize Inputs
i = 1; s = 3'b000; #100;
i = 1; s = 3'b001; #100;
i = 1; s = 3'b010; #100;
i = 1; s = 3'b011; #100;
i = 1; s = 3'b100; #100;
i = 1; s = 3'b101; #100;
i = 1; s = 3'b110; #100;
i = 1; s = 3'b111; #100;
// Wait 100 ns for global reset to finish
end
 EXPERIMENT-5

Aim: Design Verilog HDL to implement Decimal adder

Theory: BCD stands for binary coded decimal. It is used to perform the addition of BCD
numbers. A BCD digit can have any of ten possible four-bit representations. Suppose, we
have two 4-bit numbers A and B. The value of A and B can vary from 0(0000 in binary) to
9(1001 in binary) because we are considering decimal numbers. There is the following table
used in designing of BCD-Adder.

If the sum of two numbers is less than or equal to 9, then the value of BCD sum and binary
sum will be same otherwise add 6 (0110 in binary).

Program: BCD Adder

Verilog Code:

module DeciAdd(a,b,Cin,Sum,Cout);
input [3:0]a,b;
input Cin;
output[3:0]Sum;
output Cout;
reg [4:0]temp;
reg [3:0]Sum;
reg Cout;
always@(*)
begin
temp=a+b+Cin;
if(temp>19)
 begin
Sum= temp[3:0];
Cout=1;
end
else if(temp>9)
begin
temp=temp+6;
Cout=1;
Sum=temp[3:0];
end
else
begin
Cout=0;
Sum=temp[3:0];
end
end
endmodule

Testbench code –

initial begin
// Initialize Inputs
a = 4'b0110;b = 4'b0010;Cin = 0;#100;
a = 4'b0110;b = 4'b1000;Cin = 0;#100;
a = 4'b1100;b = 4'b0111;Cin = 0;#100;
a = 4'b1010;b = 4'b1010;Cin = 0;#100;

// Add stimulus here

end
 Experiment-6

Aim: Design Verilog program for implementing various types of Flip-Flops such as SR, JK and
D.

Theory:

A flip flop in digital electronics is a circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs. Flip-flops and latches
are fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems. Both are used as data storage elements.
Flip-flop is a circuit that maintains a state until directed by input to change the state. A basic
flip-flop can be constructed using four-NAND or four-NOR gates. Flip flop is popularly
known as the basic digital memory circuit. It has its two states as logic 1(High) and logic
0(low) states. A flip flop is a sequential circuit which consist of single binary state of
information or data. The digital circuit is a flip flop which has two outputs and are of
opposite states. It is also known as a Bistable Multivibrator.

S-R Flip Flop : This is the most common flip-flop among all. This simple flip-flop circuit has a
set input (S) and a reset input (R). In this system, when you Set “S” as active, the output “Q”
would be high, and “Q‘” would be low. Once the outputs are established, the wiring of the circuit
is maintained until “S” or “R” go high, or power is turned off.

Block diagram

S Q

CLK SR
Flip-Flop

R Qʹ

Truth Table

S R Q Qʹ
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 -
1 1 1 -
K-Map

Verilog Code:

module Sr_FFF(s,r,clk,q,qbar);
input s,r,clk;
output reg q,qbar;

always@(posedge clk)
begin
case({s,r})
2'b00:begin q<=q; qbar<=qbar;end
2'b01:begin q<=1'b0; qbar<=1'b1;end
2'b10:begin q<=1'b1; qbar<=1'b0;end
2'b11:begin q<=1'bz; qbar<=1'bz;end
endcase
end
endmodule

Test Bench:

Sr_FFF uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qbar(qbar));

initial begin
clk = 1'b0;
end

always #5 clk=~clk;
initial begin
// Initialize Inputs
s = 1'b0;r = 1'b0;#100;
s = 1'b0;r = 1'b1;#100;
s = 1'b1;r = 1'b0;#100;
s = 1'b1;r = 1'b1;#100;
end
JK Flip-Flop:

The JK flip flop has two inputs ‘J’ and ‘K’. It behaves the same as SR flip flop except that it
eliminates undefined output state (Q = x for S=1, R=1).For J=1, K=1, output Q toggles from
its previous output state.

Block diagram

J Q

CLK

K Qʹ

RESET
Verilog Code:

module Jk_FFF(j, k, clk, q);

input j,k,clk;
output reg q;

always @ (posedge clk)

case ({j,k})
2'b00:begin q<=q; end
2'b01:begin q<=1'b0; end
2'b10:begin q<=1'b1; end
2'b11:begin q<=~q; end

endcase
endmodule

Test Bench:

Jk_FFF uut (
.j(j),
.k(k),
.clk(clk),
.q(q)
);

initial begin
clk = 1'b0;
end

always #5 clk = ~clk;

initial begin
j = 1'b0;k = 1'b0;#100;
j = 1'b0;k = 1'b1;#100;
j = 1'b1;k = 1'b0;#100;
j = 1'b1;k = 1'b1;#100;

end
D FlipFlop:

D flip flop is an electronic devices that is known as “delay flip flop” or “data flip flop”
which is used to store single bit of data. D flip flops are synchronous or asynchronous. The clock
single required for the synchronous version of D flip flops but not for the asynchronous one. The
D flip flop has two inputs, data and clock input which controls the flip flop. When clock input is
high, the data is transferred to the output of the flip flop and when the clock input is low, the
output of the flip flop is held in its previous state.

Verilog Code:

module D_FFF(Q,D,clk,reset);
input D;
input clk;
input reset;
output reg Q;
 always @(posedge clk or posedge reset)
begin
if (reset == 1'b1 )
Q <= 1'b0;
else
Q <= D;
end
endmodule

Test Bench:

initial
begin
clk = 1'b0;
forever #20 clk =~clk ;
end

initial
begin
reset = 1'b1;#100;
reset = 1'b0;#100;
D = 1'b0;#100;
D = 1'b1;#100;

end
endmodule
 Experiment-7

Aim: Given a 4-variable logic expression, simplify it using appropriate technique and simulate
the same using basic gates.

Theory: There are two 4-variable logic expression has implemented. Four variables are a, b, c,
and d. First logic expression is f = a’c’+bd’+ad. Second logic expression is f =
a’d’+b’d’+ab’c.

1. f = a’c’+bd’+ad

Truth Table:

K-map:

Verilog code:

module rk_4_var_logic(input a, b, c, d, output f);

assign f= (~a & ~c) | (b & ~d) | (a & d);
endmodule

Test bench:

a = 0;b = 0;c = 0;d = 0; #50;

a = 0;b = 0;c = 0;d = 1; #50;
a = 0;b = 0;c = 1;d = 0; #50;
a = 0;b = 0;c = 1;d = 1; #50;
 a = 0;b = 1;c = 0;d = 0; #50;
a = 0;b = 1;c = 0;d = 1; #50;
a = 0;b = 1;c = 1;d = 0; #50;
a = 0;b = 1;c = 1;d = 1; #50;

a = 1;b = 0;c = 0;d = 0; #50;

a = 1;b = 0;c = 0;d = 1; #50;
a = 1;b = 0;c = 1;d = 0; #50;
a = 1;b = 0;c = 1;d = 1; #50;

a = 1;b = 1;c = 0;d = 0; #50;

a = 1;b = 0;c = 1;d = 1; #50;
a = 1;b = 1;c = 0;d = 0; #50;
a = 1;b = 1;c = 1;d = 1; #50;

2. f = a’d’+b’d’+ab’c

Truth Table:

K-map:

Verilog code:

module rk_4_var_logic_ex2(a,b,c,d,f);
input a,b,c,d;
output f;
assign f= (~a&~d) | (~b&~d) | (a&~b&c);
endmodule
Test bench:
a = 0;b = 0;c = 0;d = 0; #50;
a = 0;b = 0;c = 0;d = 1; #50;
a = 0;b = 0;c = 1;d = 0; #50;
a = 0;b = 0;c = 1;d = 1; #50;

a = 0;b = 1;c = 0;d = 0; #50;

a = 0;b = 1;c = 0;d = 1; #50;
a = 0;b = 1;c = 1;d = 0; #50;
a = 0;b = 1;c = 1;d = 1; #50;

a = 1;b = 0;c = 0;d = 0; #50;

a = 1;b = 0;c = 0;d = 1; #50;
a = 1;b = 0;c = 1;d = 0; #50;
a = 1;b = 0;c = 1;d = 1; #50;

a = 1;b = 1;c = 0;d = 0; #50;

a = 1;b = 0;c = 1;d = 1; #50;
a = 1;b = 1;c = 0;d = 0; #50;
a = 1;b = 1;c = 1;d = 1; #50;
 Experiment-8

Aim: Design a 4 bit full adder and subtractor and simulate the same using basic gates.

Theory: A Binary Adder-Subtractor is capable of both the addition and subtraction of binary
numbers in one circuit itself. The operation is performed depending on the binary value the
control signal holds. It is one of the components of the ALU (Arithmetic Logic Unit).

4-Bit Adder: A 4-bit full adder is a combinational circuit that performs addition of two 4-bit
binary numbers, along with a carry input from the previous bit. It produces a 4-bit sum and a
carry output. The truth table for a full adder is as follows:

Verilog code: 4-Bit Adder

module adder_4bit(output [3:0]sum,output cout,input [3:0]a,b);

wire c1,c2,c3,c4;
full_3 ad0( .a(a[0]), .b(b[0]), .cin(0), .s(sum[0]), .cout(c1));
full_3 ad1( .a(a[1]), .b(b[1]), .cin(c1), .s(sum[1]), .cout(c2));
full_3 ad2( .a(a[2]), .b(b[2]), .cin(c2), .s(sum[2]), .cout(c3));
full_3 ad3( .a(a[3]), .b(b[3]), .cin(c3), .s(sum[3]), .cout(c4));
assign cout = c4;
endmodule
module full_3(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s = a^b^cin;
assign cout = (a&b)|(b&cin)|(a&cin);
endmodule

Test bench:

initial begin
// Initialize Inputs
a = 4'b0000;b = 4'b0001;#100;
a = 4'b0001;b = 4'b0001;#100;
a = 4'b0010;b = 4'b0001;#100;
a = 4'b0100;b = 4'b0101;#100;
a = 4'b1100;b = 4'b1101;#100;
// Wait 100 ns for global reset to finish

// Add stimulus here

end

4-Bit Subtractor: A 4-bit full subtractor is a combinational circuit that performs subtraction of
two 4-bit binary numbers. It takes two 4-bit inputs (minuend and subtrahend) and a borrow
input from the previous lower significant bit. It produces a 4-bit difference and a borrow
output. The truth table for a 4-bit full subtractor is as follows:

Verilog code: 4-Bit Subtractor

module rk_subtractor_4bit(output [3:0]diff,output bout,input [3:0]a,b);

wire c1,c2,c3,c4;
sub_3 sb0( .a(a[0]), .b(b[0]), .bin(0), .d(diff[0]), .bout(c1));
sub_3 sb1( .a(a[1]), .b(b[1]), .bin(c1), .d(diff[1]), .bout(c2));
sub_3 sb2( .a(a[2]), .b(b[2]), .bin(c2), .d(diff[2]), .bout(c3));
sub_3 sb3( .a(a[3]), .b(b[3]), .bin(c3), .d(diff[3]), .bout(c4));
assign bout = c4;
endmodule
module sub_3(a,b,bin,d,bout);
input a,b,bin;
output d,bout;
assign d = a^b^bin;
assign bout = (~a&b) | (~(a^b) & bin);
endmodule

Testbench

initial begin
// Initialize Inputs
a = 4'b1100; b = 4'b0101;#100
a = 4'b1100; b = 4'b0111;#100
a = 4'b0010; b = 4'b0011;#100
// Wait 100 ns for global reset to finish
#100;

end
Experiment-9