Author : ABHAY KUMAR SINGH

 Instruction is a command to the processor to perform a given

task on specified data.
 A computer performs tasks on the basis of the instruction
provided.  Instructions specify one operand.
 Instruction format :  The operation is performed between the operand and an
1. Opcode specifies the operation to be performed. implicit accumulator or register.
2. Operand specifies that data to be operated upon .
Example : X=(A+B* (C+D)
3. The Mode specifies how the operand will be located.
LOAD A AC = M[A]
ADD B AC = AC + M[B]
T s of operation performed by STORE T M[T] = AC
 Data transfers between memory and CPU registers . LOAD C AC = M[C]
 Arithmetic and logic operation on data . ADD D AC = AC + M[D]
 Program sequencing and control :manage the execution of MUL T AC = AC * M[T]
instructions in a program STORE X M[X] = AC
 I/O transfers
 stack is the zero addressing instruction
Example  Stack organized computer does not use an address field for the
instructions ADD and MULL .
ADD R1, R2, R3
ADD is the opcode Example : X=(A+B* (C+D)
R1, R2 , R3 is the register or operand where the data for the
operation is stored PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
1.
PUSH D TOP = D
 Instructions specify three operands.
ADD TOP = C+D
 The operation is performed between the two source operands,
MUL TOP = (C+D)*(A+B)
and the result is stored in the destination operand.
POP X M[X] = TOP
Example : X=(A+B* (C+D)
Numarical : Evaluate arithmetic statement X=(A+B*
(C+D) using a general register computer with three ,
ADD R1, A, B R1 = M[A] + M[B] two , one address instruction format a program to
evaluate the expression
ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

 Instruction cycle is a complete process of instruction
2. execution .
 Instructions specify two operands.  It is a basic operational process of a computer .
 The operation is performed between the two explicitly  Instruction cycle is divided into three sub cycles :
specified operands, and the result is stored in one of the
operands.  The CPU retrieves the next instruction from memory.
 Address is determined by the Program Counter (PC) register.
Example : X=(A+B* (C+D)
 The fetched instruction is analyzed to identify the operation
and operands.
MOV R1, A R1 = M[A]  Opcode (operation code) and addressing modes are
determined.
ADD R1, B R1 = R1 + M[B]
 The CPU carries out the operation specified by the instruction.
 Involves arithmetic, logical operations, data movement, or
MOV R2, C R2 = M[C] control transfers

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1
  Microoperations are elementary operations that manipulate
data stored in registers or perform control operations within
the CPU.

 Involve the transfer of data between registers.

 Examples: Load, Store, Transfer, Exchange.

 Involve arithmetic operations on data in registers.

 Examples: Add, Subtract, Increment, Decrement.

 Involve logical operations on data in registers.

 Examples: AND, OR, NOT, XOR.

 Involve shifting the bits of data within registers.

 Examples: Shift Left, Shift Right.


 Shift microoperations involve moving the bits of a binary

number to the left or right within a register. There are two
main types of shift operations: logical shifts , arithmetic shifts ,
circular shifts

Left Logical Shift (LSL):

 Control unit consists of :  In a left logical shift, zeros are shifted into the vacated bit
1. Instruction register positions on the right, and the leftmost bits are shifted
2. Number of control logic gates out.
3. Two decoders  Example: If 110110 is left logically shifted by 2 positions,
4. 4-bit sequence counter the result is 011000.
 The instruction is fetched from memory and stored in the
Right Logical Shift (LSR):
Instruction Register (IR).
 In a right logical shift, zeros are shifted into the vacated
 IR is divided into I bit, opcode, and operand (address part).
bit positions on the left, and the rightmost bits are shifted
 The first 12 bits (0-11) are sent to control logic gates.
out.
 Process the first 12 bits to perform specific operations.
Example: If 110110 is right logically shifted by 2 positions,
 Opcode bits (12-14) are decoded using a 3x8 decoder.
the result is 001101.
 Produces eight outputs (D0 through D7) for control logic.
 The last bit (15) of IR is transferred as an addressing mode.
 Sequence Counter Counts from 0 to 15 in binary. Left Arithmetic Shift (ASL):
 Output is decoded into 16 timing pulses (T0 through T15).  In a left arithmetic shift, the bits are shifted to the left,
 Control of Sequence Counter Can be incremented by the INR and the vacated bit positions on the right are filled with
input. the sign bit (the leftmost bit).
 Can be cleared by the CLR input synchronously. Example:If 110110 is left arithmetic shifted by 2 positions,
the result is 011000.
Right Arithmetic Shift (ASR):
 In a right arithmetic shift, the bits are shifted to the right,
and the vacated bit positions on the left are filled with the
sign bit (the leftmost bit).
Example: If 110110 is right arithmetic shifted by 2 positions,
the result is 111101.

Circular Left Shift :

 each bit is shifted to the left by the specified number of
positions. The bits that are shifted out on the left re-enter
from the right.
Example: If 110110 is Left Circular shifted by 2 positions,
the result is 011011.
Circular Right Shift :
 each bit is shifted to the right by the specified number of
positions. The bits that are shifted out on the right re-
enter from the left.
Example: If 110110 is right Circular shifted by 2 positions,
the result is 101101.

 CISC stands for Complex Instruction Set Computer.

 It features a complex instruction set, encompassing a wide
range of operations.
 CISC instructions have a variable-length format.
 The execution of instructions in CISC architectures may take a
varying number of clock cycles.
 CISC processors allow direct manipulation of operands residing
in memory.
 This supports versatile data handling capabilities.
 CISC architectures aim to simplify the compiler's task.
 CISC architectures support a diverse set of instructions,
including arithmetic, memory access, and complex data
manipulation operations.  Pipelining involves breaking down a sequential process into
 Microprogrammed control is used in cisc smaller sub-operations.
 Each sub-operation is executed in its own segment.
Example : MULADD R4, R1, R2, R3  All segments run in parallel with each other, facilitating
concurrent processing.
 Operations are organized in a way that facilitates concurrent
execution, leading to overall time savings.
 100-250 instructions in the set.
 Pipelining is like optimizing a production line for efficiency in
 Inclusion of infrequently used specialized tasks.
assembling a product.
 5-20 diverse addressing modes.
 Creates and organizes a pipeline of instructions for the
 Variable-length instruction formats.
processor to execute in parallel.
 Emphasis on manipulating operands in memory.
 Enables parallel processing of multiple instructions, enhancing
overall performance.

 RISC stands for Reduced Instruction Set Computer.

An instruction pipeline has five stages:
 Fixed-length instruction formats for simplicity.
 Data is stored in processor registers for computations.
 IF: Instruction Fetch
 Results are transferred to memory using store instructions.
 ID: Instruction Decode
 All instructions in RISC have simple register addressing.
 OF: Operand Fetch
 A limited number of addressing modes are used.
 IE: Instruction Execute
 CISC architectures aim to simplify the processor’s task.
 OS: Operand Store
 RISC architectures typically have a large number of registers in
the processor unit.
 Hardwired control is used in risc

Example :
LDA R1, 1000(R2)
ADD R3, R1, R2

 Limited instruction set, often around 50-100 instructions.

 Predominance of simple instructions with uniform execution
time.
 Minimal addressing modes, typically 3-5 modes.
 Fixed-length instruction formats for simplicity.
 Emphasis on register-to-register operations, reducing memory
access.

1.
 Designed for high-speed floating-point arithmetic operations,
including addition, multiplication, and division.
 Multiple arithmetic logic units (ALUs) are integrated into the
system to perform parallel computation in various data formats.
 This type of pipelining is particularly effective in scenarios  Signal Generator: It is a combinational circuit that generates
where a significant number of arithmetic calculations need to the control signals depending upon their input.
be performed rapidly.  Clock: The clock implement in the control circuitry is such that
it completes one clock cycle for each step of instruction
 Overlaps the execution of multiple instructions to improve execution.
throughput and efficiency.  External Inputs: The external input component acknowledges
 The execution of one instruction is overlapped with the the control circuitry about the external signal such as interrupts.
execution of the subsequent instruction. It is also known as  Conditional signal : These components help the control unit in
"instruction lookahead." generating the control signals for branching instructions.
 Instruction pipelining is a common technique in modern
processors to enhance overall instruction execution speed by There are four simplified and systematic methods
breaking down the instruction processing into stages. for the design method :
 State table method or one-hot method .
 Processors are pipelined to handle the same data stream.  Delay element method
 The data stream is initially processed by the first processor,  Sequence counter method
and the result is stored in memory. The subsequent processors  PLA method
access and refine the result obtained by the previous processor.
 This type of pipelining is often used in scenarios where
different processors specialize in different aspects of data
processing, and the output of one processor becomes the input  It is a component within a computer's central processing unit
for the next. (CPU) that uses microcode to control and execute instructions.

 It is a controller as a sequential logic circuit or a finite state

machine that generates a sequence of control signals in
response to the externally supplied instruction
 Control logic is implemented with gates, flip-flop , decoders ,
and other digital circuits .
 A hardwired control requires changes in the wiring among the
various components if the design has to be modified or  Sequence of control signals to be generated by the controller
changed can be stored in a special ROM also called Control MEMORY .
 Each step in this sequence is completed in one clock cycle.  Memory control word is written for each micro-operation and
 A counter may be used to keep the track of control steps . these control words are stored in a serial ascending memory
location .
 Control word is accessed serially from the control memory .
 Control words are stored in the ROM permanently .
 The output of the control memory provides the required
control signals .
 If the control memory is sequentially accessed by incrementing
control memory location . then the sequence of control signals
stored in successive word of ROM can be generated.

 Instruction Register: The instruction fetched from the main

memory is placed in the instruction register and the instruction
remains there till its execution is completed.
 Instruction Decoder: The instruction decoder interprets the
opcode and the addressing mode from the instruction register
and determines what actions have to be taken.
 Step Counter: Tracks progress in instruction execution.
It Specifies the current step among instruction fetch,
decode, operand fetch, execute, and operand store.