6.2 PROGRAMMABLE INTERRUPT CONTROLLER 8259A The processor 8085 had five hardware interrupt pins. Out of these five interrupt pins, four pins were allotted fixed vector addresses but the pin INTR was not allotted any vector address, rather an external device was supposed to hand over the type of the interrupt, i.e. (Type 0 to 7 for RSTO to RST7), to the microprocessor. The microprocessor then gets this type and derives the interrupt vector address from that. Consider an ap- plication, where a number of I/O devices connected with a CPU desire to transfer data using interrupt driven data transfer mode, In these types of applications, more number of interrupt pins are required than available in a typical microprocessor. Moreover, in these multiple interrupt systems, the processor will have to take care of the priorities for the interrupts, simultaneously occurring at the interrupt request pins. To overcome all these difficulties, we require a programmable interrupt controller which is able to handle a number of interrupts at a time. This controller takes care of a number of simultaneously appearing interrupt requests along with their types and priorities. This relieves the processor from all these tasks. The program- mable interrupt controller 8259A from Intel is one such device. Its predecessor 8259 was designed to operate only with 8-bit processors like 8085. A modified version, $259A was later introduced that is compatible with 8-bit as well as 16-bit processors. 6.2.1 Architecture and Signal Descriptions of 8259A The architectural block diagram of 8259A is shown in Fig. 6.12. The functional explanation of each block is given in the following text in brief: Interrupt Request Register (IRR) The interrupts at IRQ input lines are handled by Interrupt Request Reg- ister internally. IRR stores all the interrupt requests in it in order to serve them one by one on the priority basis. In-Service Register (ISR) This stores all the interrupt requests those are being served, ic, ISR keeps a track of the requests being served. Priority Resolver This unit determines the priorities of the interrupt requests appearing simultane- ously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR, has the highest priority while the IR, has the lowest one, normally in fixed priority mode. The priorities however may be altered by programming the 8259A in rotating priority mode. Interrupt Mask Register (IMR) This register stores the bits required to mask the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver. Interrupt Control Logic This block manages the interrupt and the interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.ina INT Control Logic Ro : Interrupt sortie Priority Request Ri Register Resolver Reg. : (RR) | | Lor, CASI —~) Cascade CAS; Buffer! |«— comparator CAS, —>| Interrupt Mask ft —— Register IMR Internal Bus Fig.6.12 82594 Block Diagram Data Bus Buffer — This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words, status and vector information pass through data buffer during read or write operations. Read/Write Control Logic This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus. Cascade Buffer/Comparator This block stores and compares the [Ds of all the 8259As used in the system. The three /O pins CASO-2 are outputs when the 8259A is used as a master. The same pins act as inputs when the 8259A is in the slave mode. The 8259A in the master mode, sends the ID of the interrupting slave device on these lines. The slave thus selected, will send bus during the next INTA. pulse. Figure 6.13. shows the pin configuration of 8259A, followed by their functional description of each of the signals in brief. pre-programmed vector address on the data €S This is an active-low chip select signal for enabling RD and WR operations of 8259. INTA function is independent of CS, WR This pin is an active-low write enable input to 8259A.. This enables it to accept command words from CPU, RD This is an active-low read enable input to 8259A.. A low on this line enables 8259A to release status conto the data bus of CPU.D,=D, These pins form a bidirectional Minimum mode data bus that carries 8-bit dataeither to control. word or from status word registers. This also GS [| 1 287) Vee carries interrupt vector information. me? 27h] A CAS)-CAS, Cascade Lines A singke 0 (| 26 [7] INTA 8259A provides eight vectored interrupts. If Or [| 4 25) Ry more interrupts are required, the 8259A isused —-p, -| 5 24 IRs in the cascade mode in which a master 8259A along with cight slaves 8259A can provide up - [| 6 237] IRs to 64 vectored interrupt lines. These three lines & Cj7 22 [_) IRy act as select lines for addressing the slaves, [| g 82508 21) iR 8259A. b Cs 20 [7] Re PS/EN This pin is a dual purpose pin. 0, Cj 10 19 [7] IR, When the chip is used in buffered mode, itean oy [| 44 18|5) IR be used as a buffer enable to control buffer tran- = cA sreceivers. If this is not used in buffered mode CASe CL] 12 ve wt then the pin is used as input to designate whether CAS: [—] 13 167] SPIEN the chip is used as a master (SP = 1) oraslave GNO [—] 14 15[7) cas2 (EN =), Fig.6.13 8259 Pin Diagram INT This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU and is connected to the interrupt input of CPU IRo-IR;(Interrupt requests) These pins act as inputs to accept interrupt requests to the CPU. In the edge triggered mode, an interrupt service is requested by raising an IR pin from a low to a high state. It is held high until it is acknowledged, and just by latching it to high level, if used in the level triggered mode INTA (Interrupt acknowledge) This pinis an input used to strobe-in 8259A interrupt vector data on to the data bus. In conjunction with CS, WR, and RD pins, this selects the different operations like, writing command words, reading status word, etc. The device 8259A can be interfaced with any CPU using either polling or interrupt. In polling, the CPU keeps on checking each peripheral device in sequence to ascertain if it requires any service from the CPU. If any such service request is noticed, the CPU serves the request and then goes on to the next device in sequence. After all the peripheral devices are scanned as above the CPU again starts from the first device. This type of system operation results in the reduction of processing speed because most of the CPU time is consumed in polling the peripheral devices. In the interrupt driven method, the CPU performs the main processing task tll itis interrupted by a service requesting peripheral device. The net processing speed of these type of systems is high because the CPU serves the peripheral only if it receives the interrupt request. If more than one interrupt requests are received at a time, all the requesting peripherals are served one by one on priority basis. This method of interfacing may require additional hardware if number of peripherals to be interfaced is more than the interrupt pins available with the CPU.6.2.2 Interrupt Sequence in an 8086 System The interrupt sequence in an $086-8259A system is described as follows: 1. One or more IR lines are raised high that set corre- sponding IRR bits. 2, 8259A resolves priority and sends an INT signal to CPU. __ 3. The CPU acknowledges with INTA pulse, 4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive data bus during this period. _ 5, The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to data bus from where it is read by the CPU. 6. This completes the interrupt cycle. The ISR bitis reset at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine. 6.2.4 Operating Modes of 8259 The different modes of operation of 8259 can be programmed by setting or resting the appropriate bits of the ICWs or OCWs as discussed previously. The different modes of operation of 8259A are explained in the following text: Fully Nested Mode This is the default mode of operation of 8259A. IR, has the highest priority and IR, has the lowest one. When interrupt requests are noticed, the highest priority request amongst them is de- termined and the vector is placed on the data bus. The corresponding bit of ISR is set and remains set till the microprocessor issues an EOI command just before returning from the service routine or the AEOT bit is set. If the ISR (In Service) bit is set, all the same or lower priority interrupts are inhibited but higher levels will generate an interrupt, that will be acknowledged only if the microprocessor’s Interrupt enable Flag (IF) is set. The priorities can afterwards be changed by programming the rotating priority modes. End of Interrupt (EOI) The ISR bit can be reset either with AEOI bit of ICW, or by EOI command, issued before returning from the interrupt service routine, There are two types of EOI commands specific and non-specific. When 8259A is operated in the modes that preserve fully nested structure, it can determine which ISR bit is to be reset on EOL. When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR bit out of those already set. When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to determine the last level acknowledged. In this case a specific EOI command is issued to reset a particular ISR bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-specific EOI of 8259A, if itis in special mask mode. Automatic Rotation This is used in the applications where all the interrupting devices are of equal priority. In this mode, an Interrupt Request (IR) level receives lowest priority after it is served while the next device to be served gets the highest priority in sequence. Once all the devices are served like this, the first device again receives highest priority.Automatic EO] Mode Till AEOI=1 in ICW,, the 8259A operates in AEOI mode. In this mode, the 8259A performs a non-specific EOI operation at the trailing edge of the last INTA_ pulse automatically. This mode should be used only when a nested multilevel interrupt structure is not required with a single 8259A. Specific Rotation —_In this mode a bottom priority level can be selected, using Ly, Ly and Ly in OCW, and R= I, SL= 1, EOI= 0. The selected bottom priority fixes other priorities. If IRs is selected as a bottom priority, then IR will have least priority and IR, will have a next higher priority. Thus IR, will have the high- est priority. These priorities can be changed during an EOI command by programming the rotate on specific EOI command in OCW). Special Mask Mode _ In the special mask mode, when a mask bit is set in OCW, it inhibits further inter- rupts at that level and enables interrupt from other levels, which are not masked, Edge and Level Triggered Mode This mode decides whether the interrupt should be edge trig- gered or level triggered. If bit LTIM of ICW, = 0, they are edge triggered, otherwise the interrupts are level triggered. Reading 8259 Status The status of the intemal registers of 82594 can be read using this mode. The OCW, is used to read IRR and ISR while OCW, is used to read IMR. Reading is possible only in no polled mode. Poll Command __In the polled mode of operation, the INT output of 8259A is neglected, though it functions normally, by not connecting INT output or by masking INT input of the microprocessor. The poll mode is entered by setting P= 1 in OCW . The 82594 is polled by using software execution by microproces- sor instead of the requests on INT input, The 8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there is a request. The priority level is read and a data word is placed on to data bus, after RD is activated. The data word is shown in Fig. 6.19. Dy Ds Ds De Ds D2 2, Do blow) x | xe) x | we] wy | Wo tt FT Binary code L___,. w=4, mere isan ot highest priory interrupt level Fig. 6.19 Data Word of 8259A poll command may give you more than 64 priority levels. Note that this has nothing to do with the 8086 interrupt structure and the interrupt priorities. Special Fully Nested Mode — This mode is used in more complicated systems, where cascading is used and the priority has to be programmed in the master using ICW,. This is somewhat similar to the normal nested mode. In this mode, when an interrupt request from a certain slave is in service, this slave can further send requests to the master, if the requesting device connected to the slave has higher priority than the one .g currently served. In this mode, the master interrupts the CPU only when the interrupting device has a higher of the same priority than the one currently being served. In normal mode, other requests than the one being served are masked out. When entering the interrupt service routine the software has to check whether this is the only request from the slave. This is done by sending a non-specific EOI command to the slave and then reading its ISR and checking for zero. If its zero, a non-specific EOI can be sent to the master, otherwise no EOI should be sent. This mode is important, since in the absence of this mode, the slave would interrupt the master only once and hence the priorities of the slave inputs would have been disturbed. Buffered Mode = When the 8259A is used in the systems in which bus driving buffers are used on data buses (c.g. cascade systems), the problem of enabling the buffers arises. The 8259A sends a buffer enable signal on §P/EN pin, whenever data is placed on the bus. Cascade Mode The 8259A can be connected in a system containing one master and eight slaves (maximum) to handle upto 64 priority levels. The master controls the slaves using CASg~CAS, which act as chip select inputs (encoded) for slaves. In this mode, the slave INT outputs are connected with master IR inputs. When a slave request line is activated and acknowledged, the master will enable the slave to release the vector address during the second pulse of INTA sequence. The cascade lines are normally low and contain slave address codes from the trailing edge of the first INTA pulse to the trailing edge of the second INTA pulse. Each 8259A in the system must be separately initialized and programmed to work in differ- ent modes. The EOI command must be issued twice, one for master and the other for the slave. A separate address decoder is used to activate the chip select line of each 8259A. Figure 6.20 shows the details of the circuit connections of 8259As in cascade scheme.