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/ 15
Hazards, Critical Races, and Metastability
Stephen H. Unger, Fellow, JEEE
Absiract—The various mode of falure of asynchronous se
qventat loge ciecults due te timing problems are considered.
‘Fie are hazards, erlcal races and_ metastable state Tt i
shown that thee l' mechanioes common to all Torms of hazards
inate metartabie sates A similar mechanism, with added com
‘leations, tx shown to characterize critical race Means for de-
Fenting various types ef hazards ad eral roees through the use
cTomided delay constrains are ltroduced. A. method Is de-
Seria for determining trom ow table siunons in whi
tnetartable states may be entered. A circuit technique ls presented
{Br extending = previousty knows technique for defeating metas
ity problems in sified system Ts sewn thatthe use of
Simulation for verifying the correcines of s circa with #0
Index Terms—Asynchronvus, critical race, delay dynamic
hazards, esental Aazards, inertial delays, pare
teinys Sequentia logis ming problems, ing seelaton
1. etRopUuCTION
COMBINATIONAL logic circuits can operate correctly in the
tease that theic steady state outputs are correct, while
generating spurious pulses, often termed glitches, when the
input siaes change. If, depending on the values of relative
delays along varioes paths, such behavior is possible, then We
say that there sre combinational hazards inthe design. A baz=
ard is manffesed, in the operation of a physical instance of
fuch a clout, if glitch actually occurs. A particalar cicult
with hazards may consistently manifest them, or occasionally
the hazards may be manifested (depending peshaps on variable
factors such as temperature or power supply voltages that can
‘cause delay magnitudes to fuctuate), oF the delays may be 30
‘elated that, forthe inpat state changes that oceur in practice,
the hazards are never manifested. In some situnions these
transients are of no consequence, as is the ease for some cir
cuits embedded in synchronous systems. But offen they can
lead to significant malfunctions, for example where the combi-
national logic generates signals controling intemal variables
‘of sequential ciuit, in which case the transient errors may be
‘converied into steady-state errors.
‘Combinational hazards are classified as either static or dy-
namic, depending upon whether the output is specified to remain
‘constant after the input change, or fo change, respectively. A
State I-hazard is one where te output bot: before and after the
{input change is euppored to remain constant at | and a negative
going pulse may be generated. Stale O-hazards are unalogously
defined where te ouput is supposed to remain constant at O. A
‘dynamic hazard is one Where a gllich may appear prior © an
‘utp change from 0 to | or from | 100,
His well known [6], (26] that combinational logic functions
can always be realized with circuits that have no hazards for
siagle-input-ehange (SIC) operntion. Stated in another way.
‘combinational hazards for SIC operation can always be elimi
‘ated. When more than one input may be changed simulkane~
‘ously, ie, for multiple-nput-change (MIC) operation, certain
bhazards, called fancrion hazards, are inevitable {6} I there is
hazard in a circuit thar is not a function hazard (ie. the fime=
tion can be realized without this hazard), thea itis a character
‘stl ofthe logic design, and is refered to asa fogic hazard
"Where tf not possible oF not desirable 10 eliminate haz~
and by means of logic design, it may be possible to defer it,
that isto prevert it from being manifested. This can be done
by ensuring that the delays along certain critical paths are not
0 relaied as to cause the glitches to oceur. Another way 10
deal with hazards is to allow them to be manifested, but to
filter them out tough the use of inertial delays of sufficient
rmagnitade to suppress the glitzbes. Coping with them in this
‘way is usually considered to be a last resort since may be
costly and may significantly slow down clrcuit operation,
‘in many cases, defeating hazards is not feasible because it
ray necessiate guaranteeing that the delays along two (oF
‘more) different paths be constrained to differ by no tore than
‘some very small amount. This is generally not achievable, On
‘constraints
bounded below by the maximum delay along another path. In
some cases, particularly where only certain input changes are
‘possible, one-sided constrains may be sufficient.
(Other types of timing malfunctions are endemic to sequen-
tial eirouls Ifa sequential function is realized by a circuit with
more than one intemal variable, and if, for certain situations,
fan intemal state change entails the simultaneous change of
‘more than one state variable, then this Is ealled a race condi
tion, IF the stable state ultimately reached depends on the out-
ome of the ace, then itis refered to a8 a critical race. Gen
rally we would consider critical races as being design defects,
ince iti difficalt to control path delays £0 as 10 ensure par
fieular outcomes of races. It is always possible to eliminate
cntical races by appropriate choices of state assignments
“Fixing” races by meant of one-sided constraint, on path der
lay values, is sometimes an acceptable option.
‘Another class of timing problems in sequential circuits art
those arising from situations where, if cireuit delays are suck
that an internal state change resulting from an input change &
perceived somewhere in the cicuit as having occured befort
fhe precipitating input change, then the system generates mf
oo18-s3400ss04000 19 WOR: HAZARDS, CRITICAL RACES, AND METASTAMILITY
‘usput glitch or goes to the wrong intemal staté. When such
‘behavior is inherent inthe function being realized, we say that
the function has ar essential hazard If the resulting walfunc-
jon is an output glitch, then it isa transient essential hazard. If
the system might wind u
problem is designated as steady state essential hazard. Both
‘delay constrains. In particular, delays in the intemal variable
tranches (j-branches) will always do the job [25
‘Nocmally, we expect that, except during very brief,
‘bounded, time intervals, each of the intemal variables of 3
sequential circuit has one of te valucs (usually designated as
(or 1). However, under certain conditions, any nontrivial se-
1, and is negative if
the first change is 1 —» 0.) The width of the pulse is the time
interval between the changes. If his interval is short, we would
say we have here a short pulse. In any real circuit, there exists
‘atime vate such that ithe width of short ple is below that
‘value, the pulse will defiaizely be ignored, due to the inertial
[properties of real systems, Ifthe width is increased from this
‘vale, the pulse is marginally recognized, inthe sense that it
‘may or may not have an effect at differnt gate inputs. Finally,
if the pulse wideh exceeds some larger vale, then it will
definitely be recognized by the circuit. A pulse whose wid is
im the marginal range, is referred to as a runt pulse. (Pulse
ample js also at factor here. Runthood is in general a prop-
‘ery of both width and amplitude, the basic idea being that
runt pulse is a pulse whose existence is marpinal) As is shown
late, runt pulses are related to metastability.
All of these timing problems are particularly important in
Lunclocked, or slftimed, systems where, especially on control
‘ices, all wanstions, at any time, may be considered signif-
‘cant. in such systems, even those termed “delay insensitive,” it
{s necessary to pay atenton to delays along certain paths. This
{is because, even in the absence of essential hazards (discussed.
below), a circuit module must indicate to its environment when
{tis ready for input changes. Such signals are meaningless if|
there ae arbitrarily large delays on certain internal paths. Re
lated 10 this isthe concept of isochronic forks, diseussed by
Manin [14], and by Brzozowski [5]. OF course, where un-
clocked systems use "delay bundling” (see for example the
‘ork of Sutherland (24]) attention must be paid to delay val-
us in virtually all paths. Hence, the methods presented i this
paper for coping with various timing problems by controling
‘lative delays along ceriin circuit paths does not constitte
the inteduetion ofan otherwise unecessary typeof constraint
‘on the design of such systems "Bea
‘An objective of this paper ist show how a particular cit-
cit festire, namely the possibility of » gate receiving cone:
‘iciory signals simultaneously on diffrent inputs, is common
to al ofthe Uming problems mentioned above, It ale stows
thatthe various problems may be uosly viewed tom difer
ent vanuage points: boolean logic expression, Kamaugh maps,
flow tables, and logic circuit diagrams. Tht is Helpful in en-
haveing our understanding ofthe mechanisms involved, deat
fing problem trnations, and devising means to eliminate
‘defeat problems. Techuijees are prsescd for defeting any
dynamic hazard and many critical races with one-sided delay
consains.A simple procedate is described for determining
by inepection ofa flow table is panicular input ransition can
lead to metasabiliy. A variation on a previously known eeult
technique for fikering out the effects of maetactabliy i pre=
‘seated which caa cope with ¢ broader class of problems. I is
Shown that timing simulators cannot be reid! upon to tt for
the presence of timing problems, Finally, tis demonstrated
that replacing pare delays with inertial delays ea, under or=
tain eicustances, actually intedce timing problems aot
previously prose
“The systems discussed here are assumed to be constricted
‘of AND, OR. and INVERTER gute. Extensions ofthe resus
to cover systems, including NAND and NOR gates are
sirightforvard. Delays with given upper and lower bounds,
‘te misociated with all wires. (Gate delays may be absorbed in
the delays of wines a the outputs) In orr to rp the dl
‘casions, it f asmmed that each dey is pure, and thatthe
‘delays fr rising an fling signals are the same Ie snot diff
cal to extend the reset models with mixed pure and iner-
til delays and wit cfferent delay values depending upon the
direction of a value change. Where multipe-inut-eaanges
(QdICs) re cscasse, it ssumed tht all ofthe put vari
ables involved change simultanenusly. Variations from simule
taney can easly be taken ino seount by delays inthe wires
Weeding rom the tputs
'A basic ureducton to asynchronous sequent circuits con-
sistent wits the approach taken in this poper isi (28) , and a
tmore detailed treatment of hazards and eral races can be
{ound in (26). The origins of the theory of combirationa baz
ards ace mainly in 8], (13), (6](mulipleinpet change state
‘uazard) (26), (1, 2] (muipe-inpu change dynsmic bazar)
“The basic work on critical races and state ssigament fee of
them isin (7h (121, [25]. More recent approaches t some of
thee problems ar in (11), 18}, Methods for evading the pro
lean by using locally gencmied clock pulses were itoded in
[5]. 27]. A more sophisicated approsch i (17). The origi
tte basi Meas pertaining to metasabily are in 4] (9), (19),
{22, (13} More recent work en this topic sin (10), (20)
‘Static and dynamie combinational hazards ae treated inthe
next two sections. In Sections [V and V two types of essential
Inner re shown tobe acrciated with sequent fansions that
carmot be eliminated, but which can te defeted. They are
Shown to be tclned to sinc combinational tua. Ia So
‘ion V1 i it shown that sequential dynamic hazards also exit but that these are not inherent in the functions. Metastability
treated in Sestion VIL, where iis shown that situations where it
‘can be initiated by either runt pulse inputs or the intemal genere-
tion of ran pues following multiple input changes can easily be
Ientifed fom the flow ‘able point of view. It is also shown,
there that the effects of metastabiliy can be prevented ftom
reaching outputs by a circuit filer. Citeal races are examined
fiom a crcl as well as flow table point of view in Section VII
“The resemblance, with a twist, between critical races and essea~
tial hazards is pointed out, and a technique for using one-sided
‘elay constraints that goes beyond “ficing” races is presented
that allows the we of some state assignments with erical races.
{A consequence ofthe technique for defeating dynamic hazards is
‘hown 19 Section IX to provide a counterexample to the idea that
if-a circuit works properly with some delay clemeat assigned
ther of two specifi values then it will also work forall inter-
mediate values Finally, its shown in Section X that pure delays
fre not always more toublesome than inertial delays with re-
spectto timing problems.
IL. STATIC COMBINATIONAL HAZARDS
Assume we restrict ourselves for the moment to logic cir-
cuits composed only of AND, OR and INVERTER gates. tis
noe difficult to show tha the basie model for static hazard gen
tration is the configuration shovin in Fig. 1a, for t-hazards,
‘vith the dual shown in Fig. 1b, for O-tzards. (Note that &
NANDegate could replace the OR-gate, and that « NOR-gate
could replace the AND-gate.)
et x =
Tz
(a) Vasa () o-nazard
Fig. 1 Bae mode rst aad,
In the case of a I-hazard, for example, ifthe delay through
the lower paih to the OR-gate (Fig. 1a) were sufficiently long
relative to the delay through the inverter in a particular physi~
‘al circuit, then no hazard would be manifested for a change of |
Strom I fo 0. But then, fora change of X from 0 to I the haz~
ard would defintely be manifested. The hazard would aot be
manifested for either change if the delays are so related that
the opposite changing signals arrive almost simultaneously. An
intermediate situation would be if the time interval between the
signal arivals is marginal, in which case a runt pulse might be
produced. This point will be refered to again later in the dis-
‘cussion of metastable states.
EXAMPLE I. Consider the logic function specified in the
“t-vatiable Karnaugh map shown as Fig. 2. A sumof-
produets (SOP) expression for this function is:
Z=AB+Ac+BC+BCD
“This can be factored to yield:
Z=(AsB(A+C)+8C0
o
@
{EEE TRANSACTIONS ON COMPUTERS, VOL At, NO. 5 JUNE i998
Fig 2. Karsagh map of ction
“The circuit shown as Fig. 3 comesponds to this expression.
o——, J *
[ 8
¥
Fig 3. Reaavon offi. 2 fnction
Examining the circuit inthe light of the preceding discussion,
rote that, from the A-inpxt, thee are two paths 10 AND-gale-T,
‘one with one inverter, and the other with no inverers. Both paths
Se sensitized when B = D and C = 0. Thus, under these con-
‘Grains, when A changes, there is a O-hazard at the ouput of
gate7, However, ifD = 1, this ourpur doesnot propagate tothe
Sulput Z, since Z will be held at | by the I-input from gate-6.
Bur if D'~ 0, the ouput of Z is same as that of gate-7: that is
there can be negative glitch atthe circuit output. Ths, we have
fs O-hazard when A changes while B = C~D~0.
‘An essentially equivalent process can be carried out on (2),
‘whieh mirrors the eicuit. Observing the appearance of both A
ind A in the expression, we attempt to fix the other variables
to as 10 reduce the expression to AA. This can be done by
fering B= 0 to convert the fist parenthesized subexpression
TOA, and then, setting C~0 conver the second parenthesized
Subexpression to. A. All that remains is to set D = 0 thereby
‘eliminating the BCD tem.
"A third way to arrive atthe same result is a bit different
‘Mutiiply out the product in (2), a hazard-preserving operation,
‘and do rot eliminate the resulting AA term (that would nor be
Inazard-preserving). The result is:
Z=AB+AC+BC+AA+BCD °
Setting B= C = D= 0 reduces (3) to AA again revealing the
Ochazard.
"Now consider variable B. There are two paths from B eo
‘verging at final OR-gate-f, one path with « single inverter on
it and the other with no inverters. Both paths are sensitized if
A= 0, €=0, and D = |. This corresponds to a L-hazard atthe
‘utput. The same conclusion can be reached from (2) by not
{ng that setting A = C = O and D~ I reduces that expression 10 UNGER HAZARDS, CRITICAL RACES, ANO METASTAMLITY
BoB. A diferent way wo se his, usng (3), 6 note thatthe
consensus term, betveen AB and BCD. namely ACD, is
inssing fom the expression. Thus, within the cube defined by
ACD there isa hazardous warsiton. Finally, an examination
ofthe K-map of Fig.2 shows that none ofthe chosen sububes
covers the transition under discussion (the mising cube is of
course ACD), confirming again tha thee i a I-bazard for
transitions between 0001 and O1O1. The hazard canbe clin
nated by adding to the circuit a path that corresponds to
Koo.
‘Note thatthe same techniques use to identify the azar
could be used on the O-tazid, by complementing the map,
xpressions, and crcuit (Complementing the cea would
tmean swapping AND-gaes and ORpates and complementing
All inputs) There ia aso a Ichazard for wasiions between
1001 and 101. I can be detected using the same techniques
AMustrate for the |-zard between 0001 and O10
‘Consider next a multiple inp change. Suppose that with A
and B both fixed a 0, Cand D are both changed from 0 to |
Paths from (ith one inverter) and from D (with no invert
x) converge at AND-zal-6, With B set at 0, we have the
nditions fora postive glitch atthe ouput of gate-6. With
‘A= B™0, the output of gate i 0, which forces the ouput of
tite and hence the lower input to gate‘ to be 0, so thatthe
lth ill be propagated to the output Z. This we have an
[MIC hazard for transitions between 0000 ad 0011, Note that,
‘with A™ B= 0, @) reduces to CD. This term (coresponding
to.an AND-gas) has ts two inpas changing in oppo ec:
tions when C and D both change inthe same direction. An
‘amination ofthis transition on the K-map of Fig. 2, shows
tat, between the initial and inal states ofthis transition, both
of which are O-poins of the function, tere isa minima-length
ath that passes through the point 0001, where Z'= 1. Thi is
the condition fora fiction O-bazard.
“There is no way to eliminate the function hazard. xt, a8
roted above, it can be handled in ane of two ways. One is
Simply to place an inertial delay clement a the out of gues
or gave. IF its magnitude exceeds that ofthe maximum pos-
sible width ofthe glitch, which isthe maximum difrence in
the delays along the two ertical paths, then the apurious pulse
will be filtered out. Suppose that instead of this approach,
hich delays the ciruit ouput, we atemps to defeat the haz-
ard, Leto prevent the lich from being generated. This might
te dene by ensuring that, forthe 0900 — 0011 wanson, the
signal rom C, which would fold the gate cust a0, aves
before the signal from D. which would tum om the ouput of
‘:me-6. This could be done by inserting a suficently large
‘ela clement (pure o inertia) inthe path fom D to gate,
But now observe what would happen forthe inverse transition,
‘ie, 0011 ~» 0000. Again, the effect ofthe C-chunge would
reach gate-6 before the elect ofthe D-change. The resus
thatthe ouput of inverter? goes to | before the signal fom D
toes to O 0 that dh hazard efntely manifested. Tas this
fppreach is useful only where the input sequences are re
‘ited so that such inverse pis of tensions donot occur.
for sone ectnotoges ther may be « way and this
praia Suppos tthe curt engl ees
‘ends wih lave ideo tou change fv hem Ot
(Certs lnverer ouput fal uch) we tig mock
Tongro repo tan +0 chugs nC esti nen
pet ae ow). This indeed connoponta te Wa
Dan NMOS lever. biteenes te ope ae ee ah
‘ho prodicesinlareftess) Then the ey tthe ph
fom to exe, for sgl ung bah dton, eo
Srin’"»bebeteen feo dl ales fer te ph foe
then tay be posnbl ode! the haa for oh ant
Noes. Ths apronehy which ena wo-ied Gly con
‘si, apple ald ae asad
II, DYNAMIC COMBINATIONAL HAZARDS
For input changes that cause the output of an OR-gate 10
change from 0 to 1, dynamic hazard can be generated a (as
opposed to being propagated to) the output ofthis eae, only if
| postive glitch occurs atone of its inputs and then torminates
before the arival st another input to the OR-gate of a signal
changing monotonically from 0 10 |. Such a sitution is de-
Picted in Fig. 41 gy and gy, and m are simultaneously turned
on, tien complementary input changes occur at the inputs 10
the AND-gate, which, as shown in Fig-1b, i the basic mecht-
nist for producing @ glitch atthe output of the AND-gate (the
signal labelled G). Note thet, turns on the glteh and gp turns
G off. The I-hazard is manifested if the offect of gis felt at
the AND-gute before the effect of a» The monotonically in-
czeasing signal is m. Thus, if she signal fom m arives st the
OR-gace afer. the G signal at the input t the OR-gate has
zone on and then off, we would have a spurious pulse at Z
receding the steady-state change of Z from 0 0 1
[aes
eh
Fig A Base eda for dais hares
Assume now that there is =. MIC involving m, and gy
‘The dynamic hazard would be manifested ifthe pth delays in
the circuit ae such as to cause evens to occur inthe ondee
specified above. Thai, ithe order ofthe tree input changes
vas peccived at the the inputs to the OR-gate as having been
Bs (required to produce a gltch a G), and then
‘twill now be shown tat, uli the ease of static hazards,
al dyramie hazards (both loge and funtion hzarés) can be
defeated for changes In book diets, by one-sided delay
consirains (There me actually two different sts of constrains
that can be used in each case.) Suppose that the path delays
fiom go, gs, and m tothe OR-gate inputs are respectively do.
4, and dy. Then there are two ways to defeat the dynamic ha
ard forthe case where Z isto change from 0 10 1 (i forthe
‘MIC in which all tree inputs go on), One way Isto prevent
the glitch at G from occuring. This can be done by making ‘dy > dh. The second way is to make the glitch overlap the
fuming on of m (ie, foreing the effect of the m going on to be
fet while the glitch is sil on). This will occur if o> da
"Now consider the reverse transition, Le, where all three input
variables are switched off. Now the generation of the glitch at G
is prevented if da > d), which constitutes one constraint for de-
feating the dynamic hazard. The dynamic hazard can also be
‘defeated by allowing the G glich, but overlapping it with the m-
Signal (Le, by ensuring thatthe effect of m going off is delayed
luni the effect of go going ofT is perceived by the OR-gate). This
Is achieved by imposing the constraint da > do.
"Now observe thet if dy > diy dy es do > dy and dp > dy)
then the dynamic hazard Is defeated for transitions in both di
rections. The same is true If dy «ye
“The simplest example of such a hazard is illusirated in
Fig. 5,8 SIC dynamic hazard. Here all sree of the basic inputs
are derived from the single input-variable X. Corresponding to
this circuit is the logic expression: Z= XX4X, The first X
‘symbol corresponds to gj, the second X to go the product XX
10 G, and the third X to m. The branch delays are denoted 25 =
(Gvhich includes the faverer delay), b, ¢, and d. The dynamic
hazards for changes of X in elther direction are both defeated
by the constraints 8 +d >> +4, anda + d> c, or altematively
byatd 1 MIC dynamic logic hazard for the
‘transition 1101 > 1011, Le, forthe inpat state change BLCT
when A= D~ 1. For this situation, m = C, G)=8, 9) = C,
G=BC (the output of gate 6). The hazard and the reverse,
‘hazard can both be defeated by constraining the fp path delay
to either exceed or be less than the delays in the gy and m
‘paths. For example, we could require the delays in the path
from C through gates 2 and 6 to the input of gate $ (this i the
‘ path) to exceed the delays in the path from C through gates
Sand 7 to the input of gate 8 (his isthe m path) and the delays
in the path from B through gates 1 and 6 to the input of gate 8
(Qhis is the g path). Alternatively, we could alter the above
‘constraints by replacing the phrase “to exceed” by the phrase
be less than”
‘The circuit (not shown) corresponding to Z = ABC-+ AEC
ittustrtes a dynamic function hazard for inpat changes be-
‘yween 000 and 111. The G signal is generated atthe output of,
the ABC gate, and the m signal is generated at the output of
the ABC gate, Both A and B produce go signals, C produces
the only g signal, and A, B, and C all convibute to m. If we
delay the paths from both A and B to the ABC gate by an
mount larger than the other delays, then, during the
(000 > 11 transition, tat gate wl ot tuo the gitch uni
‘er the m signal has timed on Z, which defeats the hzard for
that transition Forth revere transition, the ABC. gate will
not see the A and & signals go on until after it sees the C sig-
‘al poof. so tht no giteh is produced, therby defesting the
reverse hazard a wel
“A similar argument shows that minimizing the delays fom
‘A ind through te ABC. tale the inpot ofthe final OR-
{ll als defeat both hazards. Asa practical attr, when
this route fs chosen, the action taken would be t erase the
‘sles in cher or both of the other elvan: path. fac, he
fen seacgy might be to choose the solution that extals the
leat contin terms of delay peding.
“The above discussion easly extended to cover circuits
termiamting in AND-gates by simply using doalsrgumeats, OF
Course NAND and NOR yates are alo inclaed in tho discus
Sions of AND and OR yates respectively (Oe UU are
imply compleersed).
Tr some cases there ry te several OR-gate pats at which
CG-signale may appear, and perhaps several inp at hich
signals appear, Sufficient conditions for defeating the dy
‘Humic hazards such cass are eal specified by, for exan-
Pie, constraining dy valves for all the Osigals to exceed alld
ales und all dy values, Weaker sts of consrants may be
found in sine exten by more carefil analyses taking into a¢-
‘count various glitch overaps
“The renal ere extendhble in a straghtorward manner to
cases here the delays for rising aod fling signals ar ifer-
Sat and it makes no difference whether the crea delys ae
ure or inertial In a pariculer circuit wih several distinctly
{iterendymamie hazards there may be contradictions among
the delay constants required wo defeat certain subsets ofthese
aca
“The importance of the above result follows fom the fact
‘ht, in many case involving MIC operation, it has. been
show, by Bredeson (2), tat rat all dynamic logic bazards ea,
bochminated. Thais for some furctos, wtile any particular
‘Snanic hazard can be eliminated by 8 redealan ofthe logic
‘ents the new sire will have some other MIC hazard in
face the funtion dovribed in Fig. 2 and realized by the creat
ofFig 3 u an cxample of ach 4 fonction. This isan example
in which thee ar a numberof potental namic fgic hazards
in the fincton. Its possible t elimiate some, but not all
(without introducing static logic hazards) by logic design using
Bredeson's method: and then to defeat the est by the method
‘iscribed above. tis not clear whether this can be dove forall
finetions, In prctcal cases fi import to nderstand that,
{hc to inpu Constraint, transitions corresponding to many of
the MIC havards may never soeur, so that some hazards need
tot be daft with tal. This fase treated, for the potnt of
View of eliminding (as opposed to defeating) hazards in
sage logis cre, by Nowik and Dill (18)
IV. SequenniaL CincurTs:
"TRANSIENT ESSENTIAL HAZARDS
‘Consider next those hazards that are inherent to sequential OH: HAZARDS, CRITICAL RACES. AND METASTAMEATY
cireuts. To begin with, let us examine those hazards that are
{herent i certain sequential functions. That i, they cannot be
ciminated, although they can be defeated by suitably con-
seraining relative delays along cersain paths. The subsequent
‘iacussion is restricted fo single output-change (SOC-no out-
put signal is specified to change more than once as a result of a
Single change in any input signal) soquential functions and
‘operations are assumed to be SIC.
‘An example of such a hazard is embedded in the sequential
function described by the flow table of Fig. 68. With the given
‘encoding ofthe rows in terms ofthe single intemal variable y,
itis simple to obtain the K-maps of Fig. 6b for ¥ and Z. From
thee the logic expressions below are easily generated:
YaAy+8, Z=ABy
‘The detailed logic circuit diagram corresponding 10 the
above expressions is shown in Fig. Ge. Clearly there are no
‘ritical races or combination logic hazards (for SIC operation).
ay ERE,
(Rat ea Aa 8.BO,
Fle 5. Trnsentesentaharac
Blut now consider carefully (referring to Fig 6a) what might
hhappen when B is turned on with the system initially in the
state I-10. According to the flow table specification, the frst
‘event is state change 10 I-11, corresponding to a lateral move
{in the flow table to the frst row of the {column The ourpit
‘remains at 0, Since the next-state entry is 2, the next specified
event is a change in the internal state 10 row2, which brings
the system to state 2-11, a stable state. Note that in all threo of
the states involved in this transition, the output, Z, is specified
toremain fixed at 0,
In terms of a general block diagram that represents any cir-
cuit realizing the function, the above process begins with a
‘change at the B-input, which propagates through the logic
block to the Z- and’ Y-terminals (in general, several Y-
variables might be involved). Next, the change in the Y-
variable(s) causes a change in the corresponding y-varisble(s)
at the input end of the logic. The subsequent y-change(s) then
‘propagate through the logic again to the Z- and Y-terminals.
‘Suppose that, due to a relatively long delay in the path from
‘the Brinput fo the Z-output, the signal from the y-terminal
reaches the Z-terminal before the signal from B. Then it would
‘appear at the Z-terminal as though the intemal state change
had occured defor the inpat change that pecptte it. From
the poit of view ofthe flow table iti a ugh the vere
transition oceared before the horizontal tanstion, Les that
the sequen of states was 110, 2-10, 21. But this i te
‘ay things lok fom the 2-terminel, th out would change
tol fora brit itera dorng the transition, conespondng
the difference in arval times at Z of dhe signals fren 8 and
fiom y. This consites x spurious pole, or glitch a2. The
osibilty of such a muifunction i referred to as a onsiont
‘stertia scord Inthe cient example, the hazard woul be
‘anifexed ifthe oral path delay (see Fig. 6¢) from B to the
inpat ofthe AND-anc vi the inverter exceeds the delay in the
path fom B Yo the input ofthe ANDyate via the OR-gate
“This ope of hazard is mentioned in (26, but fot tented
detail Before analyzing this situation farther, formal dtii-
ton of transient exeatial harard x prevented below
Fit define 2, a the opt for the total ste rs, Le,
the sinte vo rows, colummc If isan inp
variable, and ifthe sable sn resched afer a single change
X withthe sate nally in stable sate oe f= and Hf the
able sate reched afer second change in X is foe, and
Par (e might be equal or) then a romsont essen hazard
xint Zin ) = 240, €) 2 20). Ths ie equvalent to say
ing tnt a tronsion essential hazard exc if for some sable
States, and for sme input variable X, the ostput ZI species
to remain unchanged when X changes once with the sytem
inially in's, bu Z is specified to change if X fe changed 8
second tine
"No change in the state assignment ofthe logic design can
climinate the possibilty ofa malfaetion if the path delays are
such ast reverse the apparent ordering of the input and inter-
nal state changes as seen at the Z-terminal. But simply inser-
‘ng a sufficiently lage delay between the Y and y terminals
oes defeat te hazard by ensuring tat no such mispereption
‘an occur anywhere inthe circu.
"Now lt us examine the situation more closely em the eit-
cuit point of view (Fig. 6, which is arranged to clarify the
Subsequent discussion). Focusing onthe par of the circuit that
fenerates 2, note that there are two path fom B to the inpuss
Of the rightmost ANDegate. One path includes aa inverter and
the other does not I we fx A a | (which isis value inthe
scenario under consideration), and fb the lower input to the
‘ORegate—which comes from y—at 0 (which i might very well
tbe during all but the very end of the scenario) then the circuit
reduces to tha of Fig. 64. This is precisely the model forthe
‘atc I-hazard shown in Fig. 26. (Ofcourse ifthe ature ofthe
fransient essential hazard was 10 produce negative glitch,
then the dual cc, Fig La, fora sate O-hazard would apply)
“The problem is also evident from an examination of the ex-
pression for Z.(.e.. ABy). The A variable is fixed at 1, reduc-
ing the expression t By, in which the B-term goes on while
the yaerm goes oft
‘From the point of view of the K-map description of the
Zefunetion Fig. 6), what "3 that a transition is
ing from the point 100 49 T11. For this MIC transition,
there ist function O-hazard. Bven though there is only a single
input change 1 the overall sequential circu, the intemal ste Prat. ie
transition introduces a second variable change, namely y. It is
waneiinetdence that the combinational hazard is a fenction
RE_Ard, since. as the previous arguments have shown, the order
Tr which the variables change determines whether or not a
pulse is produced, which is in accordance with the definition
fa function hazard,
YV. SEQUENTIAL CiRcUTTS:
[STEADY-STATE ESSENTIAL HAZARDS
'A mechanism very similar to that described in the previous
section is responsible for a related type of hazard that can
bring a circuit to the wrong stable state after certain transitions
‘The problem is illustrated in Fig. 7. A very simple sequential
functon is specified by the flow table in Fig. 7a, where a ice
fee state assignment is shown. Using this essignment, K-maps
for Y, and Yq are produced in Fig, 7b (the output Z is not
{ator in this situation). Logic expressions are:
— GBH °— 6
‘spate
Fig. 7. Rxamle of teay-suteesental ard
|A cireuit realization in standard form is shown in Fig. 7c
‘There are no race conditions (therefore no critical races) and
all logic expressions are free of hazards for SIC operation.
‘Consider now what might happen when X is tumed on with
the system initially in total state 1-0. According to the flow
fable, the total state should change from 1-0 t0 1-1 (an unstable
Sate}, and then the internal-stare should change, bringing the
Syotem to 2-1. That is, following the input-state change, there
ia an internal-state change. With the given state assignment,
following the X-change, ¥2 should change. But suppose now
that at the Yiterminal the X-change’ is perceived as having,
‘ocurred first. Then the system would appear to be ia state 2-0,
Where ¥; is supposed to change to 1. The result would be &
pulse at the Y,-terminal, which could cause the system to end
tp in state 3-1, the wrong stable state.
‘The lopic circuit has been drawn in Fig. 7e to clarify the
‘imation. From this diagram, itis clear that there are two paths
from Xt Y;_ One of these is through the inverer and the
‘AND-gate, while the other is through the Y> OR-gate and the
ANDegate. With ys Inidally 0, the lower OR-gate acts 25 =
‘tire, and we have again the situation of complementary inputs
being fed to an AND-gate, the concition for generating & tran-
sient |-pulse. The situation is very similar to that shown in
Fig 64 for the tamsient escential hazard, except that in this
‘case the glitch Is fed to the feedback circuit generating Y,
instead of directly to the output. Thus, the glitch affects 1
just the output, but also the internal stabie state. Looking at the
Capression for Yy. the problem clearly reveals itself With
¥, = 0, we have ¥; = Xyg, s0 that. when X and y, both go on.
the components of the AND-expression change in opposite
rections, thus opening the way for a spurious pulse to be
generated
fom the circuit point of view, the mechanisms for static
combinational hazards and for both transient and steady-state
Grsential hazards are the same: Signals changing in opposite
‘irections reach inputs ofa gate at abou! he same time.
"This problem is inherent in the sequential function being
realized. Such 2 steady-state essential hazard exists for any
tamition in a SOC sequential function involving a change if
fone input variable X if, stating in some siable state, a single
Change in X is specified to bring the system to a different stax
bie sate than the one specified after three changes of X. Ithas
been shown {26] that there is no way to eliminate steady-state
CSSential hazards by manipulating the state assignment or the
ircat logie. The only colttion is to defeat the hazard by con
trolling the relative delays along the critical paths. As is thi
‘cave of transient essenfial hazards, this can always be accom
plished by a delay between the Y and y nodes of thy
vevariable() that are supposed to change in the course of th
Yramition. This ensures that the precipitating input change wil
be perceived everywhere as having occurred before any resul
ing internal variable changes.
VIL. SeQueNTIAL CIRCUITS: DYNAMIC HAZARDS
‘Consider next the flow table of Fig. 8, There are no esser
tial hazards in the function described. Its a simple mater |
etive hazard-free SOP expressions for the internal varia
‘and for the output. These are:
Y=ABc+Ay,
Z= ABy+AGy.
Fig. Flow able with rt astgnment hing Seqpetl Syma has
‘There are three paths from C10 Z: A diceet path with «
inverter, corresponding to the Cin the ACy term of thy
expression, and two uninverted paths through Y, bth throt
fhe C in the ABC term of the Y expression, and then via
ttppearances of y in each of the two terms of the Z express!
‘These constitute a dynamic hazard, since they are all sensit|
wih AB | andy initially 0. The transition involved is
‘one starting in state 1-110 of the flow table, with C chant
ffom 0 10 1 Ifthe path to the y-input fo the ANDrgate ret
ing AGy has the shortest delay of the three paths, then Z 1 no CRITICAL RACES, AND METASTARILITY.
wo
ine vent events that the change in C tums off the Gin
erm ben Z goes ofT again, and remains off until the
nets through 10 tum on Z via the ABY term, What
shat uring. on C turns on Y., but the change i
Se a int by the ACY AND-pne, which sees the sys-
3 sip and therefore goes on, This same gate then sees
seo Shoe, thereby perceiving the system to be in 2-111,
ae C Vo + Va, then either there
will be no metastablity or the MSS will have terminated, and
P will quickly become 1 and Q will become 0. Transistor-n
will be tamed on, allowing Ve to fall 1o the diode threshold
voltage ss Ve, falls to 0, If metastability does occur, then while
it lasts, [Vp = Vol will remain below the threshold values of
both p and n, so that both transistors will remain cut off, leav-
‘ng Vi essentially constant at its initial value. A similar analy-
1 can be made of the situation where, i the initial state, P= |
‘and Q=0. Thus, as long as we do not allow the input sate A ~
B= |, this cireuit should eperate propery, preventing the con-
‘sequences of metastability from reaching the output Z. Note
that care must be taken in specifying the electrical parameters,
of the filter elements. It appears to be feasible to specify di-
‘odes on CMOS chips although this does not seem to be 8
‘common practice. In any event, connecting the gate terminal of
fan NMOS transistor to the drain terminal produces the anode
‘of a satisfactory diode, where the cathode is the source termi-
nal. (A similar arrangement can of course be made with a
PMOS transistor.) The operation of this filter, using such di-
‘des, has been verified by means of « SPICE simulation
‘An example of the application ofthis approach is the design
of a D-latch, shown in Fig. 10. Even ifthe setup or hold time
constraints for this latch are violated, which might lead to me
‘astability, no spurious output signals will occur at the
‘Q-ourput. The only effect of getting into a MSS is a delay st
the output of uncertain duration. This does not solve the prob-
lem for synchronous systems, but it does essentially defang
rmetastability for selftimed systems,
pe
possible to
2 0F all asyn-
| hoa
Lpof
ig. 1, Daten eh MSS ae
VII. CRITICAL RACES
‘Consider the flow table of Fig. 11 (outputs are not shown as
they play no role inthis discussion) 1f, starting in state 1-00, B
‘is tured on, then both state variables become unstable, 1,
both Yi and Y; change (in this cate to 1), If), changes firs,
then the state becomes 4-01. Since this is a stable state, the
excitation for Y; reverts 10 0. Ifthe delay in the ys-branch i
Inertial, then the ys-change is aborted and the system remains
in 4-01, Ifthe delay i that branch is pure, then, eventually yz
does change. But then, since Y; was 0 during the time that the
system was in 401, ys revers later to 0, and s0 we have oseil-
latory behavior between states 3.01 and 401. Iti also possi
ble for a runt pulse to be generated, which might take the sys=
tem into a metastable state. All of these outcomes must be fe=
garded as faulty behav
“The situation is characterized as a race condition, since sev=
eral y-variables are simultaneously changing, values. It is a
critical race, because the outcome is dependent on which
yevariable “wins the race,” ie, changes fist As was just
shown, ify; wins, then malfunctioning results. If ys wins, then
the system goes to state 2-01, where the excitations on both Ys
remain unchanged at 1, so that the correct final destination,
state 3.01, will be reached. Ifthe race ends in a draw, then the
system goes direcily to the correct final state
Fig 11. Pow able wit ste assignment istraing critical ces,
Clearly this is an undesirable situation. ‘There: are many
‘ways to generate state assignments for the flow table that are
free of critical races [26]. Since these may entail an increase in
‘circuit complexity, we might first explore the possibilities of
defeating the critical race for the given assignment. Several
‘approaches are possible. First, we might impose a one-sided
delay constraint, requiring thatthe delays in the y,-branch ex-
‘ceed those in the ybranch so as to ensure that the system
takes the path through 2-01, which leeds to the correct stable
state. Or, we could change the next-state entry in 1-01 fom 3
to 2, so thatthe logie circuitry is altered to take the system to
2-01 First. This makes the transition a two-step process. The
penalty is some slowdown in operation since there is now no
‘overlap of the time it takes to change the two state variables:
they change in strictly sequential order. Because the problem
for the transition discussed above is solvable by either of the
two methods outlined above, without changing the state as-
sigament, such a critical race is said to be removable. As is
shown nest, not al critical races can be handled so easily.
‘Still referring to Fig. 11, suppose that, again starting in state
1-00, A is tuned on instead of B. Then, once more, both
yovariables become unstable. We have another race condition,
land it is ceruinly critical, since, if yy wins, the situation is, a
Identical to the one considered previously: the system may fail
nove of three ways. But nov, even ify» wins the mace, the
Situation is essentially the same, since the Intermediate site is
2410, another rable sate. Only if both y-variables change
‘multancously would the system go te 3-10, the specified final
‘Sate. Neither of the solutions suggested for the previous «
ample are applicable. This ertical race is not removable. Of
‘course, the overall problem is solvable, namely by changing
the state assignment 10 one that is free of critieal races, but in
this ease it would be necessary to use three state variables
tig interesting to consider these situations from m circuit
point of view, Logie expressions corresponding to the given
State assignment are:
yo AB+Ay) +BY +ABs, Ys
By, + Bye + ABV + AB:
For the removable critical race transition, where A is fixed at
0, these reduce to:
Yi=B, Ye =¥2 +BY
During this process, while Y> is a function of yy. Ys is inde-
pendent of yz. The corresponding reduced circuit is shown in
Fig. 12. (Delay elements are shown between each Y.signal
‘and the corresponding y-signal. These do not necessarily rep
resent actual elements, but may simply designate inherent
‘iring delays.) Observe that y, changing 10 1 blocks ys from
changing to 1. Delaying the change of ys sufficiently gives y;
time to change and “lock up” the change via the feedback path
‘through the OR-gate
‘Note the resemblance to the corresponding circuit for
steady-state essential hazard (Fig. 7d). In both circuits there
fre two paths from the input variable to an AND-gate, one
direct and uncomplemented, and the other, through
‘Yavariable and complemented. The output of the AND-gate
feeds a second state variable. tn the essential hazard case, mal-
functioning occurs (Le., the hazard is manifested) if pulse is
teneraied at the output of the AND-gate. In the removable
Critical race ease, the absence of a sufficiently long pulse at che
‘output of the AND-gate causes malfunetioning, since the sec-
fond y-variable is supposed to be turned on and siay on. As
indicated above, by making the delay between Y, and y, suf-
ficiently long, an adequate I-pulse can be produced by the
[AND-gate thereby ensuring correct operation. In both cases, if
the logic controlling the second state variable reacts to the
change in the first y-variable before reacting to the input
Change that caused that change, then improper behavior results
(spurious y-change in the case ofthe essential hazard, and a
failure to change in the case of the critical race). Delaying the
‘change in the first y-variable by a sufficiently large amount is
ths a remedy in beth eases.
“The situation is a bit more complex with respect to nonre-
‘movable critical races. For the second critical race discussed
above, B remains fixed at O and A changes from 0 to 1. The
logic expressions are reducible 1:
AY HAT: = Als +¥e)
Yo=ve+AVs
ae
* ope {*] 4
ep
Fig. 12, Redwed crest fr aremovable ctl ae seuion
“The corresponding reduced circuit is shown in Fig. 13. Here
‘we sce that, as in the case of Fig. 12, there isan inverted and an
Iminverted path ftom the input A to AND-gate-S in the circuit
generating Y, the former path passing through ys. But there is
‘hse feedback from y; tothe ekcuit generating Y, and there are
‘hwo paths from A to AND-gate-1 inthe Y, eieuit! one direct and
uncomplemented, the other complemented via ys
Pea
mae Thy
3. Rediced crcl for anonremovable rial ce itoation.
As in the previous case, yy changing to | blocks ys ftom
‘changing 10 1. But now, the converse is also true, ie, yo chang
ingto | blocks y,ffom changing to |. Therefore delaying the Y\
change, which solved the problem for the removable critical
‘ce, will not work here because it dove not solve the converse
‘problems; once 3 goes on, it prevents y; from turing on.
However, this analysis does point to a solution. What mat-
‘ters is not when each of the y-signals actually changes. but
‘when the circuit generating the other y sees che effect of the
Change, Thus, ifthe news of the y, change is ‘ror
reeching the ¥, eireut until ys has already changed and thet
‘change has been locked up, and, conversely, ifthe news of the
Ys change ix prevented ftom reaching the y; circuit until the
Yi-shange has already been locked up, then correct operation
‘ll be ensured, The key is 10 delay not the generation of the
Y-signals, but the propagation of those signals to the other ¥-
Signal involved in the race, No effort need be made to fix" the
race, only to delay the reporting of the results to specific
points. In the current example (referring to the logic expres
ions for Y; and ¥3) a delayed version of ¥, can be used 10
[produce the Yq term in the ¥y expression, and a delayed ver~
sion of y, woul be used to preduce the J, term in the Ys ex
pression. Specifically, in teams of the circuit . ys will become
Stable at the correct value if the delay in the path from A.
through AND-gate-1, delay-2 to the input of OR-gate-3 is less
than the delay in the path ffom A through AND-gate-5, OR-
gate-s, delay-7, INVERTERS, to the input of OR-gate-3. Let-
ting & represent the delay in branch i, and assuming wiring
delays are included with the associated gate delays, this leads, tothe constrain:
dh da < ds dy 4s dy oF
> (di 49 + (4s dd oy
{in a similar manner, ys is guaranteed to stabilize at the
specified value if the delay from A on the path through gste-5,
‘gate-6, and delay-7 to the input of gate-6 is less than the delay
from A through gate-1, delay-2, INVERTER-4, and gate-3 10
the input of gate-6. This generates:
det det dy y= 41) + (yd) o
(Note that the cancelling out of the ds terms would not occur if
‘we were distinguishing between the delays in transmitting sig-
‘al changes of opposite polarities.) The right hand sides of (4)
and (5) specify how much we must delay the y> signal to Ys
fand the y; signal to Y, respectively. Clearly there is no con
flict between these constrains, as dy appears only in (5) and dy
appears only in (4)
Returning to the flow matrix (Fig. 11) the process can be
‘©camined ffom another viewpoint. Starting ia state 1-10, both
Y,and Y; change to 1. Ify, changes fist, the danger is that Y;
‘will see that change, fe, s8e the system in 4-10, Since Y; = 0
{in 4-10, the change in ysis thereby blocked. But, if ¥»s2¢3 the
‘Ys change occur frst, it sees the system in 2-10, where Y>~ |,
430 that there is no problem. Similarly, if ¥, sces the transition
as going from I-10 to 4-10 (ie, if it sees y; change first, it
{too will continue « stay at the correct valve and the overall
‘operation will be as specified,
Unfortunately, this method does not work: for all critical
race situations. The flow table in Fig. 14 is a medified version
Of the Fig. 1| table im thatthe next-state entry in state 2-01 is 4
instead of 3.
Now there are two critical races inthe O1 column: fom 1 19
3 and from 2 to 4. Consider the first of these, where y, and y2
are both supposed to change from 0 to 1. The technique pre=
sented above fails because in boch of the intermediate states,
‘Yan 0. We could however defeat this race by delaying the ¥;
and Yo signals to Y (with respect to the y1 and ys signals) in
the reduced expression forthe O1-column shown below:
Wat Ye=Wetyye
But for the race from 2 to 4, different constraints are re=
‘quired, namely that the y, and Ye signals be delayed. It does
‘ot appear possible to defeat both races simultaneously with
‘one-sided delay constrains.
The above results can be generalized to races involving
‘more than two variables. A careful inspection of the flow ma-
trix is necessary (0 determine if delaying the propagation of
‘signals (0 circuits generating other y-signals will ensure cor-
‘ect excitations forall transitions. This will always be the case
{or flow table columns with only one unstable sate, regardless
‘of how many y-variables are contestants in the race,
IX. SIMULATION AND TIMING PROBLEMS
Suppose a circuit has been designed that is believed to be
free of the kinds of problems addressed here. Before proceed:
ing to the fabrication stage, itis generally considered wise
‘verify this by carrying out a series Of tests with «simulltor that
ean deal with timing as well as logic. This would be done by
repeatedly applying to the simulated system a set of tests cal~
enlated to check out its behavior in a reasonably thorough
‘manner. Ifthe circuit is not too complex, the test set might be
designed to cause the execution of each transition in the flow
table describing the desired circuit behavior. Each repetition of
the test sot would be carried oxt with a different combination
‘of values for the delays in the various branches, Its generally
assumed that upper and lower bounds are available for the
‘delays in each branch. How should the delay configurations be
‘chosen for each run through the test set?
‘Clearly, since each branch delay lies somewhere ina con
tinuous range, it isnot even theoretically possible to text forall
possible delay values in even one of the circuit branches. An
approach that seems plausible is to try all combinations of
‘branch delays in which either the maximum or minimum delay
is assigned fo each branch. For a large circuit this would be a
formidable task, since, if there are branches, the test set
‘would have to be applied 2" times. (If we allow both pure and
Inertial delays in our model for each branch or allow different
‘delay values depending on whether the branch outpat is ine
creasing or decreasing, then the exponent would have 1 be
lied by 2 oF 4, compounding the problem significantly.)
Itis ebvious that this approach would be feasible only for cle-
‘cuits of modest size. But the situation is even worse than it
‘ould appear from this analysis.
At first it might seem as though if citeut worked property
when, with all other delays fixed, d, the delay in branch i were
44, of du, then it would slso work properly for any other value
fd between dy and dy. Thus ifthe above described series of
tests were actualy carried out, we could be sure thatthe circuit
‘would have no timing problems as Jong as the branch delay
vvalues were confined to the given ranges (and, of course, as-
suming that our general model was realistic). But consider now
the result presented in Seetion II] above with respect to dj-
namic hazards. It was shown that a dynamic hazard (of any
subclass) could be defeated if the delays along a particular
path, py ether exceeded the delays in each of two other paths,
‘rand ps, or was exceeded by the delays in each of these other
‘wo paths. Suppose now that the branch | is in py and that,
‘when ds in the neighborhood of its maximum value, the total
‘delay in py exceeds the delays in both p> and p,, and tha, when
‘is in the neighborhood of its minimam value, the total delay
inp) is less than the delays in both p: and pp. Then the circuit
‘would work properly with dy at either its maximum or mini= mum valve, but the dymamic hazard would be manifested for
mam range of vale of contained within the bounds defined
Sy sand dy that satisfied neither requirement. Thu, it isnot
{ficient to simulate using only maximam and minimum val-
tes of branch delays.
“An important consequence of this results that, while simat-
lacion may be a useful tool for cheeking out circuits, we cannot
rely om i 10 expose all timing problems. Iti necessary to un-
‘derstand the various cases of ming falures and to take ex-
plicit steps to elimina, defeat, or cope with all hazards, erii-
al races or metastable state conditions, For each transition
Sssoeinted with a problem condition, itis necessary to iemtify
various ertcal paths and to ensure thatthe total delays along
‘hove paths are propery related to one another.
X. PURE AND INERTIAL DELAYS.
1 i assumed here that all signals are strictly binary, ie.
2-yalued. A pure delay does nothing more 1 x signal than de-
{ay itby the magnitade ofthe delay. It does not alter the wave
form. An ideal inertial delay of magnitude D does not respond
to any input change of duration less than D, and its response is
layed by D. Ths a inertial delay element suppresses posi
tive or negative pulses whose widths ae Jess than D, and oth-
‘cowise behaves inthe same way as a pure delay. Neither tye
Of delay can be realized physically in an exact manner. Even
for close approximations fo Ideal inertial delays, rouble occurs
‘with pulses whose widths are elose to the value of D. The Out-
puts in sch eases may be runt pulses. Assume forthe purposes
‘f our present discussion, that sch pulses do not occur.
fm the preceding material dealing with the generation of
altches associated with hazards of various types, the simplest
‘Esumption about the cieult delays is that they are pure.
however, we assume that sme or all ofthe delays are inertial
then, while the mecianism for glitch generation would not be
changed, there would be situations in which glitches would be
filtered out by inertial delays in subsequent stages of fie.
‘One might be tempted to infer fom this that replacing pare
lays with inertial delays can only eliminate malfumetions due
te hazards, never easing additional manifenations of hazards
“This inference sot valid.
“The difficulty i that sieuations can exist in which glitches
‘can cancel out ther glitches, If am inertia delay fiters outa
flitch that cancels another glitch, the result can be an output
iMunetion or a runition to an incorrect intemal state. Such a
‘Situation is hatrated in Fig. 1S.
"Assure delays: y= 9, da~ 7, y= 5, da~ ts ds ™ 5, 1-16
the delays ae all put, ther, following a change of X fom 0 t0 1
lat 0, Ohazard fe manifested at the output ofthe AND-gate
Staring at t= | and ending at t= 5. Tati, a pals of with 4
“tppears atthe point pin the circuit at ~ 1, It is delayed by
branch delay dy 30 that ft bonis at t= 6 a the Jowest input 10
the OR-gate. If the signal q were fixed at 0, then a t-hazard
\would be manifested at point, dhe outpat ofthe OR-gat in the
form of a negative pulse of width 2 beginning att = 7, Observe
fhow hat the L-pulse at q overlaps the O-pulse completely, 30
the the signal att remains fied tI s does the circuit ovtpat 2.
;b—*
he
Fi 15. eampe emt crete
‘Thus all the delays ae pure, no hazard is manifested atthe
circuit output.
‘But now suppose that dy, the branch delay between p and,
is changed from a pure £o an inertial delay (with the sume
‘magnitude, ramely 5). Then the glitch produced by the com
flicking inpats tothe AND-gate, which is of width 4, is Htered
fou by dy The q-input tothe OR-gate remains fixed at 0, and
So the |-bazard produced by the OR-gate is manifested at a8
{2 O-puls of width 2. I is tansmited to Z with a delay of one
‘nit of time.
"Thus, changing a pure delay inthe circit to an inertial de-
lay introduces an ouspat plich that was not previously preset.
(Rote tht the result would have been the same if al! of the
elays were made inertial) It follows then that, for an overall
‘eat, changing pure delays to inertial delays may somtimes
Ineroduce faulty skgals not previously generated.
XL. CONCLUSIONS
‘Timing problems in logic ciceuits are generally caused by
diferent inpat signals to-2 gate changing in oppesite
