EL071 - Sistem Digital
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Marina ArtiyasaEL071 - Sistem Digital
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Marina ArtiyasaMachine Translated by Google
COURSE MODULE
DIGITAL SYSTEM
EL071 -2 credits
FACULTY OF ENGINEERING DRAFTING TEAM
BUDI LUHUR UNIVERSITY
JAKARTA EKA PURWA LAKSANA
AKHMAD MUSAFA
VERSION 1.0
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FOREWORD
We give thanks and respect to the presence of Allah SWT, because above
His permission, so that we can complete the Digital Systems module
This.
Highest appreciation and deepest thanks
to all academics at the Faculty of Engineering, Budi Luhur University, who have
provide assistance and support in compiling this course module.
The drafting team has compiled this course module as closely as possible,
However, we realize that the compilers are certainly not free from errors and mistakes
just. The drafting team is very open to various input, ideas and suggestions from
various parties so that this course module can be even better.
We really hope that this course module can be useful as material
Teaching for students at the Faculty of Engineering, Budi Luhur University.
Jakarta, January 2020
Drafting team
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LIST OF CONTENTS
Cover Page
Endorsement page ................................................ ......................................... 1
Foreword ................................................ ................................................................ 2
List of contents ................................................ ................................................................ ......... 3
MEETING 1. NUMBER SYSTEMS ................................................ .................... 8
1.1. Tuition Contract ................................................ .....11
1.2. Values of Virtue ................................................ 14
1.3. Understanding Number Systems ......................................... 14
1.4. Binary Number System .................................................. ... 16
1.5. Octal Number System .................................................. ....19
1.6. Decimal Number System ................................................ 20
1.7. Hexadecimal Number System.................................. 21
1.8. Binary Number Operations................................................ .. 22
1.9. Octal Number Operations.............................................. .. 23
1.10. Decimal Number Operations............................................ 24
1.11. Hexadecimal Number Operations .................................... 25
MEETING 2. NUMBER CONVERSION ........................................... .............. 28
2.1. Binary Number Conversion .......................................... 30
2.2. Octal Number Conversion ........................................... 33
2.3. Decimal Number Conversion ........................................... 36
2.4. Conversion of Hexadecimal Numbers.................................. 37
MEETING 3. LOGIC GATES ................................................ .................. 42
3.1. Types of Logic Gates .................................... 44
3.2. Truth Table ................................................ ........44
3.3. AND Logic Gate................................................ ..... 45
3.4. OR Logic Gate................................................ ....... 49
3.5. NOT Logic Gate (Inverter)................................... 53
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3.6. Basic Logic Gate Combinations ................................. 55
MEETING 4. BOOLEAN ALGEBRA ............................................ ................. 57
4.1. Explanation of Boolean Algebra .......................................... 59
4.2. Single Variable Theorem ........................................... 59
4.3. Multiple Variable Theorem............................................ 60
4.4. Expressing logic circuits Algebraically ................. 61
4.5. Logic Circuit Output Analysis.............................. 62
4.6. Implementation of Logic Gate Circuits
Boolean Expressions ................................................ ......... 63
MEETING 5. NAND AND NOR LOGIC GATES ...................................... 66
5.1. NAND Logic Gate ................................................ .. 68
5.2. NOR Logic Gate ................................................ ....70
MEETING 6. EX-OR AND EX-NOR LOGIC GATES ................................. 73
6.1. EX-OR Logic Gate ................................................ ... 75
6.2. EX-NOR Logic Gate ................................................ 79
MEETING 7. REVIEW OF MEETING 1 TO MEETING 6 ..................... 83
7.1. Review of Meeting 1 to Meeting 6 ................... 85
MEETING 8. Midterm Exam ............................................ ............. 91
8.1. Midterm Exam Questions ............................................ 93
MEETING 9. K-MAP (MINIMATION) ......................................... ...................... 94
9.1. Minimization ................................................ ................... 96
MEETING 10. K-MAP (IMPLICATIONS) ......................................... ................... 107
10.1. Sum Of Product (Minterm) ............................................ 109
10.2. Product Of Sum (Maxterm) ....................................... 110
MEETING 11. CODE CHANGING ........................................... .............. 117
11.1. BCD 8421 ................................................ ................ 119
11.2. Binary Complement ................................................ .....122
MEETING 12. FLIP FLOP ......................................... ............................. 129
12.1. Definition of Flip Flop ................................................ ........131
12.2. SR Flip Flop ................................................ .............. 134
12.3. JK Flip Flop .................................................. ................ 137
12.4. D Flip Flop .................................................. .................. 139
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MEETING 13. T – FLIP FLOP ........................................... ......................... 142
13.1. T – Flip Flop ................................................ ............... 144
MEETING 14. COUNTER ................................................ ............................. 148
14.1. Asynchronous Binary Up Counter ................................ 150
14.2. Asynchronous Binary Down Counter Decade Counter 151
14.3. Asynchronous Up Down Counter ................................. 152
14.4. Synchronous Binary Up Counter .................................. 153
14.5. Synchronous Binary Down Counter.............................. 154
14.6. Synchronous Binary Up Down Counter........................... 154
MEETING 15. REVIEW OF MATERIALS MEETING 9 TO MEETING 14 ...... 156
15.1. Review of Meeting Materials 9 to 14 ..... 158
MEETING 16. FINAL SEMESTER EXAMINATION ............................................ .........162
16.1. Final Semester Exam Questions............................................ 164
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MEETING TOPIC LEARNING OUTCOMES
1 NUMBER SYSTEM 1. Students can take part
lectures according to contract
lectures
2. Students are able to apply
internal noble values
implementation of lectures
3. Students are able to understand
Binary, Octal, Decimal number systems
and Hexadecimal.
4. Students are able to do it
Binary, Octal, number conversion
Decimal and Hexadecimal
2 NUMBER CONVERSION Students are able to understand binary,
octal, decimal and number conversions
Hexadecimal
3 LOGIC GATES Students are able to understand the
various types of basic logic gates,
truth tables, AND logic gates, OR
logic gates, logic gates
inverter (NOT).
4 BOOLEAN ALGEBRA Students are able to understand Algebra
Boolean.
5 NAND AND LOGIC GATES Students are able to form a gate
NOR NAND and NOR and compiling tables
truth.
6 EX-OR LOGIC GATES AND Students are able to form
EX-NOR Gates From EX-OR and EX- gates
NOR and constructing a truth table.
7 MEETING REVIEW 1 Students are able to review the material
UNTIL MEETING 6 meeting 1 to meeting
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8 MIDTERM EXAM Students are able to answer and solve
problems
given in the question
9 K-MAP (MINIMATION) Students are able to understand the
Karnough Map.
10 K-MAP (IMPLICATIONS) Students are able to understand maps
Karnough.
11 CODE CHANGING Students are able to understand
code changes.
12 FLIP FLOP Students are able to understand the working
principles of flip-flops and their use
13 T - FLIP FLOP Students are able to understand the principles
flip-flop working and usage
14 COUNTERS Students are able to understand how
counter circuit work
15 REVIEW MEETING MATERIALS Students are able to review the material
9 TO 14 from meeting 9 to meeting
14
16 FINAL EXAMS Students are able to answer and solve
problems
given in the question
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 1
NUMBER SYSTEM
Achievements : 1. Students can take part
Learning lectures according to contract
lectures
2. Students are capable
apply values
inner virtue
implementation of lectures
3. Students are able to understand
Binary, Octal, number system
Decimal and Hexadecimal.
4. Students are able to do it
Binary, Octal, number conversion
Decimal and Hexadecimal
Sub Principal : 1.1. Tuition contract
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Discussion 1.2. Virtuous values and
deep application
lectures
1.3. Understanding Number Systems
1.4. Binary Number System
1.5. Octal Number System
1.6. Decimal Number System
1.7. Number Systems
Hexadecimal
1.8. Binary Number Operations
1.9. Octal Number Operations
1.10.Decimal Number Operations
1.11.Number Operations
Hexadecimal
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
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”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
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1.1. Tuition Contract
Short Course Description
This course explains digital systems, how to design logic circuits
and further applications.
Course Weight
This course has a weight of 2 credits
Learning Outcomes
The learning outcomes of this course are as follows:
1. Master the basic concepts of digital logic
2. Able to apply basic digital systems including binary number systems, gates
logic, combinational circuits, and sequential circuits
3. Able to simplify the implementation of combinational circuits
with the Karnaugh Map technique.
4. Demonstrate a responsible attitude towards work in their field of expertise
independently.
Lecture Schedule
The Lecture Schedule for Digital Systems Courses is as follows:
Method Meeting Learning materials
Lectures
1 Face to face 1. Tuition contract
2. Virtuous values and
deep application
lectures
3. Understanding Number Systems
4. Binary Number System.
5. Octal Number System.
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6. Decimal Number System
7. Number System
Hexadecimal
8. Binary Number Operations
9. Octal Number Operations
10. Decimal Number Operations
11.Number Operations
Hexadecimal
2 Face to face 1. Binary Number Conversion
2. Octal Number Conversion
3. Conversion of Decimal Numbers
4. Number Conversion
Hexadecimal
3 E-Learning 1. Types of gates
basic logic
2. Truth Table.
3. AND Logic Gate.
4. OR logic gate.
5. Inverter logic gate
(NOT)
6. Combination of logic gates
base
4 Face to face 1. Explanation of Boolean Algebra
2. Single Variable Theorem
3. Multiple Variable Theorem
4. State the logic circuit
algebraically
5. Analysis of Circuit Output
Logic
6. Implementation Suite
Logic Gates Against
Boolean Expressions
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5 Face to face 1. NAND logic gate
2. NOR logic gate
6 E-Learning 1. EX-OR logic gate
2. EX-NOR logic gate
7 E-Learning Review of meeting materials 1
until Meeting 6
8 Face to face MIDTERM EXAM
9 Face to face Minimization
10 E-Learning 1. Sum Of Product (Minterm)
2. Product Of Sum (maxterm)
11 E-Learning 1. BCD 8421
2. Binary complement
12 Face to face 1. D flip-flop
2. JK flip-flop
3. SR flip-flop
13 E-Learning 1. T flip-flop
14 E-Learning 1. Asynchronous Binary Up
Counters
2. Asynchronous Binary Down
Decade Counter
3. Asynchronous Up Down
Counters
4. Synchronous Binary Up
Counters
5. Synchronous Binary Down
Counters
1. 6. Synchronous Binary Up
Down Counter
15 Face to face Review of Meeting Materials 9
to 14
16 Face to face Final exams
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Assessment Percentage
The Assessment Percentage is:
Duty and Virtue : 30 %
Midterm Exam (UTS) : 30 %
Final Semester Examination (UAS) : 40 %
1.2. Values of Virtue
There are 9 types of virtue, namely:
1. Be patient, be grateful
2. Love
3. Likes to help
4. Be honest
5. Responsibility
6. Be humble
7. Tolerance
8. Cooperation
9. Manners
1.3. Understanding Number Systems
A number system is a way to represent the magnitude of a physical item.
Number systems that are widely used by humans in everyday life
Day is a decimal number system, namely a number system based on 10 and
uses 10 digits to represent a quantity. This system is widely used
because humans have 10 fingers which are used to help with calculations.
In contrast to computers, logic in computers is represented in a two-element form
circumstances ie off (no current) and on (there is current). This concept is used
in the binary number system, namely a number system based on 2 and
uses 2 digits to represent a quantity
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Types of Number Systems
The various number systems are as follows:
1. Binary number system
2. Octal number system
3. Decimal number system
4. Hexadecimal Number System
Each number system has a Base or Radix (r), namely its number
numbers and Digits (d) used in a number.
Writing Numbers
A number N = dn dn-1 dn-2 .......... d2 d1 d0 d-1 d-2.......
Where :
dn = the digit with the highest weight and is written on the leftmost
d0 = digit with a weight of one and written last before the comma
d-2 = digit with a weight of 1/r-2 and written last
dn = also called MSD (Most Significant Digit)
d-2 = also called LSD (Least Significant Digit)
Example :
Binary number system : = 4210
Octal number system : 17108 = 96810
Decimal number system : 878610 = 878610
Hexadecimal number system : DEA1710 = 91189510
Number Weight
Number weight is the equivalent value of a number in the system
decimal number. The weight of the number will depend on the radix and the order of the digits
the digits.
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Example :
A number N = (137.56)10 has a numerical weight:
Digit 1 represents 1 x hundreds number (102 ) = 100
Digit 3 represents 3 x tens number (101 ) = 30
Digit 7 represents 7 x ones number (100 ) =7
Digit 5 represents 5 x decimal number (10-1 ) = 0.5
Digit 6 represents 6 x hundredths (10-2 ) = 0.06
So: (137.56)10 = (1 x 102 ) + (3 x 101 ) + (7 x 100 ) + (5 x 10-1 ) + (6 x 10-2 )
General Formula for Number Weights:
(N)r = dnr n + dn-1r n-1 + .... + d3r 3 + d2r 2 + d1r 1 + d0r 0 + d-1r -1 + d-2r -2 + ....
Example :
(10.11)2 = (1 x 21 ) + (0 x 20 ) + (1 x 2-1 ) + (1 x 2-2 ) = 2.7510
(76.54)8 = (7 x 81 ) + (6 x 80 ) + (5 x 8-1 ) + (4 x 8-2 ) = 62.687510
(168.7)10 = (1 x 102 ) + (6 x 101 ) + (8 x 10-7 ) = 168,710
(C7,E)16 = (C x 161 ) + (7 x 160 ) + (E x 16-1 ) = 199.87510
1.4. Binary number system
The Binary System is a number system that only uses two symbols
(0.1). This number is usually said to have a radix of 2 and is usually called
base 2 numbers, each binary digit is called a bit.
Why use the Binary system?
• The use of the binary number system is basically due to
simplicity of the way, where the binary digits 0 and 1 are related to
physical implementation. The binary digits 0 and 1 can be easily expressed by
digital component voltage as low (low) or high (high)
• The binary system can only process binary numbers or binary coded numbers from
other number systems such as decimal. Restrictions on all digital systems
(binary) This results in that the numbers are given in another form
must be converted to binary form first before being processed by a system
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digital at the end of the process the results (in binary form) can be converted
returns to its original number system form.
Weight of Each Digit in Binary Numbers
23 22 21 20 2 -1 2 -2 2 -3
=8 =4=2=1 . = 1/2 = 1/4 = 1/8
Per Per Per
Eights Fours TwosOnes
two four eighty
Most Least
Binary
Significant Significant
point
Beets Beets
The position value of the binary number system is a power of 2.
Example :
1 0 0 1 (2) = …… (10)
So 1 0 0 1 (2) = 9 (10)
Binary Number Counting
23=822=421=220 = 1 Decimal Equivalent
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
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0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Binary Quantity Representation
In a digital system, information is usually processed
expressed in binary form. Binary quantities can represent various
equipment that has only 2 possible operating conditions.
For example, a switch only has 2 operating conditions, namely
ON (closed) and OFF (open). In this case the open switch can be
represented by binary 0 (logic LOW), and a closed switch can be stated
with binary 1 (logic HIGH).
In digital engineering logic 1 (HIGH) is expressed by a voltage between 2
Volts up to 5 Volts. Meanwhile, logic 0 (LOW) is expressed by voltage
between 0 Volts to 0.8 Volts. For voltages between 0.8 Volts to
with 2 Volts not being used or often called a floating logic condition.
This is because it is not included in LOW or HIGH logic.
Binary 1: Various voltages whose values are between 2 Volts and 5 Volts.
Binary 0: Various voltages whose values are between 0 Volts and 0.8 Volts.
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In digital engineering, the exact value of voltage is not a thing
absolute, for example a voltage of 3.6 Volts will be considered the same as a voltage of 4.3
Volts, namely, both have a HIGH logic value. This does not apply in
analog system. In the analog system, the exact/certain value of voltage is something
which is very important.
1.5. Octal Number System
The octal number system has a base or radix of 8 with the digits being 0, 1,
2, 3, 4, 5, 6, and 7.
Weight of Each Digit in Octal Numbers
83 828180 8 -1 8 -2 8 -3
=512 =64 =8 =1 . =1/8 =1/64 =1/512
Most Least
Octal
Significant Significant
point
Digits Digits
The position value system of octal numbers is a power of 8.
Example :
12(8) = ..... (10)
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1.6. Decimal Number System
The decimal number system has a base or radix of 10 with the digits being
0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
Weight of Each Digit in Decimal Numbers
103 102 101 100 10-1 10-2 10-3
= 1000 = 100 = 10 = 1 . = 0.1 = 0.01 = 0.001
Per Per Per
Thousands Hundreds Tens of Units
tens hundreds Thousand
Most Least
Decimals
Significant Significant
point
Digits Digits
Decimal Integer
A rounded decimal value, for example 8598, can be interpreted as:
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Position value ÿ the weighing or weight of each digit depends on
position, namely the base value raised to the power of the position.
Absolute value ÿ the value for each digit of the number
Decimal Fractions
A decimal value that contains a fractional value after a comma, for example value
183.75 is a decimal fraction which can be interpreted as:
1.7. Hexadecimal Number System
The hexadecimal number system has a base or radix of 16 with its digits
are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e and f. Where A = 10, B = 11, C= 12,
D = 13 , E = 14 and F = 15.
The position value in the hexadecimal number system is a power of 16
Weight of Each Digit in Hexadecimal Numbers
163 162 161 160 16-1 16-2 16-3
=4096 =256 =16 =1 . =1/16 =1/256 =1/4096
Most Least
Hexadec.
Significant Significant
point
Digits Digits
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Hexadecimal Example
1.8. Binary Number Operations
Addition of Binary numbers
The basis for adding binary numbers is:
0+0=0
0+1=1
1+0=1
1+1=0 with a carry (movement) of 1, namely 1 + 1 = 2, because of the digits
largest Binary 1, then it must be reduced by 2 (base),
so 2 – 2 = 0 with carry (movement) 1.
Example :
1111(2) + 10100(2) = ....... (2)
So 1111(2) + 10100(2) = 100011 (2)
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Binary Number Subtraction
The basis for subtracting binary numbers is:
0-0=0
1-0=1
1-1=0
0 – 1 = 1 With borrow (borrow) 1, (borrow 1 from the next position
left).
Example :
1011(2) – 101(2) = ..... (2)
So 1011(2) – 101(2) = 110 (2)
1.9. Octal Number Operations
Addition of Octal numbers
When adding octal numbers, add them sequentially starting with the digits
to the right. If the sum result is more than 7 then carry will occur
(move) 1 which will be added to the digit to the left.
Example :
25(8) + 127(8) = ....... (8)
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So 25(8) + 127(8) = 154 (8)
Octal Number Reduction
Octal Number Subtraction can be done in the same way as
subtracting decimal numbers.
Example :
154(8) - 127(8) = ..... (8)
So 154(8) - 127(8) = 25 (8)
1.10. Decimal Number Operations
Adding decimal numbers
Example :
129(10) + 107(10) = ......(10)
11 Carry (Transfer) 1
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129
197+
326
So 129(10) + 107(10) = 32610)
Subtracting decimal numbers
Example :
117(10) + 99(10) = .....10)
-1-1 Borrow (Borrow) 1
117
99 -
18
So 117(10) + 99(10) = 1810)
1.11. Hexadecimal Number Operations
Addition of hexadecimal numbers
Example :
BAD(16) + 431(16) = ..... (16)
So BAD(16) + 431(16) = FDE (16)
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Subtraction of hexadecimal numbers
Example :
12E1(16) – 627(16) = ..... (16)
So 12E1(16) – 627(16) = CBA (16)
SUMMARY
There are 4 types of number systems, namely Binary number system, Number system
Octal, Decimal number system, and Hexadecimal number system. Every system
The number has a Base or Radix (r), namely the number of numbers and digits
(d) which is used in a number.
EXERCISE
1. Calculate the number weight of:
a. (10.01)2 e. (3.26)10
b. (10011001101)2 f. (43.9)10
c. (552.31)8 g. (90d,2f)16
d. (74.52)8 h. (6,af)16
2. Write the numbers 1 to 100 in the Binary, Octal, number system
Decimal, and Hexadecimal.
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3. Calculate:
a. 1011(2) + 10011(2) = ....... (2)
b. 1100010(2) - 110111(2) = ....... (2)
c. 232(8) + 111(8) = ....... (8)
d. 240(8) – 157(8) = ....... (8)
e. 134(10) + 156 (10) = .......(10)
f. 134(10) - 96 (10) = .......(10)
g. 679(16) + 487 (16) = .......(16)
h. DEA(16) - 156 (16) = .......(16)
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 2
NUMBER CONVERSION
Achievements : Students are able to understand the
conversion of Binary, Octal, Decimal
Learning
and Hexadecimal numbers
Sub Principal : 1.1. Binary Number Conversion
Discussion 1.2. Octal Number Conversion
1.3. Decimal Number Conversion
1.4. Number Conversion
Hexadecimal
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
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”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
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2.1. Binary Number Conversion
Convert Binary Numbers to Octal Numbers
To convert binary numbers to octal numbers, you can do this by:
how to group each digit in a binary number into 3 digits
for each group. Then convert each group into
corresponding octal number. What must be remembered is that grouping is done
order from the digit with the lightest weight (Least Significant Digit / LSD).
Octal Digits 0 1 2 3 4 5 6 7
Binary
000 001 010 011 100 101 110 111
Equivalents
Example :
11010100(2) = ....... (8)
(011 010 100)2
3 2 4
Then 11010100 (2) = 324 (8)
Converting binary numbers to octal numbers can also be done with
how to calculate the weight of the binary number first and continue
by dividing the weight of the number (in the form of a decimal number) by
dividing factor 8.
Example :
11010100(2) = ....... (8)
The first step is to calculate the weight of the binary number.
(1 1 0 1 0 1 0 0) (2)
x x x x x x x x
27 26 25 24 23 22 21 20
128+ 64 + 0 + 16 + 0 + 4 + 0 + 0 = 212(10)
The second step, divide the weight value of the binary number (in the form of a number
decimal) with a dividing factor of 8
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212 : 8 = 26, remaining 4 LSD
26 : 8 = 3, remaining 2
3 : 8 = 0, remaining 3 MSD
Then 11010100 (2) = 324 (8)
Convert Binary Numbers to Decimal Numbers
A binary number can be converted to a decimal number with
how to multiply each bit in a number by its position value.
Converting binary numbers to decimal numbers can also be interpreted as
calculate the weight of the value of the binary number.
Example :
1001(2) = .... (10)
(1 0 0 1) (2)
x x x x
23 22 21 20
8+0+0+1 = 9(10)
Then 1001(2) = 9(10)
Convert Binary Numbers to Hexadecimal Numbers
To convert binary numbers to hexadecimal numbers can be done
by grouping each digit in the binary number into 4
digits for each group. Then convert each group
into a suitable hexadecimal number. What you have to remember is that
Grouping is done in order of the digit with the lightest weight (Least
Significant Digits / LSD).
Example :
111010010 (2) = ..... (16)
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(0001)(1101)(0010)
(1) (13) (2)
(1) (D) (2)
So 111010010 (2) = 1D2 (16)
Converting Binary Numbers to hexadecimal numbers can also be done
by calculating the weight of the binary number first and
followed by dividing the number weights (in the form of numbers
decimal) with a dividing factor of 16.
Example :
111010010 (2) = ..... (16)
The first step is to calculate the weight of the binary number.
(1 1 1 0 1 0 0 1 0) (2)
x x x x x x x x x
28 27 26 25 24 23 22 21 20
256 +128 + 64 + 0 + 16 + 0 + 0 + 2 + 0 = 466(10)
The second step, divide the weight value of the binary number (in the form of a number
decimal) with a dividing factor of 16
466 : 16 = 29, 2 LSD left
29 : 16 = 1, remainder 13 = D
1 : 16 = 0, remaining 1 MSD
Then 11010100 (2) = 1D2 (16)
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2.2. Octal Number Conversion
Convert Octal Numbers to Binary Numbers
To convert octal numbers to binary numbers, namely each one digit
Octal numbers are expressed in three digit binary numbers.
Example :
542(8) = ..... (2)
(54 2) 8
101 100 010
So 542 (8) = 101100010 (2)
Converting Octal Numbers to Binary numbers can also be done by
how to calculate the weight of Octal numbers first and continue with
divide the weight of the number (in the form of a decimal number) by factors
divider 2.
Example :
542(8) = ..... (2)
The first step is to calculate the weight of the Octal number.
(5 4 2) (8)
x x x
82 81 80
320 + 32 + 2 = 354(10)
The second step, divide the weight value of the octal number (in the form of a number
decimal) with a dividing factor of 2.
354 : 2 = 177, remaining 0 LSD
177 : 2 = 88, remaining 1
88 : 2 = 44, remaining 0
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44 : 2 = 22, remaining 0
22 : 2 = 11, remaining 0
11 : 2 = 5, remaining 1
5 : 2 = 2, remaining 1
2 : 2 = 1, remaining 0
1 : 2 = 0, remaining 1 MSD
So 542 (8) = 101100010 (2)
Convert Octal Numbers to Decimal Numbers
Converting octal numbers to decimal numbers is in principle the same
like converting binary numbers to decimal numbers. That is the first time
all you have to do is multiply each digit by the appropriate weight. Next
by adding together the results of the multiplication. Convert
octal numbers to decimal numbers can also be interpreted as calculating weights
the value of the octal number.
Example :
Then 24.6 (8) = 20.75 (10)
Convert Octal Numbers to Hexadecimal Numbers
To convert octal numbers to hexadecimal numbers is done
in a two-stage way. The first stage is to convert each one first
one digit octal number to three digit binary number. The second stage is
converts each four digit binary number to one digit number
hexadecimal.
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Example :
542(8) = ..... (16)
The first step converts octal numbers to binary numbers
(54 2) 8
101 100 010
The second step converts the binary number to hexadecimal
101100010(2) =..... (16)
(0001)(0110)(0010)
(1) (6) (2)
So 542(8) = 162 (16)
Converting octal numbers to hexadecimal numbers can also be done
by calculating the weight of the octal number first and
followed by dividing the number weights (in the form of numbers
decimal) with a dividing factor of 16.
Example :
542(8) = ..... (16)
The first step is to calculate the weight of the octal number.
(5 4 2)8
x x x
82 81 80
320 + 32 + 2 = 354(10)
The second step, divide the weight value of the octal number (in the form of a number
decimal) with a dividing factor of 16.
354 : 16 = 22, 2 LSD left
22 : 16 = 1, remaining 6
1 : 16 = 0, remaining 1 MSD
So 542(8) = 162 (16
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2.3. Decimal Number Conversion
Convert Decimal Numbers to Binary Numbers
To change a decimal number to another radix, you can do it with
How to continuously divide a decimal number by radix
the desired new number (until the result = 0). The remainder of each division
will be the digits of the new number. The remainder of the first division
becomes the rightmost digit (LSD) and the remainder of the last division becomes
leftmost digit (MSD). So convert the decimal number to binary number
This is done by repeatedly dividing the decimal number by the dividing factor
is 2.
Example :
45 (10) = ….. (2)
45 : 2 = 22, remaining 1 LSD
22 : 2 = 11, remaining 0
11 : 2 = 5, remaining 1
5 : 2 = 2, remaining 1
2 : 2 = 1, remaining 0
1 : 2 = 0, remaining 1 MSD
Then 45 (10) = 101101 (2) (written from bottom to top)
Convert Decimal Numbers to Octal Numbers
Convert decimal numbers to octal numbers using division
repeating decimal numbers with a dividing factor of 8. By dividing
decimal number with 8 then take the remainder of the division.
Example :
385 (10) = …. (8)
385 : 8 = 48 , 1 LSD remaining
48 : 8 = 6 , remaining 0
6:8=0 , remaining 6 MSD
Then 385 (10) = 601 (8) (written from bottom to top)
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Convert Decimal Numbers to Hexadecimal Numbers
Converting decimal numbers to hexadecimal numbers is done by:
Repeated division of decimal numbers with a dividing factor of 16.
Example :
378(10) = ....... (16)
378 : 16 = 23 , remaining 10 ÿ A LSD
23 : 16 = 1 , remaining 7
1 : 16 = 0 , remaining 1 MSD
Then 378(10) =17A (16) (written from bottom to top)
2.4. Hexadecimal Number Conversion
Convert Hexadecimal Numbers to Binary Numbers
To convert hexadecimal numbers to binary numbers is done
by converting each hexadecimal digit to four binary digits.
Example :
AC2(16) = ..... (2)
(A C 2) 16
10 12 2
1010 1100 0010
So AC2 (16) = 101011000010 (2)
Converting Hexadecimal Numbers to Binary numbers can also be done
by calculating the weight of the hexadecimal number first and
followed by dividing the number weights (in the form of numbers
decimal) with a dividing factor of 2.
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Example :
AC2(16) = ..... (2)
The first step is to calculate the weight of the Hexadecimal number.
(AIR CONDITIONING 2) (16)
(10 12 2) (16)
x x x
162 161 160
2560 +192 +2 = 2754(10)
The second step, divide the weight value of the Hexadecimal number (in the form
decimal number) with a dividing factor of 2.
2754 : 2 = 1377, remaining 0 LSD
1377 : 2 = 688, remaining 1
688 : 2 = 344, remaining 0
344 : 2 = 172, remaining 0
172 : 2 = 86, remaining 0
86 : 2 = 43, remaining 0
43 : 2 = 21, remaining 1
21 : 2 = 10, remaining 1
10 : 2 = 5, remaining 0
5 : 2 = 2, remaining 1
2 : 2 = 1, remaining 0
1 : 2 = 0, remaining 1 MSD
So AC2 (16) = 101011000010 (2)
Convert Hexadecimal Numbers to Octal Numbers
To convert hexadecimal numbers to octal numbers can be done
with 2 stages. The first stage is to convert each one first
digits of a hexadecimal number to four digits of a binary number. The second stage is
converts each three digit binary number to one digit octal number.
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Example :
5A8 (16) = ....... (8)
The first step converts hexadecimal numbers to binary numbers
(5 A 8) 16
5 10 8
0101 1010 1000
The second step converts binary numbers to octal numbers
10 110 101 000(2) =..... (8)
(010) (110) (101) (000)
(2) (6) (5) (0)
So 5A8 (16) = 2650 (8)
Converting Hexadecimal Numbers to octal numbers can also be done
by calculating the weight of the hexadecimal number first and
followed by dividing the number weights (in the form of numbers
decimal) with a dividing factor of 8.
Example :
5A8 (16) = ....... (8)
The first step is to calculate the weight of the Hexadecimal number.
(5 A 8) (16)
(5 10 8) (16)
x x x
162 161 160
1280+160+8 = 1448(10)
The second step, divide the weight value of the Hexadecimal number (in the form
decimal number) with a dividing factor of 8.
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1448 : 8 = 181, remaining 0 LSD
181 : 8 = 22, remaining 5
22 : 8 = 2, remaining 6
2 : 8 = 0, remaining 2 MSD
So 5A8 (16) = 2650 (8)
Convert Hexadecimal Numbers to Decimal Numbers
Conversion of hexadecimal numbers to decimal numbers in principle is
just like converting octal numbers to decimal which consists of two stages.
That is, the first thing you have to do is multiply each digit in it
hexadecimal numbers with appropriate weights. Then continue with
add up the total of the multiplication results.
Example :
So C7(16) = 199 (10)
SUMMARY
Number Conversion is a process in which one number system with
A certain base will be made into a number with another base. In general
to convert a certain number to a certain number can be done with
calculate the weight of the number (in decimal number form), next
Conversion is carried out to the desired number by dividing
with the radix of the target number until it runs out.
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EXERCISE
Explain the answer to the lost conversion below:
= =
1. 100010(2) ...........(8) ......... (10)= ....... (16)
= =
2. 567(8) = ......... (10) ......... (16) ........(2)
= = =
3. 987(10) .......... (8) .......... (16) ....... (2)
= = =
4. ADE(16) .......... (2) ............ (8) ....... (10)
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 3
LOGIC GATES
Achievements : Students are able to understand
Learning various kinds of logic gates
basis, truth table, Gate
AND logic, OR logic gates,
Inverter logic gate (NOT).
Sub Principal : 3.1. Various kinds of gates
Discussion basic logic
3.2. Truth Table.
3.3. AND Logic Gate.
3.4. OR logic gate.
3.5. Inverter logic gate
(NOT)
3.6. Combination of logic gates
base
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Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[43]
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3.1. Types of Logic Gates
Logic Gates or in English are called Logic Gates is
the basis for forming a Digital System which functions to change two or more
input/input (except note gates which only have 1 input/input)
but only produces one output. one or more Inputs
(input) into a logical output signal. Logic gates
operates based on the binary number system, namely numbers that only have 2
The symbol codes are 0 (Low) and 1 (High) using Algebra Theory
Boolean. In most logic gates, the low part is around zero volts (
0 V), while the high part is about five positive volts (+5 V).
The types of basic logic gates are as follows:
1. AND logic gate
2. OR logic gate
3. NOT logic gate
3.2. Truth Table
The truth table is a table that states the input relationships
with output. This table explains how the output logic occurs
depending on the input logic given to the circuit. In figure 3.1,
An example of a logic circuit with 2 inputs is given to produce a table
truth that states the combination of possible input logic and logic
The appropriate output for each input combination is as shown in table 3.1
Figure 3.1 Example of a logic gate with 2 inputs
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Table 3.1 Example of a truth table with 2 inputs
Input Output
A BX = A + B
0 0 0
0 1 1
1 0 1
1 1 1
From table 3.1 it appears that the output logic that occurs is very dependent
on the given input logic. They are as follows:
– When the input logic A and B both have logic 0, then the output logic is X
is 0.
– When the input logic A is 0 and B is 1, then the output logic X is 1.
– When the input logic A is 1 and B is 0, then the output logic X is 1
– When both inputs A and B have logic 1, then the output logic X is 1.
3.3. AND Logic Gate
AND logic gates are called “All or none” gates. Expression
AND logical operation is X = A . B (read: X = A AND B). Multiplication sign on
The AND logical operation is the same as ordinary multiplication of the numbers 1 and 0.
The logical AND operation will produce a logical output of 1 if and only if
all variables have a logical value of 1. Conversely, if there is one or more
from an input variable that has logic 0, the output logic is obtained
will have a value of 0.
For example, in Figure 3.2, there is an AND logic gate with
2 input. From the truth table it appears that if all the logic variables
input value is 1 then the output logic will have a value of 1. Conversely, if it is minimal
if one of the inputs has logic 0, then the output logic will have a value of 0.
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Figure 3.2 An AND logic gate with 2 inputs
The Boolen equation expression for the AND logic gate is:
Q=A.B
The truth table for the AND logic gate can be seen in table 3.2:
Table 3.2 Truth table for AND logic gate with 2 inputs
Input Output
A BQ = A . B
0 0 0
0 1 0
1 0 0
1 1 1
In figure 3.3 is an example of an AND logic gate with 3 and 4 inputs
input. A, B, C and D are the inputs and Q is the output of the logic gate
AND.
Figure 3.3 An AND logic gate with 3 inputs and 4 inputs
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In table 3.3 is the truth table for the 3 input OR logic gate and
4 inputs.
Table 3.3 Truth table for AND logic gates with 3 inputs and 4 inputs
AND logic gates can also be described as two series circuits
switch. To understand the working principle of the AND logic gate, you can see
figure 3.4. In figure 3.4, two switches A and B are shown arranged
in series which is used to turn on the lights. The light will just turn on
if switch A and switch B are active/closed/have a value of 1. Meanwhile the light will remain on
turns off if no switches are active or only one switch is active
(switch A or switch B).
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Figure 3.4 AND gate equivalent circuit
The IC for the AND logic gate is:
1. The types of TTL ICs include:
• 74LS08 quad 2 input AND Gate
• 74LS11 triple 3 input AND Gate
• 74LS21 dual 4 input AND Gate
2. The types of CMOS ICs include:
• CD4081 quad 2 input AND Gate
• CD4073 triple 3 input AND Gate
• CD4082 dual 4 input AND Gate
The pin configuration for logic gate ICs can be seen in Figure 3.5.
Figure 3.5 Pin configuration for AND logic gates
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There are currently 2 types of ICs for logic gates, namely: IC
from the TTL family ( Transistors Logic ) and ICs from the CMOS family
( Complementary Metal-Oxide-Silicon). TTL ICs are marked with the initial numbers 74LSXX
or 74HCXX, while CMOS ICs begin with the letters CDXXXX. Each IC
have their own weaknesses and advantages. The main difference between TTL IC and IC
CMOS can be seen in table 3.4.
Table 3.4 Differences between IC –TTL and IC - CMOS
IC No – TTL IC – CMOS
1 Resistant to static electricity Not resistant to static electricity
Greater electrical power consumption More efficient in terms of power consumption
2 compared to CMOS ICs electricity
The Vcc voltage is around 4.75V
The Vcc voltage ranges from 3V to 18 V
3 up to 5.25V
4 Susceptible to Noise Resistant to noise
Logic “0” is in the range Logic “0” is in the range
voltage 0 – 0.8V voltage 0 – 1.5V
5
Logic “1” is in the range Logic “1” is in the range
voltage 2.0 to 5V voltage 3.0 to 18V
Prices are more expensive in comparison
6 Cheap price
with TTL IC
3.4. OR Logic Gate
The OR logic gate is also called “any or all”. Mathematical expression of
OR logic is X = A + B (read: X = A OR B). The + sign indicates an operation
OR logic is not an ordinary number addition operation in general. Logic operations
OR will produce logic 1 if at least one of the variables is present
has a value of 1. The logical OR operation will produce a logical 0 if all variables are
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there is a value of 0.
In figure 3.6 is an example of an OR logic gate with 2 inputs. A and
B is the input and X is the output of the OR logic gate.
Figure 3.6 An OR logic gate with 2 inputs
The Boolean equation expression for OR logic is:
Q=A+B
The truth table for the OR logic gate is shown in table 3.5
Table 3.5 Truth table for OR logic gate with 2 inputs
Input Output
A BQ = A + B
0 0 0
0 1 1
1 0 1
1 1 1
In figure 3.7 is an example of an OR logic gate with 3 and 4 inputs
input. A, B, C and D are the inputs and Q is the output of the OR logic gate.
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Figure 3.7 An OR logic gate with 3 inputs
Table 3.6 Truth table for OR logic gates with 3 inputs and 4 inputs
The OR logic gate can also be described as a two parallel circuit
switch. To understand the working principle of the OR logic gate, you can look at the picture
3.8. In Figure 3.8, two switches A and B are shown arranged sequentially
parallel used to turn on the lights. The light will turn on when
one of the A/B switches or both switches is active/closed/has a value of 1. Meanwhile, the lights
will turn off if no switch is active.
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Figure 3.8 OR gate equivalent circuit
Logic gates can be found on the market in the form of chips or ICs.
The following is an IC for an OR logic gate.
1. IC from the TTL family: 74LS32 quad 2 input OR GATE
2. IC from the CMOS family: CD4071 quad 2 input OR GATE
3. IC from the CMOS family: CD4075 Tripe 3 input OR GATE
4. IC from the CMOS family: CD4072 Dual 4 input OR GATE
An image of the IC - iC leg configuration can be seen in Figure 3.9
Figure 3.9 IC pin configuration - OR logic gate IC
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3.5. NOT Logic Gate (Inverter)
The NOT gate is a logic circuit that functions as an "Inverter".
The NOT operation is different from the OR and AND operations, namely that the NOT operation can
applied to a single input variable. For example, if against
variable A is applied NOT operation, the output result X can be expressed as
or where the sign ( ' ) or declares the NOT operation.
In figure 3.10 is an example of a NOT logic gate with 1 input. A
is the input and Q is the output of the NOT logic gate.
Figure 3.10 A NOT logic gate
The NOT logic gate has a Boolean expression:
The truth table for the NOT logic gate is as in table 3.7
Table 3.7 Truth table for NOT logic gate
Input Output
A Q=
0 1
1 0
If the input (A) = "1", then the output (Y) = "0", and vice versa, input
(A) = “0”, then the output is (Y) = “1”.
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Figure 3.9 Equivalent circuit of NOT gate
Figure 3.9 shows a logic circuit equivalent to
a NOT gate. The NOT gate operation can be explained as follows. If
the input is in the low state (switch is open), then the NOT operation
produces output (Y) High (1) so that the light turns on. On the other hand, when
the input is in the High state (switch is closed), then the NOT operation
produces a low (Y) output (1) so the light turns off.
NOT logic gates in IC form include:
1. From TTL IC:
• 74 LS04 Hex Inverting NOT Gate
• 74LS14 Hex Schmitt Inverting NOT Gate
• 74LS004 Hex Inverting Drivers
2. From the CMOS IC:
• CD4009 Hex Inverting NOT Gate
• CD4069 Hex Inverting NOT Gate
The NOT logic gate IC pin configuration can be seen in Figure 3.10.
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Figure 3.10 NOT logic gate IC pin configuration
3.6. Basic Logic Gate Combinations
Example question 1
Create a logic gate from the equation :
Answer:
Example question 2
Create a logic gate from the equation :
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SUMMARY
Logic gates are three basic types of logic gates, namely gates
AND logic, OR logic gates and NOT logic gates.
EXERCISE
1. Create a logic gate from the equation
2. Create a logic gate from the equation
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 4
BOOLEAN ALGEBRA
Achievements : Students are able to understand
Learning Boolean Algebra
Sub Principal : 4.1. Boolean Algebra Explained
Discussion 4.2. Single Variable Theorem
4.3. Multiple Variable Theorem
4.4. State a logic circuit
algebraically
4.5. Circuit Output Analysis
Logic
4.6. Implementation Suite
Logic Gates Against
Boolean Expressions
Bibliography : 1. Malvino, Principles and
Digital Implementation.
[57]
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2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[58]
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4.1. Boolean Algebra Explained
Boolean algebra is a branch of algebra studied in
arabic mathematics. Boolean algebra was first introduced by an expert
English mathematician George Boole (2 November 1815 – 8 December
1864) in his writing entitled An Investigation of ofLaw Thoughts on
in 1854.
Boolean algebra uses the values 1 and 0 as input and output. Value 0
and 1 corresponds to the binary number system. Boolean algebra is basic
in designing digital circuits and use in computing equipment
modern today. In digital electronic circuits, condition "1" is expressed by
voltage is 5V and the condition "0" is expressed as a voltage of 0V or can also be
with the OFF condition as logic "0" and ON as logic "1".
There are 2 types of theorems in Boolean algebra, namely variable theorems
single and multiple variable theorems.
4.2. Single Variable Theorem
The single variable theorem is derived from the basic logical operations OR, AND and
NOT, table 4.1 shows the single variable theorem of Boolean algebra.
Table 4.1 Single variable theorem of Boolean algebra
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4.3. Multiple Variable Theorem
The plural variable theorem is generally the same as the theorem in algebra
normal. The multiple variable theorem can be seen in table 4.2.
Table 4.2 Boolean algebra multiple variable theorem
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Proof of Absortib Law
4.4. Expressing logic circuits algebraically
A logic circuit, no matter how complex, can be expressed in depth
an equation that expresses a Boolean operation. This is due to
In principle, a logic gate (AND, OR and NOT) is an operation
Basic level Boolean. As in Figure 4.1, here is a logic circuit
which is expressed in a Boolean operating equation.
A
X = AB + C
B C
A
X = (A+B) C
B C
Figure 4.1 Example of an AND and OR logic gate circuit
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Boolean operational expressions contain the two basic operations, namely AND and
OR. The AND operation is carried out first (X = AB + C, where AB is processed first
formerly). This is because the priority of multiplication is higher than addition.
For the second example (A+B) it is processed first (X = (A+B) C).
If a NOT gate/Inverter is present in a logic circuit, then
the gate's output will be equal to the inverse of its input, which is normal
expressed with a sign and is pronounced “bar” or “accent”.
Figure 4.2 Example of a logic gate circuit containing a NOT logic gate
4.5. Logic Circuit Output Analysis
If the Boolean operation equation can be determined, then the circuit
output logic can be easily defined for each pair of inputs
which are given. Below are two simple examples of how to do this
analysis of determining the overall logic of a logic circuit.
Suppose the input is given for a boolean operation
are: A = 0, B = 1, C = 1, D = 1.
Then as the next example, let's say the input is for a
Boolean operations are A = 0, B = 0, C = 1, D = 1, E = 1.
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In general, the following steps must be carried out if desired
analysis of determining the output of a logic circuit that has been expressed in
Boolean equation, namely:
1. For all inversions, do this by changing the logic input value
with the opposite.
2. Process all Boolean expressions contained in curly braces,
because it has a higher priority.
3. Process AND operations before OR, unless there are priority brackets.
If there is a bar sign above an expression, then process it first
First the expression and then invert the value.
4.6. Implementation of Logic Gate Circuits for Expressions
Boolean
The operation of a digital circuit is defined by expressions/equations
Boolean, then based on the Boolean expression the logic gate circuit can be
determined. Suppose it is desired to create a circuit of logic gates
which has an output expression/equation Boolean Expressions
It has 3 parts, namely . Then those three parts
combined with OR surgery. For this reason, an OR gate with 3 inputs is needed,
with each input given being
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Figure 4.3 Example of an OR logic gate circuit with 3 inputs
Each input from the OR gate is an output from the gate
AND. 3 AND gates are required for all OR gate inputs.
Figure 4.4 AND logic gate circuit
Next, the use of the inverter gate is to produce
Overall the circuit in question is as in the picture
4.5 .
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Figure 4.5 Overall logic gate circuit
SUMMARY
Boolean algebra is the basis for designing digital circuits and
used in today's modern computing equipment.
EXERCISE
1. Prove Boole's theorem using a truth table.
2. Determine the value are: A = 1, B = 1, C = 0, D = 1.
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 5
LOGIC GATES
NAND AND NOR
Achievements : Students are able to form
Learning NAND and NOR gates as well
construct a truth table.
Sub Principal : 5.1. NAND Logic Gate
Discussion 5.2. NOR Logic Gate
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
[66]
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”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[67]
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5.1. NAND Logic Gate
NAND logic gates are a combination of AND logic gates and gates
NOT logic, or AND logic gate which has an inverter at the output.
Figure 5.1 NAND logic gate symbol with 2 inputs
The Boolean equation for a NAND logic gate can be written as follows.
So the truth table for the NAND logic gate is as follows
Table 5.1 Truth Table for NAND logic gates
Input Output
A BQ =
0 0 1
0 1 1
1 0 1
1 1 0
It can be seen from the truth table that the output of the NAND logic gate (Q) will be
is 1 if any or all of the inputs are 0, only if all
the input has a value of 1 (A = 1, B = 1)
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Figure 5.2 NAND gate equivalent circuit
Figure 5.2 shows a logic circuit equivalent to
a NAND gate. NAND gate operation can be explained as follows.
If one of the inputs is low (switch is open), then operation
AND produces a low output (0) so it is the opposite (inversion) of the result
this gives a high final output (1). Only if all inputs are high (second
switch is closed) then the AND operation will produce high output (1) and
next the final output is low (0).
NAND IC components include:
1. IC TTL type 74LS00, 74LS10, 74LS20, 74LS30
2. CMOS IC type CD4011, CD4023, CD4012
The following is the pin configuration of several NAND logic gate ICs
Figure 5.3. NAND IC pin configuration
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5.2. NOR Logic Gate
A NOR (NOT OR) gate has two or more than two input signals
but only one output signal. To obtain high output, all
input must be low. This means that NOR only recognizes input
all bits are zero (low).
A NOR gate is a combination of an OR gate with
A inverter(NOT). With this gate arrangement, the output is NOT
from the results of the OR operation on the inputs. Originally this gate was called
NOT-OR gate but can be shortened to NOR gate.
Figure 5.4 NOR logic gate symbol with 2 inputs
The Boolean equation for a NOR logic gate can be written as follows.
So the truth table for the NOR logic gate is as follows
Table 5.2 Truth Table for NOR logic gate
Input Output
A B Q=
0 0 1
0 1 0
1 0 0
1 1 0
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It can be seen from the truth table that the output of the NOR logic gate (Q) will be
has a value of 1 if all inputs are 0, and will have a value of 0 if any
The input value is 1.
Figure 5.5 NOR gate equivalent circuit
Figure 5.4 shows a logic circuit equivalent to
a NOR gate. The operation of a NOR gate can be explained as follows. If
input is low (open switch), final output is high.
If one of the inputs is low and the other is high (switch closed), then
the output goes low (0) and if both inputs are high (both switches
closed), the output remains low (0).
NOR IC components include:
1. TTL IC type 74LS02, 74LS27, 74LS60
2. CMOS IC type CD4001, CD4025, CD4002
The following are several examples of NOR logic gate IC leg configurations.
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Figure 5.6 NOR logic gate IC pin configuration
SUMMARY
1. NAND logic gates are a combination of AND logic gates and gates
NOT logic, or AND logic gates that have an inverter on
the output.
2. The NOR gate is a combination of an OR gate with
A inverter(NOT).
EXERCISE
1. Draw the logic Gate circuit from the equation +
uses NAND and NOR logic gates
[72]
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 6
LOGIC GATES
EX-OR AND EX-NOR
Achievements : Students are able to form
Learning Gate From EX-OR gate and
EX-NOR and compiling tables
truth.
Sub Principal : 6.1. EX-OR logic gate
Discussion 6.2. EX-NOR logic gate
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
[73]
Machine Translated by Google
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[74]
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6.1. EX-OR Logic Gate
Ex-OR Logic Gate is a combination of complex logic gates
which is used to form arithmetic logic circuits, comparators and
circuit to detect errors. The EX-OR logic gate is a combination of gates
AND, OR and NOT logic. EX-OR is short for Exclusive OR.
The Ex-OR logic gate is symbolized as in Figure 6.1.
Figure 6.1 EX-OR Logic Gate Symbol
In Boolean algebra form, Ex-OR logic can be written as follows.
or it can also be described as Boolean algebra for Ex-OR as follows:
The truth table for Ex-OR logic is as shown in table 6.1.
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Table 6.1 Truth table for EX-OR logic gate with 2 inputs
Input Output
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
It can be seen from the truth table that if one of the two inputs is 1 (High), then
The output X will be 1 (High). If the input is 0 (Low) all or
all values are 1 (high), then the output X will have a value of 0 (Low).
Apart from having 2 inputs, Ex-OR logic gates also have 3 inputs
variable. The symbol for a logic gate with 3 variable inputs can be seen as shown in
the following image.
Figure 6.2 Ex-OR logic gate symbol with 3 variable inputs
The Boolean algebra for Ex-OR with 3 variable inputs can be written as follows
A truth table for Ex-OR logic with 3 variable inputs can be created
as seen in table 6.2.
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Table 6.2 Truth table for EX-OR logic gate with 3 inputs
Ex-OR logic gates can also be composed of logic gates
base. The following is the Ex-OR logic equivalence formed using
AND, OR and NAND gates.
Figure 6.3 Ex-OR logic made from OR, AND and NAND logic gates
The output of Figure 6.3 can be simplified as follows
by following De Morgan's rule, namely , then you get it
Where , then you get:
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Ex-OR logic gates can also be formed from NAND logic gates only, namely:
Figure 6.4 Ex-OR logic formed from NAND logic gates only
Ex-OR logic gates are usually used to create operating circuits
Adder and Half-Adder special arithmetic and calculations . Ex-OR logic gate
can function as a “carry-bit” or as an inverter controller, whichever is wrong
one input passes binary data and the other input functions as a signal giver
control.
Ex-OR logic gate ICs include:
1. IC TTL series 74LS86 Quad 2 input Ex-OR
2. CMOS IC 4030 series Quad 2 input EX-OR
The configuration of the IC legs can be seen as in Figure 6.5.
Figure 6.5 IC 74LS86 and 4030 quad 2 input Ex-OR pin configuration
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6.2. EX-NOR Logic Gate
The Ex-NOR logic gate is a combination of an Ex-OR logic gate with a gate
NOT logic.
Figure 6.6 Combined Ex-OR logic gate and NOT logic gate form
Ex-NOR logic
The Ex-NOR logic gate is symbolized as in Figure 6.7.
Figure 6.7 combined Ex-NOR logic gate
The Boolean algebra for the Ex-NOR logic gate can be written as follows:
The truth table for Ex-NOR logic is as shown in table 6.3
Table 6.3 EX-NOR logic gate truth with 2 inputs
Input Output
A B Q
0 0 1
0 1 0
1 0 0
1 1 1
Similar to Ex-OR logic gates, Ex-NOR logic gates also exist
which has 3 variable inputs as in Figure 6.8
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Figure 6. 8 Ex-NOR logic gate symbols with 3 inputs
The Boolean algebra for an Ex-NOR logic gate with 3 variable inputs is:
Then the truth table for Ex-NOR logic can be created as shown in the table
6.4.
Table 6.4 EX-NOR logic gate truth with 3 inputs
Similar to Ex-OR logic gates, Ex-NOR logic gates too
can be assembled using basic logic gates. One of them
can be seen in figure 6.9.
Figure 6.9 logic circuit formed from NOT, OR and AND logic gates
to form Ex-NOR logic
[80]
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Figure 6.9 shows a series of AND, OR and NOT logic gates
to form an Ex-NOR logic. In addition, Ex-NOR logic can also
formed using only NAND logic gates as shown
in figure 6.10.
Figure 6.10 NAND logic gate circuit to form Ex-NOR logic
The Ex-NOR logic gate is used to form the operating circuit
arithmetic and checking data such as ADDERS, SUBTRACTORS or PARITY
CHECKERS. EX-NOR logic gates can also be used for digital circuits
Comparator. ICs which are EX-NOR logic gates include:
1. IC TTL series 74LS66 quad 2 input Ex-NOR
2. CMOS IC 4077 series quad 2 input Ex-NOR
The Ex-NOR IC leg configuration can be seen in Figure 6.11.
Figure 6.11 pin configuration for IC 74LS66 and 4077
[81]
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SUMMARY
1. Ex-OR logic gates are usually used to create operating circuits
Adder and Half-Adder special arithmetic and calculations .
2. The Ex-NOR logic gate is used to form the operating circuit
arithmetic and checking data such as ADDERS, SUBTRACTORS or PARITY
CHECKERS
EXERCISE
1. Make a logic gate circuit from
[82]
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 7
REVIEW MEETING 1 TO
MEETING 6
Achievements : Students are able to review
Learning meeting materials 1 to
with meeting 6.
Sub Principal : 7.1. Review material from meetings 1
Discussion
to meeting 6
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
[83]
Machine Translated by Google
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[84]
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7.1. Review Material from Meeting 1 to Meeting 6
The material provided from meeting 1 to meeting 6 is:
1. Number Systems and Number Operations (Binary, Octal, Decimal and
Hexadecimal)
2. Number Conversion (Binary, Octal, Decimal and Hexadecimal)
3. Logic Gates and truth tables (AND, OR, NOT)
4. Boolean Algebra
5. NAND and NOR Logic Gates and constructing truth tables
6. EX-OR and EX-NOR Logic Gates and constructing a truth table
A number system is a way to represent the size of an item
physique. The various types of number systems are Binary number systems, Number systems
Octal, Decimal number system, and Hexadecimal number system.
Number weight is the equivalent value of a number in the system
decimal number. The weight of the number will depend on the radix and the order of the digits
the digits.
The Binary System is a number system that only uses two symbols
(0.1). This number is usually said to have a radix of 2 and is usually called
base 2 numbers, each binary digit is called a bit. The octal number system has
base or radix 8 with digits 0, 1, 2, 3, 4, 5, 6, and 7. Number system
decimal has a base or radix of 10 with the digits being 0, 1, 2, 3, 4, 5, 6, 7, 8,
and 9. The hexadecimal number system has a base or radix of 16 with its digits
are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e and f. Where A = 10, B = 11, C= 12,
D = 13 , E = 14 and F = 15.
Number conversion is a process in which one number system with
A certain base will be made into a number with another base. In general
to convert a certain number to a certain number can be done with
calculate the weight of the number (in decimal number form), next
Conversion is carried out to the desired number by dividing
with the radix of the target number until it runs out
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AND logic gates are called “All or none” gates. Expression
The Boolen equation for the AND logic gate is:
Q=A.B
The OR logic gate is also called “any or all”. Equation expression
The Boolean for OR logic is:
Q=A+B
The NOT gate is a logic circuit that functions as an "Inverter".
The NOT logic gate has a Boolean expression:
Boolean algebra uses the values 1 and 0 as input and output. Value 0
and 1 corresponds to the binary number system. Boolean algebra is basic
in designing digital circuits and use in computing equipment
modern today.
There are 2 types of theorems in Boolean algebra, namely variable theorems
single and multiple variable theorems.
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NAND logic gates are a combination of AND logic gates and gates
NOT logic, or AND logic gate which has an inverter at the output.
The Boolean equation for a NAND logic gate can be written as
following.
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A NOR gate is a combination of an OR gate with
A inverter(NOT). With this gate arrangement, the output is NOT
from the results of the OR operation on the inputs. Originally this gate was called
NOT-OR gate but can be shortened to NOR gate.
The Boolean equation for a NOR logic gate can be written as
following.
The Ex-OR gate is a combination of complex logic gates
which is used to form arithmetic logic circuits, comparators and
circuit to detect errors. EX-OR logic gate is a combination of gates
AND, OR and NOT logic. EX-OR is short for Exclusive OR.
In Boolean algebra form, Ex-OR logic can be written as follows
This.
or it can also be described as Boolean algebra for Ex-OR as follows:
Ex-OR logic gates are usually used to create operating circuits
Adder and Half-Adder special arithmetic and calculations .
The Ex-NOR logic gate is a combination of the Ex-OR logic gate with
NOT logic gate.
The Boolean algebra for the Ex-NOR logic gate can be written as follows:
The Ex-NOR logic gate is used to form the operating circuit
arithmetic and checking data such as ADDERS, SUBTRACTORS or PARITY
CHECKERS.
[88]
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SUMMARY
1. There are 4 types of number systems, namely Binary number system, Number system
Octal, Decimal number system, and Hexadecimal number system. Every
This number system has a Base or Radix (r), which is the number
numbers and Digits (d) used in a number.
2. Number conversion is a process in which one number system with
A certain base will be made into a number with another base. In general
to convert certain numbers to certain numbers can be done
by calculating the weight of the number (in decimal number form),
Next, the conversion is carried out to the desired number by means of
perform division by the radix of the target number until it is finished.
3. There are three types of basic logic gates, namely AND logic gates, gates
OR Logic and NOT Logic Gates.
4. Boolean algebra is the basis for designing digital circuits and
used in today's modern computing equipment.
5. NAND logic gates are a combination of AND logic gates and gates
NOT logic, or AND logic gates that have an inverter on
the output.
6. A NOR gate is a combination of an OR gate and an OR gate
inverter(NOT).
7. Ex-OR logic gates are usually used to create operating circuits
Adder and Half-Adder special arithmetic and calculations.
8. The Ex-NOR logic gate is used to form the operating circuit
arithmetic and checking data such as ADDERS, SUBTRACTORS or PARITY
CHECKERS.
[89]
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EXERCISE
1. Calculate the weight of the number from (342.71)8
2. 432(8) = ......... (10)
= ......... (16)
= ........(2)
3. Create a logic gate from the equation
4. Determine the value are: A = 0, B = 0, C = 1, D = 1.
5. Draw the logic Gate circuit from the equation
+ uses NAND and NOR logic gates
6. Make a logic gate circuit from
[90]
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 8
MIDTERM EXAM
Achievements : Students are able to answer
Learning and solve problems
given in the question.
Sub Principal : 8.1. Midterm Exam Questions
Discussion
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
[91]
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questions, Second edition, publisher
Erlangga, 1996
5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[92]
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8.1. Midterm Exam Questions
1. Convert the numbers below
a. 653 (10) =.......... (8)
b. 1011.1001 (2) = .......... (10)
c. 2A6(16) = ..........(10)
d. 111001010011.010110011 (2) = .......... (8)
2. 11100011(2) - 1100110(2) = .....
3. 345 (8) - 267 (8) = ....
4. ABE (16) – 128 (16) = ....
5. Using the 2's Complement Method calculate 167 – 244 =
6. Determine the equation of X!
7. Determine the equation of F!
[93]
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 9
K-MAP (MINIMATION)
Achievements : Students are able to understand maps
Learning Karnough.
Sub Principal : 9.1. Minimization
Discussion
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2.M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988, Electronics
Digital Computer.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
[94]
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5.Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[95]
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9.1. Minimization
Karnaugh Map or what is usually called K-Map is a technique
simplifying logical functions by mapping. K-Map consists of boxes
which consists of the number of variables and logic functions or the number of inputs
of the logic circuit we are calculating.
The formula for determining the number of boxes in a K-Map is 2n . n is
the number of variables / inputs.
General K-Map mapping steps:
• Compile Boolean algebra first
• Draw digital circuits
• Create a Truth Table
• Formulate the Truth Table
• Then enter the Truth Table formula into the K-Map (Checkerboard
K-Map Rules
1. Each group formed cannot contain any cells
contains zero values
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2. A group may be formed horizontally or vertically,
but it can't be diagonal.
3. The number of cells per group allowed is 2n . Like 1,
2, 4, 8, and so on.
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4. Each group must be formed with a large number of cells
thus producing as few groups as possible.
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5. Every cell that contains the value 1, must be part of a
group.
6. Groups are allowed to overlap
[99]
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7. Groups are allowed by Wrapping
Simplification of Two Variables
Note: Bar =
The table of K-Map 2 variables is as follows
Problems example
[100]
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So the way to do it is as follows
Bar / is usually written as the number 0 while the
number 1 is without Bar / without
And it can be simplified further as follows
can be simplified in K-Map to only 2 / multiples of 2 from the box
next to each other while if it is like the box above then the simplification is as
following
Grouping the K map into 01 + 11 and 10 + 11. Method
The simplification is by writing the same number (1 circle) and translating it into letters
such as A and B.
The method :
01
11
1 The same thing is the number 1 at the back, because it is located at the back
(second) then it is B (B is taken from the K-Map table above). If the same
the number 0 in second place is . It has been mentioned above that
[101]
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number 0 = Bar/ .
10
11
1 The same is the number 1 in front, because it is located in front
(first) then it is A (A is taken from the K-Map table above). If the same
the number 0 in the first sequence is . It has been mentioned above that
number 0 = Bar/ .
So the conclusion from the example above is from the equation:
H = AB + B + A can be simplified using K-Map to BA / AB
(can be reversed alphabetically but must be 1 friend or cannot be reversed with
letters separated by addition or subtraction).
Three Variable Simplification
Note: Bar =
The table of K-Map 3 variables is as follows
Problems example
H = ABC + BC+ C+AC
So the way to do it is as follows
Bar / is usually written as the number 0 while number 1 is without Bar / .
[102]
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And it can be simplified further as follows
What can be simplified in K-Map is only 2 / multiples of 2 from the box
next to each other and whereas if it is like the box above then it is simplified
become
Grouping the K map into 001 + 011 + 101 + 111 is the method
simplification by writing the same number (1 circle) and
translate it into letters like A, B, C.
The method :
011
011
101
111
The same 1 is the third 1 from the front, because it is located third
from the front then it is C (C is taken from the K-Map table above). If the same
the number 0 in the third place is . it has been mentioned above
that the number 0 = Bar/ .
So the conclusion from the example above is from the equation:
H = ABC + BC+ C+AC can be simplified using K-Map to C.
[103]
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Simplification of 4 variables
Note: Bar =
The table of K-Map 4 variables is as follows
Problems example
H=
So the way to do it is as follows
Bar / is usually written as the number 0 while the number 1 is without Bar /
And it can be simplified further as follows
What can be simplified in K-Map is only 2 / multiples of 2 from the box
next to each other, whereas if it were like the box above then the simplification would be
as follows
[104]
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Grouping the K map into 1111 + 1011 and 1111 + 1110 and 1110 +
1100. The method above simplifies it from the far right side by side
leftmost in 1 row.
The simplification method is by writing the same number (1 circle) and
translate it into letters like A, B, C, D.
The method :
1111
1011
The same 1 11 is the first, third and fourth 1. Therefore
are A, C, and D (A, C, and D are taken from the K-Map table above) if they are the same
the number 0 in the first, third and fourth then that is .
It was mentioned above that the number 0 = Bar/ .
1111
1110
The same 111 is the first, second, and third 1. Then it is
A, B, C (A, B, C taken from the K-Map table above) if the same number is 0 in
first, second, and third order then that is . Above already
it is stated that the number 0 = Bar/ .
1110
1100
11 The same thing is the first and second number 1. Then it is A and
B (A and B are taken from the K-Map table above) if the same number is 0 in the sequence
first and second then that is . It has been mentioned above that numbers
0 = Bar/ .
So the conclusion from the example above is from the equation:
[105]
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H = AB + A'B + AB' can be simplified using K-Map to become
ACD + ABC + ABD' (can be reversed alphabetically but must be 1 friend or not
can be reversed with letters separated by addition or
subtraction).
SUMMARY
1. General K-Map mapping steps:
• Compile Boolean algebra first
• Draw digital circuits
• Create a Truth Table
• Formulate the Truth Table
• Then enter the Truth Table formula into the K-Map (Checkerboard
2. K-Map Rules
• Each group formed cannot contain cells containing zero values
• A group may form horizontally or vertically, but not
can be diagonal.
• The number of cells per group allowed is 2n. Like 1, 2, 4, 8,
etc
• Each group must be formed with a large number of cells so that
produce as few groups as possible
• Every cell that contains the value 1, must be part of a group
• Groups are allowed to overlap
• Groups are allowed by Wrapping
EXERCISE
Simplify with K-Map
[106]
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 10
K-MAP (IMPLICATIONS)
Achievements : Students are able to understand maps
Learning Karnough.
Sub Principal : 10.1. Sum Of Product (Minterm)
Discussion 10.2. Product Of Sum (Maxterm)
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital
Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
[107]
Machine Translated by Google
Erlangga, 1996
5. Rummi Sirait, Teaching Materials
System Digital, Faculty
Budi Luhur University Engineering,
2009
[108]
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10.1 Sum Of Products (Minterm)
A boolean function can be expressed in the form of SOP (Sum of Product), namely
the sum of multiplications.
The SOP form can be expressed in the minterm function.
is the minterm function.
Example :
State the function into the form of SOPs and minterm functions
appropriate !
Solution:
Steps taken:
– Explain the multiplication.
– Determine the number of existing variables.
In this example question there are 4 variables: A, B, C, D
– Complete each existing group so that it contains all four variables
exists (done by multiplying by the sum of the variables
not yet available with complement)
Form a complete SOP from Y to determine the appropriate minterm function
– State the desired minterm function.
A, B, C, D = 1
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11111011111010100111 110001100100
15 11 14 10 7 12 6 4
And the desired minterm function is:
10.2 Product Of Sum (Maxterm)
A boolean function can be expressed in POS (Product of Sum) form.
namely the multiplication of the sum.
The POS form can be expressed in the maxterm function.
is the maxterm function.
Example :
State the function into POS form and maxterm function
appropriate!
Completion
Remember :
So the form of the question can be
ÿ desired POS form
To determine the maxterm function, it must be derived.
Remember :
So it becomes
Complete each existing group so that it contains all four variables
exists (done by adding and multiplying the variables
not yet available with complement)
[110]
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State the desired maxterm function.
A, B, C, D = 0
0000000100100011
0 1 2 3
0000000110001001
0 1 8 9
00010101 1001 1101
1 5 9 13
And the desired maxterm function is:
SUMMARY
1. A boolean function can be expressed in the form of SOP (Sum of Product)
namely the sum of multiplications.
2. The SOP form can be expressed in the minterm function.
3. A boolean function can be expressed in POS (Product of Sum) form
namely the multiplication of the sum.
4. The POS form can be expressed in the maxterm function.
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EXERCISE EXAMPLES
Given f(A,B,C,D) = m (0, 1, 2, 3, 6, 7, 12, 13, 14, 15)
a. Create a suitable K-Map
b. Simple SOP function
c. The logic gate circuit of the SOP function
d. Simple POS function
e. Logic Gate Circuit for the POS function
Solution:
f(A,B,C,D) = m (0, 1, 2, 3, 6, 7, 12, 13, 14, 15)
a. Corresponding K-Map
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b. Simple SOP form
There are 3 groups of K-Map created
Group 1 :
Group 2 :
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Group 3 :
So the SOP function has been simplified with K – MAP:
c. The logic gate circuit of the SOP function
d. Simple POS function
[114]
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There are 3 groups of K-Map created
Group 1 :
Group 2 :
Group 3 :
So the SOP function has been simplified with K – MAP:
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e. Logic Gate Circuit for the POS function
EXERCISE
1. State the function into the form of SOPs and minterm functions
in accordance !
2. State the function into POS form and maxterm function
appropriate!
[116]
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 11
CODE CHANGING
Achievements : Students are able to understand
Learning code change
Sub Principal : 11.1.BCD 8421
Discussion 11.2.Binary Complement
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
[117]
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5. Rummi Sirait, Teaching Materials
Digital Systems, Faculty of Engineering
Budi Luhur University, 2009
[118]
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11.1. BCD 8421
BCD code is a code that uses binary coded decimal
(Binary-code decimal). This BCD code consists of 4 (four) bits, 5 bits, and
which is more than 5 bits, which means each decimal number represents 4 bits
(binary digit), 5 bits, or more than 5 bits.
The BCD code consisting of 4 bits that is commonly used is BCD 8421
because it is identical to binary numbers up to 9 decimal numbers and above 9
different from binary numbers.
Example :
1. What is BCD 8421 of 684 decimal numbers?
Answer :
6 = 0110
8 = 1000
4 = 0100
So 68410 = 0110 1000 0100BCD 8421
2. How much BCD is 8421 of (7289)10?
Answer :
7 = 0111
2 = 0010
8 = 1000
9 = 1001
So BCD 8421 of 7289 = 0111 0010 1000 1001
From the example above, it can be seen that each decimal number represents 4 bits
BCD 8421. Because the BCD 8421 code is the most basic type of code,
then it is usually written as BCD only. Therefore, between decimal numbers
binary numbers, and the BCD code 8421 can be made into a conversion table like
seen in table 11.1.
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Table 11.1 Conversion Table for Decimal Numbers, Binary Numbers and BCD Numbers
Decimal Binary BCD
0 0 0000
1 1 0001
2 10 0010
3 11 0011
4 100 0100
5 101 0101
6 110 0110
7 111 0111
8 1000 1000
9 1001 1001
10 1010 0001 0000
11 1011 0001 0001
12 1100 0001 0010
13 1101 0001 0011
14 1110 0001 0100
15 1111 0001 0101
16 10000 0001 0110
17 10001 0001 0111
18 10010 0001 1000
19 10011 0001 1001
20 10100 0010 0000
From table 11.1 it can be seen that to convert decimal numbers to BCD
It's very easy as long as the BCD from decimal 0 to 9 is memorized correctly and BCD
is the same as binary from decimal 0 to 9. Additionally, in binary addition
Of course it's easier than adding BCD because the result of adding BCD if
more than 9, then the sum result will be wrong. More details can be found
Look at some of these examples.
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Example :
1. What is the sum of the decimal 16 + 7 in binary and BCD?
Answer :
Binary BCD wise
16 10000 0001 0110
7+ 111+ 0111+
23 10111 0001 1101
If you look at the addition in binary and decimal, the result is
is right. However, the BCD addition, 1101 is not recognized in the BCD code.
This means that the BCD addition is not complete. how to solve it?
How to solve BCD addition if it is more than decimal 9, then
then added 0110 or 6. This is done because there are 6 possibilities
which exists. This means that BCD only uses 10 possibilities, namely from 0000 to
with 1001.
Therefore, the example above can be solved as follows:
0001 0110
0111+
0001 1101
0110+
0010 0011
So 0001 0110 + 0111 = 0010 0011
2. What is the result of adding 28 + 17 in BCD?
Answer :
28 0010 1000
17+ 0001 0111 +
45 0011 1111
0110+
0100 0101
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3. What is the result of adding 349 + 57 in BCD?
Answer :
349 0011 0100 1001
75+ 0111 0101 +
424 0011 1011 1110
0110 0110 +
0100 0010 0100
So 0011 0100 1001 + 0111 0101 = 0100 0010 0100
From the 3 examples above, it can be seen that each sum results in more
from 1001, then 0110 must be added.
11.2. Binary Complement
Expressing Number Signs
In binary machines, binary numbers are represented by a set
binary storage device (usually a Flip-Flop). For example, a 6 bit FF register can
stores binary numbers from 000000 to 111111 (0 to 63 in decimal)
. This expresses the magnitude of a number. Because almost all computers and calculators
digital handles positive numbers as well as negative numbers, a
method is needed to express the number sign (+ or -). This is usually done
by adding another bit to the number called the sign bit
. The generally accepted convention is that 0 in the sign bit represents
positive numbers and 1 in the sign bit represent negative numbers. This is shown
in figure 6. register A contains the bits 0110100. 0 is the leftmost bit (A6)
is the sign bit which indicates positive. The other six bits represent the magnitude
the number 1101002, which is equal to 52 in decimal. So that number
stored in register A is +52. Likewise, numbers are stored
in register B is -31, because the sign bit is 1 which represents negative.
The sign bit is used to indicate whether the stored binary number is positive or negative.
For positive numbers, the remaining bits (other than sign
bit) is always used to express the size of a number in binary form.
But for negative numbers there are three forms that are used for
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expresses the magnitude of a binary number, namely true-magnitude form, form
1st complement, and 2nd complement form.
Figure 11.1. Expressing Number Signs
True Magnitude Form True
Magnitude form is the representation shown in figure 2.1,
where the actual magnitude of the number is given in binary form. First bit
is always a sign bit.
1st Complement Form
The 1st complement form of every binary number is obtained by
changes every 0 in the number to a 1, and every 1 in the
number becomes 0. In other words, it changes each bit to its complement.
For example, the 1st complement of 101101 is 010010, and the 1st complement of
011010 is 100101. When negative numbers are expressed in the form
1's complement, the sign bit is made 1 and the size is converted from binary form
actually becomes its 1st complement. For example, the number -57 will be
stated as follows:
Note that the sign bit is not complemented but kept constant
as 1 to indicate a negative number. Here are some additional examples
of negative numbers expressed in 1's complement form.
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- 14 = 10001
-7.25 = 1000.10
- 326 = 1010111001
2nd Complement Form
The 2nd complement form of a binary number is formed by
takes the 1's complement of the number and by adding 1 to the
least significant bit position. The procedure is shown as below for
Converts 111001 (decimal 57) to its 2's complement form.
So, in 2's complement representation of – 57 would be written as
1000111. Also here, the leftmost bit is the sign bit. the other 6 bits
is the 2nd complement form of the magnitude of the number. As another example
The 2nd complement of -14 is written 10010. The three forms of expressing numbers are
The negative numbers for -57 are summarized in Figure 2.2.
Figure 11.2. Three ways are used to represent binary numbers
negative
These three forms are now used in digital systems.
Some digital machines store negative numbers as true
magnitude form, but first convert it to 1's complement or
2's complement before performing each arithmetic operation. Machine-
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Other machines store negative numbers in 1's complement form and
2nd complement. On almost all modern digital machines, for operations
Arithmetic operations on negative numbers are in 1's complement or
2nd complement form. Currently, 2nd complement representation is the most common
used. It must be remembered that in all three systems, the true magnitudes are complementary
1st and 2nd's complement, positive numbers are always in binary form
actually and with sign bit 0. The difference lies in the representation
the negative numbers. Use of 1's complement forms and
2's complement due to its use makes it possible to perform operations
subtraction using only the addition operation. This is important because
means that a digital machine can use the same circuit for
both add and subtract, therefore saving space
and tools.
Changing Complement Form to Binary
To convert from 1's complement to true binary only
required to complement each bit again. To change from
2's complement to binary is actually only needed for
complements each bit and then adds 1 to its LSB.
Addition in the 2nd Complement System
The 1st complement system and the 2nd complement system are very similar.
But however, the 2nd complement system is the commonly used one
because of the advantages contained in the implementation of the series.
Case I: Two Positive Numbers
The addition of two positive numbers is direct.
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Note that the sign bit of the added and the added two-
both are 0 and the sign bit of the sum is 0, indicating that
this number is positive. Also note that the plus ones and the ones
add is made to have the same number of bits. This should always be done
in the 2nd complement system.
Case II: Positive Numbers and Smaller Negative Numbers
For example, adding +9 and -4. Remember that -4 will be in complement form
to 2. So, +4 (00100) should be changed to -4 (11100).
Note that the sign bits are also involved in the process
summation. It turns out that a carry is generated at the position of the addition result
final. This carry is always ignored, so the final sum is equal to 00101 (+5).
Case III: Positive Numbers and Larger Negative Numbers
Example of adding -9 and +4.
Here the number has sign bit 1, which indicates a number
negative. Since the sum is negative, it is the to's complement form
2, so the last four bits (1011) represent the 2's complement of 0101
(equivalent to decimal 5). So 11011 is equivalent to -5.
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Case IV: Two Negative Numbers
Again this result is negative and in 2nd's complement form with
sign bit 1.
Case V: Equal and opposite numbers
Reduction in the 2nd Complement System
Subtraction operation using the 2nd complement system
actually involves an addition operation and is not at all different
with various kinds of cases which have been discussed in sub-chapter 1.9. When
subtracting one binary number from another binary number, then the procedure
are as follows :
1. Find the 2nd complement of the subtractor, including the sign bit. If
the subtractor is a positive number, so it must be changed to
a negative number in 2's complement form. If the subtractor is
is a negative number, this will convert it to a positive number
in true binary form.
2. After finding the 2's complement of the subtractor, add it to
which is reduced. The subtracted number is retained in the form
the original. The result of this addition is the difference sought. Sign bits of
This difference determines whether the sign is + or – and whether it is a
true binary form or 2nd complement form.
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Example :
Which is reduced (9) 01001
Subtraction (+4) 00100
Change the subtractor to its 2's complement (11100). Now add it
this number with subtracted:
SUMMARY
The conversion code is a BCD Code consisting of 4 common bits
used is BCD 8421 because it is identical to binary numbers up to the number 9
decimal number.
EXERCISE
1. What is the result of adding the decimal 10 + 8 in binary and in binary
BCD?
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 12
FLIP FLOP
Achievements : Students are able to understand
Learning flip-flop working principle and
use
Sub Principal : 12.1. Flip Flop Definition
Discussion 12.2. SR Flip Flop
12.3. JK Flip Flop
12.4. D Flip Flop
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital
Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
[129]
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”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5. Rummi Sirait, Teaching Materials
System Digital, Faculty
Budi Luhur University Engineering,
2009
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12.1. Flip Flop Definition
A flip-flop has 2 stable states, and will stay in one of them
two states until a trigger occurs that causes them to change states. Flip-
flop is sometimes also called button, multivibrator, binary, but currently it will be used
just the term flip-flop.
Flip-flops can be assembled from NAND logic gates or can be purchased pre-assembled
I.C. Flip-flops are used for storage, timing, counting and sequencing
A flip-flop is a single memory cell. The flip-flop output state can be
in high/low state for the desired time interval. For
Changing this state requires a trigger input. Flip-flops have
2 complementary outputs, namely Q and Q'.
Flip-flops is a digital system that has bistable and synchronous properties
(synchronous bistable). The synchronous nature means that the flip-flop output will
changes if and only if a clock signal is given. Output changes
This occurs synchronously with the given clock signal
Flip-flops are a type of multivibrator. There are 3 types of multivibrators:
1. Monostable Multivibrator ( one-shot multivibrator ), this type of multivibrator only
stable in one logic state (stable in either LOW or HIGH).
2. Bistable Multivibrator, this type of multivibrator is stable in both logical states
(stable at LOW and stable at HIGH).
3. Astable Multivibrator, this type of multivibrator is unstable in both states
logic (unstable at LOW and unstable at HIGH), often used as
oscillator (beat signal generator).
NAND Gate Latch
The basic Flip-Flop circuit can be composed of two NAND or NOR gates
gate. If it is composed of NAND gates, it is called a NAND gate latch or system
simply called a latch, as shown in figure 12.1 (a). Two NANDs
The gate is crossed between the NAND gate-1 output connected to one of the NAND gate-2
inputs, and vice versa. The gate output (output latch) is named Q and Q'.
Under normal conditions the two outputs are opposite to each other. Latch input is given
names SET and RESET. Figure 12.1 (b) shows the symbol of a NAND gate latch.
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Figure 12.1 NAND gate latch
Table 12.1. NAND gate latch truth table
Set Reset FF output
1 1 Q (unchanged)
0 1 Q = 1; Q' = 0
1 0 Q = 0; Q' = 1
0 0 Uncertain
Overview of NAND gate latch:
1. SET = 0, RESET = 1 always results in Q = 1, regardless
previous FF output state. This is called setting or setting FF on
state 1 or high state.
2. SET = 1, RESET = 0 always results in Q = 0, regardless
previous FF output state. This is called resetting FF to state 0 or
low state.
3. SET = 1, RESET = 1 does not affect the FF state. FF remains on
previous situation.
4. SET = 0 , RESET = 0 is an erratic state and should not be
used.
NOR Gate Latch
Two NOR gates that are crossed together are known as a NOR gate latch.
with two opposing outputs Q and Q' and two SET inputs
and RESET, as shown in figure 12.2 If logic 1 is given at the input
S, then this condition causes FF to be set to 1 (Q=1). If logic 1 is assigned to
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input R, then this condition causes FF to be reset to 0 (Q=0).
Figure 12.2 NOR gate latch
Table 12.2. NOR gate latch truth table
Set Reset FF output
0 0 Q (unchanged)
1 0 Q = 1; Q' = 0
0 1 Q = 0; Q' = 1
1 1 Uncertain
Overview of NOR gate latch:
1. SET = 1, RESET = 0 always results in Q = 1, regardless
previous FF output state. This is called setting or setting FF on
state 1 or high state.
2. SET = 0, RESET = 1 always results in Q = 0, regardless
previous FF output state. This is called resetting FF to state 0 or
low state.
3. SET = 0, RESET = 0 does not affect the FF state. FF remains on
previous situation.
4. SET = 1 , RESET = 1 is an erratic state and should not be
used.
5. price 1 in SET or RESET, which is used to change the state
FF, can be a DC voltage or a momentary pulse.
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Clock Pulse (Clock Signal)
Almost all digital systems operate as sequential systems
synchronous or synchronous sequential system. What is meant is that sequence
operations are synchronized by a pulse called a clock pulse. Clock pulses ie
periodic pulses that are usually square (duty cycle 50%),
as shown in figure 12.3.
Operations that occur in a digital system are attempted to occur on
the times a clock pulse transitions from 0 to 1 or from 1 to 0. Times
This transition is shown in Figure 12.3. The 0-to-1 transition is called the rising edge
edge) or the edge towards the positive, the transition from 1-to-0 is called the falling edge
or the side towards the negative.
Figure 12.3 Clock Pulse (Clock signal)
These clock pulses are used in the Flip-Flop to change states
on either the rising or falling side of the clock pulse. In other words a clock pulse
The FF will change states at the appropriate clock transition and will
silence/rest (rest) between consecutive clock pulses. Frequency of pulse-
The clock pulse is usually determined by how long the FF takes and
gates in the circuit to respond to levels of changes
changes commanded by clock pulses.
12.2. SR Flip Flop
Figure 12.4 shows a clocked SR flip-flop commanded by
the positive side of the clock pulse. This means that FF will change state
only when a signal is given to the clock input (abbreviated as CLK or C )
performs a transition from 0 to 1. The S and R inputs control the FF state
in the same way as described for the basic SR FF (unclocked),
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but the FF will not respond to these inputs until now
the rising edge transition of the clock pulse occurs. This is indicated by the waveform
in figure 12.5
Figure 12.4 Clocked SR Flip-Flop with high active clock pulse
The SR flip-flop truth table is as shown in table 12.3.
Table 12.3 S - R Flip flop truth table
If S = 1, R = 0, the flip-flop will be in the SETS state when changing
LOW to HIGH logic. The input logic values S and R can be changed at any time (on
when the clock signal is LOW or HIGH) except around the clock signal transition).
Diagrammatically, the time can be explained in Figure 12.5.
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Figure 12.5 S – R Flip flop timing diagram
From figure 12.5 it can be seen that the FF output is not affected by the leading edge
negative of the clock pulse. Also note that the S and R levels are missing
influence on FF except when there is a transition to the positive of the pulse
clock. The S and R inputs are essentially controller inputs, which are
controls which state the FF output goes to when a clock pulse occurs. Clock input
is the trigger input, which actually causes a change in the FF state
corresponds to the levels of the S and R inputs.
Figure 12.6 shows the symbol for a Clocked SR FF that is CLK
The input gets triggered when it transitions to negative. That little circle
drawn on the CLK input shows that this FF will be triggered on
when CLK changes from 1 to 0.
Figure 12.6 Clocked SR Flip-Flop with low active clock pulse
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In fact, the internal circuit of the Clocked SR FF already exists in IC form,
The circuit consists of two parts, namely:
1. NAND latch composed by NAND-3 and NAND-4
2. A series of pulses composed by NAND-1 and NAND-2
Figure 12.7 Clocked SR Flip-Flop Circuit
12.3. JK Flip Flop
Figure 12.8 shows a clocked JK FF that is edge-triggered
towards the positive of the clock pulse. The J and K inputs control the FF state with
the same way as S and R inputs except for one major difference: state
J = K = 1 does not produce an uncertain output. for this situation
FF will always be in the opposite state.
Figure 12.8 Clocked JK Flip-Flop
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The JK flip-flop truth table is as shown in table 12.4.
Table 12.4 J - K Flip flop truth table
The operation of this FF is shown by the waveform in Figure 12.9,
which can be analyzed as follows:
1. Initially all inputs are 0 and the output Q is equal to 1.
2. If the positive side of the first clock pulse occurs
conditions J=0 and K=1, then the output Q=0
3. The second clock pulse gets J=0 and K=0 when making the transition
positively, this causes the output Q to remain at its previous state i.e
Q=0.
4. The third clock pulse gets J=1 and K=0 when making the transition
positively, this causes the output Q=1.
5. The fourth clock pulse gets J=1 and K=1 when making the transition
positively, this causes FF to toggle so that the output Q is opposite of
previous condition, namely being Q=0.
Figure 12.9 J – K Flip flop timing diagram
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From this waveform it should be noted that FF does not
affected by the negative side of the clock pulse. JK FF is much better
than SRFF because it does not have uncertain working conditions.
The state J=K=1, which produces the toggle operation, is very common
its use in all types of binary calculating devices. Therefore, JKFF
widely used in almost all digital systems.
Figure 12.10 JK FF circuit
12.4. D Flip Flop
Figure 12.11 shows the symbol of a clocked D FF that gets
trigger of a positive transition on the CLK input. D input is a controller input
single that determines the working state of the FF according to the truth table. On
In essence, the Q FF output will enter the same working state as that
exists at the D input if a positive transition occurs at the CLK input.
Note that every time a positive transition occurs in the CLK input, output
Q has the same value as that at input level D. Transition
Negative CLK input has no effect.
Figure 12.11 Clocked D Flip-Flop
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The truth table for the D flip-flop is as shown in table 12.5
Table 12.5 D Flip flop truth table
Figure 12.12 D Flip flop timing diagram
D FF is principally used in binary data transfer. SR FF and JK FF
can easily be modified to operate as a D FF as shown
in figure 12.13.
Figure 12.13 Arrangement of JK FF working as D FF.
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D FF can also be formed from NAND gates as shown in Figure 12.14.
Figure 12.14. D FF which is composed of NAND gates
SUMMARY
A flip-flop is a single memory cell. The flip-flop output state can be
in high/low state for the desired time interval. For
Changing this state requires a trigger input. Flip-flops have
2 complementary outputs, namely Q and Q'.
EXERCISE
1. Explain the main differences between SR FF and JK FF
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 13
T - FLIP FLOP
Achievements : Students are able to understand
Learning principle Work flip-flop and
use
Sub Principal : 13.1.T flip-flop
Discussion
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital
Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
[142]
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questions, Second edition, publisher
Erlangga, 1996
5. Rummi Sirait, Teaching Materials
System Digital, Faculty
Budi Luhur University Engineering,
2009
[143]
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13.1. T Flip Flop
T FF can be formed from modifications Cloked SR FF, D FF, and JK FF. On
Figure 13.1 shows the JK FF modification used as a T FF. T FF
has an input terminal T and two output terminals, namely Q and Qnot.
Inputs J and K on JK FF are connected with logic "1" or in series
The discrete is connected to VCC +5 Volt, while the input is T FF
is clock on JK FF. The output state Q will change every time there is a pulse clock
(trigger signal) at its input.
Figure 13.1. The T FF circuit is built from the JK FF.
T FF or flip-flop toggle is a flip-flop circuit that can be built from
modification clocked RS FF, D FF and JK FF. Named toggle Because
the ability of this flip-flop to change its state.
Figure 13.2. Toggle Circuit Symbol with FF RS.
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Figure 13.3. Toggle Circuit Symbol with FF JK.
Figure 13.4. Toggle Circuit Symbol with FF D.
The T-FF circuit is formed from SR-FF by utilizing the Set relationship
and Reset as well as outputs Q and Q' which are fed back to inputs S and R. T-
FF formed from JK-FF only needs to add the value "1" to the J inputs
and K (remember nature toggle from JK-FF). The T-FF circuit is formed from D FF only
by adding a simple combinational circuit to the input.
FF JK working principle:
• The two inputs (J and K) are combined into one so that only one exists
one way in and you will get a flip-flop that has an output
reversed from before.
• Output (Q) will always be toggle or contrary to previous conditions,
If a logic 1 input is given, the output condition will be
remains or is the same as the previous output condition when given input
logic 0.
• If the flip-flop output state is 0, then after a trigger signal
the next state becomes 1 and if the state is 1, then there is
trigger state changes to 0.
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• If T FF is kept high then each clock pulse changes
causes the output state to change.
• The same process will occur when the next pulse comes on
input because the output varies between logic 1 and 0 accordingly
with input pulse. Thus, changes in output will occur
at half the frequency of the input.
Table 13.1 T Flip Flop Truth Table
Inputs Outputs
Q Qn+1
0 Qn Hold / remain
1 Toogle
or
Inputs Present Next State
Q State Q'
Q
0 0 0
1 0 1
0 1 1
1 1 0
The T input is the only input on this type of flip-flop,
while the output remains two, like all flip-flops in general. T symbol
means Toggle, which indicates that the circuit will mend toggles (invert)
state output when T = 1. The graphic symbol of T FF is as follows:
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SUMMARY
T FF can be formed from modifications Cloked SR FF, D FF, and JK FF.
EXERCISE
1. What flip-flops can T flip-flops be built from?
2. Explain the characteristics of T flip-flop?
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BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 14
COUNTERS
Achievements : Students are able to understand
Learning how the counter circuit works.
Sub Principal : 14.1. Asynchronous Binary Up
Discussion Counters
14.2. Asynchronous Binary
Down Counter Counter
Decade
14.3. Asynchronous Up Down
Counters
14.4. Synchronous Binary Up
Counters
14.5. Synchronous Binary Down
Counters
14.6. Synchronous Binary Up
Down Counter
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Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital
Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5. Rummi Sirait, Teaching Materials
System Digital, Faculty
Budi Luhur University Engineering,
2009
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Counter is a sequential logic circuit that can function for
calculates the number of incoming pulses expressed in binary number form.
Almost all electronic equipment uses a digital system internally
The circuit contains a tool that can control the sequence of program operations. Tool
is called counter or counter.
In general, counters are formed from several series of flip-flops
The amount is adjusted according to needs. According to how credit input works
into each flip-flop, the counter can be divided into:
1. Asynchronous binary counter
2. Synchronous binary counter
Meanwhile, according to the sequence of calculations formed in the output, then
counters can be divided into:
*
Up counter
* Down counter
*
Up and down counters
14.1. Asynchronous Binary Up Counter
This counter can count binary numbers in order from bottom to top
on. If 4 flip-flops are used, then we can do the most calculations
high is 1111.
A counter that can count up to 1111 is called bit binary counter4 .
Because you can count upwards , so it's called
asynchronous 4 bit binarycounter , as shown in Figure 14.1.
A B C D
SET SET SET SET
J Q J Q J Q J Q
K CLR Q K CLR Q K CLR Q K CLR Q
Figure 14.1
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In the above circuit, the J and K inputs of all the flip-flops are made in
state 1. Before the first pulse to be counted enters the input, then
all output counters L4, L3, L2 and L1 are made to 0 first by running
makes clear in 0 state even for a moment.
When the first pulse moves from 1 to 0, the flip-flop output A will be
changes from 0 to 1, Output B will remain constant due to the signal entering the clock input
changed from 0 to 1. The 3rd and 4th flips also didn't change because they haven't
there is a change in the clock input. So it can be concluded that after the pulse
first comes the output state of L4, L3, L2, L1 is 0001.
Next, if the second pulse moves from 1 to 0, flip-flop output 1 will
returns to 0, as a result there is also a change in the clock input of flip-flop 2
(from 1 to 0) so that the output of flip-flop 2 becomes 1. While flip flops 3 and 4
the output has not changed because the input clock pulse has not
changes from 1 to 0. So now the output of this counter circuit is
0010.
And so on until the 15th pulse comes. The four circuit outputs
The counter will be worth 1111. Once the 16th pulse is entered (change from 1 to 0)
comes then the output of each flip-flop will change to 0000
(like the initial state).
14.2. Asynchronous Binary Down Counter Decade Counter
The working principle of this counter is the opposite of the up counter, namely counting
binary numbers in order starting from top to bottom (from large to small).
The working principle of this counter is also no different from the up counter, only each output
flip-flop is taken from the output Q, while the input is connected to Q from the flip-flop
previous flop. For more details, see Figure 14.2.
A B C D
SET SET SET SET
J Q J Q J Q J Q
K CLR Q K CLR Q K CLR Q K CLR Q
Figure 14.2
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The working principle can be explained as follows:
Before the first pulse arrives and enters the input, the entire counter outputs
Q3,2,1,0 is made 0 by using direct clear even for a moment. On
when the first pulse moves from 1 to 0, the flip-flop output 0 will change
becomes 1. Note Q flip-flop A changes from 1 to 0 as well. The results of these changes will be
goes into flip-flop 1 causing the output of Q2 to become 1. Same thing
also happens to flip-flops 2 and 3 so that their output changes to 1. So
After the first pulse enters the counter output will change to 1111.
When the second pulse comes in (changes from 1 to 0), the flip-flop outputs
first it will change from 1 to 0, which means the output note Q also changes from 0
to 1. This change in the Q note output will be passed on to the second flip-flop. But
will not cause changes to the second flip-flop (Q second flip-flop still
fixed 1). The same thing happens on the third and fourth flips. So on credit
in the second, the output of the four flip-flops is 1110.
And so on until the 15th pulse so that the output becomes 0001.
When the 16th pulse comes the circuit output changes to 0000. So the circuit
This is a series of counters from the highest value (top) to the value
The lowest (bottom) is from 1111 to 0000.
14.3. Asynchronous Up Down Counter
An electronic circuit that uses a digital system often
requires a counting tool that can count up and down
counting down.
A counting device that can perform such calculations is called Binary
Up Down Counter which can count up and down by setting
a particular controller.
[152]
Machine Translated by Google
Figure 14.3
By using the up and down buttons in Figure 14.3 you can
The counting process is carried out from above or from below.
14.4. Synchronous Binary Up Counter
If on an asynchronous counter the pulses to be counted do not arrive simultaneously,
then in this synchronour counter the pulse that you want to count is entered
each flip-flop simultaneously (together) so that the output of each flip-flop changes
will happen simultaneously. Therefore the calculation process on
This synchronous counter will be faster when compared to asynchronous
counters.
Figure 14.4
[153]
Machine Translated by Google
14.5. Synchronous Binary Down Counter
The same as the synchronous binary up counter above, only the circuit is different
This performs calculations from top to bottom. The circuit can be seen at
figure 14.5.
Figure 14.5
14.6. Synchronous Binary Up Down Counter
In this series, the counting process can be carried out up or down
by utilizing the calculation process control button. The circuit can be
seen in figure 14.6.
Figure 14.6
If we use up counter control then the active circuit is
Figure 14.7
[154]
Machine Translated by Google
Meanwhile, if we use a down counter then the active circuit is
By combining several JK flip-flops, several can be formed
counter type. The amount of counting capability of the counter depends on the number
flip-flop used. The more flip-flops used, the more
the number of calculations that can be done is also large.
Apart from being able to count pulses, the counter can also be used as a divider
frequency. The output frequency of a flip-flop is half the frequency
the input. So, a counter that uses four flip-flops will
divides the input frequency by 16 (f output = 1/16 f input).
SUMMARY
A counter is a sequential logic circuit that can function
to calculate the number of incoming pulses expressed in number form
binary.
EXERCISE
Explain about Asynchronous binary counter and Synchronous binary counter!
[155]
Machine Translated by Google
BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 15
REVIEW OF MEETING MATERIALS 9
UNTIL MEETING 14
Achievements : Students are able to review
Learning meeting materials 9 to
with meeting 14
Sub Principal : 15.1. Review Meeting Materials
Discussion 9 to meeting 14
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital
Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
[156]
Machine Translated by Google
”Digital Principles”. Series
Schaum's book Theory and Problems
questions, Second edition, publisher
Erlangga, 1996
5. Rummi Sirait, Teaching Materials
Digital Systems, Faculty
Budi University Engineering
Sublime, 2009
[157]
Machine Translated by Google
15.1. Review Meeting Materials 9 to 14
Karnaugh Map or what is usually called K-Map is a technique
simplifying logical functions by mapping. K-Map consists of boxes
which consists of the number of variables and logic functions or the number of inputs
of the logic circuit we are calculating.
The formula for determining the number of boxes in a K-Map is 2n . n is
the number of variables / inputs.
General K-Map mapping steps:
• Compile Boolean algebra first
• Draw digital circuits
• Create a Truth Table
• Formulate the Truth Table
• Then enter the Truth Table formula into the K-Map (Checkerboard
K-Map Rules
• Each group formed cannot contain cells containing zero values
• A group may form horizontally or vertically, but not
can be diagonal.
• The number of cells per group allowed is 2n . Such as 1, 2, 4, 8, and
so on
• Each group must be formed with a large number of cells so that
produce as few groups as possible
• Every cell that contains the value 1, must be part of a group
• Groups are allowed to overlap
• Groups are allowed by Wrapping
A boolean function can be expressed in the form of SOP (Sum of Product), namely
the sum of multiplications.
•
• The SOP form can be expressed in the minterm function.
[158]
Machine Translated by Google
• is the minterm function.
A boolean function can be expressed in POS (Product of Sum) form, namely
multiplication of the sum.
•
• The POS form can be expressed in the maxterm function.
• is the maxterm function.
The BCD code consisting of 4 bits that is commonly used is BCD 8421
because it is identical to binary numbers up to 9 decimal numbers and above 9
different from binary numbers.
A flip-flop has 2 stable states, and will stay in one of them
two states until a trigger occurs that causes them to change states. Flip-
flop is sometimes also called button, multivibrator, binary, but currently it will be used
just the term flip-flop.
T FF can be formed from modifications Cloked SR FF, D FF, and JK FF.
The T-FF circuit is formed from SR-FF by utilizing the Set and Reset relationships
as well as outputs Q and Q' which are fed back to inputs S and R. The T-FF circuit
formed from JK-FF, you only need to add the value "1" to the J and K inputs
(remember nature toggle from JK-FF). The T-FF circuit is formed from D FF only
by adding a simple combinational circuit to the input.
Counter is a sequential logic circuit that can function for
calculates the number of incoming pulses expressed in binary number form.
Almost all electronic equipment uses a digital system internally
The circuit contains a tool that can control the sequence of program operations. Tool
is called counter or counter.
[159]
Machine Translated by Google
SUMMARY
1. General K-Map mapping steps:
o Compile Boolean algebra first
o Drawing digital circuits
o Create a Truth Table
o Formulate the Truth Table
o Then enter the Truth Table formula into the K-Map (Checkerboard
2. K-Map Rules
o Each group formed cannot contain any cells that contain it
zero value
o A group may form horizontally or vertically, but
cannot be diagonal.
o The number of cells per group allowed is 2n . Like 1, 2,
4, 8, and so on
o Each group must be formed with a large number of cells
thus producing as few groups as possible
o Every cell that contains the value 1, must be part of a
group
o Groups are allowed to overlap
o Groups are allowed by Wrapping
3. A boolean function can be expressed in the form of SOP (Sum of Product)
namely the sum of multiplications.
4. The SOP form can be expressed in the minterm function.
5. A boolean function can be expressed in POS (Product of Sum) form
namely the multiplication of the sum.
6. The POS form can be expressed in the maxterm function.
7. The BCD code consisting of 4 bits that is commonly used is BCD 8421
because it is identical to binary numbers up to 9 decimal numbers.
8. A flip-flop is a single memory cell. The flip-flop output state can be
in high/low state for the desired time interval. For
Changing this state requires a trigger input. Flip-flop
has 2 complementary outputs, namely Q and Q'.
[160]
Machine Translated by Google
9. is that T FF can be formed from modifications Cloked SR FF, D FF, and JK
FF.
10.Counter is a sequential logic circuit that can function
to calculate the number of incoming pulses expressed in the form
binary numbers.
EXERCISE
1. Simplify with K-Map
2. State the function into POS form and maxterm function
appropriate!
3. What is the result of subtracting the decimal 17 - 8 in binary and in binary
BCD?
4. Explain the main differences between SR FF and JK FF
5. Explain the characteristics of T flip-flop?
6. Explain about Asynchronous binary counter and Synchronous binary
counters!
[161]
Machine Translated by Google
BUDI LUHUR UNIVERSITY
FACULTY OF ENGINEERING
MEETING 16
FINAL EXAMS
Achievements : Students are able to answer
Learning and solve problems
given in the question
Sub Principal : 16.1. Final Semester Exam Questions
Discussion
Bibliography : 1. Malvino, Principles and
Digital Implementation.
2. M. Morris Mano, Digital
Design
3. Malvino, Tjia, 1988,
Digital Computer Electronics.
4. Roger L. Tokheim, Sutisna,
”Digital Principles”. Series
Schaum's book Theory and Problems
[162]
Machine Translated by Google
questions, Second edition, publisher
Erlangga, 1996
5. Rummi Sirait, Teaching Materials
System Digital, Faculty
Budi Luhur University Engineering,
2009
[163]
Machine Translated by Google
16.1. Final Semester Exam Questions
1. function Y = (A + B) (B + C') (Score 50)
a. Express it in SOP form
b. State the appropriate minterm function
c. Create a K-Map
d. Write the K-Map Logic equation
e. Make a logic gate circuit from the K-Map logic equation
2. Given f (A, B, C, D) = m(2, 3, 6, 7, 9, 11, 12) (Score 40)
a. Write down the Binary
b. Create a K-Map
c. Write the K-Map Logic equation
d. Make a logic gate circuit from the K-Map logic equation
3. Circle it and write the logical equation. (10 marks)
[164]
Machine Translated by Google
FACULTY OF ENGINEERING
BUDI LUHUR UNIVERSITY
Jl. Raya Ciledug, North Petukangan, Pesanggrahan
South Jakarta, 12260
Tel: 021-5853753 Fax: 021-5853752
http://ft.budiluhur.ac.id
[165]
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