Physical Design

Power Planing

Power planing is process of providing the power resources to all the componets in the
design like macros , std cells and any other cells.
The aim of low power VLSI design is to minimize the individual components of power as
much as possible, hence decreasing the total power consumption.
➢ Power Routing also called Pre-Routing
➢ Pre-Routing includes creating Power Ring, Stripes/Mesh/Grid, and Standard Cell
Power Rails
➢ To connect Power to the Chip by considering issues like EM and IR Drop

Levels of Power Distribution :

➢ Rings :
VDD and VSS Rings are formed around the Core and Macro

➢ Trunks :
Connects Ring to Power Pad

➢ Stripes :
• Carries VDD and VSS around the chip
• Carries VDD and VSS from Rings across the chip
• Power Stripes are created in the Core Area to tap power from Core Rings to
the core area

➢ Rails (Special Route) :

• Connect VDD and VSS to the standard cell

• Standard Cell Rails are created to tap power from Power Stripes to Std. Cell
Power/Ground Pins
➢ Power Vias :

• Insert all Power Vias between Ring & Grid, Grid & Rail and Vertical Grid &
Horizontal Grid
➢ Types of Power Dissipation in IC :

Total power = Static power + Dynamic Power

• Ptotal=(fclk*Cdyn*VDD2)+(Tsc*VDD*Ipeak)+(VDD * I leakage)

• Static power dissipation

• Dynamic power dissipation
 ❖ Static Power Dissipation :
power will be dissipated irrespective of frequency and switching of the system. It is
continuous and has become more dominant at lower node technologies. The structure
and size of the device results in various leakage currents.
• Pstatic=VDD * I leakage
➢ Causes for static power dissipation :
• Sub-threshold current
• Gate oxide leakage
• Diode reverse bias current
• Gate induced leakage
❖ Dynamic Power Dissipation:
There are two reasons of dynamic power dissipation
• Switching of the device and short circuit path from supply (VDD) to ground (VSS).
• Pshort=Tsc⋅VDD⋅Ipeak

• This occurs during operation of the device. Signals change their logic state
charging and discharging of output mode capacitor.
• Pswitch=fswitch*CL*VDD2
 ❖ IR Drop :

• the power supply in the chip is distributed uniformly through metal layers
across the design and these metal layers have their finite amount of resistance.
when we applied the volatge the current starts flowing through these metal
layers and some voltage is dropped due to that resistance of a metal wire and
current. this drop is called IR Drop.
• IR drop(V2) = V1 – I.R

Tools used for IR drop analysis:

• Redhawk from Apache
• Voltage storm from cadence

➢ Reasons for IR drop:

IR drop could occur due to various reasons but some main reasons are as bellow.
• Poor design of power delivery network (lesser metal width and more
separation in the power stripes)
• inadequate via in power delivery network
• Inadequate number of decap cells availability
• High cell density and high switching in a particular region
• Rush current
• Insufficient number of voltage sources

➢ Static IR Drop:
This drop is independent of cell switching and this is calculated with the help of metal
own resistance.
Methods to improve static IR Drop
• We can go for higher layers if available.
• Increase the width of the straps.
• Increase the number of wires.
• Check if any via is missing then add more via
 ➢ Dynamic IR Drop:
This drop is calculated with the help of the switching of cells. when a cell is
switching at the active edge of the clock the cell requires large current or voltage
to turn on but due to voltage drop suffficient amount of voltage is not reached to
thr particular cell and cell may be goes into metastable state and effect the timing
and performance.
Methods to improve Dynamic IR Drop
• Use De-Cap Cells.
• Increase the number of straps.

Electromigration :
hen a high density of current is flowing through metal layers, the atoms (electron) in the
metal layers are displaced from their origional position causing open and shorts in the metal
layers. Heating also accelerates EM because higher temperature cause a high number of
metal ions to diffuse

Methods to solve EM:

• Increase the width of wire
• Buffer insertion
• Downsize the driver
• Switch the net to higher metal layers.
• Adding more vias
• Keep the wire length short
Tools used for power plan:
✓ Synopsis : ICC2
✓ Cadance : Inovus
❖ Inputs of power planning:
➢ Netlist(.v)
➢ SDC
➢ physical and logical libraries (.lef & .lib)
➢ TLU+
➢ UPF

UPF Contents :
Power intent specifies :
Distribution Architecture:
• Power domains – Group of elements which share a common set of power
supply requirements
• Supply rails – Power distribution (ports, nets, sets & switches)
• Shutdown control
Power Strategy:
• Power state tables – Legal combination of states of each power domain
• Operating voltages
Usage of Special cells :
▪ Isolation cells
▪ Level shifters
▪ Power switches
▪ Retention registers

Steps In POWER PLAN :

• Perform logical connections of VDD and VSS
Commands:
create_net -power VDD
create_net -ground VSS
connect_pg_net -net VDD [get_pins -hier */VDD*]
connect_pg_net -net VSS [get_pins -hier */VSS*]
• Set attributs for tie cells
set_attribute [get_lib_cells */tie*]
• Create straps or strips
create_pg_straps -layer M9…
 create_pg_mesh _pattern…..

• Create rails for std cells

create_pg_std_cell_conn_pattern…
• Create vias between straps and rails
create_pg_vias -nets {VDD VSS} -from_layers M1 -to_layers M9
• Perform the checks
check_pg_connectivity
check_pg_drc
PG CHECKS:
• Check_pg_Connectivity :

- it shows floating pins

- floating wires

• Check_pg_drc :
- Min metal area spacing errors
- Insufficient spacing of metal
- Opens
- Shorts
- Spacing between metals
- Min width voilations ect…
Min metal area spacing error insufficient spacing error
❖ Low Power Techniques: The aim of low power VLSI design is to minimize the individual
components of power as much as possible, hence decreasing the total power
consumption.

• Power Gating
• Clock Gating
• Vlotage and frequency scaling
• Multi Threshold voltages (Vt swapping)
• Multi supply voltages
• Multi channel length technology’s

❖ Objectives of Power plan :

• Providing power supply to each component

• Power grid should meet the IR drop targets
• Power grid should meet the EM targets
• Reducing Power Consumption
• Optimal resources usage for congestion_effort

- VENU KUMAR KARE

https://www.linkedin.com/in/venu-kumar-kare-
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