NAME : SHAMBHAVI V

BATCH : BPD18

FINAL PROJECT REPORT

RISC-V
Objective: To take RISC V design through Physical design Stages- from RTL to GDS.
EDA tools: Synopsys Design Compiler and Synopsys IC Compiler 2.

1) DC Flow
Design Compiler takes RTL (Register Transfer Level) descriptions of digital circuits as input
and generates optimized gate-level netlists that represent the logical structure of the circuit.
The main objective of Design Compiler is to translate the high-level RTL description into a
gate-level representation while meeting specific design constraints such as timing, area,
power, and design rules.

->Invoke Synopsys Design Compiler in Topographical mode (also referred to as Design

Compiler Topographical Technology or DCT) is an advanced logic synthesis technique that
leverages a "virtual layout" concept to achieve more accurate post-layout timing, power,
and area (PPA) predictions during the early stages of the design flow.

>dc_shell -topo
->Execute the following script to do the synthesis flow

############ Synthesis RUN.tcl ###################

### Input- technology file##

set tech_file {../../ref/tech/saed32nm_1p9m.tf}

set synthetic_library dw_foundation.sldb
#set mw_path "../libs/mw_libs"

### Input- Library files ##

set mw_ref_libs "../libs/mw_libs/saed32_io_fc ../libs/mw_libs/saed32nm_lvt_1p9m"

set my_mw_lib RISC V_mw_lib.mw

### creating project library ###

create_mw_lib $my_mw_lib \
-technology $tech_file \
-mw_reference_library $mw_ref_libs \
-open
set target_library {\
../../ref/DBs/saed32lvt_ss0p95v125c.db \
../../ref/DBs/saed32lvt_ss0p95v125c.db \
../../ref/DBs/saed32rvt_ss0p95v125c.db \
../../ref/DBs/saed32hvt_ss0p75v125c.db \
../../ref/DBs/saed32sramlp_ss0p95v125c_i0p95v.db}

set link_library {\
../../ref/DBs/saed32lvt_ss0p95v125c.db \
../../ref/DBs/saed32lvt_ss0p95v125c.db \
../../ref/DBs/saed32rvt_ss0p95v125c.db \
../../ref/DBs/saed32hvt_ss0p75v125c.db \
../../ref/DBs/saed32sramlp_ss0p95v125c_i0p95v.db}

set ref_libs {\
../../ref/DBs/saed32lvt_ss0p95v125c.db \
../../ref/DBs/saed32lvt_ss0p95v125c.db \
../../ref/DBs/saed32rvt_ss0p95v125c.db \
../../ref/DBs/saed32hvt_ss0p75v125c.db \
../../ref/DBs/saed32sramlp_ss0p95v125c_i0p95v.db}

### Input- TLU plus files( parasitic information ####

set_tlu_plus_files\
-max_tluplus ../../ref/tech/saed32nm_1p9m_Cmax.lv.tluplus \
-min_tluplus ../../ref/tech/saed32nm_1p9m_Cmin.lv.tluplus

### reading RTL files ###

## since there are many files it is recommendable to have a seperate filefor RTLs,
and then source it##
source ./risc_rtl.tcl

current_design msrv32_top
source ../constraints/risc_core.upf

#sourcing floorplanning constraints

source ../constraints/floorplan_constraints.pcon

### reading SDC ( synopsis design constraints ), mainly clock info ###

read_sdc ../constraints/constraints_file1.sdc
#set_wire_load_model -name wire_load.tcl
set_svf RISC_V.svf
 ### Command to sythesize the RTL and produce Gate level Netlist ###
compile_ultra -no_autoungroup -no_boundary_optimization

### Check schematic in GUI ###

# dft constraints
set_dft_signal -view existing_dft -type ScanClock -port ms_riscv32_mp_clk_in -timing [list
45 55]
set_dft_signal -view existing_dft -type Reset -port ms_riscv32_mp_rst_in -active_state 1
set_scan_configuration -chain_count 4
create_test_protocol
dft_drc
preview_dft
insert_dft

### To get output files from the tool ###

write_icc2_files -output ../results/riscv -force
write -hierarchy -format ddc -output ../results/riscv.ddc

### Output- various reports from Synthesis ###

report_area > ../reports/riscv.rpt

report_hierarchy > ../reports/riscv.rpt
report_design > ../reports/riscv.rpt
report_timing -path full > ../reports/riscv.rpt
 ### output- Gate level Netlist ###
write -hierarchy -format verilog -output ../results/riscv.v

### Output- SDF(Standard Delay format) file ,containing timing information of the
circuits ###
write_sdf ../reports/riscv.sdf
write_parasitics -output ../results/riscv_v_parastics_8_6

### Output- Updated SDC file from synthesis tool ###

write_sdc ../results/riscv.sdc
write -format ddc -h -o ../results/riscv.ddc

puts "Finished"
#exit
 PLACE AND ROUTE USING IC Compiler II

ICC2 FLOW
ICC2 is used in the physical design phase of the IC design flow. It takes the gate-level netlist
generated by synthesis tools like Design Compiler and performs the physical
implementation of the design, including floorplanning, placement, and routing.

->Invoke ICC2

>icc2_shell

TCL SCRIPT FOR P&R FLOW

### library creation, we use the same reference files that we used forsynthesis
###
create_lib -technology ../../ref/tech/saed32nm_1p9m.tf -ref_libs \
{../../ref/CLIBs/saed32_1p9m_tech.ndm ../../ref/CLIBs/saed32_hvt.ndm \
../../ref/CLIBs/saed32_lvt.ndm ../../ref/CLIBs/saed32_rvt.ndm \
../../ref/CLIBs/saed32_sram_lp.ndm} riscv_block_2

# Creates the library {riscv_block_2}

#reading netlist and SDC that we got from Design Compiler
read_verilog ../netlist/riscv.v

read_sdc ../constraints/riscv.sdc

#parasitic reading
read_parasitic_tech -name {new_model} -tlu
{../../ref/tech/saed32nm_1p9m_Cmin.lv.tluplus} -layermap \
{../../ref/tech/saed32nm_tf_itf_tluplus.map}
 ### Setting PVT corner for optimization ###

current_corner default
set_parasitic_parameters -early_spec new_model -late_spec new_model
set_process_number 0.99 -corners default
set_temperature 125 -corners default
set_voltage 0.75 -corners default
current_mode default

### reading SDC that we got from DC ###

read_sdc ../constraints/riscv.sdc
set_scenario_status default -active true -setup true -hold true -max_transition true -
max_capacitance true -min_capacitance true -leakage_power true \
-dynamic_power true

###Floor planning stage##

link_design
set_auto_floorplan_constraints -core_utilization 0.7
initialize_floorplan -side_ratio {3 3} -core_offset {5}
set_block_pin_constraints -self -allowed_layers “M3 M4 M5 M6”
#pins placement
place_pins -self

# power plan
source risc_v_pns1.tcl

## create the PG nets

create_net -power VDD
create_net -ground VSS

## Making Logical Connections

connect_pg_net -net VDD [get_pins -hierarchical "*/VDD"]
connect_pg_net -net VSS [get_pins -hierarchical "*/VSS"]

connect_pg_net

set_pg_via_master_rule pgvia_8x10 -via_array_dimension {8 10}

create_pg_mesh_pattern top_layers \
-layers { \
{ {horizontal_layer: M7} {width: 1.104} {spacing: interleaving} {pitch: 13.376} {offset: 0.856} {trim : true}
}\
{ {vertical_layer: M8} {width: 4.64} {spacing: interleaving} {pitch: 19.456} {offset: 6.08} {trim : true} } \
}\
-via_rule { {intersection: adjacent} {via_master : pgvia_8x10} }

#{ {vertical_layer: M8} {width: 4.64 } {spacing: interleaving} {pitch: 19.456} {offset: 6.08} {trim : true} } \

create_pg_mesh_pattern m2_layer \
 -layers { \
{ {vertical_layer: M2} {track_alignment : track} {width: 0.44 0.192} {spacing: 3.724 4.456} {pitch: 9.728}
{offset:2.216} {trim : true} } \
}
set_pg_strategy S_default_vddvss \

-core \
-pattern { {name: top_layers} {nets:{VSS VDD}} {offset_start: {4 4}} } \
-extension { {{stop:design_boundary_and_generate_pin}} }

set_pg_strategy S_m2_vddvss \
-core \
-pattern { {name: m2_layer} {nets: {VDD VSS}} {offset_start: {4 4}} } \
-extension { {{direction:BT} {stop:core_boundary}} }

set_pg_strategy_via_rule S_via_m2_m7 \
-via_rule { \
{ {{strategies: {S_m2_vddvss}} {layers: { M2 }} {nets: {VDD}} } \
{{strategies: {S_default_vddvss}} {layers: { M7 }} } \
{via_master: {default}} } \
{ {{strategies: {S_m2_vddvss}} {layers: { M2 }} {nets: {VSS}} } \
{{strategies: {S_default_vddvss}} {layers: { M7 }} } \
{via_master: {default}} } \
}

compile_pg -strategies {S_default_vddvss S_m2_vddvss} -via_rule {S_via_m2_m7}

suppress_message PGR-599

create_pg_ring_pattern P_HM_ring -horizontal_layer M5 -horizontal_width {1} -vertical_layer M6 -vertical_width {1} -

corner_bridge false
set_pg_strategy S_HM_ring_top -core -pattern { {pattern: P_HM_ring} {nets: {VSS VDD}} {offset: {0.3 0.3}} }
set_pg_strategy_via_rule S_ring_vias -via_rule { \
{{{strategies: {S_HM_ring_top}} {layers: {M5}}} {existing: {strap }}{via_master: {default}}} \
{{{strategies: {S_HM_ring_top}} {layers: {M6}}} {existing: {strap }}{via_master: {default}}} \
}
compile_pg -strategies {S_HM_ring_top} -via_rule S_ring_vias

#create_pg_macro_conn_pattern P_HM_pin -pin_conn_type scattered_pin -layers {M5 M4}

#set_pg_strategy S_HM_top_pins -core -pattern { {pattern: P_HM_pin} {nets: {VSS VDD}} }

#compile_pg -strategies {S_HM_top_pins}

create_pg_std_cell_conn_pattern P_std_cell_rail -layers {M1 M2}

set_pg_strategy S_std_cell_rail_VSS_VDD \
-core \
-pattern {{pattern: P_std_cell_rail}{nets: {VSS VDD}}} \
-extension { {{direction:BT} {stop:core_boundary}} }
#{{stop: outermost_ring}{direction: L B R T }}

set_pg_strategy_via_rule S_via_stdcellrail \
-via_rule {{intersection: adjacent}{via_master: default}}

compile_pg -strategies {S_std_cell_rail_VSS_VDD} -via_rule {S_via_stdcellrail}

save_block -as fp_n_pp_done

check_pg_drc
### Placement stage ###
###check if the design is ready for placement ###
check_design -checks pre_placement_stage

### setting Options like blockages, and timing driven, congestion driven
placement & also the effort of the tool is increased considering future violations##
set_app_options -name plan.place.auto_create_blockages -value auto
create_placement -floorplan -timing_driven -congestion -effort medium
place_pins -self

place_opt
legalize_placement
 save_block -as placement_done

check_pg_connectivity

###clock route###
### checking if the design is ready to go further for CTS ###
check_design -checks pre_clock_stage
 set_app_options -name time.remove_clock_reconvergence_pessimism -value true
report_clock_settings

report_qor -summary
set_app_options -name place.coarse.continue_on_missing_scandef -value true

clock_opt

save_block -as cts_done

###Routing Stage ###

### Check whether design is ready to go for routing ###
check_design -checks pre_route_stage
#set_routing_rule all -clear -default_rule -min_routing_layer 1 -max_routing_layer 9
route_auto -max_detail_route_iterations 30

### setting application options to give timing and crosstalk driven trackassignment
and detailed routing ###
set_app_options -name route.track.timing_driven -value true
set_app_options -name route.track.crosstalk_driven -value true
set_app_options -name route.detail.timing_driven -value true
set_app_options -name route.detail.force_max_number_iterations -value true

route_opt
route_eco

save_block -as routing_done

report_constraints -all_violators

Cell sizing
report_constraints

report_qor -summary
check_lvs

#script writing
write_script -force -format icc2 -output ../reports/riscv_spef
write_parasitics -output ../reports/riscv_spef_generation_1
write_sdf ../results/riscv_1.sdf
write_verilog ../results/riscv_1.v
write_gds ../results/riscv.gds
write_sdc -output ../results/riscv_v.sdc

Reports
Results

report_congestion (Post Routing)

report_timing
report_utilization

report_power
report_design