Department of Electronics Engineering

National Chiao Tung University

Hsinchu, Taiwan

Memory Test
 Density and Defect Trends
 1970 -- DRAM Invention (Intel) 1024 bits
 1993 -- 1st 256 MBit DRAM papers
 1997 -- 1st 256 MBit DRAM samples
 1 ₵/bit --> 120 X 10-6 ₵ /bit
 Kilburn -- Ferranti Atlas computer (Manchester U.)
-- Invented Virtual Memory
 1997 -- Cache DRAM -- SRAM
cache + DRAM now on 1 chip

Memory cells per chip

2 VLSI Testing L a b @ N C T U
 Test Time in Seconds
Number of Test Algorithm Operations
Size (n)

1Mb 0.06 1.26 64.5 18.3 hr

4Mb 0.25 5.54 515.4 293.2 hr
16Mb 1.01 24.16 1.2 hr 4691.3 hr
64Mb 4.03 104.7 9.2 hr 75060.0 hr
256Mb 16.11 451.0 73.3 hr 1200959.9 hr
1Gb 64.43 1932.8 586.4 hr 19215358.4 hr
2Gb 128.9 3994.4 1658.6 hr 76861433.7 hr

cycle time: 60ns

3 VLSI Testing L a b @ N C T U
 Memory Test Levels
 Three levels
1. chip level
2. array level
3. board level

4 VLSI Testing L a b @ N C T U
 Memory Models
while (i>j) {
a += (d>>2); Behavioral model
}
Increasing fault localization capability
Increasing level of abstraction

RAM RAM RAM

Functional model
Control

&
>1 Logical model
&

VDD
Electrical model
VSS

Geometrical model

Models and levels of abstraction

5 VLSI Testing L a b @ N C T U
 Functional RAM Chip Model
Address Refresh

Address latch Column decoder Refresh logic

Memory
Row decoder Write driver
cell array

Data flow Sense amplifier Data register

Control flow

Data Data
Read/write and
out in
chip enable
6 VLSI Testing L a b @ N C T U
 Functional Faults
Functional fault
a Cell stuck
b Driver stuck
c Read/write line stuck
d Chip-select line stuck
e Data line stuck
f Open circuit in data line
g Short circuit between data lines
h Crosstalk between data lines
i Address line stuck
j Open circuit in address line
k Shorts between address lines
l Open circuit in decoder
m Wrong address access
n Multiple simultaneous address access
o Cell can be set to 0 (1) but not to 1 (0)
p Pattern sensitive cell interaction

7 VLSI Testing L a b @ N C T U
 Reduced Functional Model
 During chip testing one is not interested in
locating a fault because a chip cannot be
repaired. One is only interested in detecting a
fault.
 Simplified functional model
Address

Address decoder

Memory cell array

Read/write logic

Data
8 VLSI Testing L a b @ N C T U
 Notations
 0 : a cell is in logical state 0
 1 : a cell is in logical state 1
 x : a cell is in logical state x, where 𝑥 ∈ {0,1}
 ↑ : a write 1 operation to a cell containing a 0
 ↓ : a write 0 operation to a cell containing a 1
 ↕ : a write 𝑥 operation to a cell containing a 𝑥
 →: a write 𝑥 operation to a cell containing a 𝑥
 ∀ : any operations; ∀∈ ↑, ↓, ↕, →
 < 𝐼 𝐹 > : a fault in single cell
 I describes the condition; F describes the value of faulty cell
 < 𝐼1, … , 𝐼𝑛 − 1; 𝐼𝑛 𝐹 > : a fault involving n cells

9 VLSI Testing L a b @ N C T U
 Stuck-at Fault
 The logic value of a stuck-at (SA) cell or line is
always 0 (SA0 fault) or 1 (SA1 fault); it is always
in state 0 or in state 1 and cannot be changed to
the opposite state.
 < ∀ 0 >, < ∀ 1 >

w0 w1 w1 w0 w1

S0 S1 S0 S1
w0 w1 w0

state diagram of a good cell SA0 fault SA1 fault

10 VLSI Testing L a b @ N C T U
 Transition Fault
 A cell or line which fails to undergo a 0 → 1
transition when it is written is said to contain an
up transition fault; similarly, a down transition
fault is the impossibility of making a 1 → 0
transition.
 < ↑ 0 >, < ↓ 1 >

w0 w1 w1 w0 w1 w1

S0 S1 S0 S1
w0 w0

11 VLSI Testing L a b @ N C T U
 Coupling Faults
 Coupling Fault (CF): Transition in bit j causes
unwanted change in bit i
 2-Coupling Fault: Involves 2 cells, special case of
k-Coupling Fault
 Must restrict k cells to make practical
 Inversion and Idempotent CFs -- special cases of
2-Coupling Faults
 Bridging and State Coupling Faults involve any #
of cells, caused by logic level
 Dynamic Coupling Fault (CFdyn) -- Read or write
on j forces i to 0 or 1

12 VLSI Testing L a b @ N C T U
 Inversion Coupling Faults (CFin)
 ↑ or ↓ in cell j inverts contents of cell i
 Condition: For all cells that are coupled, each
should be read after a series of possible CFins
may have occurred, and the # of coupled cell
transitions must be odd (to prevent the CFins
from masking each other).
 <↑; ↕>, <↓; ↕>

13 VLSI Testing L a b @ N C T U
 Good State Transition Diagram (2 cells)

w0/i, w0/j w1/j w0/i, w1/j

S00 S01
w0/j

w0/i w1/i w0/i w1/i

w1/j
S10 S11

w1/i, w0/j w0/j w1/i, w1/j

14 VLSI Testing L a b @ N C T U
 CFin State Transition Diagram

w0/i, w0/j w0/i, w1/j

S00 S01
w0/j
w1/j

w0/i w1/i w0/i w1/i

w1/j

S10 S11

w1/i, w0/j w0/j w1/i, w1/j

15 VLSI Testing L a b @ N C T U
 Idempotent Coupling Faults (CFid)
 ↑ or ↓ transition in cell j sets cell i to 0 or 1
 Condition: For all coupled faults, each should be
read after a series of possible CFids may have
happened, such that the sensitized CFids do not
mask each other.
 Asymmetric: coupled cell only does ↑ or ↓
 Symmetric: coupled cell does both due to fault
 <↑; 0 >, <↑; 1 >, <↓; 0 >, <↓; 1 >

16 VLSI Testing L a b @ N C T U
 CFid Example

w0/i, w0/j w0/i, w1/j

S00 S01
w0/j

w1/j
w0/i w1/i w0/i w1/i

w1/j
S10 S11

w1/i, w0/j w0/j w1/i, w1/j

17 VLSI Testing L a b @ N C T U
 Dynamic Coupling Faults (CFdyn)
 Read or write in cell of 1 word forces cell in
different word to 0 or 1
 < 𝑟0 𝑤0; 0 >, < 𝑟0 𝑤0; 1 >,
< 𝑟1 𝑤1; 0 >, < 𝑟1 𝑤1; 1 >
 | Denotes “OR” of two operations
 More general than CFid, because a CFdyn can be
sensitized by any read or write operation

18 VLSI Testing L a b @ N C T U
 Bridging Faults
 Short circuit between 2+ cells or lines
 0 or 1 state of coupling cell, rather than coupling
cell transition, causes coupled cell change
 Bidirectional fault -- i affects j, j affects i
 AND Bridging Faults (ABF):
 < 0,0 0,0 >, < 0,1 0,0 >, < 1,0 0,0 >, < 1,1 1,1 >
 OR Bridging Faults (OBF):
 < 0,0 0,0 >, < 0,1 1,1 >, < 1,0 1,1 >, < 1,1 1,1 >

19 VLSI Testing L a b @ N C T U
 State Coupling Faults
 Coupling cell / line j is in a given state y that
forces coupled cell / line i into state x
 < 0; 0 >, < 0; 1 >, < 1; 0 >, < 1; 1 >
w0/i, w0/j

S00

w1/j
w0/i w1/i w0/i

w1/j
S10 S11

w1/i, w0/j w0/j w1/i, w1/j

example of <1;1>

20 VLSI Testing L a b @ N C T U
 Neighborhood Pattern Sensitive Fault (1/2)
 Neighborhood Pattern Sensitive Fault (NPSF)
 The contents of a cell, or the ability to change the
contents, is influenced by the contents of all other cells
in the memory.
 The NPSF can be considered the most general
case of the k-coupling fault.

Memory array

d
d b d
d
b: base cell
d: deleted neighborhood cell
b+d: neighborhood

21 VLSI Testing L a b @ N C T U
 Neighborhood Pattern Sensitive Fault (2/2)
 Active NPSF (ANPSF)
 also called Dynamic NPSF
 The base cell changes its contents due to a change in
the deleted neighborhood pattern.
 Passive NPSF (PNPSF)
 The content of the base cell cannot be changed (it
cannot make a transition) due to a certain deleted
neighborhood pattern.
 Static NPSF (SNPSF)
 The content of a base cell is forced to a certain state
due to a certain deleted neighborhood pattern.

22 VLSI Testing L a b @ N C T U
 Address Decoder Faults (ADFs)
 Address decoding error assumptions:
 Decoder does not become sequential
 Same behavior during both read & write
 Multiple ADFs must be tested
 Decoders have CMOS stuck-open faults

CX AX CX
AX CX
AY CY AY
Fault 1 Fault 2 Fault 3 Fault 4
No cell accessed No address to Multiple cells Multiple addresses
for AX access cell CX accessed with AY for cell CX

23 VLSI Testing L a b @ N C T U
 Theorem 9.2
 A March test satisfying conditions 1 & 2 detects
all address decoder faults.
 ... Means any # of read or write operations
 Before condition 1, must have wx element
 x can be 0 or 1, but must be consistent in test

Condition March element

1 (𝑟𝑥, … , 𝑤𝑥)
2 (𝑟𝑥, … , 𝑤𝑥)

24 VLSI Testing L a b @ N C T U
 Proof Illustration

AX CX AX CX AX CX
AX CX
AY CY AY CY AY CY
Fault A (1+2) Fault B (1+3) Fault C (2+4) Fault D (3+4)

AV CV AV CV

AW CW AW CW AX CX AV CV

AX CX AX CX AY CY AW CW

AY CY AY CY AZ CZ AX CX

AZ CZ AZ CZ

Fault C Fault D1 Fault D2 Fault D3

25 VLSI Testing L a b @ N C T U
 Necessity Proof
 Removing 𝑟𝑥 from Condition
Condition March element
1 prevents A or B fault
detection when 𝑥 read 1 (𝑟𝑥, … , 𝑤𝑥)
 Removing 𝑟𝑥 from Condition 2 (𝑟𝑥, … , 𝑤𝑥)
2 prevents A or B fault
detection when 𝑥 read
AX CX AX CX AX CX
 Removing 𝑟𝑥 or 𝑤𝑥 from AX CX
CY AY CY AY CY
AY
Condition 1 misses fault D2 Fault A (1+2) Fault B (1+3) Fault C (2+4) Fault D (3+4)
 Removing 𝑟𝑥 or 𝑤𝑥 from
AV CV AV CV
condition 2 misses fault D3
AW CW AW CW AX CX AV CV
 Removing both writes misses AX CX AX CX AY AW CW
CY
faults C and D1
AY CY AY CY AZ CZ AX CX

AZ CZ AZ CZ

Fault C Fault D1 Fault D2 Fault D3

26 VLSI Testing L a b @ N C T U
 Sufficiency Proof
 Faults A and B: Detected by SAF test
 Fault C: Initialize memory to ℎ (𝑥 or 𝑥).
Subsequent March element that reads h
and writes ℎ detects Fault C.
 Marching ⇑ writes ℎ to Av.
Detection: read Aw
AX CX AX CX AX CX
 Marching ⇓ writes ℎ to Az. AX CX
CY AY CY AY CY
Detection: read Ay AY

Fault A (1+2) Fault B (1+3) Fault C (2+4) Fault D (3+4)

 Fault D: Memory returns
AV CV AV CV
random result when multiple
AW CW AW CW AX CX AV CV
cells read simultaneously.
AX CX AX CX AY CY AW CW
Generate fault by writing Ax,
AY CY AY CY AZ CZ AX CX
Detection: read Aw or Ay (⇑ or ⇓
AZ CZ AZ CZ
marches)
Fault C Fault D1 Fault D2 Fault D3

27 VLSI Testing L a b @ N C T U
 Reduced Functional Faults
Fault Functional fault
SAF a Cell stuck
SAF b Driver stuck
SAF c Read/write line stuck
SAF d Chip-select line stuck
SAF e Data line stuck
SAF f Open circuit in data line
CF g Short circuit between data lines
CF h Crosstalk between data lines
AF i Address line stuck
AF j Open circuit in address line
AF k Shorts between address lines
AF l Open circuit in decoder
AF m Wrong address access
AF n Multiple simultaneous address access
TF o Cell can be set to 0 (1) but not to 1 (0)
NPSF p Pattern sensitive cell interaction

28 VLSI Testing L a b @ N C T U
 Fault Modeling Example 1

SA0
SAF
AF+SAF

SCF<0;0> SA1 SCF<1;1>

SA0 TF< /0>
TF< /1>

29 VLSI Testing L a b @ N C T U
 Fault Modeling Example 2
SA1 gg SA1+SCF

ABF
ABF
SCF
SA0

ABF
30 VLSI Testing L a b @ N C T U
 Multiple Fault Models
 Coupling Faults: In real manufacturing, any # can
occur simultaneously
 Linkage: A fault influences behavior of another
 Example March test that fails:
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑤0, 𝑤1 ; ⇕ 𝑟1 }
 Works only when faults not linked

(a) Unlinked faults (b) Linked faults

31 VLSI Testing L a b @ N C T U
 Multiple Fault Examples
 cases 1, 2, 3 & 5 – unlinked
 cases 4 & 6 – linked

Case 1 Case 2 Case 3

Case 4 Case 5 Case 6

32 VLSI Testing L a b @ N C T U
 Fault Hierarchy

Linked TF Linked TF
CFid Linked CFid and CFin and CFid

CFin

TF

SAF Certain CFins linked with CFids

AF SCF SOF CFdyn DRF

33 VLSI Testing L a b @ N C T U
 Traditional Tests
 Zero-One
 Checkerboard
 GALPAT and Walking 1/0
 Sliding Diagonal
 Butterfly

34 VLSI Testing L a b @ N C T U
 Zero-One
 This minimal test consists of writing 0s and 1s to
the memory.
 This algorithm is also known under the name
MSCAN (memory scan)
 Covered faults
 some AF, SAF, some TF, some CF

Step 1: write 0 in all cells; Step

Step 2: read all cells; 1 2 3 4
Step 3: write 1 in all cells;
Step 4: read all cells; Ma w0 r0 w1 r1
Ma = all memory addresses
Zero-One algorithm
Zer0-One scheme

35 VLSI Testing L a b @ N C T U
 Checkerboard
 The cells of the memory are divided into two
groups, cell-1 and cell-2, forming a checkerboard
pattern.
 Covered faults 1 2 1 2
2 1 2 1
 some AF, SAF, some TF, some CF 1 2 1 2
2 1 2 1

Step 1: write 1 in all cells-1 and 0 in all cell-2; 1 0 1 0 0 1 0 1

Step 2: read all cells; 0 1 0 1 1 0 1 0
Step 3: write 0 in all cells-1 and 1 in all cell-2; 1 0 1 0 0 1 0 1
Step 4: read all cells;
0 1 0 1 1 0 1 0
Step 1 Step 3
Checkerboard algorithm

36 VLSI Testing L a b @ N C T U
 GALPAT and Walking 1/0
 The algorithm for GALPAT (GALloping PATtern)
and Walking 1/0 are similar.
 Memory is filled with 0s (or 1s) expect for the
base-cell, which contains a 1 (or 0). During the
test, the base-cell walks through the memory.
 Covered faults
 AF, SAF, TF, CF

0 0 0 0 0 0 0 0

0 1 0 0 0 1 0 0

0 0 0 0 0 0 0 0
Walking 1/0 GALPAT

37 VLSI Testing L a b @ N C T U
 Sliding Diagonal
 The Sliding Diagonal test was developed as a
shorter alternative to GALPAT; it uses a diagonal
of base cells instead of a single base cell.
 Cells on the diagonal are used because each cell
has a different row and column address.
 Covered faults
 some AF, SAF, TF, some CF

1 0 0 0 0 0 1 0

0 1 0 0 0 0 0 1

0 0 1 0 1 0 0 0

0 0 0 1 0 1 0 0
First diagonal Third diagonal

38 VLSI Testing L a b @ N C T U
 Butterfly
 As in GALPAT, the memory is filled with 0s (or 1s)
expect for the base cell, which contains a 1.
 During the test, the base cell walks through the
memory. However, it reads cells which have the
same row and column with certain distances 1, 2,
4, 8, 16, etc.
 Covered faults
0 N 0 0 0 0
 some AF, SAF W b E E 0 W
0 S 0 0 0 0
0 S 0 0 0 0
0 0 0 0 0 0
0 N 0 0 0 0

39 VLSI Testing L a b @ N C T U
 March Test
 A march test consists of a finite sequence of
march elements.
 A march element is a finite sequence of
operations applied to every cell in memory before
proceeding to the next cell.
Address Operation
Addr 0 write 0
March test example Addr 1 write 0
Addr 2 write 0
Addr 3 write 0
⇕ 𝑤0 ; ⇑ (𝑟0, 𝑤1) Addr 0 read 0
M1 M2 Addr 0 write 1
Addr 1 read 0
Addr 1 write 1
March element
Addr 2 read 0
Addr 2 write 1
Addr 3 read 0
Addr 3 write 1

40 VLSI Testing L a b @ N C T U
 Notations for March Test
 r : read a memory location
 w : write a memory location
 r0 : read a 0 from a memory location
 r1 : read a 1 from a memory location
 w0 : write a 0 to a memory location
 w1 : write a 1 to a memory location
 ⇑ : increasing memory addressing
 ⇓ : decreasing memory addressing
 ⇕ : either increasing or decreasing

41 VLSI Testing L a b @ N C T U
 March Tests (1/2)
 MATS
 {⇕ 𝑤0 ; ⇕ 𝑟0, 𝑤1 ; ⇕ 𝑟1 }
 MATS+
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0 }
 MATS++
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0, 𝑟0 }
 Marching 1/0
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1, 𝑟1 ; ⇓ (𝑟1, 𝑤0, 𝑟0); ⇕ 𝑤1 ; ⇑ (𝑟1, 𝑤0, 𝑟0); ⇓
𝑟0, 𝑤1, 𝑟1 }
 March X
 ⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0 ; ⇕ (𝑟0)
 March Y
 ⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1, 𝑟1 ; ⇓ 𝑟1, 𝑤0, 𝑟0 ; ⇕ (𝑟0)
42 VLSI Testing L a b @ N C T U
 March Tests (2/2)
 March C
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇑ 𝑟1, 𝑤0 ; ⇕ 𝑟0 ; ⇓ 𝑟0, 𝑤1 ; ⇓
𝑟1, 𝑤0 ; ⇕ (𝑟0)}
 March C-
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇑ 𝑟1, 𝑤0 ; ⇓ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0 ; ⇕
(𝑟0)}
 March A
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1, 𝑤0, 𝑤1 ; ⇑ 𝑟1, 𝑤0, 𝑤1 ; ⇓
𝑟1, 𝑤0, 𝑤1, 𝑤0 ; ⇓ 𝑟0, 𝑤1, 𝑤0 }
 March B
 {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1, 𝑟1, 𝑤0, 𝑟0, 𝑤1 ; ⇑ 𝑟1, 𝑤0, 𝑤1 ; ⇓
𝑟1, 𝑤0, 𝑤1, 𝑤0 ; ⇓ 𝑟0, 𝑤1, 𝑤0 }

43 VLSI Testing L a b @ N C T U
 MATS+ Example (1/3)
 Cell (2,1) SA0 fault
 MATS+ : {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0 }
M1 M2 M3

0 0 0 1 1 1 0 0 0
Good Machine 0 0 0 1 1 1 0 0 0
0 0 0 1 1 1 0 0 0
after M1 after M2 after M3

0 0 0 1 1 1 0 0 0
Bad Machine 0 0 0 0 1 1 0 0 0
0 0 0 1 1 1 0 0 0
after M1 after M2 after M3

44 VLSI Testing L a b @ N C T U
 MATS+ Example (2/3)
 Cell (2,1) SA1 fault
 MATS+ : {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0 }
M1 M2 M3

0 0 0 1 1 1 0 0 0
Good Machine 0 0 0 1 1 1 0 0 0
0 0 0 1 1 1 0 0 0
after M1 after M2 after M3

0 0 0 1 1 1 0 0 0
Bad Machine 1 0 0 1 1 1 0 0 0
0 0 0 1 1 1 0 0 0
after M1 after M2 after M3

45 VLSI Testing L a b @ N C T U
 MATS+ Example (3/3)
 Cell (2,1) AF Type C A(2,1) C(2,1)
 Cell (2,1) is not addressable
A(3,1) C(3,1)
 Address (2,1) maps into (3,1)
 MATS+ : {⇕ 𝑤0 ; ⇑ 𝑟0, 𝑤1 ; ⇓ 𝑟1, 𝑤0 }
M1 M2 M3

0 0 0 1 1 1 0 0 0
Good Machine 0 0 0 1 1 1 0 0 0
0 0 0 1 1 1 0 0 0
after M1 after M2 after M3

0 0 0 1 1 1 1 1 1 0 0 0
Bad Machine X 0 0 X 0 0 X 1 1 X 0 0
0 0 0 1 0 0 1 1 1 0 0 0
after M1 after M2 after M2 after M3
for (2,1)

46 VLSI Testing L a b @ N C T U
 Comparison of memory tests
Fault coverage Test time L=Locate
Algorithm LS=Locate Some
AF SAF TF CF Others Order
D=Detect
Zero-One - L - - 𝑂(𝑛) DS=Detect Some
Checkerboard - L - - Refresh 𝑂(𝑛)
Walking 1/0 L L L L SA recovery 𝑂(𝑛2 )
GALPAT L L L L Write recovery 𝑂(𝑛2 )
Sliding Diagonal LS L L - 𝑂(𝑛 ⋅ 𝑛)
Butterfly LS L - - 𝑂(𝑛 ⋅ 𝑙𝑜𝑔2 (𝑛))
MATS DS D - - 𝑂(𝑛)
MATS+ D D - - 𝑂(𝑛)
MATS++ D D D - 𝑂(𝑛)
Marching 1/0 D D D - 𝑂(𝑛)
March X D D D D Unlinked CFins 𝑂(𝑛)
March Y D D D D Linked TFs 𝑂(𝑛)
March C- D D D D Unlinked CFins 𝑂(𝑛)
March A D D D D Unlinked CFs 𝑂(𝑛)
March B D D D D Linked CFs 𝑂(𝑛)
47 VLSI Testing L a b @ N C T U
 DRAM/SRAM Fault Modeling (1/2)
DRAM or SRAM Faults Model
Shorts & opens in memory cell array SAF, SCF
Shorts & opens in address decoder AF
Access time failures in address decoder Functional
Coupling capacitances between cells CF
Bit line shorted to word line IDDQ
Transistor gate shorted to channel IDDQ
Transistor stuck-open fault SOF
Pattern sensitive fault PSF
Diode-connected transistor 2 cell short
Open transistor drain
Gate oxide short
Bridging fault

48 VLSI Testing L a b @ N C T U
 DRAM/SRAM Fault Modeling (1/2)
DRAM Only Fault Modeling
DRAM only Faults Model
Data retention fault (sleeping sickness) DRF
Refresh line stuck-at fault SAF
Bit-line voltage imbalance fault PSF
Coupling between word and bit line CF
Single-ended bit-line voltage shift PSF
Precharge and decoder clock overlap AF

SRAM Only Fault Modeling

SRAM only Faults Model
Open-circuited pull-up device DRF
Excessive bit line coupling capacitance CF

49 VLSI Testing L a b @ N C T U
 Test Influence on SRAM Fault Coverage

(SAF, CFin, SNPSF)

SAF test

CF test

SNPSF test

50 VLSI Testing L a b @ N C T U
 Influence of Addressing Order on Fault Coverage

(sense amplifier recovery & write recovery F)

change order
of bit line or
word lines

CF test
performs
better

51 VLSI Testing L a b @ N C T U
 Critical Path Length
 Length of parallel wires separated by dimension
of spot defect size
 TFs and CFids happen only on long wires
Spot defect size (𝜇𝑚)
Fault class
<2 <3 <5 <7 <9 <2 <9
Stuck-at 78 213 227 269 269 51.3% 49.8%
Stuck-open 32 64 64 64 64 21.0% 11.9%
Transition 0 36 38 38 38 0% 7.0%
State coupling 15 15 51 71 71 9.9% 13.2%
Idempotent Coupling 0 0 0 0 18 0% 3.3%
Data retention 27 29 80 80 80 17.8% 14.8%
Total 152 357 460 522 540 100% 100%

52 VLSI Testing L a b @ N C T U
 Fault Frequency
 Obtained with Scanning Electron Microscope
 CFin and TF faults rarely occurred
Cluster # Devices Fault class
0 714 Stuck-at and Total failure
1 169 Stuck-open
2 18 Idempotent coupling
3 9 State coupling
4 8 ?
5 5 ?
6 26 Data retention
- - ?
14 2 ?
10% cannot be classified

53 VLSI Testing L a b @ N C T U