Introduction to VLSI Circuits and Systems Chapter 09 Advanced Techniques in CMOS Logic CircuitsBead oa Outline Mirror Circuits Pseudo-nMOS Tri-State Circuits Clocked CMOS Dynamic CMOS Logic Circuits Dual-Rail Logic NetworksMirror Circuits © Mirror circuits are based on series-parallel logic gates. but are usually faster and have a more uniform layout » Output 0’s imply that an nFET chain is conducting to * “ty ro around epee » Output 1’s means that a pFET group provides support from | thos the power supply ' — a) Circuit ] 20 eb bef ZBL aSh] Onderices | 6) 5 [oem ie $8) & |S 1 o| i | oer io] 6 |loee te ©) ‘apo Figure 9.1 XOR function table Figure 9.2 XOR mirror circuitXOR & XNOR © The advantages of the mirror circuit are. more symmetric layouts and shorter rise 5.4 | . ' and fall times G In Figure 9.3, transient calculations of © > XOR t t Figure 9.3 Switching mode for F,=CygQRI+CR, OA) transient calculations (KOR) where xis porn 2227, (9.2) t,=22r, (9.3) G In Figure 9.4, a example of XNOR a®b=a-b+a-b (9.4) Figure 9.4 Exclusive-NOR (XNOR) circuitBead ow? Outline Mirror Circuits Pseudo-nMOS Tri-State Circuits Clocked CMOS Dynamic CMOS Logic Circuits Dual-Rail Logic NetworksPseudo-nMOS Yoo o Adding a single pFET to otherwise nFET-only circuit “san f Pull-up produces a logic family that is called pseudo-nMOS 7 Load » Less transistor than CMOS f » For N inputs, only requires (N+1) FETs aE pult-down » Pull-up device: pFET is biased active since the grounded co amay gate gives Vig) = Vip » Pull-down device: nFET logic array acts as a large switch Figure 9.5 General structure between the output fand ground of a pseudo-nMOS logic gate » However, since the pFET is always biased on, Vo, can never achieve the ideal value of 0 V z Vp v © Asimple inverter using pseudo-nMOS as Figure 9.6 -- te a + | ym St Vo Weu Var} on “Moh (4) Yn * . 6, You A vi " Vin Win ¥r)= Wan Veh EH “Kel (5) ok * Figure 9.6 Pseudo-nMOS inverternFET Array in Pseudo-nMOS © The design of nFET array of pseudo-nMOS is the ra same as in standard CMOS = ie » Series and parallel logic FETs » Smaller simpler layouts, and interconnect is much simpler ae{[26, 2ma|b+ © » However, the sizes need to be adjusted to insure proper von 2alpea electrical coupling to the next stage » Resize in physical design 7 tw rate ~ —e° ab arb + H. “ge (a) NOR2 (&) NAND2 (©) Layout Figure 9,7 Pseudo-nMOS NOR and NAND gates Figure 98 AOI gateDead oa Outline Mirror Circuits Pseudo-nMOS Tri-State Circuits Clocked CMOS Dynamic CMOS Logic Circuits Dual-Rail Logic NetworksTri-State Circuits © Atri-state circuit produces the usual 0 and 1 voltages, but also has a third high impedance Z (or Hi-Z) » Useful for isolating circuits from common bus lines » In Hi-Z case, the output capacitance can hold a voltage even though n hardwire connection exists © Anon-inverting circuit ( a buffer) can be obtained by adding a regular static inverter to the input a fee mete of z | oa he 1 | Data 1 Figure 9.10 Tri-state layout (a) Symbol and operation () CMOS circuit Figure 9.9 Tri-state inverterDead oa Outline Mirror Circuits Pseudo-nMOS Tri-State Circuits Clocked CMOS Dynamic CMOS Logic Circuits Dual-Rail Logic NetworksClock-CMOS (C2MOS) a Static CMOS: the output of a static logic gate is valid so long as the input value are valid and the circuit has stabilized © However, logic delays are due to the “rippling” : . Ypp- through the circuits ° » Not reference to any specific time base ° rt » So on, Clock CMOS, or C2MOS is proposed Vp A . 4 © C*MOS concept: non-overlapping clock cs -: He)-al)=0 (9.9) Figure 9.11 Clock signals =H0)=Viy dle) 10) » But in physical signal, the clocks may overlap slightly during a transitionC2MOS Networks © C2MOS is composed of a static logic circuit with tri-state output network (made up of FETs M1 and M2) that is controlled by ¢ and ¢ » When ¢=0, both MI and M2 are active, and become to a standard static logic gate » When ¢=1, both MI and M2 are cutoff, so the output is a Hi-Z state = Yop Boo) PEETY Inputs valid / \ yo f (a,b,c) % As Veni HZ HEZ Figure 9.12 Structure of a C7MOS gateExample of C7-MOS <9 Yoo ~d] i (b) Nora Figure 9.13 Example of C2MOS logic gate fay--------- 4 A ‘Gnd ] cnt] ¢ 6 (a) Inverter (b) NAND2 Figure 9.14 Layout examples of CMOS circuitsLeakage in C7MOS (1/2) corr, | Yop © Charge leakage: since the output node cannot hold — 3-; ~df- 4 dove sean the charge on V,,, very long p+) » This places a lower limit on the allowable clock frequency © Ifa voltage is applied to the drain or source, a small leakage current flows into, or out of, the device » One reason is due to the required bulk connections » The current off of the capacitor by iy vw connection (a) Bulk leakage currents (b) Logie 1 voltage decay Figure 9.15 Charge leakage problemLeakage in C?7MOS (2/2) “4 ( 50x10" (See) i KD=05 sec sons) - 250 see (sox1s [85 \ye0s asso (2 jo “ ~ iv. 1W)=-C,W)F (9.16) (9.17) (9.18) (9.19) (9.20) (9.21) (9.22) (9.23) bur Lv p-substrate connection (@) Bulk leakage currents vi 0 th (b) Logie 1 voltage decay Figure 915 Charge leakage problemgoa0ngdadudcad Dd Outline Mirror Circuits Pseudo-nMOS Tri-State Circuits Clocked CMOS Dynamic CMOS Logic Circuits Dual-Rail Logic NetworksDynamic CMOS Logic Circuits (1/2) © Adynamic logic gate uses clocking and charge storage a properties of MOSFETs to implement logic operations oe = » Provide a synchronized data flow » Result is valid only for a short period of time » Less transistors, and may be faster than static cases © Based on the circuit in Figure 9.17 » The clock ¢ drives a complementary pair of transistors M, and M, » AnnFET array between the output node and ground to perform the logic function » When §=0, itis called precharge phase » When ¢=1, it is called evaluation phase Figure 9.17 Basic dynamic logic gateDynamic CMOS Logic Circuits (2/2) a Adynamic NAND3 is s own in Figure 9.18 feabe (9.24) © When f= 1, charge leakage reduces the voltages held on the output node Es ite Mn Gnd eabe Figure 9.18 Dynamic logic gate exampleCharge Sharing Problem © The origin of the charge sharing problem is the parasitic node capacitance C, and C, between FETs » When clock . and the capacitor voltage V, and V, are both 0 V gibi time, the total charge is Vout! Vo » The worst-cas@chGrgbusharif2Bondition is when the inputs are at (a, b,c) =(1, 1,0) AF colar Oridi BPERAR EE” flow ceases) Figure 9.19 Charge sharing circuit wa, + CV, + OV, +646, (9.27) (Se. (9.30) us < Gu + G 4G, a SO= (Cy tC +O,=CuVop (9.28) V, ab+asatb=a-b (9.42) Figure 9.32 CPL AND/NAND circuit © CPL has several 2-input gates that canbe) ee Bs created by using the same transistor topology with different input sequences ee eof Ht » Less layout area oH 4 a—He » However, threshold will be loss and the fact that a tl Lt an input variable may have to drive more than one aes ao ae FET terminal (a) OR/NOR (b) XOR/XNOR Figure 9.33 2-input CPL arrays