IEEE Press «445 Hoes Lane, PO Box 1331 Piscatavay. NJ 08855-1331 Editorial Board John B. Anderson, Editor in Chief S.biiog De win 1M Moura sen S.V.Karalopoulos 1 Peden Mbt PLapane E, Since Sinencio Moline A. Lab Shaw F Hoyt M.Lighine Di. Wells Dudley R. Kay, Director of Book Publishing Russ Hall, Senior AcqustonsEitor Cari Briggs, Administrative Assistant Lisa S. Mizrahi, Review and Publicity Coontinator Valerie Zaborki, Praduction iltor IBEE Ciruits and Systems Society, Sponsor S'S Liaison o IEEE Press Edgar Sinchez-Sinencio Technical Reviewers Andress Andreu Stepon H Lewis Johns Hopkins Univesity Universi of Califor, Davin Sing Chin Po Lim National Semicondvctor Crome ne ek Cocoa Edgar Since Sinncio estig- Packard Laboratories “Texan A&M University Rote Jewett ‘Bang Sup Song Hewtit-ackard Laboratories University oF iis Aare Karanicols ‘Stan Tewsbury Masschusets Insitute of Tecnology West Vigna Unversity Principles of Data Conversion System Design Behzad Razavi ATAT Bell Laboratories IEEE PRESS TEBE Circuits and Systems Society, Sponsor ‘The Insti of Elected and leetoncs Engines nc, New York‘Ths book may be purchased at discount fro the publisher when ordered in blk quantities. For moe information contct IEEE PRESS Marketing ‘Am: Special Sales PO, Box 1331 4445 Hoes Lane Piscataway, NJ 08855-1331 ax: (908) 981-8062 (©1995 by ATCT. Al ight reserved Alsip reserved No pt his book may he rprodced in any form, ‘noe may the sored narra pte tansited ia a or, ‘without writen permission fom te publishes Prine inte Unto States of America wosT6s 4321 ISBN 0-7803-1093-4 IEEE Order Number: PC4465 rary of Canges Cage Pbleation Data aan Beha Anda phil frencs aides, 2, big ana oonerer”Doign ad count irate cr To the memory of my motherContents PREFACE xi CHAPTER 1 INTRODUCTION TO DATA CONVERSION AND PROCESSING 1 CHAPTER2 ASIC SAMPLING CIRCUITS. 7 21. General Considerations 7 2.2 Perfomance Metics 11 23 Sampling Switches 13 21 MOS Switches 14 232. Diode Swiches 19 233 Comparison of MOS and Dine Switches 23 2.34 Improvements in MOS Switch Performance 24 References 27 CHAPTERS SAMPLEAND-HOLD ARCHITECTURES 29 5.1 Comentonal Opentoop Architecture 29 3.2 Comantional Closed-Loop Architecture 31 13 Opentoop Architecture with Miller Capacitance 33Harries cuaerer s CHAPTER 6 34 Multiplexed-Input Architectres 35 355 Recycling Architecture 39 3.6. Switched-Capactr Architecture 40 37 Currentode Architecture 42 References 4 BASIC PRINCIPLES OF DIGITAL-TO-ANALOG CONVERSION 45 44.1 General Considerations. 45 42 Performance Metis 47 463. Reference Multiplication and Division 49 431 oage Division 50 432 Curent Division £8 433, Change Division 63 444 Switching and Logical Functions in DACs 70 “44.1 Suiting Fonction in Resistor Ladder DACS 4142 Switching Functions in Cutet Steering DACs 483 Switching Functions in Capacitor DACS. 74 {S858 Binay-toTemomeer Code Comersion 76 References 77 DIGITAL-TO.ANALOG CONVERTER ARCHITECTURES 5.1 Restantadder DAC Architectores 79 SLL" Laer Arciecte with Switched Suber 51.2 laemmeshed Ladle Archtstures RE 5.2 Curent. Stering Architectres 84 52.1 RaRNework Bised Awhitectres 522 Segmentod Archtetres 90 References 94 ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.1. General Considerations. 96 6.2 Perfomance Merics 99 6.3 Flash Architectures 101 631. Reference Ladder DC and AC Bowing 108, {632 Nonlinear lout Capacitance 106 ” bs CHAPTER CHAPTERS 64 65 66 67 68 633 Kickback Noe 107 634 Sparkes in ThemometerCode 108, 635. Metsability 110 636 Slew-Depedont Sampling Poin 12 637 Clock Jter apd Dispersion 112 638 Gay Encoding 114 Two-Step Architectures 116 G1 Elect of Nondalies 121 642 ‘TwoStep Recycling Achicure 124 G83 ‘Two-Step Sabunging Architecture 125 Intepolative and Folding Architectures 126 65.1 Inespostion 127 Pipelined Architectures 140 Successive Approximation Architectres 143 Inereavel Architectres 147 Reieences 149 BUILDING BLOCKS OF DATA CONVERSION SYSTEMS 152 7 72 Amplifier 453 TL Opee-Loop Amplifiers 153 212 Choseditonp Ampiies 160 7113 Operon Amplifier 164 714 Gain Boosting Testnigues TL 7.15 Common Moe Feedback 172 Comparators 177 721" Bipolar Compactors 1 722 CMOS Conparstors 188 723 BICMOS Comparten, 191 References 195 PRECISION TECHNIQUES 198 aa Comparator Offset Cancellation 198 S11" Input Orfe Stone 199 5.12 Ouipu Off Storage | 201 813 Mulistage set Storage 202 ALA Compara Using Offe-Canclled Lathes 206 6.2 Op Amp Ofiset Cancellation 208CHAPTERS 83 Calibration Techniques 211 831 DACCaliation Tehigues 211 832 ADC Calton Techniques 208 184 Range Overlap and Digital Corection 228 References 229 TESTING AND CHARACTERIZATION. 232 9.1 General Considerations 232 9.2, Sampling Circuits 234 93. DIAConverers 239 9.4 AD Converters 239 51 State Testing 299 942. Dynamic Testing 241 INDEX. 252 Preface Data conversion provides the link between the analog world and digital sys- ‘ems ands performed by means of sampling cireuits, analog-o-digital (ND) comerers, and digal(o-analog (D/A) converters. With the increasing use of digital Compating and signal processing in applications such as medical maging, inswumentaton, consumer electronics, and communications, the field of data conversion systems has rapidly expanded over the past twenty year. Monolithic integration, new architectures, and advances im integrated ‘iret (IC) technology have dramatically change the design style of these systems and created new ares for research and development. Asa result the body of knowledge related to this field, primarily in te frm of conference proceeuings and journal papers, has grown to sch extent thet stents and Practicing engineers typically spend more than a year on the learning curve after they have competed other IC design courses. The lack of systematic, comprehensive treatment the subject has made the task of learning dificult ‘nd nefcient ‘This book has been written as 2 unified text dealing withthe analysis and design of dat converters. Intended fer classroom apt 3s well as industrial practic, it methodically lead the reaer from basic concepts to advanced topics while explaining design issues at boh circuit and system level. In addition, to broaden the readers view of technalogy-dependent ‘design style, the text provides examples of CMOS, bipolar. ast BICMOS implementations fr various ctcuits and discusses the trade-ofs in eahcase.‘Thereader is assumed to have a solid understanding of analog IC design, preferably atthe eel of Analysis and Design of Analog Integrated Circuits by P-R Gray and R. G. Meyer and Analog MOS Integrated Circuits or Signal Processing by R. Gregorian and G. C. Temes. Some knowledge of digital ‘tet and th theory of signals and systems is also assumed ‘The book consists of nine chapters. Chapter | serves a an introductory overview, familiarizing the reader withthe role of data conversion in larger systems and providing the "big picture” Chapter 2 deals with basic sampling ‘Grits and analy es the behavior of MOS and bipolar switches with emphasis ‘on ther speed-precision trade-offs. Circuit echniques that relax such trade: fsa aso described, Chapter 3 extends these techniques to the architecture level by introducing various simple-and-hod topologies. ‘Chapter 4 suits basi digital-o-analog conversion viewing this ane tion as reference mliplication or division. Topologies in which the reer cence is voltage, curen, or charge are analyzed and the switching functions equiredin such cireuits are described. These concept are applied to system- level design in Chapter 5, where dgital-to-analog converter architectures are presented. Chapter 6 deals with analog-to-igtt converter architectures. Fash, two-step, interpolating, folding pipelined, successive approximation, and imerleaved architectures are sted and thee design issu and sources of| ‘eror are examined. Chapter 7 describes the design of building blocks of data conversion systems. ‘(Open-oop amplifiers, operational amplifiers, and comparators are discussed and means of improving thet performance are introduce. Chapter 8 focuses on precision techniques applicable to high-resolution «data conversion. Comparator and op amp offset cancellation, DIA and A/D calibration, and overlap a digital corection are covered in this chapter. Chapter 9 is concerned with the important topic of testing and character ization. Various approaches fo evaluating the static and dynamic performance ‘of sampling ercuits and D/A and AD converters are described in det act chapter is accompanied with an extensive set of references allow ing the reader to access the evil work olted teach topic, understand the intricate detail t more depth, and learn techniques not described in the text, Publishing a book isan elaborate, sometimes overwhelming tsk that can be cared out only with the support of great many people. During the two years I worked on ths ok, the stimulating environment st AT&T Bell Labs and the guidance of my supervisor, Robert Swartz, enabled me to efficiently interleave research and writing. When the Rist draft Wa f= ‘shod. numberof expert rom both industry and academia reviewed various parts ofthe msanusrip and provide helpful comments, In particu Brian Brandt (IBM), Sing hin (National Semiconductor) Robert Jewett (HP Labs), Andrew Karaicolas (ATT Belt Labs), Stephen Lewis (UC Davis), Peter {Lim (Chrontel, Krishnaswamy Nagaraj (ATCT Bell Labs), Marcel Pelgom (Philips), David Rich (AT&T Bell Labs), and Bang-Sup Song (University of ‘Minos, Urbana-Champaign) contibued with their meticlous reviews and swish to express my’ gratitude to all f them. Iam ofcourse solely responsible for any erors or inconsistencies that may have emained in the text, ‘During the publication process. | have henetited from the kind suppor ofthe IEEE Press staff and would like to thank especially Russ Hl, Valerie Zaborski, Denise Gannon, and Dudley Kay for ltr efor. Behzad Raza1 Introduction to Data Conversion and Processing ‘The proliferation of digital compating and signal processing in clecwonic 9- tems is often described a5 “the world is becoming more digital every day Compared with ther analog counterpans, digital circuits exhibit lower sen- ‘Skit to noise and more robustness to supply and process variations, allow casier dosign an est automation, and oer more extensive programmability But, the primary factor tht his made digital eiruis and processors Ubi ‘ous inal spots of our lives is the hows in their perfomance as a result of| advances in integrated circuit technologies. In paris. scaling properties ‘of very large seal integration (VLSI) processes have allowed every w2¥ gen- eration of digital circuits wo attain higher speed. more functionality per chip lower power dissipation. or lower cost, These tends have also been aug ‘nesied by cout and architecture innovations as well as improve analysis and synthesis computer-aided design (CAD) tos ‘While the above mers of digital circuits provide a strong incentive 10 _make the world digital. two aspects of out physical environment impede such slobalization: (1) naturally eocurring signals re analog (2) human beings perceive and retain information in analog fom (atleast on a macsoscopic Scale). Furthermore, when digital signals are corrupted by the medium sich that they Become comparable with nose, itis often necessary #0 teat them ssanalog signals. For example, acording to information theory fora digital ‘Sigal buried in ose, amplitade digitization and subsequent decoding (soft decision decoding”) can impeave the bi error rate2 India Das Comenion and Prcesing Ch. Inorderto interface digital processors withthe analog word, data aegu ‘ition and reconstruction creuts must be used: analog-o-dgital converters (ADCS) to acai und dite the signal atthe frontend, and digbal-o-anaog. converers(DACS) to reproducethe signal al thebackend. Thisisillstatein Figure 11 iA Imefice truce lg Weel and gil proces DDataconversion interfaces find application in consumer products suchas compact disc players, camera recorders (camcorders), telephones. modems, ‘nd high-definition television (HDTV), 2s wells in specialized systems such ‘ss medical imaging, speech processing, insinimentation, industrial conto, ‘nd radar. We study one ofthese applications to illstate tbe importance of both data conversion and digital processing in a typical product. Figure 12isa simplified block diagram of poable cameorer electron ies [1]. The imaging front end consists ofan ara of charge-coupled devices (CCDs that produce charge output proportional to the light intensity. The ‘charg packets fomall the CCDs are sensed serially und converted to voltage, ‘andthe resulting signals digitized the ADC. Subsoquentl, operations such ssautofocusng, image stabilization, luminance/chrominance (Y/C)process- ing and zooming are performed using one oF more digital signal processors (DSPs). The processed video signal is then converted to analog form and recorded onthe ape. Wihile adding many Features tothe recorder and improving its user in terface the signal processing functions in Figure 1. are far oo complex tobe implemented nthe analog domain, In fact, most of these functions have been ‘ukled to camcoder simply because the ADC already provides the signals in digital form. “The performance required of the data conversion circuits used in video systems sich as that of Figure 1.2 varies rom one application to another In portable camcorders, a conversion rate ofa few wees of mepahertz with 10-bit resoltion is adequate, but the power dissipation (and prefealy the (Chap. 1 natin Da Conenion nd Passing 3 toons ee? |[ oe tee ne Lal onc [+ Yio, see re precesing outa Fig 12 Siplited ack dng of porate camer eons. supply voltage) must he minimized. In HDTY, seeds as high as 70 MHz are esiable, whereas in high-quality studio recording, reslions of 12 (0 14 bits are necessary. ‘Since data conversion interfaces must deal with both analog and digital signals, their design becomes increasingly difficult if they are to maintain comparable performance with their coresponding digital systems, ie, not ‘appear asa bottleneck inthe signal path. This is because the primary wade olf in digital circuits is between speed and power, wheres tht in analog circuits is between any 180 of speed, power, and precision (including res olution, dynamic ange. and linearity). Furthermore, the operation of both analog and digital eiuis onthe same chip leads to coupling ofthe noise generated bythe digital section tothe sensitive signals inthe analog setoe. “This coupling occurs via shared supply lines, substrate currents, or eros lk between adjacent ins High-performance data conversion systems have often been bil sh ‘nd strates, wherein diferent parts ofthe system are designed in diferent technologies and pled and interconnected on a common (nonconducting) subsite, This flexibility usally allows hybrids to achieve a higher speed ‘han teie monolithic countrparts—sbe kv to ther survival. However. issues such x cos. reliablty. and power dissipation have seated a trend woward im plementing these interfaces in monolithic (VLSI technologiesand ultimately Integrating an entire data processing ysiem on a single chip Most ofthe a= chitecture and design concepts described in his book are used in both hybrid an! monolithic aplications, but the emphasis son the later ype ‘The integration of data conversion systems in VLSI technologies entails ifculties due to sealing, the very technique adopted t0 improve the per formance of digital circus. As supply voltages and device dimensions are reduced, many effects oocur tat ae not predicted by the ideal scaling theory. For example, dynamic range becomes more limite invinsi gan f devices egrades, and device mismatch increases. In ation to these problems, ‘many ther analog design issues suchas devi noise and accurate control‘ Innditon to Ea Comeion an Proesng Chap. of device characteristics ate usualy ignored in optimizing VLSI technolo ses, and modeling of devices i spically performed with litle concern for Parameters important w analog design. Consequem'y, oaining the required precision becomes the primary concer in analog and sexed analog-igal ‘routs, often necessitating conservative design and sacrifice in speed and power dissipation. ‘Lets now closely examine the data conversion interfaces of Figure 11 ‘The analogtowigital (WD) interface converts continvous-amplitude, continvous-time input to a discrete-amplitide, discrete-time signal. Shown in Figure 13 this interface in more det. Fist, an analog low-pas filter lim its the input signol bandwidth so that subsequent sampling does no alas any ‘uated noise oF signal components into the acta signal band. Next, the filter ouput is spl soa o produce adicrete-time signal. The amplitude ‘ofthis waveform is then “quantized” 4, approximated with level from a set of xed references thus generating a dseete-ampliudesgeal. Finally, a 38 ay AT. an ‘where 5) dnote the Dirac dela funtion, Tiscaus the signa specu to teconolved withatrainof impulses ithe frequency domain, hs repiating ad shifting the signal spe by integer males of nin= xe S B-fyan Lee TeX “This peta yields signals that are easy to analyze but sno practical because of thediicultiesin generating an del impulse or any reasonable approxima: tion thereof. Als, the samples produced his operation re often difcul to process because circuits following the Sampler usally requie thatthe sampled signal have a nonzero duration, ey S21 Genera Comision , In the second scheme [Figure 21] the value ofthe waveform atthe sampling instant is captured and eld until the next sampling instant. This equivalent to multiplying the waveform by a periodic tain of impulses ad ‘snvolving the result witha rectangle Function [ro Eaewofenge-p. eo mo) whote Flr/Ts~ 1/2) denstes single pulse with unity amplitude fom = 0 {or = Ts, the frequency domain. aspect similar that of Figure 2.1) is obtained bu iis mulipied by sine function: mn nian gy sete einen eet = yatn = fay $50 -ars- B] on es) te 2 Ts vane Sei os amy pert re Baw® ai Sampling Cis Chap. 2 In contrast with the ideal stmpler, the zeroorder-old and the track and-hold schemes yield ouput speeta that have sine envelope, ic. are “distored.” This problem mandates sine compensation techniques (1 f the sampler is wed atthe back end of a data processing system, Tor example following a DIA converter (Chapter 1). However, the zero-oner-hold and track-and-hold circuits ean be used at the fron end of A/D converters with no concer forthe sinc distortion. Thisis possible because A/D converters sense ‘he output of th front-end sampler only during the bold mode, and hence the digtied value corresponds to sampled points on the inpt waveform. In ‘other wows, the combination of the front-end tack-and-hold and the A/D jomerter operates as an ideal sampling circuit In high-speed systems, the distinction berween the outputs of the er0- ‘order hold and track-and: hold schemes bepins to diminish because the per ‘ure window width becomes comparable withthe sampling period. Asa esl except for special application where te aperture window is inthe picosecond ‘ange [2], most monolithic sampling circuits operate asin the wack-and-hold ‘Scheme. In this book, we consider implementations of his scheme, which are often called sample-and-hold amplifiers (SHAS) or wack-and-bold amplifies (THAs, Figure 22 shows a simple sample-and-hold circuit. Inthe sampling cqusion) mode, switch $ controlled by CK ison and the ouput voltage, Vo. tack the inp voltage, Vi. Inthe transition to the old mode, S turns cf and Vay remains constant until the ext sampling period. In this circuit, the switching operation ind the transient cuments drawn by Cy introduce ‘noise atthe input, often manting the use ofa front-end buffer. Furthermore, since the voltage stored on Cy daring the hold mode can be corrupted by any constant or wansientcurent drawnby the Following circuit, a buffer must also be placed atthe output resulting in the ciruit shown in Figure 2.3. cK es Fig. 22 Simple anpleans old Inpractice, the nonidealities ssocated withthe buffers andthe sampling switch in Figure 23 necessitate substantial added complexity to achiew a $66.22 Peformance Metie " aiven set of performance specifications. In act, as discussed in Chapter 3, Some SHA architectures are considerably different from that of Figure 23, Input Output Butter CK Butter Pte. iP. ig. 23 Sample nd ld hou with ip and tpt ters Before describing various nonidealities that accompany the building blocks of SHAs. we need to define performance specifications of sampling 2.2. PERFORMANCE METRICS In omer to characterize sampling cireuits thoroughly, a large number ofp rameters must be evaluated. The terminology and definitions adopted for SHA metrics by different manufacturers are not exactly the same anc an «cause confusion when dlferent designs ae compare. I his section we de fine a number of terms commonly used to describe the performance of SHAS ‘0 8 to establish a consistent set of metrics fr ths book. Fora more com prehensive set of definitions, the readers refered to the erature [3] and 10 manufacturer” data books, ‘The performance metrics defined below are illustrated graphically in Figure 24 and discussed using the SHA architecture of Figure 2.3 ‘Acquisition time, fg, the time after the sampling command re- ‘quired forthe SHA output to experience a full-scale transition and Sle within specified ertoe ind around its Gina vale. Acqui- Sivon ime is determined by the recovery delay of By and Bs the lon-resistance of 5, the valve of Cy, and the maximum allowable * Hold setting ime, ty, is the time after the hold command required for the SHA output to sete within a specified error band around its final value. This ime is given primarily by the seing ime of Ba. ‘+ Dynamie range isthe rato ofthe maximum allowable input swing and ‘the minimum input level that an be sampled with specified accuracyasi SamplingCreuis Chip. 2 Dynamic range is limited by supply voltage, sreshold or tum-on voltage of devices used in he eteit, and input-reered noise ofthe Nonlinearity errors the maximm deviation ofthe SHA inpavoutput ‘Ad in Figure 24(b)]. Usually specitied forthe held values of the i ertor originates fom nonlinearities in By and oan ‘ar dependence upon big ofthe charge injected by onto Cy and ‘aration ofthe sith on-esstnce wit the input voltage. Aperture iter isthe random variation inthe time requited for the sampling switch o turnoff after the hold command is asserted. Also called “aperture uncertain” this eor isa measure ofthe deviation of sampling instants fom equally spaced points in time and arises from the nose that afects the hold command assertion eter in transitions of CR. Pdestal ero voltage isthe errorintoduced atthe SHA output during the transition fom sample to hold, This eror sms rom the charge iupcted by § lo Cy when this switch turns of. Gain error the deviation ofthe slope of line AB from its deal value (usually unity), Tis eror results from the gain eror of By and Bs and input dependent pedesal volage Hold-mode feedthrough i the percetageof the input signal that ap- pears tthe output during the hold mode. This effet appears because ssc 5 usually ha a parasitic capacitive path between its input and ‘oviput terminals even in the off sae. This path conducts voltage ‘ariations and gives rise to input feedthrough during the hold mode Droop rate isthe rate of discharge of the capacitor during the hold mode. Droop rate is fuetion of the leakage curents draw by paras de paths from node X wo other nodes (eg, the substrate). the Input bias current of Bs, and the value of Cy, Signalto-noise aio (SNR) isthe ratio the signal power tthe noise poster atthe output inthe hold mode (usualy Toe sinusoidal inp) [SNR is limited by the noise contributions fom Ay, ahd San he aperture iter, Signal-to (noise + distortion) ratio (SNDR) isthe rato ofthe signal power tothe foal noise and harmonic power atthe ouput in the hold ‘mode (or sinsoidal input SNDR s limited by the nose sources ‘mentioned above nd nonlneariies resulting vom By, Ba, and charge Injection of 5. S063 Sampling Stces 2 i) < Vor co Fe 24 Sample sl psfrmace mis 2.3 SAMPLING SWITCHES ‘As noted in the previous secon, large number of SHA Timitation orgi- tat fom nonidealities of the sampiag Switch. Acquistion time, aperture jitter. nonlinearity, pedestal erro, feedthrough, and SNDR of these circuits te strongly inlvenced by the sampling switch performance Tn this section, we describe two types of sampling switches commonly ibiza in €MOS and bipolar SHAS. In Chapter 3, we will se that depending, fn the architecture, other switching techniques can be employed to improve the performance.4 ‘Basi Sumpling Cacais Chap 2 23.1 MOS Switches ‘AnMOS transstorcan be wed as an analog swith, wit is gate vollage controlling the resistance berween ls source and dean (Figure 25), For ‘square law NMOS device that operates in the linea (see) eegon, this resistance can be expressed as ' aC EVs — Vand" were isthe eestron mobility in the channel, Cs the gate oxide capac itane per unit fe, W and Lae the Tete with and length of the device, respectively, Vos isthe gate-source voliage, and Vr isthe threshold velage For a fixed sampling capacitor, the acquisition time can be deceased only by lowering Ry. ie. by increasing the tems inthe denominator of (210) 1m agiven CMOS process, Cx is normally constant and Vos sully ean- not exceed the supply voltage, leaving W/L as te only variable in (2.10) ‘Thus highspeed applications often incorporate MOS switches with a large wie. Rew ¥ oe E Vou Ym * q You @ o ig 28-0) MOS sling ces () equal owe te mpg In addition (0 a finite on-resistance, MOS switches exhibit channel charge injection and clock feedthrough. When on, a MOSFET caries acer tain amount of charge in i channel that, under strong inversion conditions, can be expressed as Oa © WEE Ves ~ Vr. eu ‘When the device tums ofthis charge leaves the channel through the soars and dean terminals, introducing an eror voltage onthe sampling capacitor (igure 26). This ewor appears aban offset if Qe is constant, again eror i (Qs incaly proportional othe inp sigh, oa nonlinear erm if Oy has 3 ‘nonlinear depenienc athe inp signal, While the isttwo peso errorcan be tolerated in some applications ee, data converters used in digital signal Se. 23 Sampling Shes processing), the thin type Tits se inearty ofthe SHA and contributes Frmonic distortion. The nonlneat component in Qc aes rimarily from the nonlinear dependence of Vig i (2.11) onthe input voltage through body cles. “The charge injection mechanism in MOS switches hasbeen analyzed ‘extensively [4 5,6), These studies show thatthe faction of de charge in jected onto the sree and drain terminals depends on both the impedance ‘een a these noes and the clock ans tne [6]. In ado, these stad ies have provided mathematical descriptions ofthe inet theoretical and experimental plots ofthe injected charge asa function of the impedanoes and clock tassiton time [6 In practice, however. itis dificult to accurately pret or contol these variables or apply the ero figures me ‘Sued fora given opology 1 anoereieuit. More importandy, most ofthe present circuit simulation programs do ot sodel this mechasism accurate! For these reasons, many citeut techniques have been inves © suppress charge injection ero eeardles ofthe exact valve of such prameters as ter- nial impedances and clock transition ies. These techniques ae described inthe context of SHA architectures in Chapter 3 "Amote soce of erin MOS switcesis cock feeiouh,causedby the nite overlap capacitance between he gte and source or drain terminals. ‘As depicted in Figure 2.6, when the gate contol voltage CX changes sate te turn the switch, Cw conducts the transition and changes the voltage sored fon Cu by at amount equal 10 Cu meu where Vex is the amplitude of CK. This equation insicees that clock Feedthrough is independent ofthe input signal if Cy is constant and thus “appears aan offset nthe inpuoupat characteristic ave ery6 ase Samping Cats Chap. 2 A frequency-dependest nonlinearity err in MOS sampling circuits arises from the variation of the switch o-tsistance with the input voltage, ite the dependence of Rag n'2.10) upen Vos. As shown in Figure 27 or high-frequency inputs this variation inroducesinputdependent phase shit an hence harmon distortion. Yin on igh Fig.27-Dstonion ced hy swith on estan aio inte hing Another eror that appears in high-speed MOS sampling circuits stems from the inpt-dependent sampling insta. Since the MOS switch turns off ‘only when it gate-source voltage has fallen below Vn. the time at which the device turns off and the cicut enters the hold mode) depends on the insantaneous level ofthe input. For example, if the switch fs an NMOS. ‘wansistor, then the circuit enters the hold made slighty later whe the input Signal is near ground potential than when its higher. Mlusraed in Figure 28, this phenomenon introduces iter and harmonie distortion and becomes noticeable when the cock transition ime s comparable with the inp signal slew rate. Fora sinusoidal input with ampliude A and frequency fi it has ‘been shown hi this phenomenon limits the signal-t-distrton ratio (SDR) ofthe SHA to Vor ai where Vx and ty are the clock amplitude and fllime, respect ‘An important aspect of sampling ereit is the hold-mode fedtvough because it can conibute noise o the output. As shown in Figure 2.9, for 44 MOS soit tis error results from the path through the soure-gate and gate drain overlap capacitance and canbe expressed 3s SDR po = 20boy See.23Sumping Swit: ” Fig. 28 Depends Sampling isnt ing ee Yat e1) Ve where Ryu denotesthe output esistance ofthe switch driver and itis assumed Cor & Cr The vale of Rou shouldbe chosen such that he feedthrough at ‘maximum input Fequeney i suficently small ke fee Coy... Vy AE ~ 3 Min I” Mout Fig 20 Hothnode Fediroush, “The sampling switeh input and output ange can aso mit he Fllseate voltage swing ofa sampling circuit. Fora supply voltage of Vin. the cir cuit of Figure 2.5 has @ maximum full-scale range of Vo — Via. Where Vi ncludes the body effet where appropriate. In practic, the input swing hardly exceeds (Vip — Vni)/2 because ofthe substantial increase in switch resistance and the resulting Fequency-dependeat harmonic distortion. This” Base Samoting Crees Chap. 2 range can be extended to supply rails ifthe swith i welized asa comple- ‘mentary pit. As depicted in Figure 2.10 ths s accomplished by controling the gates of a» NMOS and a PMOS devi with complementary clocks so thatthe two devices turn on and off simultaneously, I transistor conducts for 0 = Va < Veo ~ Vass while the PMOS device is on for [Viyol < Vn = Vo. thereby providing ait input and output range cK ma Fig 210 Complementary MOS anping ches In addition to an extended range, the circuit of Figure 210 has another important advantage over that of Figure 2.5: the equivalent on-esistnce of {8 CMOS switch, compared with that ofa single NMOS or PMOS device, ‘ares mach less a a funtion ofthe input voltage. Figure 21 plots the on- resistance of an NMOS, a PMOS, and a complementary MOS switch versus the input volage, indicating only @ small peak inthe CMOS on-esistance near the middle ofthe range. The relatively constant on-esistance across the entire inpuvoutput range allows reasonable sizes forthe switches and also ‘minimizes the harmonic distortion caused by variation of switch resistance ‘While it may seem that M and Af in Figure 2.10 cancel cach others charge injection if they have identical dimensions. equation (21 indicates ‘hat [Qual depends on [Vos — Vn and hence will noc be equal for Mf, and (Ma if Vg has an arbitrary vale. lohighspeed applications, the complementary clocks required for ‘CMOS switchescan pose timing problem. Unless the clock edgesare aligned such tha the two transistors tun off a prccsey the same instant ether one ‘cul be conducting weakly for short while, intodocing an input dependent pase shift or sampling instant An important feature of MOS switches stat they intodee 2x0 offset (level shit) fom ther source to their drain if the following circuit draws no 6.23 Sampling Sn » Pol Pus: os. 0 re foo Vin Min current, This isin contrast with the behavior of diode switches described below. 2.3.2 Diode Switches Semiconductor diodes exhibit sal on-esstanee, larg off-esistance, high-speed switching. and thus poental for the switching function in sam Pling circuits. simplitid diagram o typical diode switchs shown in Fig ‘e212 [8]. Here, four diodes form abridge that proves a low-impedance: Pat foo V0 Vay When eureet sources 7; and 2 are on and in the ideal ease) isolates Vg trom gehen fy and Js ae off, Nominal, f) = f= 1 For sonall signals a Vp and Vag, the equivalent on-resistance of the site, Ry equal tothe parallel combination ofthe resistance ofthe 180. branches consisting of Dy-Dz and Dy-Dy. Each diode exhibits an incremental resistance, I/gq, resting from its exponential -V characteristics, as well san oie resianee, 7, due to comet and material resistance. Thus, +0 es, Ineniero minimize Ry, gq canbe increased by raising the bias cureat ‘or ean be lowered by inreasing the area of each diode, The latter remedy, however, increases the junetion capacitance of the diodes, thus causing larger feeathrough inthe hold mode. This effet is quanied late. ‘Actual implementations ofthe diode sampling bridge often control only ‘one ofthe curtent sources, usually 1, while the other is always on. Tis js because i is ficult to tam off and Jp at precisely the same instant,” Base Sampling Crests Chap. 2 ig 212 Diode snp sch ‘especially if high-speed pnp or PMOS trunsstrs are not availabe, Figure 2.13 illstates such ab implemenation. Here, when CX is high, Qy is ‘off, Qs on, andthe circuit isi the acquisition mode, When CK goes ow. (0; tums 0a, O> and hence the bridge turn of, and the circuit enters the hold ‘mode. Note tht 1) need aot bea high-speed device frit operate asa passive ‘Component, but the capacitance i introduces at node X is etic Inthe creitof Figure 213g), when CX is low andthe bridge sof, Qs ‘may enter stuation because the voltage at node X isnot well-defined. Figure 2.1Mb> depicts a modification where clamp diodes Ds and Dg and current Ssowee Fy are added to the circuit. Typically. [2 ~ J) + /s and the clamp voltage Vpy is atthe midpoint ofthe inpot voltage range. When Cis high, (Q2 sink bosh f and, and Ds and Dg are reverse-iased if Vp} ~ Vo ion = Vin < Var + Vosgay. When CK goes low, Fs flows from node X, Ds turns ‘onand Vy iselamped to Vai ~ Voson. wile Fy lows through Dy and Vy is clamped © Vay + Vos "The variation ofthe on-esistanceof a diode switch function ofthe inpat voltage is differen from that of a MOS device. Inthe circuit of Figure 211, when the input voltage goes through a positive excursion, Cy draws turrent from Dz; therefore, Dy and Dy condvct les, whereas Dy and Ds conduct more. Ifthe change Inthe curents of Dy-Da isa smal fraction oF their quiesentcurent fo, then the increase inthe resistance of Dy and Dy is compensated by the decrease inthe resistance of Dz and Ds espetively. ® » Fig212_(Siplebiptr sampling ig; ( mated wihlany thereby yleking negligible variation inthe on resistance ofthe ove switch, ‘We can formulate the above condition by noting that Vin Ve Asin 216) ‘hen the maximum curent drawn by Cy occurs when = nx /eandisequalto Bog I = Conn cnet, ern Cube es) ‘This current must remain much les than. CwAw et. a9 ‘The charge injection and feedhrough behavior of diode switches is also Afferent from tht of MOS devices. Since a diode biased at a current Ip carries «charge equal to fo re, where tes the transit dime, the charge injection eroris relatively constant because, as expltned above, ina properly designed switch Jp remain atl constant. Thus charg injection inreduces ‘only a constant offset inthe inpuvourput characters. On the other han,2 a Sain its Chip 2 in the diode bridge of Fire 213(b) the change in Vy and Vy. which is coupled to the output srough the junction capacitance of Ds and Da, causes nonlinearity and gain eror (9. To understand why, note that in the tacking mode, Vix = B+ Vos ate Vy = Vn ~ Voge. whereas inthe hold mode, Vy = Yai ~ Viv and Vy = Vai + Vow). Consequenty inthe transition fram tracking 10 hold, Vy drops by Vie — Vai + 2Voqon ad Vy tses by Vp ~ Vn + 2Vine creating an inpu-dependent pedestal at Vo. Since the junction capacitance of D> and Ds is voltage-dependent, the pedestal has 3 significant nonlinear component In order to eliminate the input dependence of the pedestal, Va can be bootstrapped 10 the held output voltage (9). This is illustrated in Fate 214, where the unty-gain ber provides a clamp voltage equ tothe he evel. Now Vx and Vy change by ~2Vpje and +2Vians espetivel, Yielding substantially less nonlinear Pig 244 Sanpin ee wih ostppa tmp waa “Thehold-modefedthrough of sampling brides depends on the junetion capacitance ofthe ridge diodes and the on-esstnce of the elap deve Sec.23 Sampo niches » For example, when the circuit of Figure 2.13() isin the hold mod, it can be simplitiod as shown in Figure 215, where the aneton eapacitance of Dy 1D is modeled with C), and the on-rexistance of Ds and Dy with Req. FOr 6) Cys the feedthrough transfer function is expressed as Vo yyw 201, Reals 220) 1 ore og i Fen N Yi Yor Fen fm GG A ingress natn ty inpne on te inp an apr oage nig ine ce of Fg 1S) ‘Sen ae ply re ist OS in a hgh tt ingens he econ a 189) fe ene tat gs mothe Vere procs 03 Vo oe nt awd {SnC ge, Acs betunima slag ving sn gna SX pation 10 Roce eer fd chsh ft gt apt due rs msmacies, Forex nPgu2 130) f= yr 8 {Dyan Do ntact ei out fat lage vn Ven SE 4 MS Von Vein + SE 4 erste ela ish been te tin cen y my 2.3.3 Comparison of MOS and Diode Switches Following ur study of MOS and nd switches in the lst two Sections, we can now compare their properts. a2 * Diode switches generally have a Jower on-esstance than MOS sovtehes. IF each diode ina bridge is based a 0.5 mA and has aPy avi Sampling Crests Chap. 2 seri (ohmic) resistance of 40 2, then the equivalent onesitance ‘ofthe bridge i approximately 90 2. Ataning such a low resistance with « MOSFET sully requires very large widh-0-length ratios, 'ypically eeatr than 1000. This in turn exacerhaes charge injection an lock feedthrough problems ‘Thea resistance and charge injection of diode switches depend much Jess on the input voltage than do those of MOS devies, making the former moe attractive Tor high-precision open-loop applications, Diode switches suchas that of Figure 2.13 operate with clock vltage ‘wings roughly an order of magnitude smaller than those of MOS ci ‘cuits, allowing sharper edges and better definition ef sampling pots in time, For this eason and dacause of lower noise in ECL circuits than i» MOS cireuits, diode switches have a potentially lowe jer than their MOS counterparts ‘+ The input voltage ange of MOS sampling circuits is generally lager ‘han that of diode suites, thus allowing a wider dynamic range. MOS switches introduce node level shift (fst from the ips the output ifthe following citeut draws no curent. Diode bridges, ‘on the other hand, serra inte offset caused by mismatches in current sources and odes, *# Diode switches are ypieally mach more complex an dissipate much more power than MOS sampling cieuls. The circuit of Figure 2.1310), for example, quires atleast six diodes, a ditlerential pit, and hrc curten surces whose magnitudes and variations with fe. perature and process mast he well-contmiled. -& MOS sampling Site, on te ater hand consists af one of two transistors. While this dfterence in complexity and power dissipation may nt be sig nificant fora single SHA, i becomes important sf sampled-data system such as an A/D converter oa filter require a great number ‘of sampling switches. 2.3.4 Improvements in MOS Switch Performance ‘The simplicity of MOS switches has made them tractive frlarge-seale analog iigrated cireuits. However, as discussed in previous sections, MOS devices suffer from large on resistance and substantial charge stored in thet chanel. Infact, the strong trade-off between these two parameters imi the level of ypeed-acuracy that cap he achieved ina simple circuit such a8 that ‘of Figure 2.5, We can formulate this trade-off by detning a figure of meric F = {(pedesial enor acquisition ney}! 222 Se. 23 Sampling Swen s ‘The pedestal rors ay, 02) 2H WLCox(Vos — Vow) uy where we have assumed hal of the channel charge of te switch is injected ‘onto Cy and nesected clock Feetirough, The acquisition time constant is Rau 225) Cu Tab Ves = Vand Note that since tay depends onthe gate-source voltage and ence varies with input, modeling the acquisition Behavior witha single ime constant sony 3 rough approximation. from (2.24) and (2.26) i flows that 1 : em 026) pie a 4 (2.28) qs ‘This equation indicates tha, ina given CMOS technology the MOS sampling -sircat of Figure 2-5 doesnot achieve a spesd-accuracy product higher than roughly 2s,/L2, This producti further degraded by clock feedthrough, Tm onder to rela the trade-off given by (2.28), numberof circuit tech niques have been proposed, two of which ae illustrated in Fighre 2.16. In Figure 2.16(a) adummy device M; with half the wid ofthe spring switch 1M, (and he same length) is added and driven By CK, the complement ofthe Sampling clock CA [16 tnthis ireut, when A tues off ad injets charge ‘nto Ci Mo turns on and absorbs charge from Cy in is ehanne, This, itexactly half ofthe My channel charge is injected onto Cy, then complete ‘aneelation occurs andthe held voltage on Cy is nt corrupted by the charge injection, However, the fraction of channel charge injected by M; onto i source and drain depends onthe impedance seen athe input and eur nodes and the clock tanstion speed [6] indicating tat Cyr may not recive ball of the Af; channel charge and that this scheme may not provide accurate cexncocon Figure 216(b) shows another sampling configuration, where the cre 1s implemented jn differential form (11). Th ths topology. Vins and Van2 ane ferential inpats (Ve, they vary by the same amount bul in opposite6 Basi Sampling inate Co. _ cK cK t My Ma Vins Yours a tm y, Cy = io Fe. 216-Cansiton of MOS cg ition ig amy sui 0) tore operate iectons) and Vay and Vag? fe diferenta outputs (ie. thee diference is sensed by the following circuit), Charge injection and clock feedthrough fro at Vg aD V2 A tthe fist order equ ad hence appear ee ‘eommon- mode (CM) component athe output. Ap important ero, however, Still ents ere: since the chanze charge of Mand My isa function of their Vas apd since Vy # Vin2 the differential eld output ineludes an Input-dependent charg injection eror tr. This term introduces gin error and nontneariy limiting the usefulness of this topology only to applications Where Vig ~ V2 ich less than the Vos ~ Vi of the swtches, ‘Another MOS sampling technigue is depicted in Figure 2.17. tn the acquisition mode, Mi and My are on. Miso, Yau = Voov andthe capacitor ‘voltage tacks the input. fn the transition othe hold mode, rst & goes kw, turning off Ma, and after a small delay falls, wring My off nd #7 00 ‘Thus. Vi drops from Vj to 0 and ence the cage in Vag i 9 10 —Va atthe sampling instant."Since 4 always tur of fis, the channel charge ‘of Mya i input dependent—does not inroce any eno. Moreover, a te gatesoure voltage of Mr is independent of Vg. the channel charge injected by this switch spears 38a constant offset tthe output. ‘While suppressing input dependent charge injection. the circuit of Fig ‘re 2.17 sues from another source of nonlinearity that limits is spec. In the transition t hold, when Vg falls from Vp t© Vino ~ Vn 8 voltage d- vision occurs between Cy ad the rain junction eaacitance of Ms, siding nonlinear component it Vou Since this capacitance is properconal to the ‘device width, i iadesdirecly with the on-esstance and hence the acquis sition time. Nevertheless, illerental Yersions ofthis topology an provide _laively high speed and high linearity. p.2 Referees 2 am, Cn Betas (217 C0 wn hs Appendix2.1 Effectaf Aperture teron SNR. Considerasine wave ‘in 2x fit samples at ¢-= ATs +, where « isthe aperture iter. Since each sampling instant can deviate from ts ideal valve bye, the sampled amplitude fas an ror of €dVg/dt. Thus, the overall sampled waveform am be viewed asthe sum ofan ideal sine wave and noise component. To taleulate the SNR for an otherwise ideal sampling crit, we assume that € Jgarandom process uncomelied with Vand expres the poise power as al (haa padd, [Matera Q. aE 029) aaa. 2230) pu) denotes the mean squared value of ¢ (12). Thus, SNR = ~2010g(23 fing) 6B: ean This relation proves wef ifjteris the dominant source of nose in a system, Ina general ese, ther sources f nose must be taken ino account a wel REFERENCES 1} R. Gregorian and G. C. Temes, aloe MOS tntegrated Circuits for Signal Processing, Zohn Wiley and Sons, New York. 1986 (21K. Rush and D. J. Oldfield, “A Data Acquisition System for a 1-Gltz Digitizing Oscilloscope." Hewlen-Puckard J, April 1986, pp, 4-11 [31 S. K. Tewksbury, etal, "Terminology Related to the Performance of SIM, A/D, and DIA Ciscuits” IEEE Trans. Creuts Syst. vol, CAS.25, Pp. 419-426, July 1978= ase Samp Cuts Chap 2 Is] B. J. Shou and C. Hu, “Switch-Induced Error Voltage on Switched Capacitor” IEEE J, Sol State Crews, vol SC-19, pp 519528, April 198, [5] W.B. Wilson etal, "Measurement ard Modeling of Charge Feedthrough in.W-Channel MOS Analog Switch," IEEE J. Solid State Circuits, vo $C-20, pp. 1206-1213, Dec. 1985 (6) G. Weamann, B.A. Vitor and F Rahal, “Charge Injection in Analog MOS Switches” IEEE J. Solid State Cireuis, vol. 8C22, pp. 1091 1097, Dec, 1987, [7] B.A. Lim, Performance Limitsof Circuits for Analog-to-Digital Conver sion, PAD. disseation, Stavord University, March 1991 [8} J.R. Gray and S.C. Ktsopculs, “A Precision Sample and Hold Circuit With Subnanosecond Switching.” IEEE Trane Circuit Theory, vol. CF 1p. 389-396, Sep. 1964 [9] K.Poution J.J.Corcorar, and. Horak, "A 1 GHz 6-Bit ADC System,” IEEE J Solid State Cireuits, vol. SC-2, pp. 962-970, Dec. 1982 [10} C. Eichenberger and W. Guggenbuhl, “Dummy Transistor Compensa- tion OF Analog MOS Switches” /EEE I Solid-State Circuits, vol SC-24 pp. 143-1145, Aug. 1989, [1] K. C. Hsieh et al, "A. Low Noise Chopper Stabilized Differential Switched Capacitor Filtering Technique,” EEE J. Solid-State Creuts, ‘ol SC-16, pp. 798-715, Dec. 1981 [12] M. Shinagawa, ¥. Akazawa, and T, Wakimoto, “Biter Analysis of High: Speed Sampling Systems," IEEE J. Solid Stare Circuits, vol. SC-25, pp. 220.204, Feb 1990, 3 Sample-and-Hold Architectures Since the inodetion ofthe fist monolithic sample-and-hold amplifier in 1074 [1], a variety of architectures amenable to integration indifferent tech otoges have been propose. Owing to these architectures, as well 38 ad- ‘ances in integrated circu technology, the performance of SHAS his dr maially improved, proifing 12-bit acquisition times of less than 25 nse in 1091 [2] compared to 10sec in 1974 [1]. These architectures generally em play circuit techniques w reduce the pedestal err without sacrificing speed land linearity ofthe system, In thischaper, we describe a number of SHA architectures often use in ata acquisition systems. Upto the mid-1980s, most sample-and-hod ics Fel into either the “open-loop” ofthe “elose-oop” eategory [I], However, the configurations introduced in recent years cannot really be classified in {his fashion because the incorporate varius local and soba feodbuck pat, ‘obscuring the disinetion between open-loop and closed-loop topologies inthe ‘conventional sexse. For this reason, we deserbe each ofthese architectures individually 3.1. CONVENTIONAL OPEN-LOOP ARCHITECTURE “The open-bop architecture has been considered attractive because of its sim Plieity and potential speed. Used in Chapter 2 to ilustate SHA propentis land shown in Figure 3, this architecture consists ofan input Buller By,” Samolean Hold ciesnes Chap. 3 ‘Sampling circuit comprising $ and Cy. and an output buffer Ba. When Sis ‘on, the crit sin the acquisition mode and Vi tacks Vi When Sturas (of, the instantancous value ofthe input is stored on Cy and the circuit enters the hold mode, Input output Butter OK Butter Fe 3M Osu ample nol cite As this topology includes no global feedback, its unconditionally st ble (if and By are stable) and can therefore be designed fr high-speed ‘operation. For example, utilizing Schottky diode bridges, this architetare has achieved rates as igh as 2 GHz [3 “The speed of the citcut in Figure 3.1 is determined by is acquis tion time and hold setling time. The acquisition time depends onthe tack: ing speed and output impedance of By, the onresitance ofS, and the value of Cr while the hold seling time is governed by the seting behavior of By In adton to ther impact on the SHAS speed, B) and By also influence the linearity ofthe system, especialy because both experience full signal swingsat teint and output. As aconscquence, the linearity requiemeats ofthe overall SHA often impose resvctions an the design of By and Ba, thus limiting their speed. In acneral, these buffers can employ aper-00p ‘configurations with varius correction echriges [3] to achive linearis up to IOC, For higher linearity, they are usually implemsntd as bih-gain amplifiers with local feedback. Chapter 7 describes various ampliter sign ‘An important drawack of this architecture results fom the inpu-de- pendent charge injected by the simpling switch onto the hold capacitor, an feminent source of nonlinearity in MOS implementations. As explained in Section 2.3 this err is not reliably canceled by dummy devices or differen ‘ial configurations and hence limits the linearity of open-loop CMOS SHAS {o approximately bits. Diode switches, on the other hand, exhibit much less inpu-dependent charge injection and have been succesfully used for Tinearites upto 12 bis in bipolar technology (3) 6.32 omen Cad Loop Arte ” {in summary the open-loop architecture offers highspeed and eatvely high linearity when realized in bipolar SHAs with diode bridges but sufers from input-dependent pedestal ertor in CMOS implementations. 3.2 CONVENTIONAL CLOSED-LOOP ARCHITECTURE Inoner to suppres input-dependent pedestal errors in a SHA, the sam plingsvitch canbe included na feedback lop such hit texperences voltage swings moch smaller than the input and output swings. This concept the brass for the closed-loop architecture shown in Figure 3.2, which cousins of transconductance amplifier Gy, sampling devices and Cy, a a voltage unpliie Ap [1]. The circuit operates as follows, In the aquisition mode, S ‘son and the cteu functions asa two-stage opamp compensated by Cry and configured as a unity-guin bu. Thus, the output closely follows the input and, if Ap is large, X is vital ground node allowing the voltage across Ci w track the input. When 5 turns of, the instantaneous utp volage is stored on Cy and the feedback circuit consisting of ay abd Cy retains te sampled voltage atthe output, Fig A2_ Credo ampli, ‘An important feature ofthis architecture arises from the virtual ground propety of node X: since inthe sapling mode the output volage of Gis also close to ground poten switch $ always tums off with a constant volt ‘age at its inp and outpat erminas, hereby injecting a constant charge onto {Cy and introducing a pedestal errr tha is independent of the inp signa [Asa rest this error appears primarily as an offset voltage and contites ‘negligible nonlinear. In order t reduce the offset resulting fom charge in- {ection and clock feedthrough, asepica ofthe sampling network can be placed atthe noninverting iu of Apso that the pedestal appears equally at bath of its inputs, ies as a common-mode voltage, This techniqoef ilestated for MOS switches in Figure 3.36], where Ms and Cp ae idemical with My and Cy, respectively. nthis et, My and M turn of simultaneously injecting chanel charge onto Cy, and C:. However these charge packets may not be2 SpleanldlllAmtcres Chap. 3 Fig. Closet oop samplant od cece wt pes anes exactly equal because My sees the output impedance of Gy on onesie whi ‘Mf sees the ground, Nonetheless, clock feedthrough components ofthe ped- estalsare equal and cancel ou. More accurate cancelation ofthe pedestals ean be achieved through the use ofthis achtectare in uly differential form 6) “The main limitation of closed-loop architecture arises fom its stabil- ity ad speed considerations. Since the circuit of Figure 8.2 functions as ‘two-stage opamp inthe sampling mode, the dominant pole piven by the ‘output impedance of Gy and the Miler multiplication of Ci must provide a reasonable phase margin so tht the output quickly racks the input with thee ‘uired accuracy. Asin atypical two-stage op amp (Chapec 7, several Factors Alegre the phase margin and, more import, the ott seing behav Joe Size Gy, and Ag usualy conibute several nondominant pols, some of ‘which may not be siciendy greater than the dominart pole seuing to high ‘ecuraces mabe slow. Furthermore. the pole given by the output impedance fof Ag andthe loacapacitance olen causes lng sting times. Additionally, the magnitude ofthis ole may vary with Ve ifthe output impedance of Ay ‘depends on the load curent, thereby inroiing output-dependent sting components (6. This effects discussed in Chapsr 7. “The above stability issues often necessitate conservative compensation ofthe closed-loop architecture so sto avoid undenfamped setling despite ‘variations in process, load capacitance. and temperature. Consequenty, this architecture does nt usually achieve the naximum potential sped of given technology. ‘Another drawback of hisarchitectre stemsrom the signal path rom Vi, to Vag through the input capacitance of Gi This pth introduces significant hold-mode feedthrough ithe capacitance between the input terminal of Gg is large ei the input tage of Guiles large deviee. The feednough is attenuated bythe outpat impedance of the unity-zain amplifer comprising ‘Aga Cir. But this impedance typically increases with the inp frequency, allowing larger feedthrough of highspeed signals, Se33.Open-Loop Acie with Miler Cputace s In summary, the closed-loop architecture suppress the input dependent ‘component ofthe hold pedestal by ineoporaing the sampling switch na fed back lop. This architecture, especially ina fully diferntal configuration. is attractive fr high-precision systems but usally suffers fom sow time response, 3.3. OPEN-LOOP ARCHITECTURE WITH MILLER CAPACITANCE ‘The conventional open-loop architecture described in Section 3.2 sues from fundamental imitation de tothe speed-precision trade-off ofthe sampling site given by (2.28). This tade-off ess rom the relationship between the on-resistance and channel charge of MOSFETs, indicating tat the hold pedestal can be reduced only if slower acquisition is acceptable. However, noting that these limitations exist imply bacatise the same capacitor is used forboth acquisition and hold, we ean avid them by using diferent capacitors in the sampling and hold modes. The open-loop architecture with Miller ‘capacitor is based on this concept and illustrate in Figure 348) (7), ‘Te circuit consists ofa sampling switch Mand an a-coupled Miler mpliiercamprising Ao, Ma. Cand C2. Inthe sampling mode, both My and ‘Mare on, As conigured as aunity-gain cireuit, providing viral ground at nodes X and ¥, and capacitors C; and Co track the put voltage (Figure 3.4b)) Inthe wansiton othe hold mode, fy and Meum olf simultaneously and CC, and Ap form feedback amplifier that introduces a capacitance of approximately AoC2 from node Z to ground (Figure 3.4()). Thus, in this architecture the hold capacitor is roughly AyC2/(C + C3) times the scquisiion capacitor thereby relaxiag the speed-prevsion rae off described in Seetion 23 by the same factor. Nove that since M always turns off with {virwal) ground potential at its source ané drain is charge injection causes negligible nonlinearity In this architecture, eventhough Ay must be a high-speed amplifier to provide alos” eutput impedance at high frequencies it nonetheless des not ee a wide dynamic range because its output voltae swing results rom only the charge injected by Ma, This simplifies ts design allowing optimization for speed In practice, the topology of Figure 34a) suffers from second-order sources of ero. Fist, ving their input-dependent switching point, Mi and Mz do not always tun of simukaneousl, thus eeating Miller ect either inthe sampling mode (hich slows down the aquisition and introduces Inputdependent delay) or after Ay has turned off and injeted its charge ‘onto Cand C> (in which ease the amplifier will not suppress the e709),Py Samples Hol Ahiecures Chap 3 Vout @ Vou Ge ° Fig.34 Opening atc wh Mile capac, Be eit (pjeqenaen ceca ine con mol (quae cet Second, when tring off, M and My iteraet through Cy and influence each others charge injection, making the charge injected by Mz somewbat inputependent. Nonetheless, Lins and Wooley [7] have shown thatthe nonlinearity introduced by this interaction is neligibe fr resolutions up 10 Sis. in summary, the open-loop architecture with Mille capacitance em- ploys two differen values of capacitance inthe aequisiion an hold moves to achieve high speed and small pedestal enor. This is accomplished using Miller ampli that mulipis the effective valu ofthe sampling capacitor by a large number when the SHA enters the hold mode, SoS Muto pa Archies s 3.4 MULTIPLEXED-INPUY ARCHITECTURES {class of SHA architectures employs input multiplexing to reconfigure the ‘iret when it goes fom the acquisition tothe hol made. In his section, we ‘describe two variants of this aehtectar, igure 354) shows the single-ended version of « multiptexed-input SH originally proposed by Ryan [8] and later mosified by Petshacher et AL [9], Icons of wansconductance amplifiers Guay and Gro abd transre- sistance ampliier R. Nominally, Gn} R = Gyo R= 1. Amplifiers Gyy and Guz ae comrolled (...mlipexed) by CK and CR. Duringsampling, Gn isenabled, Gyz is disabled, and Gy and R operate aba unity-gan ampli, allowing Vqq to Wack Vy. Note that the acquisition time constant is given Primarily bythe output sistance of Rand te value of Cy, Inthe tansion tothe hold mode, Gn is disabled, Gy is enabled, and Giga and Rare figured as « unity-ain amplifier, thecchy eaiing the sampled vale of 6708 Cr. Vino Gy Fig 3S Mukiplest ipa sche, a ingle-nda ci) ‘uct ect ie ol mse. {n order to illustrate the hold-mode operation, we consider a simplified version of the circuit, shown in Figure 350), where A= Gyo (1) and Ru topresents the open-loop output resistance ofthe amplifier. Assuming“ Sample aml Archies Chip 3 that Cy is charged toa voltage Vp atthe end of the acquisition mode and neglecting the input bas current of A, we noe: on sand @2) Ths Mew as Where # = RsCu/(1~ A) andthe origin of time isthe beginning ofthe hold ‘mode. Equation 3.3) shows that f 4 = I, then ¢ = 90: he the droop rate is zero and Vag will emain at Vo indefinitely. If A= 1+, then Ve decays witha time constant equal to RyyCir/¢; i; the droop time constant i 1/¢ times the acquisition time constant ‘Several aspects ofthis architecture make it atractive for implementa tion in bipolar technology. Fist, Ge and Gyn ean be realized as simple sifferential pairs that are multiplexed by means of a thie diferent pai, ‘lding a fst sample-o-hold transition and lw aperture jitter. Second, i Gm ad Gra are identical the charge injected onto the input node of by Gn atthe endat the sampling mode is absorbed by Gy, ths giving a smal ‘pedestal eor. Tir the Gy and & stages ean be implemented as 1ow-23, High-speed circuits because GR and G2 ned only be unity, This is particularly important ifthe proces provides no vertical pap transistors and Thence prohibits the use of high ain Sage, ‘While achieving igh speed, the architecture of Figure 3.5 presents Sv cel dificultes if employed for high-resolution appisatons. Since the ac- ‘Guistion time constant and the droop rate wade off according the deviation ‘of A from unity, Gg. Gigs and Roflen require correction techies 0 e- ‘duce that deviation (9} and approach the desired combination of acquisition speed and droop rate. Note that since this correction should remain effec ‘ve forthe entre input range, the nonlinearity (i, variations inthe gan) ‘ofthe cizcuit must be as low asthe gain error. These correction techniques, however, normally consume a substntial portion of the headroom, limiting the input voltage swing andthe dynamic range. For example, GR can be implemented as shown in Fighre 36 (9), where resistive degeneration in the emiters ad diode compensation in the collector of Qs and Qz are tilzed to achieve gan close ro unity (Chapter). Considering the voltage drop across emit and collector resistors and the headroom requied forthe clocked taileurentsouree, we noe that the input range han exceeds IV with Vex 3y, Seo 34 Muon pe Acie ” Fig.36- Linz ampere nope hop SIA. Another input-mulliplexed SHA architecture isshown in Figure3.7 [10] ‘This topology consist of transconditance amplifiers Gu and Ga mul plexed by CX and CK, tansresistance amplifier R, and sampling devices ‘5.81, Chand C. Inthe sampling mode, Gg is enabled, Gu is disabled, and Sand Sy aon, Thus the icuits configured as shown in Figure 380, ‘Gi R operates 4s & high-gain op amp, and the closed-loop gain is e9Ual 10 1 Ra/ Ry In ter words, Vag = (1+ R2/ Ri) Fes Samples Hold Acces Chap. 3 « a x) y or ig 38 ae cif dl op pen np siete) In the transtondo the hold mode, Gn i disabled, Gq is enabled, and 5} and tum of, yielding the hold configuration shown in Figure 3.80). Here, Vs ieclose 0 zero and Gyo and C; funtion a a unity-gain amir, hereby maintaining an output voltage egal that stored on ‘Theprincial feature ofthis architecture sits input independent pedestal or, This is because 5 and 5; donot experience lage voltage sings. they tum off wth Vy nd Vy closet the ground potential. Consequently, the nonlinearity intiuced by charge injection is quite small, Furthermore, i the sampling eapactor and witches are identical and the impedance in series ‘with Si (Ge the output impedance of Gui R) is smal, then the pedestal ‘Produced a the two inputs of Gu are equa. yielding zero pedestal atthe utp 13s instructive to compare the two multiplexed: input architectures de scribed in this section. While the topology shown in Figure 35 sufers from teade-ff between acquisition speed and droop rate—necessitating a Ga ® of precisely I—the topology of Figure 3.7 has no such trade-off, Moreover, since the later employs closed-loop amplifiers, i can achieve smaller non= Tinearty, but a the cost oF a potently slower time response, On the other ‘hand, both architectures have limited input range due to the stacked devices required for muliplexing. 535 RECYCLING ARCHITECTURE “The recyeing architecture is another topology in which the sampling switch experiences smal swings and hence introduce ply constant pedestal ero. ‘Shown in Figure 39 in simplified fom, this arcitetare consist of two unity iain blfers fy and By, trarsconductance amplifier Gy, and sampling ‘Secu compaising $)-B, and C|-Cs [11]. Inthe sampling mode, 8-8 are ‘on, Sis olf, ar the circuit is configured as shown in Figure 3.10). Tn this mode, Gy operates a a unity-gain amplifier. providing vial ground ar nodes X and Y. and capacitors Cy and C2 track te input voltage. Un the transition tothe hold mode, fst Sums of, at which instante input voltage is sampled on C (and C2), and subsequently SiS tum off and Stam on [Now the cteut is configured as shown in Figure 3.1046), where C2, Br, Bi and C) form uniy-zain feedback loop around Gre, thus providing an ouput ‘voltage approximately equal tothe voltage stored nC ts instructive to study’ the sourees of charge injetion inthis archi- tecture. Since Sy turns off with virual ground at X and ¥. it intrdces a ‘pedestal eror independent of the input signal, The resulting ost s partially balanced by the pedestal due tothe charge injected by S; onto C). Switch Ss. onthe other and, experiences swings equal tothe input and fjecs an Input-dependent charge onto nodes X, and Y when it urs off. Since By provides slow impedance at X1the charge injected onto this node gives 90 foe. However, the charge injected onto Vy chingesthe voltage stored on Nonetheless, the negative feedback loop suppresses the effet ofthis change «at the ouput. Thi occurs because the pedestal across C3 propagates through Bs, By, and Cand appears atthe inverting put of Gy thereby causing the ‘output of Gy to change inthe opposite direction, As result, the change in Vari equal to the pedestal voltage across C2 divided by the valtage gain of Give Ga Rays WHERE Rae the Output resistance of Gy« ample Hols Archieces Chap. 3 s 5% Ye ce, fon x % e eo cs o o ig 310 Euan ius of eying ice) Samping ode ‘i summary, the recycling architecture achieves small pedestal error, high ner and relatively high speed. 3.6 SWITCHED-CAPNCITOR ARCHITECTURE Evolved for use in AID converts he swiched-capacitor architecture em ploys MOS switches extensively. Stawn in Figure 3.11(a in single-ended Sec.36 Suits Caper Achiete « form this architecture consist of input sampling capacitor Cy. tanscondue- tance amplifier Gy, and switches SS [12]. The cireit operates as follows, In the acquisition mode, 5) and S) are on. Sis off, nd Gry functions as 2 unity-gan amplifier, creating vital ground at node X (Figure 3.110) ‘Thus, the voltage arose Cy tacks the input voltage. In the transition othe hold mode, st 5; tens of, thereby sampling the instantaneous input volt ‘age on Cin ad subsequently $) tums off and Sy tens on. This results in the hold-mode configuration depicted in Figure 3.11(c), where Cy and Gy sustain an cut voltage equal 0 the sampled input come) o © Fig AA Sich cqactor HA.) Bac ea (axa Inthe seston md) gaat eu ne Bl ma ‘Since inthis topology 5: tums off fist, the (input-dependent) charge injeted by 8, onto Cy doesnot appear inthe ld output voltage. Moreover, as Ss connected viral ground its chanael charge does not depend on ‘he input signal, In a diferent circuit, this charge would simply cause a common-mode oft, "The simplicity of this architocrre has made it quite popular in applica tions such as pipelined A/D converters, uere a large numer of SHAS are required [12] Since the dominant poe of the crcuit is usually athe output, ‘sn nrease nthe load capacitance doesnot degrade ie phase min but may ‘overeompensate the amplifier, Furthermore, a single-stage transconductance ‘mplifierean be wsed to achieve lnearities up to 13 bts [13]a Samples Hol bestees Cp. 3 In the architecture of Figure 3.118, te input suite 5) experiences large voltage swings, nioicng an inpat-dependent delay inthe acquisition ‘mode and hence harmoni distortion inthe sampled signal. Furteene, 28 ‘he linearity and precision of the SHA strongly depend on the open-loop gain (the product oftrnscondictance and output resistance) of Gy the peor ‘mance degrades if he circuit drives resistive loads, thereby limiting the use ofthe architecture to.on-chip applications 3.7 CURRENTMODE ARCHITECTURE CCarent-mode signal processing has been proposed as an aleratve 10 the ‘more conventional votage-made technique. Current-mode data conversion systems require curen-npat,curent-outPut sampling circuits. However. «even inthis case the signal is stored as voltage raber than a curent because ‘capacitors ae far easier to fabricate than are inductors. "Thus, in these a ‘chitectres, fist the input current mast be converted 0 volage so that can he stored, and then the stored voltage mist subsequently be converted to an ‘ouput curtent "The closed-loop architecture described in Section 3.2 canbe easily mod ied to operate in the curent mode, as sown in Figure 3.12. A variant of this architecture has heen used in a cureni-mode A/D converter 4]. In this ‘cit the inverting input of Gig i grounded, th input current is summed withthe ouput current of Gy at node X. the signal is stored on Ci and the output current is produced by Gina. The closed-loop architecture isa natural choice fr curreat-meode signals because, inthe sequisiton mode, ‘vides a vintal-ground summing node (X) as well as an iteral current to-volage convener (consisting of Ap and Cy). Note that Gua i ouside the global feedback loop its distortion is directly added f0 the stored signal. Fg AID Care me HA dered fm coment op ah The architecture of Figure 3,12 i topologically identical with the con- ventional elosed-ooparchitectre and hence exhibits the same time response for both curent-made inputs and voltage-mode inputs. Consequent, the curent-nodearchiteetre faces the Sune stability issues a the vollage-mode chinese REFERENCES [1] K.R Stafford eral, “A Complete Monolithic Sample/Hold Amplifier” IEEE 1. Solid-State Circus, vol. SC9, pp. 381-387, Dec 1975 [2] MJ. Chambers and LF, Linder,“ Precision Monolithic Sample-and- Hold for Video Analg-to-Digita Convers," ISSCC Dig. ech. Pup, Pp 163-169, Feb. 1991, [3] K- Poulton, JS. Kang, and JJ. Corcoran, “A 2 Gsls HBT Sample and Hold," Tech, Dig, 1988 GaAs IC Som. pp. 199-202. [4] P-Vorenkamp and J PM, Verdaasdonk, “ally Bipolar, 120-Msample/s loch Track-and-Hold Circuit.” EEE J. Solid-State Cir, vol, S27, 1p. 987.992, July 1992, [5] R,Jewet, J.J. Corcoran, and G. Steinbach, “A 12 b 20MSIsee Ripple ‘Through ADC ISSCC Dig. Tech. Pp. pp. 34-35, Feb, 1992. [6] M. Nayehi and B.A. Wooley. 10 Bit Video BiCMOS Track and Hokd Ampliier” ISSCC Dig, Teck Pap. pp. 68-69, Feb. 1989, (7} P..Limand B.A. Wooley,“ High Speed Sample-and-Hold Technique Using a Miller Hold Capacitance," IEEE J. Solid-State Circuits, vol SC: 26, pp. 643-651, April 199] [8] C.R. Ryan, “Applications of Four-Quadrant Mulipli State Cireits, vol, SC-5, pp 45-48, Feb, 1970, [9] P.Peschacher etal, “A 10:D75-MSPS Subranging A/D Converter with Integrated Sample snd Hol." IEEE J. Solid-State Circuits, vol. SC-25, pp. 1339-1346, Dee. 1990, [10] F, Moraes “A. High-Speed Curent-Multiplexed Sample-and-Hold Amplifier with Low Hid Ste." IEEE. Solid-State Circuits, vol SC-26, Pp. 1800-1808, Dee 1991 [11] P. Real and D. Mercer, “A 14 b Linear, 250 nsec Sanple-and- Hold Sobsystem with Se-Calibyation;" ISSCC Dig, Teoh Pap. 99. 164-165, Feb. 1991, IBEE Soli“ Samples ol Accor Chap 3 [12] S.-H. Lewis and P.R. Gray, “A Pipiined S-Msamplels9-bt Analog ‘o-Digital Convere:” IEEE J. Solid State Crews, SC22, pp.954-961, Dee. 1987 (3) YM. Lin, B. Kim, and PR. Gay, "A 13-b 25-MEy Self-Calibrated Pipelined A/D Converter in 3m CMOS)" IBEE J. Solid State Circuits vol, SC-26, pp. 628-636, Ape 1991 [14] D. Robertson, P. Real, and C. Mangelsdorf, “A Wideband 10-bit, 20, Msps Pipelined ADC Using Current-Mode Signals." ISSCC Dig. Teo Papers pp 160-161, Fek. 190, 4 Basic Principles of Digital-to-Analog Conversion Digital-t-analog conversion is an essential function in dat processing sys tems. Asmentioned in Chapter I D/A converters (DACS) interface the ital ‘output of signal processors with he analog world. Moreover, as explained in ‘Chapter 6, mulistepanalog-to-dgital converters employ interstage DACS to ‘reconstruct analog estimates ofthe input signal. Each of these applications imposes certain speed, precision, and power dissipation equirnents onthe DAC. mandating a good understanding of various D/A conversion techniques and thei ade Tnthis chapter we study the basic concepts and operations related to DYA conversion. Following & definition of performance metres we describe DYA conversion in terms of voltage, curent, and charge division or mulipiation Aandillustat the merits and imitations ofeach approach. Finally, we discuss the switching functions needed to generate an analog output coresponding to digital input 4.1 GENERAL CONSIDERATIONS A digia-to-analog coaverter produces an analog output A thats proportional tothe digital input D: Azan. a“ as Pips fig o-Antog Cooeson Chap where a isa proportonaiy factor, Since D isa dimensionless quantity sets both the dimension andthe full-scale range of A. For example fe isa current quantity, Jy thea the output can be expressed as A= be, 42) In some cass, its more practical o normalize D with espect to is full-seale value, 2, where m isthe resoltion, For example fa isa voltage quantity, Vier: > An Very 4s e y From (42) and (4.3), we ean se that in a DUA converter, each code atthe git input generates a certain multiple or fraction of a reference atthe ‘analog ouput In oer words, DVA conversion canbe Viewed as a reference ‘multiplication or division fnction, where therelerence may be once the three clectical quantities: voltage, curent, or charg The accuracy of his funtion ‘etermines the linearity ofthe DAC, while the sped at which each multiple or fraction of the reference can be selected and established a the ouput gives the conversion rate ofthe DAC. Figure 41 shows the inpuvoutput characteristic fof an ideal bit D/A conver. The analog levels generated atthe ouput Follow a staight line passed through the engin and the fllscale point. 000 001 010 O11 100 Tor 110 111 Digital Input Fie lpaouput chris of a el DIA come ‘We should mention that in some applications such as “sompanding” DACs, the desired relationship between D and is nonlineae [1], bu in tis ‘book we discuss only “linea or “uniform” DACS, ie. those that ideally ‘behave according 0 (4.2) oF (43). S42 Perfrmne Mei ° ‘The digital input o 4 DAC can assume any predefined format but must, eventually be of frm emily converible to analog. Shown in Figure 4.2 are twee formats offen used in DACS: binary, thermometer, and Lof-n codes. The later two are shown in column form to make thei visualization eas: Decimal | 0 1 2 9 Binary oo wn mete | 8 9 8 fF ‘Thermor oe of 44 88 8 t ad oo 1 0 ee) ig. 2 Binary herons and of cs the binary format, an m-bit number D1 D>» Dy represents decimal value of D214 Dy-22"-2 4 + Dy Inthe thermometer code, number is represented by a column of j consecutive ONEs tthe bottom and k consecutive ZEROs ontop such tht {J+ kis consiant. For example, a shown in Figure 4.2 the decimal number 3 can be represented as three ONE and one ZERO. This code an be viewed 884 thermometer thats “illed” upto the topmost ONE in the column, and hence the name. We wil also se the trm “eight o refer the numberof (ONES inthis code, Inthe of code each number is epresented a a single entry of ONE. in a column of ZEROs, with the position of that entry showing the actual vale. In Figure 42, for example the decimal number 3is depicted asa ONE. {in the third postion from the bottom, ‘As seen fom Figure 4.2, the thermometer and -of-n cade are much Jess compact than binary. Nonetheless, as discussed later, these codes are essential in DIA and AD converter design 4.2 PERFORMANCE METRICS In this section, we define a numberof tems usualy used to characterize BYA comverers. Fara more complete st, the reader is refered 10 the literature“ asi Pitino igi Ansog Comenion Cup. (2, 3] and manufacturers" data books. Figures 43 sad 44 illustrate some of these metres, « Differential nonlzearity (DNL) isthe maximum deviation in he out pul sep size fom the ideal valve of one least significant bit (LSB), nat Outpt onter ise. r Dita Fig.A3 Siac amc of DA comer Fe.44 Dynamic pametes of DIA comer, Sec43 Referens Micon nd Divison ” + tntegral nonlinearity (INL isthe masimum deviation ofthe input put characteristic from a straight lie passed through its end points “The difference between the ideal and actual characterises wil be called the INL profile + Offset isthe vertical intercept ofthe straight ine passed though the end points, ' Gain error isthe deviation ofthe slope ofthe line passed through the fend pis rom its eal yale usualy unity) ‘ Seuling time isthe time vequired for the output t experience Full scale tansition and sete within a specified error band around is final value, Glitch impulse area isthe maximum rea under any extraneous glitch that appears at the eurput after te input code changes, Thisparameter isalso called “ght energy” in the literature even ough it does not have an energy dimension * Latency is the total delay from the ine the digital input changes to the time the analog output has Setled within a specified errr band around its fina value. Latency may inclade multiples of the clock Petiod i the digital logic in the DAC is pipelined. ‘ Signal-t-(nise + distortion) ratio (SNDR) isthe rato ofthe signal power tothe ttl noise and harmonic distortion a he ouput when {he input is a digital sinusoid. Among these parameters, DNL and INL are usually determined bythe sccuracy of reference mullipication or division, settling time and delay are Functions of atput loading and switching speed, an etch impulse depends fn the DIA converter architecture and design [Note that some of these garamerers may’ be more important in some applications than in thers. For example, many stand-alone DACSequire low hich rea but may tolerate long latency. Onhe other hand, DACS uilized in ‘AID converters usually reguite short latency but ay havea claively large eliteh tea, 44.3 REFERENCE MULTIPLICATION AND DIVISION ‘The linearity and SNDR of DIA converters strongly depend on the acc racy of the eference multiplication or division employed to generate the ‘output levels. The thee electrical quantities, voltage, current, and charge,«an be multiplied or subdivided using resistor ladders, cument-steeringcir- cuits, and switched-capaitor circuits, respectively. In this section, we de serie each of these technique and th eros tha aris in typed implemen- 4.3.1 Voltage bi A given reference voltage Vay cam be divided into N equal segments using alader composed of W identical resistors Rp = Ry =o" = Ry (Nis ‘ypically a power of 2) (Figure 4.5). An m-bit DAC requires a ladder with 2" resistors, manifesting the exponential growth of the numberof resistors a a function of resolution Yer my Fs : Aya Fg === Fy % R, % a ig. age vin wing reir aie ‘An important aspect of resistor ladders i the diferential and integral nonlinearity they induce When used in DYA converters, These eros est From mismatches in he resistors comprising the ladder In order to undeestand bow resistor mismatch affects the DNL. and INL ‘of a resistor ladder DAC, we fist considera simple ease where the ladder ‘exhibits incar gradient, i, a linear variation in doping or wih from one fend othe other: This sitvation is shown in Figure 4.6. The voltage at the jth {ap of this ladder is 43 Reeee Mapleton a re s Yer ewer % noaon % ean % n AS Lr patron Surkan Wee Ver an Desk am w=» nr EY ag - Oe Vi as) Net aR ‘The INL ple is he by he difeence beeen.) ante ea tp vag. “1 ye YD on Lie apn 8 aaya fs Pips of Dipisen-AmlogComenion Chup. Assuming R > (NV ~ 1)O./2, we noe that [WL reaches @ maximum of NViee(R/SR) at j = 1/2. or the linear grant depicted in Figure 4.6, the DNL is obtained by fing the deviation of V1 V fom the teal valve of 1 LSB (=Vian/ 9) Veer DNL = Vet 4s) hich can be simplified to AR Vue Dey = j- 95) SE a9) if we assume R > (N ~ 1) AR/2. For lmge N, the magnitude ofthis eror reachesa maximum of approximately Vagr(O R/2R) at j Nol ‘Not that ifthe maximum INL and DNL ound above are toemain below 1 LSB, then the assumptions made in arriving a (8.7) and (4.9) are justified, tis imeresting to note that the nonlinearities deserted above ae caused by perfectly linear resistors, This ofcourse does nt contradict any las of linear systems because the switching operations in D/A converters make hem inherently nonlinear systems. ‘While the ease of linear gradients is simple and intuitive, i reality resistors also exhibit random mismatch. This type of mismatch originates Primarily fom uncertainties in geometry definition daring processing, a well, asrandom variations in contact resistance. Consider two resistors laid outwith ‘dential geometry and dimensions Inthe ideal ease, the value of each resistor can be expressed as sae, a where pis the resistivity, L, W, and are the length, width, and thickness ‘ofthe esistors respectively, and Represents the additonal resistance due 19 each contact. In reality, these resistors suffer fom several mismatch com ponents: resistivity mismatch, Ap, width, length and thickness mismatch, ‘AW. AL. and Av. spectively. an conact resistance mismatch, Ac. Ina typical process, AW and A result fom limited edge definition capability lithography and etching or deposition ofthe resistor material AV arises from _raientsaross the die, and 4 is eaused by random variations in the finite resistance at the interface ofthe fsisto and the interconnect (usually meta) “Taking the total diferent of (4.10), we ean express the overall mis- match between the (Wo resistors 8 Lap pAb pLaW _pLar ara Eee, 28 2ARe. (4.10 wr * wr we * iy This value can be normalize tothe mean valu ofthe resistors, R, to yet the relaive mismatch. Since in (410) 2Rc is usally a mal fraction oF, See Reece Maipcatin and isn s th fit four terms 4.1) canbe simplified by substiting 9/1 fo AR 89 ab AW ar , ake Rpt EW rR Since cont resistance dereses athe eestor wid increases, we cam write Re-=r/W, where a proportionality facto, This, BRe ~ Ar/ W. suggesting tat 12) ean be writen as AR _ Ap, AL AW ar sar eae ae Ae at ine 43» Ina ypical process, panda give, leaving LW, and R asthe only variables under the designer's conto. To minimize the overall mismatch, each of these parineters mst be maximized OF course, larger dimensions tea to higher parasitic apacitance Between the resistor and the subst, a wellas larger chip area, Some props of commonly availble monolithic resistors are given in “To analyze the nonlinearity resulting from random resistor mismatch ve must (1) assume @ probability density funtion (PDF) forthe value of ach resistor, (2) calculate the resulting PDF forthe tp voltages along the ladder, and (3) examine the mean standard deviation of these vollages in terms of those ofthe resistors. Since random mismatch aries from a large number of random variables (eesponding wo many uncorrlatedevents uring fabrication) itis plausible o assume a Gaussian PDF forthe resistor ‘values. Using such an analysis, Kuboki etal. [S] hae shown that the ap voltages of a resistor Laer follow a nearly Gaussian distribution, wih 4 ‘eae 0 jVig/ Wan standard deviation eal o any puna (Tad, 8k hr ay Tis reach maximum of Lar Wha = EV Vin R oy at j = 9/2. We souldemphasie ta this vale is standard deviation and hecea ikelnond measre rater than adsterminstic number nae words itimplis atom the average, 685 of N-segment resistor adders exhibit an ‘ores than or equa to (Vgey/VAN)AR/R) at ther midpoint Figure 47 ‘depicts an INL. profile obtained by choosing cach esitor ofa 12¥-segment ladir fom a Gaussian dsttation with R= 100 and AR = 3 2. We bots that inthis proflethe mama err does na eer at he pin a is actualy rete than that predicted by 13).= Hse Pris of Digan AniogComeriny Cag 10 os 00 me (U8) os 2 2049-60 8) 100 120 140 Ladder Tap Number He? NLmalstssrcompie seeds Despite the counterexample of Figure 4.7, equation (4. (5) dees indicate rend: 0 long a6-2.2/ remains constant the maximum enor decreases if ‘increases. Thus, ladders wih alarge numb of Segments are more likely to achieve a small (absolute) nonlinearity than ae ladders with a small number ‘of segments, Inuitvely, this is because random errors inthe value of resistors tend to average out when many segments are connected in series "Walton to random mismatch, ladders made of difsed resistors ex hibitawistnet nonlinear eration. The chickness ofthe depletion layer under those resistors volage-dependent and Yates from one ed ofthe ladder (0 ‘he othe, thereby introducing a variation in the value ofthe esis segments ‘The suing nonlinearity can be caleulated by expressing the thickness of| the resists asa square rt Tunetion ofthe local voltage along the ladder Note tha asthe diffused resistor doping increases, this nolinerity decreases, ‘whereas the depletion layer eapacitance-—which appear al along te ladder to the substie—incease, This vade-off makes diffsed-resistr lade less attractive than pol)-resstor ladders in applications where the ladder ex: Periences transient and mos ecover quickly, ‘An important aspect of resistor ladder design isthe Thevein resistance seen at each tp along the ladder. This resistance determines how fast ca ‘active loads charge or discharge to each tap's inal voltage. coneribucing (0 the setling time ofthe BAC. For an N-segment ladder, the Theveni ress tanee reaches a maximum of 4 R/4 a the midpity, This resistance grows exponentially with the number of is but canbe reduced atthe cost of higher power dissipation, Several variants of the resistor ladder sbowa in Figure 45 have been used for D/A conversion. We wil desribetheve in Chapter 5, 43.2 Current Division A reference current fay can be divided into W equal currents using N ‘identical ansistors connected as shown in Figure-48(a) (The same principle applies to both bipolar and MOS devices) These cumeots cube combined 50. © provide binary weighing, ss depicted in Figure 4 8(b) for &3.it ‘example. this simple implementation, an m-bit DAC requires 2" — 1 transistor, resulting ina lage numberof devices form = 7 noth j Ww Incr f@ a 21 ty er e480) Union cur dvs Ny cnet son Wie conceptually simple, the implementation of Figure 4.8) has two. eawsacks: the stack of current viding transistors ontop of fe iit theBasi PiniplesofDipiatte Ansog Comenion Chap & ‘output voltage range, and gy must be Nimes cach ofthe output currents ise Fe equites avery lrg device itself “These problems ean be solved by curent replication (eater than dive son) as shown in Figure 491), where V current mirors generate N output ceurreats equal 0 Ir- In practice, to improve matching aod Hiner, d= enero resistors are placed in sever with the emir, yielding he clreut shown in gure 5b). This wll be discussed ltr, a AAs Figures 4.8) and (b) may suggest, current-steeringarays can be implemented in two diferent ways, using esl oF binary-weighted curent Sources. Figure 4.10 depicts these two cases in more general form, In the circuit of Figure 4.10(), ll eurent sources are equal and controll by thermometer code so that wien the digital input increases by 1 LSB, one ‘aiionaleuzrne source is Switched t the output. Inthe circuit of Figure 4.1005). the curteat sources are binary-weighted and controlled bya binary ‘ode s that each current source contributes to the ouput current twice that ofthe next less significant bit. The configurations of Figures 4.10) and (b) ane called “segmented” and “binary” arays, respectively "Animporant feature of segmented arays is their guaranteed monotonic iy: since irements atthe digital input simply cause an ative increment Se.43— Refeene Muipieson ad Dison a ‘mene Cot Ps Bo a boar cota ‘9 M660 (ener eg at the analog output, the sansfer characterise of such arrays sa monotonic une ofthe input, even if the maximum INL exceeds 1 LSB. In binary mays, on the other hand, when the MSB current source [ef in Figure 4.10(0) tums om anda the curent sources corresponding to lower bits ura ‘othe ourput may change by nore than LSB, As rest bigh-resoltion applications such as stain gauge sensors, where the nonlinearity ofthe cane cer tse large ad hence the converte linearis ot erties, segmented nays are more altactne Because their resotion (iffrentil linearity) is ‘elaively independent oftheir integral inert ‘The overall output curent ofa current steering array ean he converted ‘0 voliage using resisor ora transimpedance amplifier, shown in Figure