Digital Design

CS302
Ref: Digital Design. M. Morris Mano , and Michael D. Ciletti.
Pearson, FIFTH EDITION, 2013
Combinational
Logic
CHAPTER 4 (PART1)
4.1 INTRODUCTION
Combinational circuit consists of logic gates whose outputs at any time
are determined from only the present combination of inputs

Sequential circuits employ storage elements in addition to logic gates

Their outputs are function of the inputs and the state of storage
elements.

Chapter 4- 3
Chapter 4- 4
SR latch

Chapter 4- 5
4.2 Combinational Circuits
A combinational logic circuit has:
◦ A set of m Boolean inputs,
◦ m inputs → 2m output
A block diagram:

Combinatori
al Circui
t

m Boolean n Boolean
Inputs Outputs
Chapter 4- 6
4.3 Analysis Procedure
Analysis : determine the function that the circuit
implements
To obtain the outputs that are a function of inputs:
1. Label all gate outputs that are a function of input variables .
Determine the Boolean functions for each gate output.
2. Label the gates that are a function of input variables and
previously labeled gates. Find the Boolean functions for these
gates.
3. Repeat step 2 until the outputs of the circuit are obtained.
4. By repeated substitution of previously defined functions,
obtain the output Boolean functions in terms of input variables.

Chapter 4- 7
F2
1. Find F1, F2, T2,T3,..
2. Substitute to find F1,F2 in
terms of inputs

Chapter 4-
8
F2=AB+AC+BC
T1=A+B+C
T2=ABC
T3= F2ʹT1
F1=T3+T2
F1 = T3+T2 = F2ʹT1 + ABC
= (AB+AC+BC)' (A+B+C)+ ABC
= (A'+B')(A'+C')(B'+C')(A + B + C )+ABC
= (A'+B'C') (AB'+AC'+BC'+B'C)+ ABC
= Aʹ BCʹ+AʹBʹC+ABʹCʹ+ABC

Chapter 4- 9
Chapter 4-
10
 4.4 Design Procedure
The specification of the design objective →
Boolean functions + logic diagram .
The procedure involves the following steps:
1. Determine the required number of inputs and outputs and
assign a symbol to each.
2. Derive a truth table or initial Boolean equations
3. Obtain the simplified Boolean functions for each output
4. Draw the logic diagram and verify the correctness of the
design

Chapter 4-
11
Code Conversion Example
◦ Code converter: from BCD to Excess-3
◦ Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
◦ BCD code words for digits 0 through 9: 4-bit patterns
0000 to 1001, respectively
◦ Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to each
BCD code word

Chapter 4- 12
 Formulation
Conversion of 4-bit codes can be most easily
formulated by a truth table
◦Variables
- BCD: A, B, C, D
◦Variables
- Excess-3:W, X, Y, Z
◦Don’t Cares
- BCD 1010 to 1111

Chapter 4- 13
Chapter 4- 14
Chapter 4- 15
Formulation
The expressions may be manipulated as follows
z = D'
y = CD + C'D' = CD + (C + D )'
x = B' C + B'D + BC'D' = B' (C + D ) + BC' D'
= B' (C + D ) + B (C + D )'
w = A + BC + BD = A + B (C + D )
Not counting input inverters, this implementation requires
four AND gates, four OR gates, and one inverter, .

Chapter 4-
16
Chapter 4- 17
 4.5 BINARY
ADDER-SUBTRACTOR
Adding two 1-bit values
results in the following
◦ 0+0=0, 0+1=1, 1+0=1
◦ (a sum with 1 bit)
and
◦ 1+1=10 (a sum with 2 bits,
including a higher significant bit
called a carry)

The Half Adder

◦ requires two input variables: x, y
◦ has two output variables:
C (carry), S (sum)

Chapter 4- 18
Half-Adder
The Boolean expressions are:
◦ S = xy’ + x’y
◦ C = xy
These can be implemented using
◦ AND and OR gates in sum-of-products form

X S
Y Half Adder C

Chapter 4-
19
Half-Adder
The Boolean expressions are:
◦ S = xy’ + x’y = x ⊕ y
◦ C = xy
These can be implemented using AND and XOR gates

Chapter 4-
20
Full-Adder
Full Adder: Additing n-bit binary numbers

X S
Y
Full
Z
Adder C

Exercise
Simplify S and C using K-map

Chapter 4- 21
S=x'y'z+x'yz'+xy'z'+xyz
C = x y+ x z+ y z
= x y + (x + y) z

Chapter 4- 22
Chapter 4-
23
Chapter 4- 24
Implementing the Adder
◦ Co = xy + xz + yz
◦ S = x’y’z + x’yz’ + xy’z’+xyz
= x’yz’ + xy’z’+ x’y’z + xyz
=(xy’+x’y)z’+((x+y’)(x’+y))z
=(x ⊕ y)z’+(x’y+xy’)’z
= (x ⊕ y)z’+(x ⊕ y)’z
=x⊕y⊕ z

Chapter 4- 25 4-
Chapter
S= x ⊕ y ⊕ z
C = xy + xy’z + x’yz
= z(xy’+x’y) + xy =z(x ⊕ y )+xy

Chapter 4- 26
Chapter 4- 27
Binary Adder
Consider the two binary numbers A = 1011 and B = 0011.
A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers.
It can be constructed with full adders connected in cascade, with the
output carry from each full adder connected to the input carry of the
next full adder in the chain

Chapter 4- 28
4-bit Parallel Adder

Chapter 4-
29
n-bit Parallel Adder

Chapter 4-
30
Chapter 4- 31
Carry Propagation
The propagation delay time in an adder is the time it takes
the carry to propagate through the full adders
• The signals from the input carry Ci to the output carry Ci+1, propagates
through an AND gate and an OR gate (two gate levels).
• If there are four full adders in the adder, the output carry C4 would have 2 x 4
= 8 gate levels From Co to C4.

Chapter 4- 32
Chapter 4- 33
Carry Lookahead Logic
Idea: each carry can be expressed in terms of Ai , Bi and C0
Carry Generate Gi = Ai Bi , must generate carry when A = B = 1
Sum and Carry can be re-expressed in terms of
generate/propagate:
Carry Propagate Pi = Ai ⊕ Bi
Pi is called Carry Propagate because it determines whether a carry into
stage i will propagate into stage i + 1
Si = Ai ⊕ B i ⊕ Ci = P i ⊕ Ci

Ci+1 = Ai Bi + Ci (Ai ⊕ Bi)

= Gi + Ci Pi (Ci Pi = Ci if Pi =1)
Chapter 4- 34
Carry Lookahead Logic
Ci+1 = Pi Ci + Gi , Pi=Ai ⊕ Bi and Gi= Ai Bi
C1 = P 0 C 0 + G 0
C2 = P 1 C 1 + G 1 = P 1 P 0 C 0 + P 1 G 0 + G 1
C3 = P 2 C2 + G 2 = P 2 P 1 P 0 C0 + P 2 P 1 G 0 + P 2 G 1 + G 2
C4 = P 3 P 2 P 1 P 0 C0 + P 3 P 2 P 1 G 0 + P 3 P 2 G 1 + P 3 G 2 + G 3

Each of the carry equations can be implemented in a

two-level logic network

Chapter 4- 35
Carry Lookahead Implementation
C0
P0
P1
C0
P0 C1 G0
C2
P1
G0

G1

C 1 = P0 C 0 + G 0 C 2 = P1 P0 C 0 + P 1 G0 + G 1

Chapter 4- 36
 Carry Lookahead Implementation
C0
P0
C0 P1
P0 P2
P1 P3
P2
G0
G0 P1
P1 P2
P2 P3
G1 C3 G1
P2 P2
P3
C4
G2 G2
P3

G3

C 3 = P2 P1 P0 C 0 + P 2 P1 G0 + P 2 G1 + G 2
C 4 = P 3 P2 P1 P0 C 0 + P 3 P2 P1 G0 + P 3 P2 G1 + P 3 G2 + G 3

Chapter 4- 37
Carry lookahead generator

Chapter 4- 38
4-bit adder with a carry
lookahead
Each sum output requires
two XOR gates
S i = A i ⊕ B i ⊕ C i = Pi ⊕ C i

This gain in speed of

operation is achieved
at the expense of
additional complexity
(hardware).

Chapter 4- 39
Binary Subtractor
The subtraction of unsigned binary numbers A-B can be done by means
of taking the 2's complement of B.

The 2's complement : take the 1's complement and add 1 to the least
significant pair of bits.

The 1's complement can be implemented with inverters.

Chapter 4- 40
Decimal Binary 1st 2nd
number number complement complement
0 0000 1111 1-0000
1 0001 1110 0-1111
2 0010 1101 0-1110
3 0011 1100 0-1101
4 0100 1011 0-1100
5 0101 1010 0-1101
6 0110 1001 0-0010
7 0111 1000 0-1001
8 1000 0111 0-1000
9 1001 0110 0-0111
10 1010 0101 0-0110
11 1011 0100 0-0101
12 1100 0011 0-0100
13 1101 0010 0-0101
14 1110 0001 0-0010
15 1111 0000 0-0001

Chapter 4- 41
 Subtraction by 1st Complement
1 1 1

74 1 0 0 1 0 1 0 74 1 0 0 1 0 1 0
- 52 - 0 1 1 0 1 0 0 - 52 + 1 0 0 1 0 1 1
1 0 0 1 0 1 0 1
22 0 0 1 0 1 1 0
+ 1
22 0 0 1 0 1 1 0
52 0 1 1 0 1 0 0
1st Comp 1 0 0 1 0 1 1

Chapter 4- 42
 Subtraction by 2nd Complement

1 1
74 1 0 0 1 0 1 0 74 1 0 0 1 0 1 0
- 52 - 0 1 1 0 1 0 0 - 52 + 1 0 0 1 1 0 0
22 1 0 0 1 0 1 1 0
22 0 0 1 0 1 1 0
ignored

52 0 1 1 0 1 0 0
1st Comp 1 0 0 1 0 1 1
+ 1
2nd Comp 1 0 0 1 1 0 0

Chapter 4- 43
Chapter 4- 44
M=0 ⇒ Adder
M=1⇒ Subtractor with 2nd Complement

Chapter 4- 45
 Four-bit adder–subtractor
The mode input M controls the operation. When M = 0, the circuit is
an adder, and when M = 1, the circuit becomes a subtractor. Each
exclusive-OR gate receives input M and one of the inputs of B.
❑When M = 0 , we have B ⊕ 0 = B. The full adders receive the value of B
, the input carry is 0, and the circuit performs A plus B .
❑When M = 1, we have B ⊕ 1 = B’ and C0= 1. The B inputs are all
complemented and a 1 is added through the input carry. The circuit
performs the operation A plus the 2’s complement of B .
❑(The exclusive-OR with output V is for detecting an overflow.)

Chapter 4- 46
Chapter 4- 47
Chapter 4- 48
Chapter 4- 49
Quiz
Find the binary output of the addition and subtraction of 25
and 13 using 2nd complement.
25 1 1 0 0 1 25 1 1 0 0 1
+13 + 0 1 1 0 1 -13 - 0 1 1 0 1

Chapter 4- 50
4.1 , 4.2, 4.4, 4.5, 4.6 a, 4.7a, 4.9,4.10
4.11,4.12,4.12(a),4.15, 4.16 (first part)
4.21, 4.23
4.25 → 4.28,4.31, 4.32
Ngw:1 , 4.2, 4.4, 4.5, 4.6 a, 4.7a, 4.9,4.10
4.11,4.12,4.12(a),4.15, 4.16 (first part)
4.21, 4.23

Chapter 4-
51