1.What is computer architecture?

b) set of principles and methods that specify the functioning, organisation, and
implementation of computer systems
2. What is computer organization?
a) structure and behaviour of a computer system as observed by the user
3. Which of the following is a type of computer architecture?
d) All of the mentioned (Microarchitecture, Harvard Architecture, Von-Neumann
Architecture)
4. Which of the following is a type of architecture used in the computers nowadays?
c) Von-Neumann Architecture
5. Which of the following is the subcategories of computer architecture?
d) All of the mentioned (Microarchitecture, Instruction set architecture, Systems design)
6. Which of the architecture is power efficient?
a) RISC
7. What does CSA stands for?
b) Computer Speed Addition
8. If an exception is raised and the succeeding instructions are executed completely, then
the processor is said to have ______
c) Imprecise exceptions
9. To reduce the memory access time we generally make use of ______
c) Cache’s
10. The IA-32 system follows which of the following design?
a) CISC
11. Which of the following architecture is suitable for a wide range of data types?
a) IA-32
12. In IA-32 architecture along with the general flags, which of the following conditional flags
are provided?
d) All of the mentioned (TF, IOPL, IF)
13. The VLIW architecture follows _____ approach to achieve parallelism.
b) MIMD
14. What does VLIW stands for?
d) Very Long Instruction Word
15. In CISC architecture most of the complex instructions are stored in _____
c) Transistors
16. Both the CISC and RISC architectures have been developed to reduce the ______
b) Semantic gap
17. ________ are the different type/s of generating control signals.
d) Both Micro-programmed and Hardwired
18. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the
value of S is (Where S is term of the Basic performance equation).
b) ~1
19. The small extremely fast, RAM’s all called as ________
d) Cache
20. For a given FINITE number of instructions to be executed, which architecture of the
processor provides for a faster execution?
b) Super-scalar
21. What is the full form of ISA?
c) International American Standard
22. Which of the following is the fullform of CISC?
d) Complex Instruction Set Computer
23. The reason for the cells to lose their state over time is ________
c) Usage of capacitors to store the charge
24. In order to read multiple bytes of a row at the same time, we make use of ______
d) Latch
25. The difference in the address and data connection between DRAM’s and SDRAM’s is
_______
b) The usage of a buffer in SDRAM’s
26. The chip can be disabled or cut off from an external connection using ______
d) Chip select
27. The controller multiplexes the addresses after getting the _____ signal.
d) Request
28. The data is transferred over the RAMBUS as _______
b) Swing voltages
29. The memory devices which are similar to EEPROM but differ in the cost effectiveness is
______
d) Flash memory
30. The flash memory modules designed to replace the functioning of a hard disk is ______
c) Flash drives
31. The drawback of building a large memory with DRAM is ______________
a) The Slow speed of operation
32. In a 4M-bit chip organisation has a total of 19 external connections, then it has _______
address if 8 data lines are there.
c) 9
33. What does ISO stands for?
c) International Standards Organisation
34. The bit used to signify that the cache location is updated is ________
d) Dirty bit
35. During a write operation if the required block is not present in the cache then ______
occurs.
a) Write miss
36. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are
used for ________
c) Tag
37. The bit used to indicate whether the block was recently used or not is _______
b) Dirty bit
38. The number successful accesses to memory stated as a fraction is called as _____
c) Hit rate
1. The ______ format is usually used to store data.
a) BCD
2. The 8-bit encoding format used to store data in a computer is ______
b) EBCDIC
3. A source program is usually in _______
c) High-level language
4. Which memory device is generally made of semiconductors?
a) RAM
5. The small extremely fast, RAM’s are called as _______
a) Cache
6. The ALU makes use of _______ to store the intermediate results.
a) Accumulators
7. The control unit controls other units by generating ___________
b) Timing signals
8. ______ are numbers and encoded characters, generally used as operands.
b) Data
9. The Input devices can send information to the processor.
a) When the SIN status flag is set
10. ______ bus structure is usually used to connect I/O devices.
a) Single bus
11. The I/O interface required to connect the I/O device to the bus consists of ______
c) Address decoder, registers and Control circuits
12. To reduce the memory access time we generally make use of ______
d) Cache’s
13. ______ is generally used to increase the apparent size of physical memory.
b) Virtual memory
14. MFC stands for ___________
b) Memory Function Complete
15. The time delay between two successive initiations of memory operation _______
c) Memory cycle time
1. The decoded instruction is stored in ______
a) IR
2. The instruction -> Add LOCA, R0 does _______
c) Adds the values of both LOCA and R0 and stores it in R0
3. Which registers can interact with the secondary storage?
a) MAR
4. During the execution of a program which gets initialized first?
c) PC
5. Which of the register/s of the processor is/are connected to Memory Bus?
b) MAR
6. ISP stands for _________
a) Instruction Set Processor
7. The internal components of the processor are connected by _______
b) Processor bus
8. ______ is used to choose between incrementing the PC or performing ALU operations.
b) Multiplexer
9. The registers, ALU and the interconnection between them are collectively called as
_____
d) data path
10. _______ is used to store data in registers.
a) D flip flop
1. The main virtue for using single Bus structure is ____________
c) Cost effective connectivity and ease of attaching peripheral devices
2. ______ are used to overcome the difference in data transfer speeds of various devices.
d) Buffer registers
3. To extend the connectivity of the processor bus we use ________
a) PCI bus
4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
c) ISA
5. ANSI stands for __________
a) American National Standards Institute
6. _____ register Connected to the Processor bus is a single-way transfer capable.
d) Z
7. In multiple Bus organisation, the registers are collectively placed and referred as ______
b) Register file
8. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
9. The ISA standard Buses are used to connect ___________
c) Harddisk and Processor
1. During the execution of the instructions, a copy of the instructions is placed in the ______
d) Cache
2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with
an average of 5 steps. For the execution of the same instruction which processor is faster?
a) A
3. A processor performing fetch or decoding of different instruction during the execution of
another instruction is called ______
b) Pipe-lining
4. For a given FINITE number of instructions to be executed, which architecture of the
processor provides for a faster execution?
c) Super-scalar
5. The clock rate of the processor can be improved by _________
d) All of the mentioned (Improving the IC technology of the logic circuits, Reducing the
amount of processing done in one step, By using the overclocking method)
6. An optimizing Compiler does _________
b) Takes advantage of the type of processor and reduces its process time
7. The ultimate goal of a compiler is to ________
a) Reduce the clock cycles for a programming task
8. SPEC stands for _______
c) System Performance Evaluation Corporation
9. As of 2000, the reference system to find the performance of a system is _____
a) Ultra SPARC 10
10. When Performing a looping operation, the instruction gets stored in the ______
b) Cache
11. The average number of steps taken to execute the set of instructions can be made to be
less than one by following _______
c) Super-scaling
12. If a processor clock is rated as 1250 million cycles per second, then its clock period is
________
d) 8 * 10 sec
-10

13. If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the
value of S is (Where S is a term of the Basic performance equation)?
c) ~1
14. CISC stands for _______
c) Complex Instruction Set Computer
15. As of 2000, the reference system to find the SPEC rating are built with _____
Processor.
b) Ultra SPARC -IIi 300MHZ
1. The instruction, Add #45,R1 does _______
b) Adds 45 to the value of R1 and stores it in R1
2. In the case of, Zero-address instruction method the operands are stored in _____
c) Push down stack
3. Add #45, when this instruction is executed the following happen/s _______
b) The value stored in memory location 45 is retrieved and one more operand is requested\
4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
5. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective
address is ______
d) EA = 5+[R1]
6. The addressing mode/s, which uses the PC instead of a general purpose register is
______
b) Relative
7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
d) 2, 3
8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
9. The effective address of the following instruction is MUL 5(R1,R2).
c) 5+[R1]+[R2]
10. _____ addressing mode is most suitable to change the normal sequence of execution of
instructions.
a) Relative
1. Which method/s of representation of numbers occupies a large amount of memory than
others?
a) Sign-magnitude
2. Which representation is most efficient to perform arithmetic operations on the numbers?
c) 2’S complement
3. Which method of representation has two representations for ‘0’?
a) Sign-magnitude
4. When we perform subtraction on -7 and 1 the answer in 2’s complement form is
_________
d) 1000
5. When we perform subtraction on -7 and -5 the answer in 2’s complement form is
b) 1110
6. When we subtract -3 from 2 , the answer in 2’s complement form is _________
c) 0101
7. The processor keeps track of the results of its operations using flags called ________
a) Conditional code flags
8. The register used to store the flags is called as _________
b) Status register
9. The Flag ‘V’ is set to 1 indicates that _____________
c) The operation has resulted in an overflow
10. In some pipelined systems, a different instruction is used to add to numbers which can
affect the flags upon execution. That instruction is _______
a) AddSetCC
11. The most efficient method followed by computers to multiply two unsigned numbers is
_______
b) Bit pair recording of multipliers
12. For the addition of large integers, most of the systems make use of ______
c) Carry look-ahead adders
13. In a normal n-bit adder, to find out if an overflow as occurred we make use of ________
d) Xor gate
14. In the implementation of a Multiplier circuit in the system we make use of _______
c) Shift register
15. When 1101 is used to divide 100010010 the remainder is ______
d) 1
1. The smallest entity of memory is called _______
a) Cell
2. The collection of the above mentioned entities where data is stored is called ______
a) Block
3. An 24 bit address generates an address space of ______ locations.
d) 16,777,216
4. If a system is 64 bit machine, then the length of each word will be _______
b) 8 bytes
5. The type of memory assignment used in Intel processors is _____
a) Little Endian
6. When using the Big Endian assignment to store a number, the sign bit of the number is
stored in _____
a) The higher order byte of the word
7. To get the physical address from the logical address generated by CPU we use
____________
b) MMU
8. _____ method is used to map logical addresses of variable length onto physical memory.
c) Segmentation
9. During the transfer of data between the processor and memory we use ______
d) Registers
10. Physical memory is divided into sets of finite size called as ______
a) Frames
1. Add #%01011101,R1 , when this instruction is executed then _________
a) The binary addition between the operands takes place
2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode
then we use _________ symbol before the operand.
c) $
3. When generating physical addresses from a logical address the offset is stored in
__________
b) Relocation register
4. The technique used to store programs larger than the memory is ____________
a) Overlays
5. The unit which acts as an intermediate agent between memory and backing store to
reduce process time is ___________
d) Cache
6. Does the Load instruction do the following operation/s?
b) Loads the contents of a location onto the accumulators
7. Complete the following analogy:- Registers are to RAM’s as Cache’s are to ___________
d) TLB
8. The BOOT sector files of the system are stored in ___________
b) ROM
9. The transfer of large chunks of data with the involvement of the processor is done by
_______
a) DMA controller
10. Which of the following techniques used to effectively utilize main memory?
c) Dynamic loading
1. RTN stands for ___________
a) Register Transfer Notation
2. The instruction, Add Loc,R1 in RTN is _______
d) R1<-[Loc]+[R1]
3. Can you perform an addition on three operands simultaneously in ALN using Add
instruction?
c) Not permitted
4. The instruction, Add R1,R2,R3 in RTN is _______
d) R3<-[R1]+[R2]
5. In a system, which has 32 registers the register id is __________ long.
c) 5 bits
6. The two phases of executing an instruction are __________
b) Instruction fetch and instruction execution
7. The Instruction fetch phase ends with _________
d) Decoding the data in MDR and placing it in IR
8. While using the iterative construct (Branching) in execution _____________
b) Branch
9. When using Branching, the usual sequencing of the PC is altered. A new instruction is
loaded which is called as ______
a) Branch target
10. The condition flag Z is set to 1 to indicate _______
c) The result is zero
1. __________ converts the programs written in assembly language into machine
c) Assembler
2. The instructions like MOV or ADD are called as ______
a) OP-Code
3. The alternate way of writing the instruction, ADD #5,R1 is ______
b) ADDI 5,R1;
4. Instructions which won’t appear in the object program are called as _____
d) Assembler Directives
5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does
________
b) Replaces every occurrence of Sum with 200
6. The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is to be stored
7. The directive used to perform initialization before the execution of the code is ______
c) Dataword
8. _____ directive is used to specify and assign the memory required for the block of code.
d) Reserve
9. _____ directive specifies the end of execution of a program.
b) Return
10. The last statement of the source program should be _______
d) End
11. When dealing with the branching code the assembler ___________
c) Finds the Branch offset and replaces the Branch target with it
12. The assembler stores all the names and their corresponding values in ______
b) Symbol Table
13. The assembler stores the object code in ______
d) Magnetic disk
14. The utility program used to bring the object code into memory for execution is ______
a) Loader
15. To overcome the problems of the assembler in dealing with branching code we use
_____
d) Two-pass assembler
1. The return address of the Sub-routine is pointed to by _______
b) PC
2. The location to return to, from the subroutine is stored in _______
d) Link registers
3. What is subroutine nesting?
c) Having one routine call the other
4. The order in which the return addresses are generated and used is _________
a) LIFO
5. In case of nested subroutines the return addresses are stored in __________
c) Processor stack
6. The appropriate return addresses are obtained with the help of ____ in case of nested
routines.
d) Stack-pointers
7. When parameters are being passed on to the subroutines they are stored in ________
d) All of the mentioned
8. The most efficient way of handling parameter passing is by using ______
a) General purpose registers
9. The most Flexible way of logging the return addresses of the subroutines is by using
_______
b) Stacks
10. The wrong statement/s regarding interrupts and subroutines among the following is/are
______
d) iii and iv
1. The private work space dedicated to a subroutine is called as ________
c) Stack frame
2. If the subroutine exceeds the private space allocated to it then the values are pushed
onto _________
a) Stack
3. ______ pointer is used to point to parameters passed or local parameters of the
subroutine.
b) Frame pointer
4. The reserved memory or private space of the subroutine gets deallocated when _______
c) When the routine’s return statement is executed
5. The private space gets allocated to each subroutine when _________
c) When the routine gets called
6. _____ the most suitable data structure used to store the return addresses in the case of
nested subroutines.
b) Stack
7. In the case of nested subroutines, the stack top is always _________
a) The saved contents of the called sub routine
8. The stack frame for each subroutine is present in ______
c) Processor Stack
9. The data structure suitable for scheduling processes is _______
c) Queue
10. The sub-routine service procedure is similar to that of the interrupt service routine in
________
d) Method of context switch & Process execution
1. In memory-mapped I/O ____________
a) The I/O devices and the memory share the same address space
2. The usual BUS structure used to connect the I/O devices is ___________
c) Single BUS structure
3. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.
b) True
4. The advantage of I/O mapped devices to memory mapped is ___________
c) The devices have to deal with fewer address lines
5. The system is notified of a read or write operation by ___________
d) Sending a special signal along the BUS
6. To overcome the lag in the operating speeds of the I/O device and the processor we use
___________
b) Status flags
7. The method of accessing the I/O devices by repeatedly checking the status flags is
___________
a) Program-controlled I/O
8. The method of synchronising the processor with the I/O device in which the device sends
a signal when it is ready is?
c) Interrupts
9. The method which offers higher speeds of I/O transfers is ___________
d) DMA
10. The process wherein the processor constantly checks the status flags is called as
___________
a) Polling
1. The interrupt-request line is a part of the ___________
b) Control line
2. The return address from the interrupt-service routine is stored on the ___________
c) Processor stack
3. The signal sent to the device from the processor to the device after receiving an interrupt
is ___________
a) Interrupt-acknowledge
4. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
d) i, ii
5. The time between the receiver of an interrupt and its service is ______
b) Interrupt latency
6. Interrupts form an important part of _____ systems.
c) Real-time processing
7. A single Interrupt line can be used to service n different devices
a) True
8. ______ type circuits are generally used for interrupt service lines.
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i, ii
9. The resistor which is attached to the service line is called _____
b) Pull-up resistor
10. An interrupt that can be temporarily ignored is ___________
c) Maskable interrupt
11. The 8085 microprocessor responds to the presence of an interrupt ___________
c) By checking the trap pin for ‘high’ status at the end of execution of each instruction
12. CPU as two modes privileged and non-privileged. In order to change the mode from
privileged to non-privileged.
b) A software interrupt is needed
13. Which interrupt is unmaskable?
c) TRAP
14. From amongst the following given scenarios determine the right one to justify interrupt
mode of data transfer.
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
d) iv
15. How can the processor ignore other interrupts when it is servicing one ___________
d) All of the mentioned
1. When dealing with multiple devices interrupts, which mechanism is easy to implement?
a) Polling method
2. The interrupt servicing mechanism in which the requesting device identifies itself to the
processor to be serviced is ___________
b) Vectored interrupts
3. In vectored interrupts, how does the device identify itself to the processor?
c) By sending the starting address of the service routine
4. The code sent by the device in vectored interrupt is _____ long.
d) 4-8 bits
5. The starting address sent by the device in vectored interrupt is called as __________
b) Interrupt vector
6. The processor indicates to the devices that it is ready to receive interrupts ________
c) By activating the interrupt acknowledge line
7. We describe a protocol of input device communication below:
i) Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value to
determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
d) Polling
8. Which one of the following is true with regard to a CPU having a single interrupt request
line and single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
a) iii
9. Which table handle stores the addresses of the interrupt handling sub-routines?
a) Interrupt-vector table
10. _________ method is used to establish priority by serially connecting all devices that
request an interrupt.
b) Daisy chain
11. In daisy chaining device 0 will pass the signal only if it has _______
b) No interrupt request
12. ______ interrupt method uses register whose bits are set separately by interrupt signal
for each device.
a) Parallel priority interrupt
13. ______________ register is used for the purpose of controlling the status of each
interrupt request in parallel priority interrupt.
d) Mask
14. The added output of the bits of the interrupt register and the mask register is set as an
input of ______________
b) Priority encoder
15. Interrupts initiated by an instruction is called as _______
b) External
1. If during the execution of an instruction an exception is raised then __________
b) The instruction is halted and the exception is handled
2. _____ is/are types of exceptions.
d) All of the mentioned
3. The program used to find out errors is called __________
a) Debugger
4. The two facilities provided by the debugger is __________
d) Both Trace and Break points
5. In trace mode of operation is ________
a) The program is interrupted after each detection
6. What is the operation in Breakpoint mode?
d) The program is halted only at specific points
7. What are the different modes of operation of a computer?
b) User and Supervisor mode
8. The instructions which can be run only supervisor mode are?
c) Privileged instructions
9. A privilege exception is raised __________
d) All of the mentioned
10. How is a privilege exception dealt with?
a) The program is halted and the system switches into supervisor mode and restarts the
program execution
1. The DMA differs from the interrupt mode by __________
d) None of the mentioned
2. The DMA transfers are performed by a control circuit called as __________
b) DMA controller
3. In DMA transfers, the required signals and addresses are given by the __________
c) DMA controllers
4. After the completion of the DMA transfer, the processor is notified by __________
b) Interrupt signal
5. The DMA controller has _______ registers.
c) 3
6. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
7. The controller is connected to the ____
b) System BUS
8. Can a single DMA controller perform operations on two different disks simultaneously?
a) True
9. The technique whereby the DMA controller steals the access cycles of the processor to
operate is called __________
c) Cycle stealing
10. The technique where the controller is given complete access to main memory is
__________
d) Burst mode
11. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
12. To overcome the conflict over the possession of the BUS we use ______
b) BUS arbitrators
13. The registers of the controller are ______
c) 32 bits
14. When the process requests for a DMA transfer?
d) process is temporarily suspended & Another process gets executed
15. The DMA transfer is initiated by _____
c) I/O devices
1. The primary function of the BUS is __________
a) To connect the various devices to the cpu
2. The classification of BUSes into synchronous and asynchronous is based on
__________
c) The Timing of data transfers
3. The device which starts data transfer is called __________
d) Initiator
4. The device which interacts with the initiator is __________
a) Slave
5. In synchronous BUS, the devices get the timing signals from __________
b) A common clock line
6. The delays caused in the switching of the timing signals is due to __________
c) Propagation delay
7. The time for which the data is to be on the BUS is affected by __________
d) Propagation delay of the circuit & Setup time of the device
8. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
a) True
9. Which is fed into the BUS first by the initiator?
d) Address, Commands or controls
10. _____________ signal is used as an acknowledgement signal by the slave in Multiple
cycle transfers.
b) Slave ready signal
1. The master indicates that the address is loaded onto the BUS, by activating _____ signal.
a) MSYN
2. The devices with variable speeds are usually connected using asynchronous BUS.
a) True
3. The MSYN signal is initiated __________
b) Soon after the decoding of the address
4. In IBM’s S360/370 systems _____ lines are used to select the I/O devices
a) SCAN in and out
5. The meter in and out lines are used for __________
a) Monitoring the usage of devices
6. MRDC stands for _______
b) Memory Ready Command
7. The BUS that allows I/O, memory and Processor to coexist is _______
c) Backplane BUS
8. The transmission on the asynchronous BUS is also called _____
d) Hand-Shake transmission
9. Asynchronous mode of transmission is suitable for systems with multiple peripheral
devices.
a) True
10. The asynchronous BUS mode of transmission allows for a faster mode of data transfer.
b) False
1. ______ serves as an intermediary between the device and the BUSes.
a) Interface circuits
2. The side of the interface circuits, that has the data path and the control signals to transfer
data between interface and device is _____
b) Port side
3. What is the interface circuit?
c) Helps in the decoding of the address on the address Bus
4. The conversion from parallel to serial data transmission and vice versa takes place inside
the interface circuits.
a) True
5. The parallel mode of communication is not suitable for long devices because of ______
a) Timing skew
6. The Interface circuits generate the appropriate timing signals required by the BUS control
scheme.
a) True
7. The status flags required for data transfer is present in _____
c) Interface circuit
8. User programmable terminals that combine VDT hardware with built-in microprocessor is
_____
d) Intelligent terminals
9. Which most popular input device is used today for interactive processing and for the one
line entry of data for batch processing?
a) Mouse
10. The use of spooler programs or _______ Hardware allows PC operators to do the
processing work at the same time a printing operation is in progress.
c) Buffer
1. The _____ circuit enables the generation of the ASCII code when the key is pressed.
c) Encoder
2. To overcome multiple signals being generated upon a single press of the button, we
make use of ______
b) Debouncing circuit
3. The best mode of connection between devices which need to send or receive large
amounts of data over a short distance is _____
c) Parallel port
4. The output of the encoder circuit is/are ______
b) ASCII code and the valid signal
5. The disadvantage of using a parallel mode of communication is ______
a) It is costly
6. In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel
port interface.
d) Status or data register
7. The Status flag circuit is implemented using _____
b) D flip flop
8. In the output interface of the parallel port, along with the valid signal ______ is also sent.
b) Idle signal
9. DDR stands for __________
a) Data Direction Register
10. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
1. The mode of transmission of data, where one bit is sent for each clock cycle is ____
d) Isochronous
2. The transformation between the Parallel and serial ports is done with the help of ______
c) Shift registers
3. The serial port is used to connect basically _____ and processor.
a) I/O devices
4. The double buffer is used for _________
a) Enabling retrieval of multiple bits of input
5. ______ to increase the flexibility of the serial ports.
b) The ports are made to allow different clock signals for input and output
6. UART stands for ________
c) Universal Asynchronous Receiver Transmitter
7. The key feature of UART is _________
d) Its enhancement of connecting low speed devices
8. The data transfer in UART is done in ______
a) Asynchronous start stop format
9. The standard used in serial ports to facilitate communication is _____
c) RS-232-C
10. In a serial port interface, the INTR line is connected to _____
a) Status register
1. The PCI follows a set of standards primarily used in _____ PC’s.
c) IBM
2. The ______ is the BUS used in Macintosh PC’s.
a) NuBUS
3. The key feature of the PCI BUS is _________
b) Plug and Play capability
4. PCI stands for _______
a) Peripheral Component Interconnect
5. The PCI BUS supports _____ address space/s.
d) All of the mentioned
6. ______ address space gives the PCI its plug and plays capability.
a) Configuration
7. _____ provides a separate physical connection to the memory.
c) PCI bridge
8. When transferring data over the PCI BUS, the master as to hold the address until the
completion of the transfer to the slave.
b) False
9. The master is also called as _____ in PCI terminology.
a) Initiator
10. Signals whose names end in ____ are asserted in the low voltage state.
b) #
1. A complete transfer operation over the BUS, involving the address and a burst of data is
called _____
a) Transaction
2. The device connected to the BUS are given addresses of ____ bit.
b) 64
3. The PCI BUS has _____ interrupt request lines.
c) 4
4. _____ signal is sent by the initiator to indicate the duration of the transaction.
a) FRAME#
5. ______ signal is used to enable commands.
d) c/BE#
6. IRDY# signal is used for _______
c) Saying that the initiator is ready
7. The signal used to indicate that the slave is ready is _____
b) TRDY#
8. DEVSEL# signal is used _________
c) By the device to indicate that it is ready for a transaction
9. The signal used to initiate device select ________
d) IDSEL#
10. The PCi BUS allows us to connect _______ I/O devices.
a) 21
1. The key features of the SCSI BUS are _________
b) The ability overlap data transfer requests
2. In a data transfer operation involving SCSI BUS, the control is with ______
d) Target Controller
3. In SCSI transfers the processor is not aware of the data being transferred.
a) True
4. What is DB(P) line?
b) That the data line is carrying the parity information
5. The BSY signal signifies _________
a) The BUs is busy
6. The SEL signal signifies _________
b) The device for BUS control is selected
7. ________ signal is asserted when the initiator wishes to send a message to the target.
d) ATN
8. The MSG signal is used _________
c) To tell that the information being sent is a message
9. _____ is used to reset all the device controls to their startup state.
b) RST
10. The SCSI BUS uses ______ arbitration.
a) Distributed
1. SCSI stands for ________
a) Small Computer System Interface
2. ANSI stands for _________
d) American National Standard Institute
3. A narrow SCSI BUS has _____ data lines.
b) 8
4. Single ended transmission means _________
c) That the signals have a common ground return
5. HVD stands for _________
a) High Voltage Differential
6. For better transfer rates on the SCSI BUS the length of the cable is limited to ______
d) 1.6m
7. The maximum number of devices that can be connected to SCSI BUS is ______
c) 16
8. The SCSI BUS is connected to the processor through _____
a) SCSI Controller
9. The mode of data transfer used by the controller is _____
b) DMA
10. The data is stored on the disk in the form of blocks called _____
c) Sectors
1. The transfer rate, when the USB is operating in low-speed of operation is _____
d) 1.5 Mb/s
2. The high speed mode of operation of the USB was introduced by _____
c) USB 2.0
3. The sampling process in speaker output is a ________ process.
c) Isochronous
4. The USB device follows _______ structure.
d) Tree
5. The I/O devices form the _____ of the tree structure.
a) Leaves
6. USB is a parallel mode of transmission of data and this enables for the fast speeds of
data transfers. b) False
7. In USB the devices can communicate with each other. b) False
8. The device can send a message to the host by taking part in _____ for the
communication path.
b) Polling
9. When the USB is connected to a system, its root hub is connected to the _______
c) Processor BUS
10. The devices connected to USB is assigned a ____ address.
d) 7 bit
11. The USB address space can be shared by the user’s memory space.
b) False
12. The initial address of a device just connected to the HUB is ________
b) 0000000
13. Locations in the device to or from which data transfers can take place is called
________
a) End points
14. A USB pipe is a ______ channel.
c) Full-Duplex
15. The type/s of packets sent by the USB is/are _______
d) Both Data and Control
1. The first field of any packet is _____
a) PID
2. The 4 bit PID’s are transmitted twice.
a) True
3. The last field in the packet is ______
d) CRC
4. The CRC bits are computed based on the values of the _____
d) Both ADDR and ENDP
5. The data packets can contain data upto ______
c) 1024 bytes
6. The most important objective of the USB is to provide ______
d) All of the mentioned
7. The transmission over the USB is divided into ____
a) Frames
8. The _____ signal is used to indicate the beginning of a new frame. b) SOF
9. The SOF is transmitted every ______
c) 1ms
10. The power specification of usb is _____
a) 5v
1. The duration between the read and the mfc signal is ______a) Access time
2. The minimum time delay between two successive memory read operations is ______
a) Cycle time
3. MFC is used to _________
c) Signal the processor the memory operation is complete
4. __________ is the bottleneck, when it comes computer performance.
b) Memory cycle time
5. The logical addresses generated by the cpu are mapped onto physical memory by
____________
c) MMU
6. VLSI stands for ___________a) Very Large Scale Integration
7. The cells in a row are connected to a common line called ______b) Word line
8. The cells in each column are connected to ______d) Sense/ Write line
9. The word line is driven by the _____b) Address decoder
10. A 16 X 8 Organisation of memory cells, can store upto _____d) 128 bits
11. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address
lines can be organized into _____
d) 1024 X 1
12. Circuits that can hold their state as long as power is applied is _______b) Static
memory
13. The number of external connections required in 16 X 8 memory organisation is _____a)
14
14. The advantage of CMOS SRAM over the transistor one’s is _________
d) Low power consumption
15. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______
address if 8 data lines are there.
c) 9
1. The Reason for the disregarding of the SRAM’s is ________
c) High Cost
2. The disadvantage of DRAM over SRAM is/are _______c) The cells are not static
3. The reason for the cells to lose their state over time is ________
b) Usage of capacitors to store the charge
4. The capacitors lose the charge over time due to ________
a) The leakage resistance of the capacitor
5. _________ circuit is used to restore the capacitor value. a) Sense amplify
6. To reduce the number of external connections required, we make use of ______
b) Multiplexer
7. The processor must take into account the delay in accessing the memory location, such
memories are called ______b) Asynchronous memories
8. To get the row address of the required data ______ is enabled. b) RAS
9. In order to read multiple bytes of a row at the same time, we make use of ______a) Latch
10. The block transfer capability of the DRAM is called ________
c) Fast page mode
\1. The difference between DRAM’s and SDRAM’s is/are ________
b) The SDRAM’s make use of clock
2. The difference in the address and data connection between DRAM’s and SDRAM’s is
_______
c) The usage of a buffer in SDRAM’s
3. A _______ is used to restore the contents of the cells.
b) Refresh counter
4. The mode register is used to _______
b) Select the mode of operation
5. In a SDRAM each row is refreshed every 64ms.
a) True
6. The time taken to transfer a word of data to or from the memory is called as ______
c) Memory latency
7. In SDRAM’s buffers are used to store data that is read or written.
a) True
8. The SDRAM performs operation on the _______
a) Rising edge of the clock
9. DDR SDRAM’s perform faster data transfer by _______
b) Transferring on both edges
10. To improve the data retrieval rate ____________
a) The memory is divided into two banks
1. The chip can be disabled or cut off from an external connection using ______
a) Chip select
2. To organise large memory chips we make use of ______
c) Memory modules
3. The less space consideration as lead to the development of ________ (for large
memories). d) Both SIMM’s and DIMS’s
4. The SRAM’s are basically used as ______
b) Caches
5. The higher order bits of the address are used to _____a) Specify the row address
6. The address lines multiplexing is done using ______
b) Memory controller unit
7. The controller multiplexes the addresses after getting the _____ signal.
d) Request
8. The RAS and CAS signals are provided by the ______
c) Memory controller
9. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read
operation. Then the refresh overhead of the chip is ______b) 0.0038
10. When DRAM’s are used to build a complex large memory, then the controller only
provides the refresh counter. a) True
1. RAMBUS is better than the other memory chips in terms of ________
b) Speed of operation
2. The key feature of the RAMBUS tech is ________c) Speed of transfer
3. The increase in operation speed is done by ________________a) Reducing the
reference voltage
4. The data is transferred over the RAMBUS as _______c) Swing voltages
5. The type of signaling used in RAMBUS is ______b) Differential signaling
6. The special communication used in RAMBUS are _________a) RAMBUS channel
7. The original design of the RAMBUS required for ________ data lines. d) 9
8. The RAMBUS requires specially designed memory chips similar to _____
c) DRAM
9. A RAMBUS which has 18 data lines is called as _______b) Direct RAMBUS
10. The RDRAM chips assembled into larger memory modules called ______a) RRIM
1. If the transistor gate is closed, then the ROM stores a value of 1. b) False
2. PROM stands for __________a) Programmable Read Only Memory
3. The PROM is more effective than ROM chips in regard to _______ d) Both Cost and
Speed of operation
4. The difference between the EPROM and ROM circuitry is _____c) The usage of an extra
transistor
5. The ROM chips are mainly used to store _______c) Boot files
6. The contents of the EPROM are erased by ________b) Exposing the chip to UV rays
7. The disadvantage of the EPROM chip is _______
d) The need to remove the chip physically to reprogram it
8. EEPROM stands for Electrically Erasable Programmable Read Only Memory.
a) True
9. The disadvantage of the EEPROM is/are ________
a) The requirement of different voltages to read, write and store information
10. The memory devices which are similar to EEPROM but differ in the cost effectiveness is
______
c) Flash memory
11. The only difference between the EEPROM and flash memory is that the latter doesn’t
allow bulk data to be written. a) True
12. The flash memories find application in ______
d) Portable devices
13. The memory module obtained by placing a number of flash chips for higher memory
storage called as _______
c) Flash card
14. The flash memory modules designed to replace the functioning of a hard disk is ______
b) Flash drives
15. The reason for the fast operating speeds of the flash drives is ____________a) The
absence of any movable parts
1. The standard SRAM chips are costly as _________
b) They house 6 transistor per chip
2. The drawback of building a large memory with DRAM is ______________
c) The Slow speed of operation
3. To overcome the slow operating speeds of the secondary memory we make use of faster
flash drives. a) True
4. The fastest data access is provided using _______
d) Registers
5. The memory which is used to store the copy of data or instructions stored in larger
memories, inside the CPU is called _______
a) Level 1 cache
6. The larger memory placed between the primary cache and the memory is called ______
b) Level 2 cache
7. The next level of memory hierarchy after the L2 cache is _______
d) Register
8. The last on the hierarchy scale of memory devices is ______b) Secondary memory
9. In the memory hierarchy, as the speed of operation increases the memory size also
increases.
b) False
1. The reason for the implementation of the cache memory is ________b) The difference in
speeds of operation of the processor and memory
2. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
3. The temporal aspect of the locality of reference means ________c) That the recently
executed instruction will be executed soon again
4. The spatial aspect of the locality of reference means ________d) That the instruction in
close proximity of the instruction executed will be executed in future
5. The correspondence between the main memory blocks and those in the cache is given
by _________b) Mapping function
6. The algorithm to remove and place new contents into the cache is called _______
a) Replacement algorithm
7. The write-through procedure is used ________c) To write directly on the memory and the
cache simultaneously
8. The bit used to signify that the cache location is updated is ________a) Dirty bit
9. The copy-back protocol is used ________b) To update the contents of the memory from
the cache
10. The approach where the memory contents are transferred directly to the processor from
the memory is called ______c) Early-start
1. The memory blocks are mapped on to the cache with the help of ______
c) Mapping functions
2. During a write operation if the required block is not present in the cache then ______
occurs. c) Write delay
3. In ________ protocol the information is directly written into the main memory.
a) Write through
4. The only draw back of using the early start protocol is _______b) Complexity of circuit
5. The method of mapping the consecutive memory blocks to consecutive cache blocks is
called ______c) Direct
6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are
used for ________
a) Tag
7. In direct mapping the presence of the block in memory is checked with the help of block
field. b) False
8. In associative mapping, in a 16 bit system the tag field has ______ bits. a) 12
9. The associative mapping is costlier than direct mapping. a) True
10. The technique of searching for a block by going through all the tags is ______c)
Associative search
11. The set-associative map technique is a combination of the direct and associative
technique. a) True
12. In set-associative technique, the blocks are grouped into ______ sets. d) 6
13. A control bit called _________ has to be provided to each block in set-associative. b)
Valid bit
14. The bit used to indicate whether the block was recently used or not is _______d) Dirty
bit
15. Data which is not up-to date is called as _______b) Stale data
1. The main memory is structured into modules each with its own address register called
______
a) ABR
2. When consecutive memory locations are accessed only one module is accessed at a
time. a) True
3. In memory interleaving, the lower order bits of the address is used to _____________b)
Get the address of the module
4. The number successful accesses to memory stated as a fraction is called as _____a) Hit
rate
5. The number failed attempts to access memory, stated in the form of a fraction is called as
_________b) Miss rate
6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one, when _____ occurs. b) Miss
7. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
incremented by one and others remain same, in the case of ______a) Hit
8. If hit rates are well below 0.9, then they’re called as speedy computers. b) False9. The
extra time needed to bring the data into memory in case of a miss is called as
__________c) Miss penalty
10. The miss penalty can be reduced by improving the mechanisms for data transfer
between the different levels of hierarchy.
a) True
1. The CPU is also called as ________b) ISP
2. A common strategy for performance is making various functional units operate parallelly.
a) True
3. The PC gets incremented _____________c) After the fetch cycle
4. Which register in the processor is single directional? MAR
5. The transparent register/s is/are __________d) All of the mentioned
6. Which register is connected to the MUX?
a) Y
7. The registers, ALU and the interconnecting path together are called as ______
c) Data path
8. The input and output of the registers are governed by __________
d) Switches
9. When two or more clock cycles are used to complete data transfer it is called as
________
10. ________ signal is used to show complete of memory operation. a) MFC
1. Is the below code segment correct, for the addition of two numbers?
R1in, Yin

R2out, Select Y, ADD, Zin

Zout, R3in

a. True
2. The completion of the memory operation is indicated using ______ signal.
a) MFC
3. _________ signal enables the processor to wait for the memory operation to complete.
c) WMFC
4. The small extremely fast RAM is called as ________a) Cache
5. The main virtue for using a single Bus structure is ________c) Cost-effective connectivity
and ease of attaching peripheral devices
6. To extend the connectivity of the processor bus we use ______
a) PCI bus
7. The bus used to connect the monitor to the CPU is ____________
a) PCI bus
8. The IDE bus is used to connect ___________c) Both Harddisk and CD/DVD drives and
Processor
9. ANSI stands for _____________
a) American National Standards Institute
10. IBM developed a bus standard for their line of computers ‘PC-AT’ called ________
c) ISA
1. The general purpose registers are combined into a block called as ______c) Register file
2. In ______ technology, the implementation of the register file is by using an array of
memory locations. a) VLSI
3. In a three BUS architecture, how many input and output ports are there? c) 2 output and
1 input4. For a 3 BUS architecture, is the below code correct for adding three numbers?
PCout, R = B, Marin, READ, Inc PC

WMFC

MDRout, R = B, IRin

R4outa, R5outb, Select A, ADD, R6in, End

a. True
5. The main advantage of multiple bus organisation over a single bus is __________
a) Reduction in the number of cycles for execution
6. CISC stands for _________c) Complex Instruction Set Computer
7. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the
value of S is (Where S is term of the Basic performance equation). c) ~1
8. In multiple BUS organisation __________ is used to select any of the BUSes for input
into ALU.
a) MUX
9. There exists a separate block consisting of various units to decode an instruction. a) True
10. There exists a separate block to increment the PC in multiple BUS organisation. a) True
1. ________ are the different type/s of generating control signals. d) Both Micro-
programmed and Hardwired
2. The type of control signal is generated based on ________d) All of the mentioned
3. What does the hardwired control generator consist of? d) All of the mentioned
4. What does the end instruction do?
c) It starts a new instruction fetch cycle and resets the counter
5. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…a) True
6. What does the RUN signal do? d) It increments the step counter by one
7. The name hardwired came because the sequence of operations carried out is determined
by the wiring. a) True
8. The benefit of using this approach is ________d) It increases the speed of operation
9. The disadvantage/s of the hardwired approach is ________
d) less flexible & cannot be used for complex instructions
10. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
1. In micro-programmed approach, the signals are generated by ______a) Machine
instructions
2. A word whose individual bits represent a control signal is ______b) Control word
3. A sequence of control words corresponding to a control sequence is called _______
a) Micro routine
4. Individual control words of the micro routine are called as ______c) Micro instruction
5. The special memory used to store the micro routines of a computer is ________
b) Control store
6. To read the control words sequentially _________ is used. c) UPC
7. Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.
a) Starting address generator
8. The case/s where micro-programmed can perform well _______________d) None of the
mentioned
9. The signals are grouped such that mutually exclusive signals are put together. a) True
10. Highly encoded schemes that use compact codes to specify a small number of functions
in each micro instruction is ________b) Vertical organization
1. The directly mapped cache no replacement algorithm is required.
a) True
2. The surroundings of the recently accessed block is called as ______c) Locality of
reference
3. In set associative and associative mapping there exists less flexibility. b) False
4. The algorithm which replaces the block which has not been referenced for a while is
called _____
a) LRU
5. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one when _____ occurs. b) Miss
6. The LRU provides very bad performance when it comes to _________a) Blocks being
accessed is sequential
7. The algorithm which removes the recently used page first is ________b) MRU
8. The LRU can be improved by providing a little randomness in the access. a) True
9. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
incremented by one and others remain same, in the case of ______
a) Hit
10. The counter that keeps track of how many times a block is most likely used is _______
b) Reference counter
1. The key factor/s in commercial success of a computer is/are ________d) Both
Performance and Cost
2. The main objective of the computer system is ________b) To provide the best
performance at low cost
3. A common measure of performance is ________a) Price/performance ratio
4. The performance depends on ________
b) The speed of fetch and execution
5. The main purpose of having memory hierarchy is to ________d) Reduce access time &
Provide large capacity6. The memory transfers between two variable speed devices are
always done at the speed of the faster device. a) True
7. An effective to introduce parallelism in memory access is by _______a) Memory
interleaving
8. The performance of the system is greatly influenced by increasing the level 1 cache. a)
True
9. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with
an average of 5 steps. For the execution of the same instruction which processor is faster.
a) A
10. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the
value of S is (Where S is a term of the Basic performance equation).
c) ~1
1. The physical memory is not as large as the address space spanned by the processor.
a) True
2. The program is divided into operable parts called as _________b) Segments
3. The techniques which move the program blocks to or from the physical memory is called
as ______b) Virtual memory organization
4. The binary address issued to data or instructions are called as ______d) Logical address
5. __________ is used to implement virtual memory organisation.
c) MMU
6. ______ translates the logical address into a physical address.
a) MMU
7. The main aim of virtual memory organisation is ________
d) All of the mentioned
8. The DMA doesn’t make use of the MMU for bulk data transfers. b) False
9. The virtual memory basically stores the next segment of data to be executed on the
_________
a) Secondary storage
10. The associatively mapped virtual memory makes use of _______a) TLB
1. The main reason for the discontinuation of semi conductor based storage devices for
providing large storage space is _________b) High cost per bit value
2. The digital information is stored on the hard disk by ____________a) Applying a suitable
electric pulse
3. For the synchronization of the read head, we make use of a _______
c) Clock
4. One of the most widely used schemes of encoding used is _________c) Manchester
5. The drawback of Manchester encoding is _________
d) The low bit storage density provided
6. The read/write heads must be near to disk surfaces for better storage. a) True
7. _____ pushes the heads away from the surface as they rotate at their standard rates.
c) Air pressure
8. The air pressure can be countered by putting ______ in the head-disc surface
arrangement.
b) Spring mechanism
9. The method of placing the heads and the discs in an air tight environment is also called
as ______
c) Winchester technology
10. A hard disk with 20 surfaces will have _____ heads.
d) 20
1. The disk system consists of which of the following?
i. Disk
ii. Disk drive
iii. Disk controller
b) i, ii and iii
2. The set of corresponding tracks on all surfaces of a stack of disks form a ______b)
Cylinder
3. The data can be accessed from the disk using _________
d) All of the mentioned
4. The read and write operations usually start at ______ of the sector. d) Boundaries
5. To distinguish between two sectors we make use of ________
a) Inter sector gap
6. The _____ process divides the disk into sectors and tracks. c) Formatting
7. The access time is composed of __________d) Both Seek time and Rotational delay
8. The disk drive is connected to the system by using the _____b) SCSI bus
9. _______ is used to deal with the difference in the transfer rates between the drive and
the bus.
c) Data buffers
10. _______ is used to detect and correct the errors that may occur during data transfers. a)
ECC
1. The logic operations are simpler to implement using logic circuits.
a) True
2. The logic operations are implemented using _______ circuits.
c) Combinatorial
3. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________
b) Full adders
4. Which option is true regarding the carry in the ripple adders?
b) Must travel through the configuration
5. In full adders the sum circuit is implemented using ________
c) XOR
6. The usual implementation of the carry circuit involves _________
b) XOR
7. A _______ gate is used to detect the occurrence of an overflow.
b) XOR

8. In a normal adder circuit, the delay obtained in a generation of the output is _______
a) 2n + 2
9. The final addition sum of the numbers, 0110 & 0110 is ____________
a) 1101

10. The delay reduced to in the carry look ahead adder is __________
a) 5
1. The product of 1101 & 1011 is ______
a) 10001111
2. We make use of ______ circuits to implement multiplication.
c) Fast adders
3. The multiplier is stored in ______
b) Shift register
4. The ______ is used to coordinate the operation of the multiplier.
c) Control sequencer
5. The multiplicand and the control signals are passed through to the n-bit adder via _____
a) MUX
6. The product of -13 & 11 is ______________
b) 1101110001
7. The method used to reduce the maximum number of summands by half is _______
b) Bit-pair recording
8. The bits 1 & 1 are recorded as _______ in bit-pair recording.
d) both -1 and 0
9. The multiplier -6(11010) is recorded as _______
a) 0-1-2
10. CSA stands for?
a) Computer Speed Addition
1. The decimal numbers represented in the computer are called as floating point numbers,
as the decimal point floats through the number.
a) True
2. The numbers written to the power of 10 in the representation of decimal numbers are
called as _____c) Scale factors
3. If the decimal point is placed to the right of the first significant digit, then the number is
called ________b) Normalized
4. ________ constitute the representation of the floating number.d) All of the mentioned
5. The sign followed by the string of digits is called as ______c) Mantissa
6. In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ______
bits.b) 23
7. The normalized representation of 0.0010110 * 2 9 is _______b) 0 10000101 0110
8. The 32 bit representation of the decimal number is called as ___________b) Single-
precision
9. In 32 bit representation the scale factor as a range of ________
a) -128 to 127
10. In double precision format, the size of the mantissa is ______b) 52 bit
1. ______ have been developed specifically for pipelined systems.c) Optimizing compilers
2. The pipelining process is also called as ______b) Assembly line operation
3. The fetch and execution cycles are interleaved with the help of ________b) Clock
4. Each stage in pipelining should be completed within ___________ cycle.a) 1
5. In pipelining the task which requires the least time is performed first.b) False
6. If a unit completes its task before the allotted time period, then _______c) It’ll remain idle
for the remaining time
7. To increase the speed of memory access in pipelining, we make use of _______c) Cache
8. The periods of time when the unit is idle is called as _____d) Both Stalls and Bubbles
9. The contention for the usage of a hardware device is called ______
a) Structural hazard
10. The situation wherein the data of operands are not available is called ______
a) Data hazard
1. The throughput of a super scalar processor is _______c) More than 1
2. When the processor executes multiple instructions at a time it is said to use _______d)
Multiple issues
3. The ______ plays a very vital role in case of super scalar processors.
a) Compilers
4. If an exception is raised and the succeeding instructions are executed completely, then
the processor is said to have ______b) Imprecise exceptions
5. In super-scalar mode, all the similar instructions are grouped and executed together.
a) True
6. In super-scalar processors, ________ mode of execution is used.c) Out of order
7. Since it uses the out of order mode of execution, the results are stored in ______c)
Temporary registers
8. The step where in the results stored in the temporary register is transferred into the
permanent register is called as ______b) Commitment step
9. A special unit used to govern the out of order execution of the instructions is called as
______a) Commitment unit
10. The commitment unit uses a queue called ______
a) Record buffer
1. The CISC stands for ___________
d) Complex Instruction set computer
2. The computer architecture aimed at reducing the time of execution of instructions is
________b) RISC
3. The Sun micro systems processors usually follow _____ architecture.d) RISC
4. The RISC processor has a more complicated design than CISC.b) False
5. The iconic feature of the RISC machine among the following is _______c) Having a
branch delay slot
6. Both the CISC and RISC architectures have been developed to reduce the ______c)
Semantic gap
7. Out of the following which is not a CISC machine.d) Motorola A567
8. Pipe-lining is a unique feature of _______
a) RISC
9. In CISC architecture most of the complex instructions are stored in _____
d) Transistors
10. Which of the architecture is power efficient?b) RISC
1. Any condition that causes a processor to stall is called as _________
a) Hazard
2. The periods of time when the unit is idle is called as ________d) Both Stalls and Bubbles
3. The contention for the usage of a hardware device is called ______
a) Structural hazard
4. The situation wherein the data of operands are not available is called ______
a) Data hazard
5. The stalling of the processor due to the unavailability of the instructions is called as
___________
a) Control hazard
6. The time lost due to the branch instruction is often referred to as ____________c) Branch
penalty
7. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
8. ____________ method is used in centralized systems to perform out of order
execution.b) Score boarding
9. The algorithm followed in most of the systems to perform out of order execution is
__________
a) Tomasulo algorithm
10. The problem where process concurrency becomes an issue is called as ___________d)
Reader-writer problem
1. The set of loosely connected computers are called as __________d) Cluster
2. Each computer in a cluster is connected using __________b) Rj-45
3. The computer cluster architecture emerged as a result of _________d) Distributed
systems
4. The software which governs the group of computers is __________c) Clustering
middleware
5. The simplest form of a cluster is __________ approach.
a) Beowolf
6. The cluster formation in which the work is divided equally among the systems is ______
a) Load-configuration
7. In the client server model of the cluster _________ approach is used.d) Round robin
8. The beowolf structure follows the __________ approach of a relationship between the
systems.
a) Master-slave
9. The most common modes of communication in clusters are ______
d) Both Message passing interface and PVm
10. The method followed in case of node failure, wherein the node gets disabled is
_________
a) STONITH
1. VLIW stands for?
a) Very Long Instruction Word
2. The important feature of the VLIW is _______
a) ILP
3. The main difference between the VLIW and the other approaches to improve
performance is ___________c) Lack of complex hardware design
4. In VLIW the decision for the order of execution of the instructions depends on the
program itself.
a) True
5. The parallel execution of operations in VLIW is done according to the schedule
determined by __________c) Compiler
6. The VLIW processors are much simpler as they do not require of _________d)
Scheduling hardware
7. The VLIW architecture follows _____ approach to achieve parallelism.d) MIMD
The following instruction is allowed in VLIW:
f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3), f4 = pm(i8, m9);
a) True
9. To compute the direction of the branch the VLIW uses _____________
b) Heuristics
10. EPIC stands for?
a) Explicitly Parallel Instruction Computing
1. For converting a virtual address into the physical address, the programs are divided into
__________
a) Pages
2. The memory allocated to each page is contiguous.
a) True
3. The pages size shouldn’t be too small, as this would lead to __________
c) Increase in access time
4. The cache bridges the speed gap between ______ and __________c) Processor and
RAM
5. The virtual memory bridges the size and speed gap between __________ and
__________
b) RAM and Secondary memory
6. The higher order bits of the virtual address generated by the processor forms the
_______
d) Page number
7. The page length shouldn’t be too long because ___________
c) It leads to wastage of memory
8. The lower order bits of the virtual address forms the __________d) Offset
9. The area in the main memory that can hold one page is called as ___________b) Page
frame
10. The starting address of the page table is stored in __________c) Page table base
register
1. The bits used to indicate the status of the page in the memory is called ______
a) Control bits
2. The _______ bit is used to indicate the validity of the page.
a) Valid bit
3. The bit used to store whether the page has been modified or not is called as _______
a) Dirty bit
4. The page table should be ideally situated within ____________
c) MMU
5. If the page table is large then it is stored in __________
b) Main memory
6. When the page table is placed in the main memory, the ___________ is used to store the
recently accessed pages.
b) TLB
7. The TLB is incorporated as part of the _________
b) MMU
8. Whenever a request to the page that is not present in the main memory is accessed
______ is triggered.
c) Page fault
9. The general purpose registers are combined into a block called as ______
c) Register file
10. What does the RUN signal do?
d) It increments the step counter by one
1. _____ register is designated to point to the 68000 processor stack.
a) A7 register
2. The word length in the 68000 computer is _______
c) 16 bit
3. Is 68000 computer Byte addressable?
a) True
4. The register in 68000 can contain up to _____ bits.
b) 32
5. The 68000 has a max of how many data registers?
d) 8
6. When an operand is stored in a register it is _______
a) Stored in the lower order bits of the register
7. The status register of the 68000 has ____ condition codes.
c) 5
8. The 68000 uses _____ address assignment.
a) Big Endian
9. The addresses generated by the 68000 is _____ bit.
c) 24
10. Instructions which can handle any type of addressing mode are said to be ___________
b) Orthogonal
1. The instructions in 68000 can deal with operands of three different sizes.
a) True
2. As the instructions can deal with variable size operands we use ____________ to resolve
this.
b) Size indicator mnemonic
3. The starting address is denoted using _________ directive.
c) ORG
4. The constant can be declared using ___________ directive.
d) DC
5. To allocate a block of memory we use ___________ directive.
b) DS
6. The Branch instruction in 68000 provides how many types of offsets?
d) 2
7. The purpose of using DBcc as a branch instruction is __________
d) None of the mentioned
8. The 68000 uses ____________ method to access I/O devices buffers.
d) None of the mentioned
9. ____________ instruction is used to set up a frame pointer for the subroutines in 68000.
b) LINK
10. The LINK instruction is always followed by ____________ instruction.
d) MOVEM
1. ARM stands for _____________
b) Advanced RISC Machines
2. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
3. ARM processors where basically designed for _______
c) Mobile systems
4. The ARM processors don’t support Byte addressability.
b) False
5. The address space in ARM is ___________
d) 232
6. The address system supported by ARM systems is/are ___________
d) Both Little & Big Endian
7. Memory can be accessed in ARM systems by __________ instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
b) i, ii
8. RISC stands for _________
c) Reduced Instruction Set Computer
9. In the ARM, PC is implemented using ___________
c) General purpose register
10. The additional duplicate register used in ARM machines are called as _______
b) Banked registers
11. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
12. Each instruction in ARM machines is encoded into __________ Word.
c) 4 byte
13. All instructions in ARM are conditionally executed.
a) True
14. The addressing mode where the EA of the operand is the contents of Rn is ______
c) Post-indexed mode
15. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is
_______
a) EA = [Rn]
1. ___________ symbol is used to signify write back mode.
d) !
2. The instructions which are used to load or store multiple operands are called as
__________
c) Block transfer instructions
3. The Instruction, LDM R10!, {R0,R1,R6,R7} ______
a) Loads the contents of R10 into R1, R0, R6 and R7
4. The instruction, MLA R0,R1,R2,R3 performs _________
c) R0<-[R1]*[R2]+[R3]
5. The ability to shift or rotate in the same instruction along with other operation is
performed with the help of _________
b) Barrel switcher circuit
6. _________ instruction is used to get the 1’s complement of the operand.
d) MVN
7. The offset used in the conditional branching is __________ bit.
a) 24
8. The BEQ instructions is used ____________
c) To check if the flag Z is set to 1 and then causes branch
9. The condition to check whether the branch should happen or not is given by
____________
b) The higher order 4 bits of the instruction
10. Which of the two instructions sets the condition flag upon execution?
i) ADDS R0,R1,R2
ii) ADD R0,R1,R2
a) i
11. __________ directive is used to indicate the beginning of the program instruction or
data.
c) AREA
12. ___________ directive specifies the start of the execution.
b) ENTRY
13. ___________ directives are used to initialize operands.
d) DCD
14. ___________ directive is used to name the register used for execution of an instruction.
b) RN
15. The pseudo instruction used to load an address into the register is _________
b) ADR
1. The address space of the IA-32 is __________
b) 232
2. The addressing method used in IA-32 is ____________
a) Little Endian
3. The floating point numbers are stored in general purpose register in IA-32.
b) False
4. The Floating point registers of IA-32 can operate on operands up to ___________
d) 64 bit
5. The size of the floating registers can be extended upto _________
c) 80 bit
6. The IA-32 architecture associates different parts of memory called __________ with
different usages.
d) Segments
7. The PC is incorporated with the help of general purpose registers.
b) False
8. IOPL stands for ________
a) Input/Output Privilege level
9. In IA-32 architecture along with the general flags, the other conditional flags provided are
___________
d) All of the mentioned
10. The register used to serve as PC is called as ___________
b) Instruction pointer
11. The IA-32 processor can switch between 16 bit operation and 32 bit operation with the
help of instruction prefix bit.
a) True
12. The Bit extension of the register is denoted with the help of __________ symbol.
c) E
13. The instruction, ADD R1, R2, R3 is decoded as ___________
d) R1<-[R2]+[R3]
14. The instruction JG loop does ______
b) jumps to the memory location loop if the result of the most recent arithmetic op is greater
than 0
15. The LEA mnemonic is used to __________
a) Load the effective address of an instruction
1. The instructions of IA-32 machines are of length up to ______
d) 12 bytes
2. The bit present in the op code, indicating which of the operands is the source is called as
________
c) Direction bit
3. The __________ directive is used to allocate 4 bytes of memory.
a) DD
4. .data directive is used _________
b) To indicate the beginning of the data section
5. The instruction used to cause unconditional jump is ________
c) JMP
6. __________ instruction is used to check the bit of the condition flags.
d) BT
7. REPINS instruction is used to __________
b) Transfer a block of data parallelly from Input device to the processor
8. Which of the following statements regarding Stacks is/are True?
i) The stack always grows towards higher addresses
ii) The stack always grows towards lower addresses
iii) The stack has a fixed size
iv) The width of the stack is 32 bits
c) ii and iv
9. The instruction used to multiply operands yielding a double integer outcome is
_________
b) IMUL
10. SIMD stands for __________
a) Single Instruction Multiple Data
11. The IA-32 system follows _________ design.
b) CISC
12. Which architecture is suitable for a wide range of data types?
c) IA-32
13. In case of multimedia extension instructions, the pixels are encoded into a data item of
_________
d) 8 bit
14. The MMX (Multimedia Extension) operands are stored in __________
c) Float point registers
15. The division operation in IA-32 is a single operand instruction so it is assumed that
___________
a) The divisor is stored in the EAX register