Diagonal 6.46 mm (Type 1/2.

8) CMOS Solid-state Image Sensor with Square Pixel for

Color Cameras

Preliminary IMX290LQR-C
Description

The IMX290LQR-C is a diagonal 6.46 mm (Type 1/2.8) CMOS active pixel type solid-state image sensor with a
square pixel array and 2.13 M effective pixels. This chip operates with analog 2.9 V, digital 1.2 V, and interface 1.8 V
triple power supply, and has low power consumption. High sensitivity, low dark current and no smear are achieved
through the adoption of R, G and B primary color mosaic filters. This chip features an electronic shutter with variable
charge-integration time.
(Applications: Surveillance cameras, FA cameras, Industrial cameras)

Features

◆ CMOS active pixel type dots

◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
◆ Input frequency: 74.25 MHz / 37.125 MHz
◆ Number of recommended recording pixels: 1920 (H) × 1080 (V) approx. 2.07M pixel
◆ Readout mode
All-pixel scan mode
720p-HD readout mode
Window cropping mode
Vertical / Horizontal direction-normal / inverted readout mode
◆ Readout rate
Maximum frame rate in Full HD 1080p mode: 120 frame / s
◆ Wide dynamic range (WDR) function
Multiple exposure WDR
Digital overlap WDR
◆ Variable-speed shutter function (resolution 1H units)
◆ 10-bit / 12-bit A/D converter
◆ Conversion gain switching (HCG Mode / LCG Mode)
◆ CDS / PGA function
0 dB to 30 dB: Analog Gain 30 dB (step pitch 0.3 dB)
30.3 dB to 72 dB: Analog Gain 30 dB + Digital Gain 0.3 to 42 dB (step pitch 0.3 dB)
◆ Supports I/O switching
CMOS logic parallel SDR output
Low voltage LVDS (150 m Vp-p) serial ( 2 ch / 4 ch / 8ch switching) DDR output
CSI-2 serial data output ( 2 Lane / 4 Lane, RAW10 / RAW12 output)
◆ Recommended exit pupil distance: –30 mm to –∞

Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits.

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Device Structure

◆ CMOS image sensor

◆ Image size
Type 1/2.8
◆ Total number of pixels
1945 (H) × 1109 (V) approx. 2.16 M pixels
◆ Number of effective pixels
1945 (H) × 1097 (V) approx. 2.13 M pixels
◆ Number of active pixels
1937 (H) × 1097 (V) approx. 2.12 M pixels
◆ Number of recommended recording pixels
1920 (H) × 1080 (V) approx. 2.07 M pixels
◆ Unit cell size
2.9 µm (H) × 2.9 µm (V)
◆ Optical black
Horizontal (H) direction: Front 0 pixels, rear 0 pixels
Vertical (V) direction: Front 10 pixels, rear 0 pixels
◆ Dummy
Horizontal (H) direction: Front 0 pixels, rear 3 pixels
Vertical (V) direction: Front 0 pixels, rear 0 pixels
◆ Substrate material
Silicon

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Absolute Maximum Ratings

Item Symbol Min. Max. Unit Remarks

Supply voltage (analog 2.9 V) AVDD -0.3 3.3 V
Supply voltage (interface 1.8 V) OVDD -0.3 3.3 V
Supply voltage (digital 1.2 V) DVDD -0.3 2.0 V
Input voltage VI -0.3 OVDD + 0.3 V Not exceed 3.3 V
Output voltage VO -0.3 OVDD + 0.3 V Not exceed 3.3 V

Application Conditions

Item Symbol Min. Typ. Max. Unit

Supply voltage (analog 2.9 V) AVDD 2.80 2.90 3.00 V
Supply voltage (Interface 1.8 V) OVDD 1.70 1.80 1.90 V
Supply voltage (digital 1.2 V) DVDD 1.10 1.20 1.30 V
Performance guarantee temperature Tspec -10 ─ 60 ˚C
Operating guarantee temperature Topr -30 ─ 85 ˚C
Storage guarantee temperature Tstg -40 ─ 85 ˚C

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USE RESTRICTION NOTICE

This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the
image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may,
at any time, modify this Notice which will be available to you in the latest specifications book for the
Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its
own use restriction notice on the Products, such a use restriction notice will additionally apply between
you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or
distributor of Sony on such a use restriction notice when you consider using the Products.

Use Restrictions
 The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with
the terms and conditions set forth in this specifications book and otherwise notified by Sony from time
to time.
 You should not use the Products for critical applications which may pose a life- or injury-threatening
risk or are highly likely to cause significant property damage in the event of failure of the Products. You
should consult your sales representative beforehand when you consider using the Products for such
critical applications. In addition, you should not use the Products in weapon or military equipment.
 Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.

Design for Safety

 Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care
to ensure the safe design of your products such as component redundancy, anti-conflagration features,
and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or
other social damage as a result of such failure.

Export Control
 If the Products are controlled items under the export control laws or regulations of various countries,
approval may be required for the export of the Products under the said laws or regulations.
You should be responsible for compliance with the said laws or regulations.

No License Implied
 The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise.
Sony will not assume responsibility for any problems in connection with your use of such information or
for any infringement of third-party rights due to the same. It is therefore your sole legal and financial
responsibility to resolve any such problems and infringement.

Governing Law
 This Notice shall be governed by and construed in accordance with the laws of Japan, without reference
to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating
to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the
court of first instance.

Other Applicable Terms and Conditions

 The terms and conditions in the Sony additional specifications, which will be made available to you when
you order the Products, shall also be applicable to your use of the Products as well as to this
specifications book. You should review those terms and conditions when you consider purchasing
and/or using the Products.

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Contents

Description ......................................................................................................................................................................1
Features ..........................................................................................................................................................................1
Device Structure ..............................................................................................................................................................2
Absolute Maximum Ratings ..............................................................................................................................................3
Application Conditions .....................................................................................................................................................3
USE RESTRICTION NOTICE ..........................................................................................................................................4
Optical Center .................................................................................................................................................................7
Pixel Arrangement ...........................................................................................................................................................8
Block Diagram and Pin Configuration ...............................................................................................................................9
Pin Description .............................................................................................................................................................. 11
Electrical Characteristics ................................................................................................................................................ 14
DC Characteristics ..................................................................................................................................................... 14
Current Consumption ................................................................................................................................................. 15
AC Characteristics...................................................................................................................................................... 16
Master Clock Waveform (INCK) ............................................................................................................................... 16
XVS / XHS Input Characteristics In Slave Mode (XMASTER pin = High) ................................................................... 17
XVS / XHS Input Characteristics In Master Mode (DMODE pin = Low, CMOS Output)............................................... 17
Serial Communication ............................................................................................................................................. 18
DLCKP / DLCKM, DLOP / DLOM............................................................................................................................. 20
I/O Equivalent Circuit Diagram ....................................................................................................................................... 22
Spectral Sensitivity Characteristics ................................................................................................................................. 23
Image Sensor Characteristics ........................................................................................................................................ 24
Zone Definition ........................................................................................................................................................... 24
Image Sensor Characteristics Measurement Method ...................................................................................................... 25
Measurement Conditions ............................................................................................................................................ 25
Color Coding of Physical Pixel Array ........................................................................................................................... 25
Definition of standard imaging conditions .................................................................................................................... 25
Measurement Method................................................................................................................................................. 26
Setting Registers Using Serial Communication ............................................................................................................... 27
Description of Setting Registers (4-wire) ..................................................................................................................... 27
Register Communication Timing (4-wire) ..................................................................................................................... 27
Register Write and Read (4-wire) ................................................................................................................................ 28
Description of Setting Registers (I2C) .......................................................................................................................... 29
Register Communication Timing (I2C).......................................................................................................................... 29
Communication Protocol............................................................................................................................................. 30
Register Write and Read (I2C)..................................................................................................................................... 31
Single Read from Random Location ........................................................................................................................ 31
Single Read from Current Location .......................................................................................................................... 31
Sequential Read Starting from Random Location ..................................................................................................... 32
Sequential Read Starting from Current Location....................................................................................................... 32
Single Write to Random Location............................................................................................................................. 33
Sequential Write Starting from Random Location ..................................................................................................... 33
Register Map ................................................................................................................................................................. 34
Readout Drive mode ...................................................................................................................................................... 50
Sync code (Parallel CMOS output / Serial LVDS output) .............................................................................................. 52
Sync Code Output Timing ........................................................................................................................................... 52
Image Data Output Format (CSI-2 output) ................................................................................................................... 53
Frame Format ......................................................................................................................................................... 53
Frame Structure ...................................................................................................................................................... 53
Embedded Data Line .............................................................................................................................................. 54
Image Data Output Format ......................................................................................................................................... 57
All-pixel scan mode (Full HD 1080p) ........................................................................................................................ 57
Window Cropping Mode .......................................................................................................................................... 63
HD720p mode ........................................................................................................................................................ 71
Description of Various Function ...................................................................................................................................... 77
Standby Mode............................................................................................................................................................ 77
Slave Mode and Master Mode .................................................................................................................................... 78
Gain Adjustment Function ........................................................................................................................................... 80

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Black Level Adjustment Function ................................................................................................................................ 81

Normal Operation and Inverted Operation ................................................................................................................... 82
Shutter and Integration Time Settings ......................................................................................................................... 83
Example of Integration Time Setting ........................................................................................................................ 83
Normal Exposure Operation (Controlling the Integration Time in 1H Units) ................................................................... 84
Long Exposure Operation (Control by Expanding the Number of Lines per Frame) ....................................................... 85
Example of Integration Time Settings .......................................................................................................................... 86
Signal Output ............................................................................................................................................................. 87
Output Pin Settings ................................................................................................................................................. 87
MIPI Transmitter......................................................................................................................................................... 92
Output Pin Bit Width Selection ................................................................................................................................. 93
Number of Internal A/D Conversion Bits Setting ....................................................................................................... 94
Output Rate Setting................................................................................................................................................. 95
Output Signal Range ............................................................................................................................................... 95
INCK Setting .............................................................................................................................................................. 96
Register Hold Setting.................................................................................................................................................. 96
Software Reset (CMOS parallel / Low voltage LVDS serial only) .................................................................................. 97
Mode Transitions........................................................................................................................................................ 98
Power-on and Power-off Sequence ................................................................................................................................ 99
Power-on sequence ................................................................................................................................................... 99
Power-off sequence ................................................................................................................................................. 100
Sensor Setting Flow ................................................................................................................................................. 101
Setting Flow in Sensor Slave Mode ....................................................................................................................... 101
Setting Flow in Sensor Master Mode...................................................................................................................... 102
Peripheral Circuit ......................................................................................................................................................... 103
Spot Pixel Specifications .............................................................................................................................................. 104
Zone Definition ......................................................................................................................................................... 104
Notice on White Pixels Specifications ........................................................................................................................... 105
Measurement Method for Spot Pixels ........................................................................................................................... 106
Spot Pixel Pattern Specification.................................................................................................................................... 107
Marking (Tentative) ...................................................................................................................................................... 108
Notes On Handling ...................................................................................................................................................... 109
Package Outline (Tentative) ......................................................................................................................................... 111
List of Trademark Logos and Definition Statements....................................................................................................... 112
Revision History........................................................................................................................................................... 113

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Optical Center

Top View
Package center
Optical center
Package reference (H, V)

12.00 ± 0.10 mm
Package
6.058 ± 0.075 mm outline H
P1-Pin A1-Pin direction

4.415 ± 0.075 mm
Package
outline V
direction
9.30 ± 0.10 mm

Sensor
scanning V
direction (normal)

Sensor
scanning H
direction (normal)
P11-Pin A11-Pin

Optical Center

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Pixel Arrangement

Reference pin
P1 pin Top View A1 pin

R G G R
G B 9 Effective margin for color processing B G

Total number of pixels: 1945(H) × 1109(V) = 2.16 M

Vertical scan direction (Normal)

Number of effective pixels: 1945(H) × 1097(V) = 2.13 M

Number of active pixels: 1937(H) × 1097(V) = 2.12 M
Number of recommended recording pixels:
1920(H) × 1080(V) = 2.07 M
Effective margin for

Effective margin for

Effective pixel side

Effective pixel side

color processing

color processing
1080
ignored area

ignored area
Recording Pixel area

Dummy
4 8 1920 9 4 3

G B B G
R G 8 Effective margin for color processing G R

10 Vertical(V) direction effective OB

2 OB side ignored area

P11 pin Horizontal scan direction (Normal) A11 pin

* Reference pin number is consecutive numbering of package pin array.

See the Pin Configuration for the number of each pin.

Pixel Arrangement (Top View)

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Block Diagram and Pin Configuration

PLL
Sensor Control Unit
12/10 Bit digital Output

Drive Circuit
Sensor
Digital Serial Output

CDS/Column Circuit Bias

Block Diagram

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A B C D E F G H J K L M N P

DLOMA DLOMB DLOMC DLOMD DLCKM DLOME DLOMF DLOMG DLOMH VDDMIF
1 (GND) (GND)
N.C. DLOPA DLOPB DLOPC DLOPD DLCKP DLOPE DLOPF DLOPG DLOPH VSSMIF N.C.
2
VLOADLM VSSHPX VSSMIF VSSMIF VSSMIF VSSMIF VSSMIF VSSMIF VSSLSC INCK
3
VDDHAN VSSHAN (GND) VSSLSC VDDLSC (GND) (GND) (GND) (GND) (GND)
4 NC NC NC NC NC NC

VRLFR VRLST (GND) (GND) (GND) VDDLSC VSSLSC VSSLIF DMO3P DMO3N
5 NC NC NC

VDDHPX VSSHPX (GND) (GND) (GND) VDDLIF VSSLIF VSSLIF DMO1P DMO1N
6 NC NC NC

VDDHCP VSSHCP (GND) (GND) (GND) VDDLIF VSSLIF VSSLIF DMCKP DMCKN
7 NC NC NC

VDDHPX VSSHPX (GND) VSSLSC VDDLSC VDDLSC VSSLSC VSSLIF DMO2P DMO2N
8 NC

VDDHAN VSSHAN (GND) (GND) (GND) (GND) (GND) VSSLIF DMO4P DMO4N
9 NC NC NC NC NC

TAMON VSSLCN VSSLSC SDO SCK SDI OMODE XCLR XHS VSSLCN
10 (GND) (GND)
N.C. N.C.
VBGR VDDLCN TENABLE XMASTER XCE XVS TOUT XTRIG VSSLSC VDDLCN
11

Analog Power Supply (2.9V) Analog GND

Digital Power Supply (1.8V) Digital GND

Digital Power Supply (1.2V) Digital GND

Clock Data output (CMOS/LVDS)

Data output (CSI-2)

*The N.C. pin that is shown with (GND) can be connected to GND.

Pin Configuration (Bottom View)

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Pin Description

Pin Analog
No. I/O Symbol Description Remarks
No /Digital
1 A1 ― ― N.C. ― GND connectable
2 A3 O A VLOADLM Reference pin
3 A4 Power A VDDHAN 2.9 V power supply
4 A5 O A VRLFR Reference pin
5 A6 Power A VDDHPX 2.9 V power supply
6 A7 Power A VDDHCP 2.9 V power supply
7 A8 Power A VDDHPX 2.9 V power supply
8 A9 Power A VDDHAN 2.9 V power supply
9 A11 ― ― N.C. ― GND connectable
10 B3 GND A VSSHPX 2.9 V GND
11 B4 GND A VSSHAN 2.9 V GND
12 B5 O A VRLST Reference pin
13 B6 GND A VSSHPX 2.9 V GND
14 B7 GND A VSSHCP 2.9 V GND
15 B8 GND A VSSHPX 2.9 V GND
16 B9 GND A VSSHAN 2.9 V GND
17 C1 O D DLOMA CMOS output / LVDS output data
18 C2 O D DLOPA CMOS output / LVDS output data
19 C3 GND D VSSMIF 1.8 V GND
20 C4 ― ― N.C. ― GND connectable
21 C5 ― ― N.C. ― GND connectable
22 C6 ― ― N.C. ― GND connectable
23 C7 ― ― N.C. ― GND connectable
24 C8 ― ― N.C. ― GND connectable
25 C9 ― ― N.C. ― GND connectable
26 C10 O A TAMON TEST output pin OPEN
27 C11 O A VBGR Reference pin
28 D1 O D DLOMB CMOS output / LVDS output data
29 D2 O D DLOPB CMOS output / LVDS output data
30 D3 GND D VSSMIF 1.8 V GND
31 D4 GND D VSSLSC 1.2 V GND
32 D5 ― ― N.C. ― GND connectable
33 D6 ― ― N.C. ― GND connectable
34 D7 ― ― N.C. ― GND connectable
35 D8 GND D VSSLSC 1.2 V GND
36 D9 ― ― N.C. ― GND connectable
37 D10 GND D VSSLCN 1.2 V GND
38 D11 Power D VDDLCN 1.2 V power supply

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Pin Analog
No. I/O Symbol Description Remarks
No /Digital
39 E1 O D DLOMC CMOS output / LVDS output data
40 E2 O D DLOPC CMOS output / LVDS output data
41 E3 GND D VSSMIF 1.8 V GND
42 E4 Power D VDDLSC 1.2 V power supply
43 E5 ― ― N.C. ― GND connectable
44 E6 ― ― N.C. ― GND connectable
45 E7 ― ― N.C. ― GND connectable
46 E8 Power D VDDLSC 1.2 V power supply
47 E9 ― ― N.C. ― GND connectable
48 E10 GND D VSSLSC 1.2 V GND
49 E11 I D TENABLE TEST Enable OPEN
50 F1 O D DLOMD CMOS output / LVDS output data
51 F2 O D DLOPD CMOS output / LVDS output data
4-wire: SDO pin
52 F10 O D SDO Communication output 2
I C: Open
High: Slave mode / Low:
53 F11 I D XMASTER Master / Slave selection
Master mode
54 G1 O D DLCKM CMOS output / LVDS output clock
55 G2 O D DLCKP CMOS output / LVDS output clock
4-wire: SCK pin
56 G10 I D SCK Communication clock
I2C: SCL pin
4-wire: XCE pin
57 G11 I D XCE Communication enable
I2C: Fixed to High
58 H1 O D DLOME CMOS output / LVDS output data
59 H2 O D DLOPE CMOS output / LVDS output data
4-wire: SDI pin
60 H10 I/O D SDI Communication input 2
I C: SDA pin
61 H11 I/O D XVS Vertical sync signal
62 J1 O D DLOMF CMOS output / LVDS output data
63 J2 O D DLOPF CMOS output / LVDS output data
Serial output interface
64 J10 I D OMODE High: LVDS / Low: CSI-2
selection
65 J11 O D TOUT TEST output pin OPEN
66 K1 O D DLOMG CMOS output / LVDS output data
67 K2 O D DLOPG CMOS output / LVDS output data
68 K3 GND D VSSMIF 1.8 V GND
69 K4 ― ― N.C. ― GND connectable
70 K5 Power D VDDLSC 1.2 V power supply
71 K6 Power D VDDLIF 1.2 V power supply
72 K7 Power D VDDLIF 1.2 V power supply
73 K8 Power D VDDLSC 1.2 V power supply
74 K9 ― ― N.C. ― GND connectable
75 K10 I D XCLR System clear High: Normal / Low: Clear
76 K11 I D XTRIG Trigger mode input OPEN
77 L1 O D DLOMH CMOS output / LVDS output data
78 L2 O D DLOPH CMOS output / LVDS output data

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Pin Analog
No. I/O Symbol Description Remarks
No /Digital
79 L3 GND D VSSMIF 1.8 V GND
80 L4 ― ― N.C. ― GND connectable
81 L5 GND D VSSLSC 1.2 V GND
82 L6 GND D VSSLIF 1.2 V GND
83 L7 GND D VSSLIF 1.2 V GND
84 L8 GND D VSSLSC 1.2 V GND
85 L9 ― ― N.C. ― GND connectable
86 L10 I/O D XHS Horizontal sync signal
87 L11 GND D VSSLSC 1.2 V GND
88 M1 Power D VDDMIF 1.8 V power supply
89 M2 GND D VSSMIF 1.8 V GND
90 M3 GND D VSSMIF 1.8 V GND
91 M4 ― ― N.C. ― GND connectable
92 M5 GND D VSSLIF 1.2 V GND
93 M6 GND D VSSLIF 1.2 V GND
94 M7 GND D VSSLIF 1.2 V GND
95 M8 GND D VSSLIF 1.2 V GND
96 M9 GND D VSSLIF 1.2 V GND
97 M10 GND D VSSLCN 1.2 V GND
98 M11 Power D VDDLCN 1.2 V power supply
99 N3 GND D VSSLSC 1.2 V GND
100 N4 ― ― N.C. ― GND connectable
101 N5 O D DMO3P CSI-2 output data
102 N6 O D DMO1P CSI-2 output data
103 N7 O D DMCKP CSI-2 output clock
104 N8 O D DMO2P CSI-2 output data
105 N9 O D DMO4P CSI-2 output data
106 P1 ― ― N.C. ― GND connectable
107 P3 I D INCK Master clock input
108 P4 ― ― N.C. ― GND connectable
109 P5 O D DMO3N CSI-2 output data
110 P6 O D DMO1N CSI-2 output data
111 P7 O D DMCKN CSI-2 output clock
112 P8 O D DMO2N CSI-2 output data
113 P9 O D DMO4N CSI-2 output data
114 P11 ― ― N.C. ― GND connectable

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Electrical Characteristics

DC Characteristics

Item Pins Symbol Condition Min. Typ. Max. Unit

analog VDDHx AVDD 2.80 2.90 3.00 V
Supply
Interface VDDMx OVDD 1.70 1.80 1.90 V
voltage
digital VDDLx DVDD 1.10 1.20 1.30 V
XHS
XVS
XCLR VIH 0.8OVDD ― ― V
INCK
XMASTER XVS / XHS
Digital input voltage
OMODE Slave Mode
SCK
SDI VIL — ― 0.2OVDD V
XCE
XTRIG

VOH IOH = -2 mA OVDD-0.4 ― ― V

DLOP [A:F] VOL IOL = 2 mA ― ― 0.4 V

DLOM [A:F]
DLCKP VCM Low voltage LVDS ― OVDD/2 ― V
DLCKM
Digital output voltage Low voltage LVDS
VOD (Termination 100 150 220 mV
resistance: 100 Ω)
XHS VOH OVDD-0.4 ― ― V
XVS XVS / XHS
SDO Master Mode
TOUT VOL ― ― 0.4 V

DLOP*
DLCKP
LVDS
VCM
output
DLOM*
DLCKM VOD

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Current Consumption

Typ. Max.
Item pin Symbol Standard Saturated Standard Saturated Unit
luminous luminous luminous luminous
intensity intensity intensity intensity
Operating current VDDH IAVDD 54 53 111 108 mA
Low voltage LVDS serial 8 ch
VDDM IOVDD 16 15 29 27 mA
12 bit 60 frame / s
Full HD 1080p mode VDDL IDVDD 77 95 123 214 mA
Operating current VDDH IAVDD 55 54 111 108 mA
MIPI CSI-2 / 4 Lane
VDDM IOVDD 1 1 2 2 mA
12 bit, 60 frame/s
Full HD 1080p mode VDDL IDVDD 94 111 143 252 mA
Operating current VDDH IAVDD 55 54 111 110 mA
CMOS parallel SDR
VDDM IOVDD 17 17 28 28 mA
12 bit, 30 frame/s
Full HD 1080p VDDL IDVDD 49 59 90 159 mA
VDDH IAVDD_STB ― 0.1 mA
Standby current VDDM IOVDD_STB ― 0.1 mA
VDDL IDVDD_STB ― 14.0 mA

Operating current: (Typ.) Supply voltage 2.90 V / 1.8 V / 1.2 V, Tj = 25 ˚C

(Max.) Supply voltage 3.00 V / 1.9 V / 1.3 V, Tj = 60 ˚C, worst state of internal circuit
operating current consumption,
Standby: (Max.) Supply voltage 3.00 V / 1.9 V / 1.3 V, Tj = 60 ˚C, INCK: 0 V, light-obstructed state.

Standard luminous intensity: luminous intensity at 1/3 of the sensor saturated

Saturated luminous intensity: luminous intensity when the sensor is saturated.

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AC Characteristics
Master Clock Waveform (INCK)

1/fINCK
Tr_inck Tf_inck
0.8 × OVDD
tWHINCK
INCK 0.5 × OVDD
tWLINCK
0.2 × OVDD

tWP
tP
Duty Ratio = tWP / tP × 100

Item Symbol Min. Typ. Max. Unit Remarks

INCK clock frequency fINCK fINCK × 0.96 fINCK fINCK × 1.02 MHz fINCK = 37.125 MHz, 74.25 MHz

INCK Low level pulse width tWLINCK 4 ― ― ns fINCK = 37.125 MHz, 74.25 MHz

INCK High level pulse width tWHINCK 4 ― ― ns fINCK = 37.125 MHz, 74.25 MHz

INCK clock duty ― 45.0 50.0 55.0 % Define with 0.5 × OVDD

INCK Rise time Tr_inck ― ― 5 ns 20 % to 80 %

INCK Fall time Tf_inck ― ― 5 ns 80 % to 20 %

*The INCK fluctuation affects the frame rate.

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XVS / XHS Input Characteristics In Slave Mode (XMASTER pin = High)

Tf_xvs Tr_xvs

0.8 × OVDD
XVS
0.2 × OVDD

Tf_xhs Tr_xhs
tWLXHS tWHXHS
0.8 × OVDD
XHS
0.2 × OVDD

tHFDLY tVRDLY

Item Symbol Min. Typ. Max. Unit Remarks

XHS Low level pulse width tWLXHS 4 / fINCK ― ― ns

XHS High level pulse width tWHXHS 4 / fINCK ― ― ns

XVS - XHS fall width tHFDLY 1 / fINCK ― ― ns

XHS - XVS rise width tVRDLY 1 / fINCK ― ― ns

XVS Rise time Tr_xvs ― ― 5 ns 20 % to 80 %

XVS Fall time Tf_xvs ― ― 5 ns 80 % to 20 %

XHS Rise time Tr_xhs ― ― 5 ns 20 % to 80 %

XHS Fall time Tf_xhs ― ― 5 ns 80 % to 20 %

XVS / XHS Input Characteristics In Master Mode (DMODE pin = Low, CMOS Output)
* XVS and XHS cannot be used for the sync signal to pixels.
Be sure to detect sync code to detect the start of effective pixels in 1 line.
For the output waveforms in master mode, see the item of “Slave Mode and Master Mode”

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Serial Communication
4-wire

0.8 × OVDD
XCLR tWLXCLR
tENXCE
0.2 × OVDD

Tf_xclr Tr_xclr
Tf_xce Tr_xce

0.8 × OVDD
XCE tWHXCE
0.2 × OVDD

tSUXCE Tr_sck Tf_sck tHDXCE

0.8 × OVDD
1/fSCK
SCK
0.2 × OVDD
tHDSDI Tr_sdi
tSUSDI Tf_sdi

0.8 × OVDD
SDI DATA DATA
0.2 × OVDD

tDLSDO
0.8 × OVDD
SDO DATA DATA
0.2 × OVDD

Item Symbol Min. Typ. Max. Unit Remarks

SCK clock frequency fSCK ― ― 13.5 MHz

XCLR Low level pulse width tWLXCLR 4 / fINCK ― ― ns

XCE effective margin tENXCE 20 ― ― µs

XCE input set-up time tSUXCE 20 ― ― ns

XCE input hold time tHDXCE 20 ― ― ns

XCE High level pulse width tWHXCE 20 ― ― ns

SDI input set-up time tSUSDI 10 ― ― ns

SDI input hold time tHDSDI 10 ― ― ns

SDO output delay time tDLSDO 0 ― 25 ns Output load capacitance: 20 pF

XCLR Rise time Tr_xclr ― ― 5 ns 20 % to 80 %

XCLR Fall time Tf_xclr ― ― 5 ns 80 % to 20 %

XCE Rise time Tr_xce ― ― 5 ns 20 % to 80 %

XCE Fall time Tf_xce ― ― 5 ns 80 % to 20 %

SCK Rise time Tr_sck ― ― 5 ns 20 % to 80 %

SCK Fall time Tf_sck ― ― 5 ns 80 % to 20 %

SDI Rise time Tr_sdi ― ― 5 ns 20 % to 80 %

SDI Fall time Tf_sdi ― ― 5 ns 80 % to 20 %

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I2C

Start Repeated Stop

condition Start condition
condition

VIH/VOH
SDA
VIL/VOL
tf tHD;DAT tSU;STA tBUF
tLOW tSU;DAT tr
VIH
SCL
VIL
tHIGH
tHD;STA tr tHD;STA tSU;STO

2
I C Specification

Item Symbol Min. Typ. Max. Unit 条件

Low level input voltage VIL -0.3 — 0.3 × OVDD V

High level input voltage VIH 0.7 × OVDD — 1.9 V

Low level input voltage VOL 0 — 0.2 × OVDD V OVDD < 2 V, Sink 3 mA

High level input voltage VOH 0.8 × OVDD — — V

Load 10 pF – 400 pF,
Output fall time tof — — 250 ns
0.7 × OVDD – 0.3 × OVDD
Input current Ii -10 — 10 µA 0.1 × OVDD – 0.9 × OVDD
Capacitance for
Ci — — 10 pF
SCK (SCL) /SDI (SDA)

I2C AC Characteristics

Item Symbol Min. Typ. Max. Unit

SCL clock frequency fSCL 0 — 400 kHz
Hold time (Start Condition) tHD;STA 0.6 — ― µs
Low period of the SCL clock tLOW 1.3 — ― µs
High period of the SCL clock tHIGH 0.6 — ― µs
Set-up time (Repeated Start Condition) tSU;STA 0.6 — ― µs
Data hold time tHD;DAT 0 — 0.9 µs
Data set-up time tSU;DAT 100 — ― ns
Rise time of both SDA and SCL signals tr ― — 300 ns
Fall time of both SDA and SCL signals tf ― — 300 ns
Set-up time (Stop Condition) tSU;STO 0.6 — ― µs

Bus free time between a STOP and START Condition tBUF 1.3 — ― µs

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DLCKP / DLCKM, DLOP / DLOM

CMOS Outputs

1/fDLCKP

DLCKP 0.5 × OVDD

tSKMINDO tSKMAXDO

DLO*

Item Symbol Min. Typ. Max. Unit Remarks

DLCKP frequency fDLCKP ― ― 74.25 MHz

DLCKP clock duty ― 40 50 60 %

DLCKP - DLO skew Max. tSKMAXDO ― ― 2 ns Output load capacitance: 20 pF

DLCKP - DLO skew Min. tSKMINDO ― ― 2 ns Output load capacitance: 20 pF

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Low Voltage LVDS DDR Output

DLCKM

DLCKP

DLCKP -
DLCKM

tSUDO tHDDO
DLOP*

DLOM*

DLOP* -
DLOM*
Valid Data

(Output load capacitance: 8 pF)

Item Symbol Min. Typ. Max. Unit Remarks

DLCKP/DLCKM clock duty ― 40 50 60 % DLCK = 297 MHz (Max.)
DLO set-up time tSUDO 400 ― ― ps Data Rate 297 MHz DDR
DLO hold time tHDDO 400 ― ― ps Data Rate 297 MHz DDR

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I/O Equivalent Circuit Diagram

: External pin

Symbol Equivalent circuit Symbol Equivalent circuit

VDDMIF VDDMIF

OMODE Digital XVS Digital

TENABLE input XHS I/O

VSSLSC VSSLSC

VDDMIF VDDMIF

XMASTER Digital SDO Digital

XCE input TOUT output

VSSLSC VSSLSC

VDDMIF

XCLR Digital Digital

input XTRIG
INCK input

VSSLSC VSSLSC

Digital
input
SDI VRLFR Analog
I/O
SCK VRLST

VSSLSC

VSSHPX

VDDHPX VDDMIF
VDDMIF
DLOPx
DLOxP DLCKP
VLOADLM
Analog DLOxN VSSMIF
VBGR I/O
DLCKP VDDMIF
TAMON DLOMx
DLCKN DLCKM
VSSMIF

VSSHPX VSSMIF

VDDLIF
VDDLIF
DMOPx
DMOPx DMCKP
DMOMx VSSLIF

DMCKP VDDLIF
DMOMx
DMCKM DMCKM
VSSLIF

VSSLIF

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Spectral Sensitivity Characteristics

(Excludes lens characteristics and light source characteristics.)

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Image Sensor Characteristics

(AVDD = 2.9 V, OVDD = 1.8 V, DVDD = 1.2 V, Tj = 60 ˚C, All-pixel scan mode, 12 bit 30 frame/s, Gain: 0 dB)

Measurement
Item Symbol Min. Typ. Max. Unit Remarks
method

1/30 s storage
4663 5486 Digit
― 12 bit converted value
(1105) (1300) (mV)
HCG mode
G sensitivity S 1
1/30 s storage
2332 2743 Digit
― 12 bit converted value
(553) (650) (mV)
LCG mode

Sensitivity R/G RG 0.45 ― 0.60 ― ―

2
ratio B/G BG 0.32 ― 0.47 ― ―
3857 Digit 12 bit converted value
Saturation signal Vsat ― ― 3
(914) (mV) LCG mode
Video signal shading SH ― ― 25 % 4 ―
12 bit converted value
Vertical line VL 90 µV 5
LCG mode
1/30 s storage
0.63 Digit
Dark signal Vdt ― ― 6 12 bit converted value
(0.15) (mV)
LCG mode
1/30 s storage
0.63 Digit
Dark signal shading ΔVdt ― ― 7 12 bit converted value
(0.15) (mV)
LCG mode
Conversion efficiency HCG mode /
Rcg 1.8 2 2.2 ― ―
ratio LCG mode

Note)
1. Converted value into mV using 1Digit = 0.2370 mV for 12-bit output and 1Digit = 0.9479 mV for 10-bit
output.
2. The video signal shading is the measured value in the wafer status (including color filter) and does not
include characteristics of the seal glass.
3. The characteristics above apply to effective pixel area that is shown below.

Zone Definition

1945

4 4

8
1097

8 1920 9
1080

Effective pixel area Ignored area

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Image Sensor Characteristics Measurement Method

Measurement Conditions
1. In the following measurements, the device drive conditions are at the typical values of the bias conditions and
clock voltage conditions.
2. In the following measurements, spot pixels are excluded and, unless otherwise specified, the optical black (OB)
level is used as the reference for the signal output, which is taken as the value of the Gr / Gb channel signal
output or the R / B channel signal output of the measurement system.

Color Coding of Physical Pixel Array

The primary color filters of this image sensor are arranged in the layout shown in the figure below. Gr and Gb
represent the G signal on the same line as the R and B signals, respectively. The Gb signal and B signal lines and
the R signal and Gr signal lines are output successively.

Gb B Gb B

R Gr R Gr

Gb B Gb B

R Gr R Gr

Color Coding Diagram

Definition of standard imaging conditions

◆ Standard imaging condition I:
Use a pattern box (luminance: 706 cd/m2, color temperature of 3200 K halogen source) as a subject. (Pattern for
evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter and image at
F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity
testing luminous intensity.

◆ Standard imaging condition II:

Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles. Use a
testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter. The luminous intensity is adjusted to the value
indicated in each testing item by the lens diaphragm.

◆ Standard imaging condition III:

Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles. Use a
testing standard lens (exit pupil distance - 30 mm) with CM500S (t = 1.0 mm) as an IR cut filter. The luminous
intensity is adjusted to the value indicated in each testing item by the lens diaphragm.

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Measurement Method
1. Sensitivity
Set the measurement condition to the standard imaging condition I. After setting the electronic shutter mode with
a shutter speed of 1/100 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of the screen, and
substitute the values into the following formula.

Sg = (VGr + VGb) / 2 × 100/30 [mV]

2. Sensitivity ratio
Set the measurement condition to the standard imaging condition II. After adjusting the average value of the Gr
and Gb signal outputs to 650 mV, measure the R signal output (VR [mV]), the Gr and Gb signal outputs (VGr,
VGb [mV]) and the B signal output (VB [mV]) at the center of the screen in frame readout mode, and substitute
the values into the following formulas.

VG = (VGr + VGb) / 2
RG = VR / VG
BG = VB / VG

3. Saturation signa l
Set the measurement condition to the standard imaging condition II. After adjusting the luminous intensity to 20
times the intensity with the average value of the Gr and Gb signal outputs, 650 mV, measure the average values
of the Gr, Gb, R and B signal outputs.

4. Video signal shading

Set the measurement condition to the standard imaging condition III. With the lens diaphragm at F2.8, adjust the
luminous intensity so that the average value of the Gr and Gb signal outputs is 650 mV. Then measure the
maximum value (Gmax [mV]) and the minimum value (Gmin [mV]) of the Gr and Gb signal outputs, and substitute
the values into the following formula.

SH = (Gmax – Gmin) / 650 × 100 [%]

5. Vertical Line
With the device junction temperature of 60 ˚C and the device in the light-obstructed state, calculates eachaverage
output of Gr, Gb, R and B on respective columns. Calculates maximum value of difference with adjacent column
on the same color (VL [μV]).

6. Dark signal
With the device junction temperature of 60 ˚C and the device in the light-obstructed state, divide the output
difference between 1/30 s integration and 1/300 s integration by 0.9, and calculate the signal output converted to
1/30 s integration. Measure the average value of this output (Vdt [mV]).

7. Dark signal shading

After the measurement item 5, measure the maximum value (Vdmax [mV]) and the minimum value (Vdmin [mV])
of the dark signal output, and substitute the values into the following formula.

ΔVdt = Vdmax – Vdmin [mV]

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Setting Registers Using Serial Communication

This sensor can write and read the setting values of the various registers shown in the Register Map by 4-wire serial
communication and I2C communication. See the Register Map for the addresses and setting values to be set.
Because the two communication systems are judged at the first communication, once they are judged, the
2
communication cannot be switched until sensor reset. The pin for 4-wire serial communication and I C
2
communication is shared, so the external pin XCE must be fixed to power supply side when using I C
communication.

Description of Setting Registers (4-wire)

The serial data input order is LSB-first transfer. The table below shows the various data types and descriptions.

Serial Data Transfer Order

Chip ID Start address Data Data Data …
(8 bit) (8 bit) (8 bit) (8 bit) (8 bit) (8 bit)

Type and Description

Type Description
02h: Write to the Chip ID = 02h register
03h: Write to the Chip ID = 03h register
04h: Write to the Chip ID = 04h register
05h: Write to the Chip ID = 05h register
06h: Write to the Chip ID = 06h register
ChipID
82h: Read from the Chip ID = 02h register
83h: Read from the Chip ID = 03h register
84h: Read from the Chip ID = 04h register
85h: Read from the Chip ID = 05h register
86h: Read from the Chip ID = 06h register
Designate the address according to the Register Map. When using a communication method
Address that designates continuous addresses, the address is automatically incremented from the
previously transmitted address.
Data Input the setting values according to the Register Map.

Register Communication Timing (4-wire)

Perform serial communication in sensor standby mode or within in the 6XHS period after the falling edge of XVS from
the blanking line output start time after valid line of one frame is finished. For the registers marked "V" in the item of
Reflection timing, when the communication is performed in the communication period shown in the figure below they
are reflected by frame reflection timing. For the registers noted “Immediately” in the item of Reflection timing, the
settings are reflected when the communication is performed. (For the immediate reflection registers other than
STANDBY, REGHOLD, XMSTA, SW_RESET, XVSOUTSEL [1:0] and XHSOUTSEL [1:0], set them in sensor
standby state.)

Frame reflection register

reflection timing

Recommended serial communication period Communication prohibited period

XVS
6XHS period
1XHS period
XHS
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line

Data line
Data line
Data line
Data line
Data line
Data line
Data line

Data line
Data line
Data line

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Register Write and Read (4-wire)

Follow the communication procedure below when writing registers.
1. Set XCE Low to enable the chip's communication function. Serial data input is executed using SCK and SDI.
2. Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling edge
of SCK. (The data is loaded at the rising edge of SCK.)
3. Input Chip ID (CID = 02h or 03h or 04h or 05h or 06h) to the first byte. If the Chip ID differs, subsequent data is
ignored.
4. Input the start address to the second byte. The address is automatically incremented.
5. Input the data to the third and subsequent bytes. The data in the third byte is written to the register address
designated by the second byte, and the register address is automatically incremented thereafter when writing
the data for the fourth and subsequent bytes. Normal register data is loaded to the inside of the sensor and
established in 8-bit units.
6. The register values starting from the register address designated by the second byte are output from the SDO
pin. The register values before the write operation are output. The actual register values are the input data.
7. Set XCE High to end communication.

Follow the communication procedure below when reading registers.

1. Set XCE Low to enable the chip's communication function. Serial data input is executed using SCK and SDI.
2. Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling edge
of SCK. (The data is loaded at the rising edge of SCK.)
3. Input Chip ID (CID = 82h or 83h or 84h or 85h or 86h) to the first byte. If the Chip ID differs, subsequent data is
ignored.
4. Input the start address to the second byte. The address is automatically incremented.
5. Input data to the third and subsequent bytes. Input dummy data in order to read the registers. The dummy data
is not written to the registers. To read continuous data, input the necessary number of bytes of dummy data.
6. The register values starting from the register address designated by the second byte are output from the SDO
pin. The input data is not written, so the actual register values are output.
7. Set XCE High to end communication.

Note) When writing data to multiple registers with discontinuous addresses, access to undesired registers
can be avoided by repeating the above procedure multiple times.

XCE
SCK
SDI 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

SDO 0 1 2 3 4 5 6 7

Data established timing

Chip ID Start address N bytes of data

Serial Communication (Continuous Address)

XCE
SCK
SDI 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

SDO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Data established timing

Chip ID Start address N bytes of data Chip ID Start address N bytes of data

Serial Communication (Discontinuous Address)

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Description of Setting Registers (I2C)

The serial data input order is MSB-first transfer. The table below shows the various data types and descriptions.

SCL (shared with SCK)

SDA (shared with SDI)

Master IMX290
OVDD

XCE

Pin connection of serial communication

SLAVE Address
MSB LSB
0 0 1 1 0 1 0 R/W

* R/W is data direction bit

R/W
R / W bit Data direction
0 Write (Master → Sensor)
1 Read (Sensor → Master)

I2C pin description

Symbol Pin No. Remarks
SCL (Common to SCK) G10 Serial clock input
SDA (Common to SDI) H10 Serial data communication

Register Communication Timing (I2C)

In I2C communication system, communication can be performed excluding during the period when communication is
prohibited from the falling edge of XVS to 6H after (1H period). For the registers marked "V" in the item of Reflection
timing, when the communication is performed in the communication period shown in the figure below they are
reflected by frame reflection timing. For the registers noted “Immediately” in the item of Reflection timing, the settings
are reflected when the communication is performed. (For the immediate reflection registers other than STANDBY,
REGHOLD, XMSTA, SW_RESET, XVSOUTSEL [1:0] and XHSOUTSEL [1:0], set them in sensor standby state.)
2
Using REG_HOLD function is recommended for register setting using I C communication. For REG_HOLD function,
see “Register Transmission Setting” in “Description of Functions”.

Frame reflection register

reflection timing
Communication prohibited period
Serial communication period Serial communication period

XVS
6XHS period 6XHS period
1XHS period 1XHS period
XHS
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line

Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Blank line
Data line
Data line
Data line
Data line
Data line

Data line
Data line
Data line
Data line
Data line

Data line
Data line

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Communication Protocol
I2C serial communication supports a 16-bit register address and 8-bit data message type.

Slave R Register Register A

DATA
S Address / A Address A Address A / P
[7:0]
[7:1] W [15:8] [7:0] A

From Master to Slave S : Start Condition R/W=

Sr : Repeated Start Condition 0: Write (Master → Sensor)
From Slave to Master P : Stop Condition
1: Read (Sensor → Master)
A : Acknowledge
Direction depend on operation A : Negative Acknowledge

Communication Protocol

―
Data is transferred serially, MSB first in 8-bit units. After each data byte is transferred, A (Acknowledge) / A
(Negative Acknowledge) is transferred. Data (SDA) is transferred at the clock (SDL) cycle. SDA can change only
while SCL is Low, so the SDA value must be held while SCL is High. The Start condition is defined by SDA changing
from High to Low while SCL is High. When the Stop condition is not generated in the previous communication phase
and Start condition for the next communication is generated, that Start condition is recognized as a Repeated Start
condition.
Start condition MSB LSB
SDA S A7 A6 A5 A4 A3 A2 A1 R/W ACK

SCL

The data changes while the clock is low

Start Condition
Bus free state

ACK/
SDA D5 D4 D3 D2 D1 D0 R/W NACK
P

SCL

Stop condition

Stop Condition

Start condition MSB

ACK/
SDA NACK
Sr A7 A6 A5 A4 A3

SCL

The stop condition is not generated.

Repeated Start Condition

After transfer of each data byte, the Master or the sensor transmits an Acknowledge / Negative Acknowledge and
release (does not drive) SDA. When Negative Acknowledge is generated, the Master must immediately generate the
Stop Condition and end the communication.

SDA A2 A1 R/W ACK

SCL

SDA A2 A1 R/W NACK

SCL

Acknowledge and Negative Acknowledge

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Register Write and Read (I2C)

This sensor corresponds to four reed modes and the two write modes.
Single Read from Random Location
The sensor has an index function that indicates which address it is focusing on. In reading the data at an optional
single address, the Master must set the index value to the address to be read. For this purpose it performs dummy
write operation up to the register address. The upper level of the figure below shows the sensor internal index
value, and the lower level of the figure shows the SDA I/O data flow. The Master sets the sensor index value to M
by designating the sensor slave address with a write request, then designating the address (M). Then, the Master
generates the start condition. The Start Condition is generated without generating the Stop Condition, so it
becomes the Repeated Start Condition. Next, when the Master sends the slave address with a read request, the
sensor outputs an Acknowledge immediately followed by the index address data on SDA. After the Master
receives the data, it generates a Negative Acknowledge and the Stop Condition to end the communication

Index
Previous index value Index M
M+1

Slave Register Register Slave

DATA
S Address 0 A Address A Address A Sr Address 1 A A P
[7:0]
[7:1] [15:8] [7:0] [7:1]

Index, value M
From Master to Slave S : Start Condition A : Acknowledge
Sr : Repeated Start Condition
From Slave to Master P : Stop Condition A : Negative Acknowledge

Single Read from Random Location

Single Read from Current Location

After the slave address is transmitted by a write request, that address is designated by the next communication
and the index holds that value. In addition, when data read/write is performed, the index is incremented by the
subsequent Acknowledge/Negative Acknowledge timing. When the index value is known to indicate the address
to be read, sending the slave address with a read request allows the data to be read immediately after
Acknowledge. After receiving the data, the Master generates a Negative Acknowledge and the Stop Condition to
end the communication, but the index value is incremented, so the data at the next address can be read by
sending the slave address with a read request.

Index Index
Previous index value, K
K+1 K+2

Slave Slave
DATA DATA
S Address 1 A A P S Address 1 A A P
[7:0] [7:0]
[7:1] [7:1]

From Master to Slave S : Start Condition A : Acknowledge

From Slave to Master P : Stop Condition A : Negative Acknowledge

Single Read from Current Location

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Sequential Read Starting from Random Location

In reading data sequentially, which is starting from an optional address, the Master must set the index value to the
start of the addresses to be read. For this purpose, dummy write operation includes the register address setting.
The Master sets the sensor index value to M by designating the sensor slave address with a read request, then
designating the address (M). Then, the Master generates the Repeated Start Condition. Next, when the Master
sends the slave address with a read request, the sensor outputs an Acknowledge followed immediately by the
index address data on SDA. When the Master outputs an Acknowledge after it receives the data, the index value
inside the sensor is incremented and the data at the next address is output on SDA. This allows the Master to read
data sequentially. After reading the necessary data, the Master generates a Negative Acknowledge and the Stop
Condition to end the communication.

Index Index Index

Previous index value, K Index M
M+1 (M+L-1) (M+L)

Slave Register Register Slave

DATA DATA DATA
S Address 0 A Address A Address A Sr Address 1 A A A A A P
[7:0] [7:0] [7:0]
[7:1] [15:8] [7:0] [7:1]

Index, value M L bytes of data

From Master to Slave S : Start Condition A : Acknowledge

Sr : Repeated Start Condition
From Slave to Master P : Stop Condition A : Negative Acknowledge

Sequential Read Starting from Random Location

Sequential Read Starting from Current Location

When the index value is known to indicate the address to be read, sending the slave address with a read request
allows the data to be read immediately after the Acknowledge. When the Master outputs an Acknowledge after it
receives the data, the index value inside the sensor is incremented and the data at the next address is output on
SDA. This allows the Master to read data sequentially. After reading the necessary data, the Master generates a
Negative Acknowledge and the Stop Condition to end the communication.

Index Index Index

Index K
K+1 (K+L-1) (M+L)

Slave
DATA DATA DATA
S Address 1 A A A A A P
[7:0] [7:0] [7:0]
[7:1]

L bytes of data
From Master to Slave S : Start Condition A : Acknowledge

From Slave to Master P : Stop Condition A : Negative Acknowledge

Sequential Read Starting from Current Location

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Single Write to Random Location

The Master sets the sensor index value to M by designating the sensor slave address with a write request, and
designating the address (M). After that the Master can write the value in the designated register by transmitting
the data to be written. After writing the necessary data, the Master generates the Stop Condition to end the
communication.

Index
Previous index value Index M
M+1

Slave Register Register A

DATA
S Address 0 A Address A Address A / P
[7:0]
[7:1] [15:8] [7:0] A

Index, value M

From Master to Slave S : Start Condition A : Acknowledge

From Slave to Master P : Stop Condition A : Negative Acknowledge

Single Write to Random Location

Sequential Write Starting from Random Location

The Master can write a value to register address M by designating the sensor slave address with a write request,
designating the address (M), and then transmitting the data to be written. After the sensor receives the write data,
it outputs an Acknowledge and at the same time increments the register address, so the Master can write to the
next address simply by continuing to transmit data. After the Master writes the necessary number of bytes, it
generates the Stop Condition to end the communication.

Index Index Index

Previous index value Index M
M+1 (M+L-1) (M+L)

Slave Register Register A

DATA DATA DATA
S Address 0 A Address A Address A A A A / P
[7:0] [7:0] [7:0]
[7:1] [15:8] [7:0] A

Index, value M L bytes of data

From Master to Slave S : Start Condition A : Acknowledge

From Slave to Master P : Stop Condition A : Negative Acknowledge

Sequential Write Starting from Random Location

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Register Map

This sensor has a total of 1280 bytes (256 × 5) of registers, composed of registers with addresses 00h to FFh that
correspond to Chip ID = 02h (write mode) / 82h (read mode), Chip ID = 03h (write mode) / 83h (read mode), Chip ID
= 04h (write mode) / 84h (read mode), Chip ID = 05h (write mode) / 85h (read mode), and Chip ID = 06h (write mode)
/ 86h (read mode). Use the initial values for empty address. Some registers must be change from the initial values,
so the sensor control side should be capable of setting 1280 bytes.

The values must be changed from the default value, so initial setting after reset is required after power-on. There are
two different register reflection timing. Values are reflected immediately after writing to register noted as
“Immediately”, or at the frame reflection register reflection timing described in the item of “Register Communication
Timing” in the section of “Setting Registers with Serial Communication” for registers noted as “V” in the Reflection
timing column of the Register Map. For the immediate reflection registers other than belows, set them in sensor
standby state.

STANDBY
REGHOLD
XMSTA
SW_RESET
XVSOUTSEL [1:0]
XHSOUTSEL [1:0]

Do not perform communication to addresses not listed in the Register Map. Doing so may result in operation errors.
However, other registers that requires communication to address not listed above may be added, so addresses up to
FFh should be supported for CID = 02h, 03h, 04h, 05h and 06h. (In I2C communication, address; 3000h to 30FFh,
3100h to 31FFh, 3200h to 32FFh, 3300h to 33FFh, 3400h to 34FFh)

For the register that is writing " * " to the setting value in description (Indicated by red letter), change the value from
the default value after the reset.

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(1) Registers corresponding to Chip ID = 02h in Write mode. (Read: Chip ID = 82h)
Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
Standby
0 STANDBY 1h Immediately
0: Operating 1: Standby
1 Fixed to “0h” 0h ―
2 Fixed to “0h” 0h ―
00h 3000h 3 Fixed to “0h” 0h 01h ―
4 Fixed to “0h” 0h ―
5 Fixed to “0h” 0h ―
6 Fixed to “0h” 0h ―
7 Fixed to “0h” 0h ―
Register hold
(Function not to update V reflection register)
0 REGHOLD 0h Immediately
0: Invalid
1: Valid
1 Fixed to “0h” 0h ―
01h 3001h 2 Fixed to “0h” 0h 00h ―
3 Fixed to “0h” 0h ―
4 Fixed to “0h” 0h ―
5 Fixed to “0h” 0h ―
6 Fixed to “0h” 0h ―
7 Fixed to “0h” 0h ―
Setting of master mode operation
0 XMSTA 0: Master mode operation start 1h Immediately
1: Master mode operation stop
1 Fixed to “0h” 0h ―
2 Fixed to “0h” 0h ―
02h 3002h 01h
3 Fixed to “0h” 0h ―
4 Fixed to “0h” 0h ―
5 Fixed to “0h” 0h ―
6 Fixed to “0h” 0h ―
7 Fixed to “0h” 0h ―
Software reset
0 SW_RESET 0: Operating 0h Immediately
1: Reset
1 Fixed to “0h” 0h ―
2 Fixed to “0h” 0h ―
03h 3003h 00h
3 Fixed to “0h” 0h ―
4 Fixed to “0h” 0h ―
5 Fixed to “0h” 0h ―
6 Fixed to “0h” 0h ―
7 Fixed to “0h” 0h ―
04h 3004h [7:0] Fixed to “10h” 10h 10h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
AD conversion bits setting
0 ADBIT 1h V
0: 10 bit, 1: 12 bit
1 ― Fixed to “0h” 0h ―
2 ― Fixed to “0h” 0h ―
05h 3005h 3 ― Fixed to “0h” 0h 01h ―
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
06h 3006h [7:0] ― Fixed to “00h” 00h 00h V
Vertical (V) direction
0 VREVERSE readout inversion control 0h V
0: Normal, 1: Inverted
Horizontal (H) direction
1 HREVERSE readout inversion control 0h V
0: Normal, 1: Inverted
2 ― Fixed to “0h” 0h ―
07h 3007h 00h
3 ― Fixed to “0h” 0h ―

4 Window mode setting

0: Full HD1080p
5 WINMODE [2:0] 1: HD720p 0h V
4: Window cropping from Full HD 1080p
6
Others: Setting prohibited
7 ― Fixed to “0h” 0h ―
08h 3008h [7:0] ― Fixed to “A0h” A0h A0h ―

0 Frame rate (Data rate) setting

FRSEL [1:0] For details, see the register setting 2h V
1 list in each operation mode.

2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
09h 3009h 02h
Conversion gain switching
4 FDG_SEL 0: LCG Mode 0h V
1: HCG Mode
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
0 LSB
1
2
3
0Ah 300Ah F0h
4 BLKLEVEL [8:0] Black level offset value setting 0F0h V
5
6
7
0 MSB
1 ― Fixed to “0h” 0h ―
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
0Bh 300Bh 00h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
0Ch 300Ch [7:0] ― Fixed to “00h” 00h 00h ―
0Dh 300Dh [7:0] ― Fixed to “00h” 00h 00h ―
0Eh 300Eh [7:0] ― Fixed to “01h” 01h 01h ―
0Fh 300Fh [7:0] ― Set to “00h” * 01h 01h ―
10h 3010h [7:0] ― Set to “21h” * 01h 01h ―
11h 3011h [7:0] ― Fixed to “00h” 00h 00h ―
12h 3012h [7:0] ― Set to “64h” * F0h F0h ―
13h 3013h [7:0] ― Set to “00h” 00h 00h ―
0 LSB
1
2
3 Gain setting
14h 3014h GAIN [7:0] 00h 00h V
4 (0.0 dB to 72.0 dB / 0.3 dB step)
5
6
7 MSB
15h 3015h [7:0] ― Fixed to “00h” 00h 00h ―
16h 3016h [7:0] ― Set to "09h" 08h 08h ―
17h 3017h [7:0] ― Fixed to “00h” 00h 00h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
0 LSB
1
2
3
18h 3018h 65h
4
5
When sensor master mode vertical
6
span setting.
7
(Number of operation lines count from 1)
0
VMAX [17:0] For details, see the item of 0465h V
1
"Slave Mode and Master Mode"
2
in the section of
3
19h 3019h "Description of Various Functions" 04h
4
5
6
7
0
1 MSB
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
1Ah 301Ah 00h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
1Bh 301Bh [7:0] ― Fixed to “00h” 00h 00h ―
0 LSB
1
2
3
1Ch 301Ch 30h
4
When sensor master mode
5
horizontal span setting.
6
(Number of operation clocks count from 1)
7
HMAX [15:0] For details, see the item of 1130h V
0
"Slave Mode and Master Mode
1
" in the section of "Description of
2
Various Functions"
3
1Dh 301Dh 11h
4
5
6
7 MSB
1Eh 301Eh [7:0] ― Fixed to “B2h” B2h B2h ―
1Fh 301Fh [7:0] ― Fixed to “01h” 01h 01h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
0 LSB
1
2
3
20h 3020h 00h
4
5
6
7
0 Storage time adjustment
SHS1 [17:0] 00000h V
1 Designated in line units.
2
3
21h 3021h 00h
4
5
6
7
0
1 MSB
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
22h 3022h 00h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
23h 3023h [7:0]
to to to Reserved ― ― ―
39h 3039h [7:0]
0 LSB
1 In window cropping mode
WINWV_OB [3:0] Cropping size designation Ch
2
(Vertical direction effective OB)
3Ah 303Ah 3 MSB 0Ch V
4 ― Fixed to “0h” 0h
5 ― Fixed to “0h” 0h
6 ― Fixed to “0h” 0h
7 ― Fixed to “0h” 0h
3Bh 303Bh [7:0] ― Fixed to “00h” 00h 00h ―
0 LSB
1
2
3
3Ch 303Ch 00h
4 In window cropping mode
5 WINPV [10:0] Designation of upper left coordinate for 000h V
6 cropping position (Vertical position)
7
0
1
2 MSB
3 ― Fixed to “0h” 0h ―
3Dh 303Dh 00h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
0 LSB
1
2
3
3Eh 303Eh 49h
4 In window cropping mode
5 WINWV [10:0] Cropping size designation 449h V
6 (Vertical direction
7
0
1
2 MSB
3 ― Fixed to “0h” 0h ―
3Fh 303Fh 04h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
0 LSB
1
2
3
40h 3040h In window cropping mode 00h
4
Designation of upper left coordinate for
5 WINPH [10:0] 000h V
cropping position (horizontal position)
6
Set to become the multiple of four
7
0
1
2 MSB
3 ― Fixed to “0h” 0h ―
41h 3041h 00h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
0 LSB
1
2
3
42h 3042h In window cropping mode 9Ch
4
Cropping size designation
5 WINWH [10:0] 79Ch V
(horizontal direction)
6
Set to become the multiple of four
7
0
1
2 MSB
3 ― Fixed to “0h” 0h ―
43h 3043h 07h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
44h 3044h [7:0]
to to to ― Reserved ― ― ―
45h 3045h [7:0]

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
Number of output bit setting
0: 10 bit, 1: 12 bit
0 ODBIT 1h Immediately
* In CSI-2 mode (OMODE = Low),
Fixed to “1h”.
1 ― Fixed to “0h” 0h ―
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
46h 3046h Output interface selection 01h
4
(In CSI-2, don't care. CSI-2 Interface
will be selected by ChipID: 06h register.)
5
0h: Parallel CMOS SDR
OPORTSEL [3:0] 0h Immediately
Dh: LVDS 2 ch
6
Eh: LVDS 4 ch
Fh: LVDS 8 ch
7
Others: Setting prohibited
47h 3047h [7:0] ― Fixed to "01h" 01h 01h ―
0 ― Fixed to “0h” 0h ―
1 ― Fixed to “0h” 0h ―
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
48h 3048h 4 XVS pulse width setting in master mode. 00h
XVSLNG [1:0] (In slave mode, setting is invalid.) 0h Immediately
5 0: 1H, 1: 2H, 2: 4H, 3: 8H
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
0 ― Fixed to “0h” 0h ―
1 ― Fixed to “0h” 0h ―
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “1h” 1h ―
49h 3049h 4 XHS pulse width setting in master mode. 08h
XHSLNG [1:0] (In slave mode, setting is invalid.) 0h Immediately
5 0: Min. to 3: Max.
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
4Ah 304Ah [7:0] ― Fixed to "00h" 00h 00h ―
XVS pin setting in master mode
0
0: Fixed to High
XVSOUTSEL [1:0] 0h Immediately
2: VSYNC output
1
Others: Setting prohibited
XHS pin setting in master mode
2
0: Fixed to High
4Bh 304Bh XHSOUTSEL [1:0] 0h 00h Immediately
2: HSYNC output
3
Others: Setting prohibited
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
4Ch 304Ch [7:0]
to to to ― Reserved ― ― ―
5Bh 305Bh [7:0]
5Ch 305Ch [7:0] INCKSEL1 The value is set according to INCK. 2Ch 2Ch Immediately
5Dh 305Dh [7:0] INCKSEL2 The value is set according to INCK. 10h 10h Immediately
5Eh 305Eh [7:0] INCKSEL3 The value is set according to INCK. 2Ch 2Ch Immediately
5Fh 305Fh [7:0] INCKSEL4 The value is set according to INCK. 10h 10h Immediately
60h 3060h [7:0]
to to to ― Reserved ― ― ―
6Fh 306Fh [7:0]
70h 3070h [7:0] ― Set to "02h" * 01h 01h ―
71h 3071h [7:0] ― Set to "11h" * 00h 00h ―
72h 3072h [7:0]
to to to ― Reserved ― ― ―
9Ah 309Ah [7:0]
9Bh 309Bh [7:0] ― Set to "10h" * 00h 00h ―
9Ch 309Ch [7:0]
to to to ― Reserved ― ― ―
A1h 30A1h [7:0]
A2h 30A2h [7:0] ― Set to "02h" * 00h 00h
A3h 30A3h [7:0]
to to to ― Reserved ― ― ―
A5h 30A5h [7:0]
A6h 30A6h [7:0] ― Set to "20h" * 10h 10h ―
A7h 30A7h [7:0] ― Fixed to “00h” 00h 00h ―
A8h 30A8h [7:0] ― Set to "20h" * 10h 10h ―
A9h 30A9h [7:0] ― Fixed to “00h” 00h 00h ―
AAh 30AAh [7:0] ― Set to "20h" * 10h 10h ―
ABh 30ABh [7:0] ― Fixed to “00h” 00h 00h ―
ACh 30ACh [7:0] ― Set to "20h" * 10h 10h ―
ADh 30ADh [7:0]
to to to ― Reserved ― ― ―
AFh 30AFh [7:0]
B0h 30B0h [7:0] ― Set to "43h" * 41h 41h
B1h 30B1h [7:0]
to to to ― Reserved ― ― ―
FFh 30FFh [7:0]

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(2) Registers corresponding to Chip ID = 03h in Write mode. (Read: Chip ID = 83h)
Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
00h 3100h [7:0]
~ ~ ~ ― Reserved ― ― ―
18h 3118h [7:0]
19h 3119h [7:0] ― Set to "9Eh" * 92h 92h ―
1Ah 311Ah [7:0]
~ ~ ~ ― Reserved ― ― ―
1Bh 311Bh [7:0]
1Ch 311Ch [7:0] ― Set to "1Eh" * 12h 12h ―
1Dh 311Dh [7:0] ― Fixed to “00h” 00h 00h
1Eh 311Eh [7:0] ― Set to "08h" * 05h 05h ―
1Fh 311Fh [7:0]
~ ~ ~ ― Reserved ― ― ―
27h 3127h [7:0]
28h 3128h [7:0] ― Set to "05h" * 07h 07h ―
The value is set according to AD
conversion bits
29h 3129h [7:0] ADBIT1 00h 00h ―
10bit : 1Dh
12bit : 00h
2Ah 312Ah [7:0]
~ ~ ~ ― Reserved ― ― ―
3Ch 313Ch [7:0]
3Dh 313D [7:0] ― Set to "83h" * 80h 80h ―
3Eh 313Eh [7:0]
to to to ― Reserved ― ― ―
4Fh 314Fh [7:0]
50h 3150h [7:0] ― Set to "03h" * 02h 02h ―
51h 3151h [7:0]
to to to ― Reserved ― ― ―
5Dh 315Dh [7:0]
The value is set according to INCK.
5Eh 315Eh [7:0] INCKSEL5 INCK = 74.25 MHz : 1Bh 1Bh 1Bh Immediately
INCK = 37.125 MHz : 1Ah
5Fh 315Fh [7:0]
to to to ― Reserved ― ― ―
63h 3163h [7:0]
The value is set according to INCK.
64h 3164h [7:0] INCKSEL6 INCK = 74.25 MHz : 1Bh 1Bh 1Bh Immediately
INCK = 37.125 MHz : 1Ah
65h 3165h [7:0]
to to to ― Reserved ― ― ―
7Bh 317Bh [7:0]

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
The value is set according to AD
conversion bits
7Ch 317Ch [7:0] ADBIT2 17h 17h ―
10bit : 12h
12bit : 00h
7Dh 317Dh [7:0] ― Fixed to “00h” 00h 00h ―
7Eh 317Eh [7:0] ― Set to "00h" * 17h 17h ―
7Fh 317Fh [7:0]
~ ~ ~ ― Reserved ― ― ―
EBh 31EBh [7:0]
The value is set according to AD
conversion bits
ECh 31ECh [7:0] ADBIT3 0Eh 0Eh
10bit : 37h
12bit : 0Eh
EDh 31EDh [7:0]
~ ~ ~ ― Reserved ― ― ―
FFh 31FFh [7:0]

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(3) Registers corresponding to Chip ID = 04h in Write mode. (Read: Chip ID = 84h)
Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
00h 3200h [7:0]
~ ~ ~ ― Reserved ― ― ―
B7h 32B7h [7:0]
B8h 32B8h [7:0] ― Set to "50h" * 01h 01h ―
B9h 32B9h [7:0] ― Set to "10h" * 00h 00h ―
BAh 32BAh [7:0] ― Set to "00h" * 05h 05h ―
BBh 32BBh [7:0] ― Set to "04h" * 00h 00h ―
BCh 32BCh [7:0]
~ ~ ~ ― Reserved ― ― ―
C7h 32C7h [7:0]
C8h 32C8h [7:0] ― Set to "50h" * 01h 01h ―
C9h 32C9h [7:0] ― Set to "10h" * 00h 00h ―
CAh 32CAh [7:0] ― Set to "00h" * 05h 05h ―
CBh 32CBh [7:0] ― Set to "04h" * 00h 00h ―
CCh 32CCh [7:0]
~ ~ ~ ― Reserved ― ― ―
FFh 32FFh [7:0]

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(4) Registers corresponding to Chip ID = 05h in Write mode. (Read: Chip ID = 85h)
Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
00h 3300h [7:0]
~ ~ ~ ― Reserved ― ― ―
2Bh 332Bh [7:0]
2Ch 332Ch [7:0] ― Set to "D3h" * D1h D1h ―
2Dh 332Dh [7:0] ― Set to "10h" * F0h F0h ―
2Eh 332Eh [7:0] ― Set to "0Dh" * 0Ch 0Ch ―
2Fh 332Fh [7:0]
~ ~ ~ ― Reserved ― ― ―
57h 3357h [7:0]
58 3358h [7:0] ― Set to "06h" * FFh FFh ―
59 3359h [7:0] ― Set to "E1h" * F3h F3h ―
5A 335Ah [7:0] ― Set to "11h" * 3Fh 3Fh ―
5Bh 335Bh [7:0]
~ ~ ~ ― Reserved ― ― ―
5Fh 335Fh [7:0]
60h 3360h [7:0] ― Set to "1Eh" * E0h E0h ―
61h 3361h [7:0] ― Set to "61h" * C0h C0h ―
62h 3362h [7:0] ― Set to "10h" * 0Dh 0Dh ―
63h 3363h [7:0]
~ ~ ~ ― Reserved ― ― ―
AFh 33AFh [7:0]
B0h 33B0h [7:0] ― Set to "50h" * 03h 03h ―
B1h 33B1h [7:0] ― Fixed to "80h" * 80h 80h ―
B2h 33B2h [7:0] ― Set to “1Ah” 00h 00h ―
B3h 33B3h [7:0] ― Set to "04h" * 00h 00h ―
B4h 33B4h [7:0]
~ ~ ~ ― Reserved ― ― ―
FFh 33FFh [7:0]

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(5) Registers corresponding to Chip ID = 06h in Write mode. (Read: Chip ID = 86h)
* These registers are set in CSI-2 interface only.
Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
00h 3400h [7:0]
to to to ― Reserved ― ― ―
04h 3404h [7:0]
0 ― Fixed to “0h” 0h ―
1 ― Fixed to “0h” 0h ―
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
4 * Refer to “Output signal
05h 3405h 20h
REPETITION
Interface Control” 2h Immediately
5 [1:0]
section.
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
06h 3406h [7:0] ― Fixed to “00h” 00h 00h ―
0 PHYSICAL_
Physically connect the Lane number 3h Immediately
1 LANE_NUM [1:0]
2 ― Fixed to “0h” 0h ―
3 ― Fixed to “0h” 0h ―
07h 3407h 03h
4 ― Fixed to “0h” 0h ―
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
08h 3408h [7:0]
to to to ― Reserved ― ― ―
13h 3413h [7:0]
0 LSB
1
2 OPB_SIZE_V Vertical (V) direction OB width setting. *
0Ah Immediately
3 [5:0] Refer to each operating setting.
14h 3414h 0Ah
4
5 MSB
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
15h 3415h [7:0]
to to to ― Reserved ― ― ―
17h 3417h [7:0]
0 LSB
1
2
3
18h 3418h 49h
4
Vertical (V) direction effective
5
Y_OUT_SIZE
6 pixel width setting. 0449h Immediately
[12:0]
7
* Refer to each operating setting.
0
1
2
3
19h 3419h 04h
4 MSB
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
1Ah 341Ah [7:0]
to to to ― Reserved ― ― ―
2Bh 342Bh [7:0]
2Ch 342Ch [7:0] 47h
THSEXIT[15:0] Global timing setting 0047h Immediately
2Dh 342Dh [7:0] 00h
2Eh 342Eh [7:0]
to to to ― Reserved ― ― ―
2Fh 342Fh [7:0]
30h 3430h [7:0] 0Fh
TCLKPRE[8:0] Global timing setting 00Fh
0 Immediately
31h 3431h 00h
[7:1] ― Fixed to “00h” 00h
32h 3432h [7:0]
to to to ― Reserved ― ― ―
40h 3440h [7:0]
LSB
41h 3441h [7:0] 0Ch
CSI_DT_FMT
RAW10: 0A0Ah / RAW12: 0C0Ch 0C0Ch Immediately
[15:0]
42h 3442h [7:0] 0Ch
MSB
Lane number setting
CSI_LANE_ 0: Setting prohibited,
[1:0] MODE 3h
43h 3443h 1: 2Lane, 3: 4Lane 03h Immediately
[1:0]
2: Setting prohibited
[7:2] ― Fixed to “00h” 00h
LSB
44h 3444h [7:0] 40h
Master clock frequency
EXTCK_FREQ 2520h: INCK = 37.125 MHz
4A40h Immediately
[15:0] 4A40h: INCK = 74.25 MHz
45h 3445h [7:0] 4Ah
MSB
46h 3446h [7:0] 47h
TCLKPOST[8:0] Global timing setting 047h
0 Immediately
47h 3447h 00h
[7:1] ― Fixed to “00h” 00h
48h 3448h [7:0] 1Fh
THSZERO[8:0] Global timing setting 01Fh
0 Immediately
49h 3449h 00h
[7:1] ― Fixed to “00h” 00h
4Ah 344Ah [7:0] THSPREPARE 17h
Global timing setting 017h
0 [8:0] Immediately
4Bh 344Bh 00h
[7:1] ― Fixed to “00h” 00h
4Ch 344Ch [7:0] 0Fh
TCLKTRAIL[8:0] Global timing setting 00Fh
0 Immediately
4Dh 344Dh 00h
[7:1] ― Fixed to “00h” 00h
4Eh 344Eh [7:0] 17h
THSTRAIL[8:0] Global timing setting 017h
0 Immediately
4Fh 344Fh 00h
[7:1] ― Fixed to “00h” 00h
50h 3450h [7:0] 47h
TCLKZERO[8:0] Global timing setting 047h
0 Immediately
51h 3451h 00h
[7:1] ― Fixed to “00h” 00h
52h 3452h [7:0] TCLKPREPARE 0Fh
Global timing setting 00Fh
0 [8:0] Immediately
53h 3453h 00h
[7:1] ― Fixed to “00h” 00h

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Default value
Address
Register after reset Reflection
bit Description
2 name By By timing
4-wire IC
register address
54h 3454h [7:0] 0Fh
TLPX[8:0] Global timing setting 00Fh
0 Immediately
55h 3455h 00h
[7:1] ― Fixed to “00h” 00h
56h 3456h [7:0]
to to to ― Reserved ― ― ―
71h 3471h [7:0]
0 LSB
1
2
3
72h 3472h 9Ch
4
Horizontal (H) direction effective
5
X_OUT_SIZE
6 pixel width setting. 079Ch Immediately
[12:0]
7
* Refer to each operating setting.
0
1
2
3
73h 3473h 07h
4 MSB
5 ― Fixed to “0h” 0h ―
6 ― Fixed to “0h” 0h ―
7 ― Fixed to “0h” 0h ―
74h 3474h [7:0]
to to to ― Reserved ― ― ―
FFh 34FFh [7:0]

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Readout Drive mode

The table below lists the operating modes available with this sensor. (N/A: Not supported mode)

Output Data rate

AD Frame
INCK bit Parallel Serial LVDS CSI-2
Window Mode conversion rate
[MHz] width CMOS [Mbps/ch] [Mbps/Lane]
[bit] [frame/s]
[bit] [Mpixel/s] 2 ch 4 ch 8 ch 2 Lane 4 Lane

10/12 10/12 30 / 25 74.25 445.5 222.75 111.375 445.5 222.75

37.125
All pixel 10/12 10/12 60 / 50 N/A N/A 445.5 222.75 891 445.5
74.25
10 10 120/100 N/A N/A N/A 445.5 N/A 891
Full HD
1080p 10/12 10/12 *1 74.25 445.5 222.75 111.375 445.5 222.75
Window 37.125
10/12 10/12 *2 N/A N/A 445.5 222.75 891 445.5
cropping 74.25
10 10 *3 N/A N/A N/A 445.5 N/A 891

10/12 10/12 30 37.125 297 148.5 N/A 297 148.5

37.125
HD720p All-pixel 10/12 10/12 60 74.25 594 297 N/A 594 297
74.25
10 10 120 N/A N/A 594 N/A N/A 594

*1: FRSEL = 2h
*2: FRSEL = 1h
*3: FRSEL = 0h

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Recording
Total number of pixels
pixels
Frame
INCK H [pixels] 1H period
Window Mode rate
[MHz] H V CMOS LVDS LVDS V [µs]
[frame/s]
[pixels] [lines] (10 bit/ CSI-2 CSI-2 [lines]
12 bit) (10 bit) (12 bit)
25 2640 3168 2640 35.6
30 2200 2640 2200 29.6
37.125 50 N/A 3168 2640 17.8
All-pixel 1920 1080 1125
74.25 60 N/A 2640 2200 14.8
100 N/A 3168 N/A 8.9
Full HD 120 N/A 2640 N/A 7.4
1080p
*1 2200 29.6
2200
Window 37.125
*2 *4 *4 N/A 2640 *5 14.8
cropping 74.25
*3 N/A N/A 7.4

25 1980 3168 2640 53.3

30 1650 2640 2200 44.4
37.125 50 1980 3168 2640 26.7
HD720p All-pixel 1280 720 750
74.25 60 1650 2640 2200 22.2
100 N/A 3168 N/A 13.3
120 N/A 2640 N/A 11.1

*1: FRSEL = 2h
*2: FRSEL = 1h
*3: FRFES = 0h
*4: Arbitrary value that was designated to cropping area
*5: Please refer to description of window cropping mode

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Sync code (Parallel CMOS output / Serial LVDS output)

The sync code is added immediately before and after “dummy signal + OB signal + effective pixel data” and then
output. The sync code is output in order of 1st, 2nd, 3rd and 4th. The fixed value is output for 1st to 3rd.
(BLK: Blanking period)

XHS
SAV EAV

System delay
System delay

System delay

H.BLK

H.BLK
DATA
DATA

DATA
DATA
2nd

2nd
3rd

3rd
4th

4th
1st

1st
… ・・・・・・・ …

XVS
System delay V.BLK H.BLK
System delay SAV V.BLK EAV H.BLK
System delay (Invalid line) (Invalid line) H.BLK

…
System delay V.BLK H.BLK
System delay Frame information line H.BLK
System delay H.OB/V.OB H.BLK
…

…
System delay H.OB/V.OB H.BLK
System delay SAV H.OB / effective pixel EAV H.BLK
System delay (Valid line) H.OB / effective pixel (Valid line) H.BLK
…

…
System delay H.OB / effective pixel H.BLK
System delay V.BLK H.BLK
…

…
System delay V.BLK H.BLK
SAV EAV
System delay V.BLK H.BLK
(Invalid line) (Invalid line)
System delay V.BLK H.BLK
…

System delay V.BLK H.BLK

System delay SAV Frame information line EAV H.BLK
System delay (Valid line) H.OB/V.OB (Valid line) H.BLK

Sync Code Output Timing

List of Sync Code

1st code 2nd code 3rd code 4th code
Sync code
10 bit 12 bit 10 bit 12 bit 10 bit 12 bit 10 bit 12 bit
SAV (Valid line) 3FFh FFFh 000h 000h 000h 000h 200h 800h
EAV (Valid line) 3FFh FFFh 000h 000h 000h 000h 274h 9D0h
SAV (Invalid line) 3FFh FFFh 000h 000h 000h 000h 2ACh AB0h
EAV (Invalid line) 3FFh FFFh 000h 000h 000h 000h 2D8h B60h

(Note 1) 10 bit is the value output to the DLOP/M [C:G] when the register ODBIT = 0 in parallel output.
(Note 2) 12 bit is the value output to the DLOP/M [B:G] when the register ODBIT = 1 in parallel output.
(Note 3) They are output to each channel seriously in MSB first when low-voltage LVDS serial.
For details, see the item of "Signal output" and "Output pin setting".

Sync Code Output Timing

The sensor output signal passes through the internal circuits and is output with a latency time (system delay)
relative to the horizontal sync signal. This system delay value is undefined for each line, so refer to the sync
codes output from the sensor and perform synchronization.

XHS

System Delay
EAV

SAV

EAV

SAV

DO DATA DATA

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Image Data Output Format (CSI-2 output)

Frame Format
Each line of each image frame is output like the General Frame Format of CSI-2. The settings for each packet
header are shown below.

DATA Type
Setting register
Header [5:0] Name Description
(I2C)
00h Frame Start Code N/A FS
01h Frame End Code N/A FE
10h NULL N/A Invalid data
12h Embedded Data N/A Embedded data
2Bh RAW10 Address: 41h, 42h 0A0Ah
(3441h, 3442h)
2Ch RAW12 CSI_DT_FMT [15:0] 0C0Ch
37h OB Data N/A Vertical OB line data

Frame Structure

FS
Embedded Data Line (EBD)

RG RG
GB GB
Packet Header

Packet Footer

Recording pixel area Line Blanking

(OB, effective pixels, color processing margin)

RG RG
GB GB
FE
Frame Blanking

FS Next Frame
Embedded Data Line (EBD)

Frame Structure of CSI-2 output

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Embedded Data Line

The Embedded data line is output in a line following the sync code FS.

Embedded Data Format

Packet Header 0Ah Tag Data Tag Data Tag Data Tag Data Tag Data 07h 07h Packet Footer

RAW10 (CSI_DT_FMT = 0A0Ah)

Packet Header 0Ah Tag Data Tag 55h Data Tag Data Tag 55h Data Tag Data 07h 55h Packet Footer

RAW12 (CSI_DT_FMT = 0C0Ch)

Packet Header 0Ah Tag 55h Data Tag 55h Data Tag 55h Data Tag 55h Data 07h 55h Packet Footer

The end of the address and the register value is determined according to the tags embedded in the data.

Embedded Data Line Tag

Tag Data Byte Description

00h Illegal Tag. If found treat as end of Data.
07h End of Data.
AAh CCI Register Index MSB [15:8]
A5h CCI Register Index LSB [7:0]
Auto increment the CCI index after the data byte – valid data
5Ah
Data byte contains valid CCI register data.
Auto increment the CCI index after the data byte – null data
55h A CCI register does not exist for the current CCI index.
The data byte value is the 07h.
FFh Illegal Tag. If found treat as end of Data.

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Specific output examples are shown below. (4-wire: Chip ID = 05h)

Address Address
Pixel [HEX] Data Byte Description Value Pixel [HEX] Data Byte Description Value
2 2
4-wire IC 4-wire IC
1 - Data Format 0Ah 58 5Ah
2 AAh 59 A0h 34A0h Fixed to "01h" 01h
CCI Register Index MSB
3 33h 60 5Ah
[15:8]
4 A5h 61 A1h 34A1h Fixed to "00h" 00h
CCI Register Index LSB
5 95h 62 5Ah
[7:0]
6 5Ah 63 A2h 34A2h Fixed to "64h" 64h
7 89h 3489h Fixed to “00h” 00h 64 5Ah
8 REGHOLD value 5Ah 65 A3h 34A3h Fixed to “00h” 00h
9 8Ah 348Ah [0]* 66 5Ah
10 5Ah 67 A4h 34A4h Fixed to "F0h" F0h
11 8Bh 348Bh Fixed to “00h” 00h 68 5Ah
12 5Ah 69 A5h 34A5h Fixed to “00h” 00h
13 8Ch 348Ch Fixed to “00h” 00h 70 5Ah
14 5Ah 71 A6h 34A6h Fixed to "F0h" F0h
15 8Eh 348Eh Fixed to "90h" 90h 72 5Ah
16 5Ah 73 A7h 34A7h Fixed to “00h” 00h
17 8Fh 348Fh Fixed to "02h" 02h 74 5Ah
18 5Ah 75 A8h 34A8h [7:0]*
Gain Setting Value
19 8Dh 348Dh Fixed to "01h" 01h 76 5Ah
20 5Ah 77 A9h 34A9h [15:8]*
21 90h 3490h Fixed to "01h" 01h 78 5Ah
22 5Ah 79 AAh 34AAh Fixed to “00h” 00h
Frame count
23 91h 3491h [7:0]* 80 5Ah
24 5Ah 81 ABh 34ABh Fixed to “00h” 00h
25 B0h 34B0h Fixed to "01h" 01h 82 5Ah
26 Black level setting value 5Ah 83 ACh 34ACh Fixed to “00h” 00h
27 92h 3492h [7:0]* 84 5Ah
28 5Ah 85 ADh 34ADh Fixed to “00h” 00h
29 93h 3493h [15:8]* 86 Shutter setting value 5Ah
30 Data format 5Ah 87 B1h 34B1h [7:0]*
31 94h 3494h RAW10: 0A0Ah [7:0]* 88 5Ah
32 RAW12: 0C0Ch 5Ah 89 B2h 34B2h [15:8]*
33 95h 3495h [15:8]* 90 5Ah
34 5Ah 91 B3h 34B3h [23:16]*
35 B4h 34B4h Fixed to “00h” 00h 92 5Ah
36 5Ah 93 B5h 34B5h Fixed to “00h” 00h
37 96h 3496h Fixed to “00h” 00h 94 5Ah
38 5Ah 95 B6h 34B6h Fixed to “00h” 00h
39 97h 3497h Fixed to “00h” 00h 96 5Ah
40 5Ah 97 B7h 34B7h Fixed to “00h” 00h
41 98h 3498h Fixed to "2Ch" 2Ch 98 5Ah
42 5Ah 99 B9h 34B9h Fixed to “00h” 00h
43 99h 3499h Fixed to "01h" 01h 100 5Ah
44 5Ah 101 BAh 34BAh Fixed to “00h” 00h
45 9Ah 349Ah Fixed to "03h" 03h 102 5Ah
46 5Ah 103 BBh 34BBh Fixed to “00h” 00h
47 9Bh 349Bh Fixed to “00h” 00h 104 5Ah
48 5Ah 105 BDh 34BDh Fixed to “00h” 00h
49 B8h 34B8h Fixed to “00h” 00h 106 5Ah
50 5Ah 107 BEh 34BEh Fixed to “00h” 00h
51 9Ch 349Ch Fixed to “00h” 00h 108 5Ah
52 5Ah 109 BFh 34BFh Fixed to “00h” 00h
53 9Dh 349Dh Fixed to “00h” 00h 110 5Ah
54 5Ah 111 C1h 34C1h Fixed to “00h” 00h
55 9Eh 349Eh Fixed to "A4h" A4h 112 5Ah
56 5Ah 113 C2h 34C2h Fixed to “00h” 00h
57 9Fh 349Fh Fixed to "01h" 01h 114 5Ah
115 C3h 34C3h Fixed to “00h” 00h

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Address Address
Pixel [HEX] Data Byte Description Value Pixel [HEX] Data Byte Description Value
2 2
4-wire IC 4-wire IC
116 5Ah 174 5Ah
117 C5h 34C5h Fixed to “00h” 00h 175 DFh 34DFh Fixed to "07h" 07h
118 5Ah 176 5Ah
119 C6h 34C6h Fixed to “00h” 00h 177 E0h 34E0h Fixed to "54h" 54h
120 5Ah 178 5Ah
121 C7h 34C7h Fixed to “00h” 00h 179 E1h 34E1h Fixed to "04h" 04h
122 5Ah 180 5Ah
123 AEh 34AEh Fixed to “00h” 00h 181 E2h 34E2h Fixed to "60h" 60h
124 5Ah 182 5Ah
125 AFh 34AFh Fixed to “00h” 00h 183 E3h 34E3h Fixed to "01h" 01h
126 Vertical line value 5Ah 184 5Ah
127 C9h 34C9h (VMAX) [7:0]* 185 E4h 34E4h Fixed to "20h" 20h
128 5Ah 186 5Ah
129 CAh 34CAh [15:8]* 187 E5h 34E5h Fixed to "01h" 01h
130 5Ah 188 5Ah
131 CBh 34CBh [23:16]* 189 E6h 34E6h Fixed to "9Ch" 9Ch
132 Horizontal clock value 5Ah 190 5Ah
133 CCh 34CCh (HMAX) [7:0]* 191 E7h 34E7h Fixed to "07h" 07h
134 5Ah 192 5Ah
135 CDh 34CDh [15:8]* 193 E8h 34E8h Fixed to "55h" 55h
136 5Ah 194 5Ah
137 CEh 34CEh Fixed to “00h” 00h 195 E9h 34E9h Fixed to "04h" 04h
138 5Ah 196 5Ah
139 CFh 34CFh Fixed to “00h” 00h 197 C4h 34C4h Fixed to "01h" 01h
140 5Ah 198 5Ah
Number of lane
141 D0h 34D0h Fixed to “00h” 00h 199 C8h 34C8h [1:0]*
142 5Ah 200 5Ah
143 D1h 34D1h Fixed to “00h” 00h 201 EAh 34EAh Fixed to “00h” 00h
144 5Ah 202 5Ah
145 D2h 34D2h Fixed to "9Bh" 9Bh 203 EBh 34EBh Fixed to “00h” 00h
146 5Ah 204 5Ah
147 D3h 34D3h Fixed to "07h" 07h 205 ECh 34ECh Fixed to "0Bh" 0Bh
148 5Ah 206 5Ah
149 D4h 34D4h Fixed to "48h" 48h 207 EDh 34EDh Fixed to “00h” 00h
150 5Ah 208 5Ah
151 D5h 34D5h Fixed to "04h" 04h 209 EEh 34EEh Fixed to "0Ch" 0Ch
152 5Ah 210 5Ah
153 D6h 34D6h Fixed to "9Ch" 9Ch 211 EFh 34EFh Fixed to “00h” 00h
154 5Ah 212 5Ah
155 D7h 34D7h Fixed to "07h" 07h 213 F0h 34F0h Fixed to “00h” 00h
156 5Ah 214 5Ah
157 D8h 34D8h Fixed to "49h" 49h 215 F1h 34F1h Fixed to “00h” 00h
158 5Ah 216 5Ah
159 D9h 34D9h Fixed to "04h" 04h 217 F2h 34F2h Fixed to "0Bh" 0Bh
160 5Ah 218 5Ah
161 BCh 34BCh Fixed to “00h” 00h 219 F3h 34F3h Fixed to “00h” 00h
162 5Ah 220 5Ah
163 C0h 34C0h Fixed to “00h” 00h 221 F4h 34F4h Fixed to "06h" 06h
164 5Ah 222 5Ah
165 DAh 34DAh Fixed to “00h” 00h 223 F5h 34F5h Fixed to “00h” 00h
166 5Ah 224 5Ah
167 DBh 34DBh Fixed to “00h” 00h 225 F6h 34F6h Fixed to "0Ch" 0Ch
168 5Ah 226 5Ah
169 DCh 34DCh Fixed to “00h” 00h 227 F7h 34F7h Fixed to “00h” 00h
170 5Ah 228 07h
171 DDh 34DDh Fixed to “00h” 00h 229 07h
172 5Ah 230 07h
173 DEh 34DEh Fixed to "9Bh" 9Bh * The value that shown in Data Byte Description is output.

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Image Data Output Format

All-pixel scan mode (Full HD 1080p)
List of Setting Register for CMOS parallel / LVDS serial output
Address Initial CMOS LVDS serial
2
bit Register Name Remarks
4-wire IC Value parallel 2 ch 4 ch 8 ch
Chip ID: 02h
05h 3005h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
[0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
07h 3007h [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
[6:4] WINMODE 0h 0h Full HD 1080p
2h 30 / 25 [frame/s]
[1:0] FRSEL 2h N/A N/A 1h 60 / 50 [frame/s]
09h 3009h
N/A N/A N/A 0h 120 / 100 [frame/s]
[4] FDG_SEL 0h 0h / 1h 0: LCG mode, 1: HCG mode
12h 3012h [7:0] ― F0h 64h Initial setting
13h 3013h [7:0] ― 00h 00h Initial setting
18h 3018h [7:0]
19h 3019h [7:0] VMAX 465h 465h 25 /30 / 50 / 60 / 100 / 120 [frame/s]
1Ah 301Ah [1:0]
1130h : 30[frame/s] /
1Ch 301Ch [7:0] 1130h / 14A0h
14A0h : 25[frame/s]
0898h : 60[frame/s] /
HMAX 1130h N/A N/A 0898h / 0A50h
0A50h : 50[frame/s]
1Dh 301Dh [7:0]
044Ch / 044Ch : 120[frame/s] /
N/A N/A N/A
0528h 0528h : 100[frame/s]
[1:0] ODBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
46h 3046h
[7:4] OPORTSEL 0h 0h Dh Eh Fh I/F selection
5Ch 305Ch [7:0] INCKSEL1 0Ch 0Ch / 18h
5Dh 305Dh [7:0] INCKSEL2 00h 00h / 00h Set according to INCK
5Eh 305Eh [7:0] INCKSEL3 10h 10h / 20h 74.25 / 37.125 MHz
5Fh 305Fh [7:0] INCKSEL4 01h 01h / 10h
Chip ID = 03h
10bit : 1Dh
29h 3129h [7:0] ADBIT1 00h 1Dh / 00h
12bit : 00h
5Eh 315Eh [7:0] INCKSEL5 1Bh 1Bh / 1Ah INCK :74.25 / 37.125 MHz
64h 3164h [7:0] INCKSEL6 1Bh 1Bh / 1Ah INCK : 74.25 / 37.125 MHz
10bit : 12h
7Ch 317Ch [7:0] ADBIT2 17h 12h / 00h
12bit : 00h
10bit :37h
ECh 31ECh [7:0] ADBIT3 0Eh 37h / 0Eh
12bit : 0Eh
Chip ID = 04h
00h 3200h [7:0]
to to to Set register value that described on item “Register map”.
FFh 32FFh [7:0]
ChipID = 05h
00h 3300h [7:0]
to to to Set register value that described on item “Register map”.
FFh 33FFh [7:0]
ChipID = 06h
00h 3400h [7:0]
to to to Changing the value is not necessary.
FFh 34FFh [7:0]

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List of Setting Register for CSI-2 serial output

CSI-2 serial
Address
Register Initial 2 lane 4 lane
bit Remarks
2 Name Value 30 / 25 60 / 50 30 / 25 60 / 50 120 / 100
4-wire IC
[frame /s] [frame /s] [frame /s] [frame /s] [frame /s]
Chip ID: 02h
05h 3005h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
[0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
07h 3007h [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
[6:4] WINMODE 0h 0h Full HD 1080p
[1:0] FRSEL 2h 2h 1h 2h 1h 0h
09h 3009h 0: LCG mode,
[4] FDG_SEL 0h 0h / 1h
1: HCG mode
12h 3012h [7:0] ― F0h 64h Initial setting
13h 3013h [7:0] ― 00h 00h Initial setting
18h 3018h [7:0]
25 /30 / 50 / 60 / 100 /
19h 3019h [7:0] VMAX 465h 465h
120 [frame/s]
1Ah 301Ah [1:0]
1Ch 301Bh [7:0] 1130h / 0898h / 1130h / 0898h / 044Ch / 30 / 60 /120 [frame / s] /
HMAX 1130h
1Dh 301Ch [7:0] 14A0h 0A50h 14A0h 0A50h 0528h 25 / 50 /100 [frame / s]
[1:0] ODBIT 1h 1h In CSI-2, fixed to “1h”.
46h 3046h
[7:4] OPORTSEL 0h 0h In CSI-2, fixed to “0h”.
5Ch 305Ch [7:0] INCKSEL1 0Ch 0Ch / 18h
5Dh 305Dh [7:0] INCKSEL2 00h 03h / 03h Set according to INCK
5Eh 305Eh [7:0] INCKSEL3 10h 10h / 20h 74.25 / 37.125 MHz
5Fh 305Fh [7:0] INCKSEL4 01h 01h / 01h
Chip ID = 03h
10bit : 1Dh
29h 3129h [7:0] ADBIT1 00h 1Dh / 00h
12bit : 00h
Set according to INCK
5Eh 315Eh [7:0] INCKSEL5 1Bh 1Bh / 1Ah
74.25 / 37.125 MHz
Set according to INCK
64h 3164h [7:0] INCKSEL6 1Bh 1Bh / 1Ah
74.25 / 37.125 MHz
10bit : 12h
7Ch 317Ch [7:0] ADBIT2 17h 12h / 00h
12bit : 00h
10bit :37h
ECh 31ECh [7:0] ADBIT3 0Eh 37h / 0Eh
12bit : 0Eh
Chip ID = 04h
00h 3200h [7:0]
to to to Set register value that described on item “Register map”.
FFh 32FFh [7:0]
Chip ID = 05h
00h 3300h [7:0]
to to to Set register value that described on item “Register map”.
FFh 33FFh [7:0]

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CSI-2 serial
Address
Register Initial 2 lane 4 lane
bit Remarks
2 Name Value 30 / 25 60 / 50 30 / 25 60 / 50 120 / 100
4-wire IC
[frame /s] [frame /s] [frame /s] [frame /s] [frame /s]
Chip ID = 06h
Data rate 445.5 891 222.75 445.5 891 [Mbps / Lane]
05h 3405h [5:4] REPETITION 2h 1h 0h 2h 1h 0h
PHYSICAL_
07h 3407h [1:0] 3h 1h 3h
LANE_NUM
14h 3414h [5:0] OPB_SIZE_V Ah Ah
18h 3418h [7:0]
Y_OUT_SIZE 0449h 0449h
19h 3419h [4:0]
41h 3441h [7:0] 0A0Ah: RAW10
CSI_DT_FMT 0C0Ch 0A0Ah / 0C0Ch
42h 3442h [7:0] 0C0Ch: RAW12
CSI_LANE_
43h 3443h [1:0] 3h 1h 3h
MODE

44h 3444h [7:0]

37.125 MHz: 2520h
EXTCK_FREQ 4A40h Set according to INCK
74.25 MHz: 4A40h
45h 3445h [7:0]

46h 3446h [7:0]

TCLKPOST 047h 057h 077h 047h 057h 077h Global timing
47h 3447h [0]
48h 3448h [7:0]
THSZERO 01Fh 037h 067h 01Fh 037h 067h Global timing
49h 3449h [0]
4Ah 344Ah [7:0]
THSPREPARE 017h 01Fh 047h 017h 01Fh 047h Global timing
4Bh 344Bh [0]
4Ch 344Ch [7:0]
TCLKTRAIL 00Fh 01Fh 037h 00Fh 01Fh 037h Global timing
4Dh 344Dh [0]
4Eh 344Eh [7:0]
THSTRAIL 017h 01Fh 03Fh 017h 01Fh 03Fh Global timing
4Fh 344Fh [0]
50h 3450h [7:0]
TCLKZERO 047h 077h 0FFh 047h 077h 0FFh Global timing
51h 3451h [0]
52h 3452h [7:0] TCLKPREPAR
00Fh 01Fh 03Fh 00Fh 01Fh 03Fh Global timing
53h 3453h [0] E
54h 3454h [7:0]
TLPX 00Fh 017h 037h 00Fh 017h 037h Global timing
55h 3455h [0]

72h 3472h [7:0]

X_OUT_SIZE 079Ch 079Ch
73h 3473h [4:0]

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8 Vertical blanking period

1 Frame information line

XVS 2 Ignored OB
10 Vertical effective OB
RG RG GR GR
GB GB 8 Effective margin for color processing BG BG
RG RG
Vertical scan direction (Normal)

GB GB
Number of recommended

Ignored area of effective

Ignored area of effective

recording pixels: 1920 (H) × 1080 (V) = 2.07 M pixel
Number of active pixels: 1937 (H) × 1097 (V) = 2.12 M pixel

for color processing

for color processing

Horizontal blanking

Horizontal blanking
Number of effective pixels: 1945 (H) × 1097 (V) = 2.13 M pixel

Horizontal dummy
Total number of pixels: 1945 (H) × 1109 (V) = 2.16 M pixel

Effective margin

Effective margin
Sync code

Sync code
pixel side

pixel side
1080
Recording pixel area

SD 4 4 8 1920 9 4 3 4 HB

RG RG
GB GB
GB GB BG BG
RG RG 9 Effective margin for color processing GR GR
VB Vertical blanking

Horizontal scan direction (Normal)

XHS

Pixel Array Image Drawing in Full HD 1080p mode (Parallel CMOS output / Serial LVDS output)

XVS

XHS

Line No. during

1 2 3 12 13 20 21 1100 1101 1109
normal operation
Line No. during
1 2 3 12 1109 1102 1101 22 21 13
inverted operation
8 1 2 10 8 1080 9 VB
30 frame/s: 7 [lines]
25 frame/s: 232 [lines]

XHS

CMOS DLCKP(SDR)

DO during horizontal
1 4 5 12 13 1932 1933 1941 1942 1945
normal operation
DO during horizontal
1945 1942 1941 1934 1933 14 13 5 4 1
inverted operation
4 4 8 1920 9 4 3 4
SD HB

: Frame information line : Sync code

: Ineffective OB / Blanking : Effective pixel side ignored area
: Effective OB : Margin for color processing
: Dummy area : Recording pixel area

SD : System delay
HB : Horizontal blanking

Drive Timing Chart for Full HD 1080p mode (Parallel CMOS output)

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XVS

XHS

Line No. during

1 2 3 12 13 20 21 1100 1101 1109
normal operation
Line No. during
1 2 3 12 1109 1102 1101 22 21 13
inverted operation
8 1 2 10 8 1080 9 VB
30, 60, 120frame/s: 7 [lines]
25, 50, 100frame/s: 232 [lines]

CH1 / DLOP/M D
2ch output

1 3 5 11 13 1931 1933 1939 1941 1943 1945

Normal 2 4 6 12 14 1932 1934 1940 1942 1944
CH2 / DLOP/M E
CH1 / DLOP/M D 1945 1943 1941 1935 1933 15 13 7 5 3 1
Inverted 1944 1942 1940 1934 1932 14 12 6 4 2
CH2 / DLOP/M E
4 2 4 960 4 2 2 4
HB HB
982 DATA

CH1 / DLOP/M D 1 5 9 13 1929 1933 1937 1941 1945

Normal CH2 / DLOP/M E 2 6 10 14 1930 1934 1938 1942

4ch output

CH3 / DLOP/M C 3 7 11 15 1931 1935 1939 1943

CH4 / DLOP/M F 4 8 12 16 1932 1936 1940 1944

CH1 / DLOP/M D 1945 1941 1937 1933 17 13 9 5 1

Inverted CH2 / DLOP/M E

1944 1940 1936 1932 16 12 8 4
CH3 / DLOP/M C 1943 1939 1935 1931 15 11 7 3
CH4 / DLOP/M F 1942 1938 1934 1930 14 10 6 2

HB 4 1 2 480 2 1 1 4
HB
495 DATA

CH1 / DLOP/M D 1 9 17 1921 1929 1937 1945

CH2 / DLOP/M E 2 10 18 1922 1930 1938
CH3 / DLOP/M C 3 11 19 1923 1931 1939
CH4 / DLOP/M F 4 12 20 1924 1932 1940
Normal CH5 / DLOP/M B 5 13 21 1925 1933 1941
CH6 / DLOP/M G 6 14 22 1926 1934 1942
CH7 / DLOP/M A 7 15 23 1927 1935 1943
8ch output

CH8 / DLOP/M H 8 16 24 1928 1936 1944

CH1 / DLOP/M D 1945 1937 1929 25 17 9 1

CH2 / DLOP/M E 1944 1936 1928 24 16 8
CH3 / DLOP/M C 1943 1935 1927 23 15 7
CH4 / DLOP/M F 1942 1934 1926 22 14 6
Inverted CH5 / DLOP/M B 1941 1933 1925 21 13 5
CH6 / DLOP/M G 1940 1932 1924 20 12 4
CH7 / DLOP/M A 1939 1931 1923 19 11 3
CH8 / DLOP/M H 1938 1930 1922 18 10 2

HB 4 244 4 HB
252 DATA

DLCK (DDR)
: Frame information line : Sync code
: Ineffective OB / Blanking : Effective pixel side ignored area
1st [9]

1st [8]

1st [7]

1st [6]

1st [5]

1st [4]

1st [3]

1st [2]

1st [1]

1st [0]

10 bit CHx
SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

Output (x = 1-8) : Effective OB : Margin for color processing

: Dummy area : Recording pixel area

DLCK (DDR) HB : Horizontal blanking

1st [11]

1st [10]

1st [9]

1st [8]

1st [7]

1st [6]

1st [5]

1st [4]

1st [3]

1st [2]

1st [1]

1st [0]

12 bit CHx
SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

Output (x = 1-8)

Drive Timing Chart for Full HD 1080p mode (Serial LVDS output)

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FS 1
PH 1 EBD(Embedded data) PF
PH 1 NULL 0 PF
10 Vertical effective OB
RG RG GR GR
GB GB 8 Effective margin for color processing BG BG
RG RG
GB GB
Ignored area of effective

Ignored area of effective

for color processing

for color processing

Horizontal blanking
Horizontal dummy
Effective margin

Effective margin
PH PF
pixel side

pixel side
1080
Recording pixel area

4 8 1920 9 4 3 HB

RG RG
GB GB
GB GB BG BG
RG RG 9 Effective margin for color processing GR GR
FE
VB Vertical blanking

Pixel Array Image Drawing in Full HD 1080p mode (CSI-2 serial output)

XVS

XHS

Line No. during

3 12 13 20 21 1100 1101 1109
normal operation
Line No. during
3 12 1109 1102 1101 22 21 13
inverted operation
8 1 1 1 10 8 1080 9 1 VB
30, 60, 120frame/s: 6 [lines]
25, 50, 100frame/s: 231 [lines]

Horizontal pixel output image

1 4 5 12 13 1932 1933 1941 1942 1945
normal operation
Horizontal pixel output image
1945 1942 1941 1934 1933 14 13 5 4 1
inverted operation
4 8 1920 9 4 3
HB
* It outputs in the format of RAW10 or RAW12.

: FS / FE : Packet header / Packet footer

: NULL : Effective pixel side ignored area
: Embedded data : Margin for color processing
: Ineffective OB / Blanking : Recording pixel area
: Effective OB : Dummy area
HB : Horizontal blanking

Drive Timing Chart for Full HD 1080p mode (CSI-2 serial output)

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Window Cropping Mode

Sensor signals are cut out and read out in arbitrary positions.
Cropping position is set, regarding effective pixel start position as origin (0, 0) in all pixel scan mode. Cropping is
available from all-pixel scan mode and vertical, horizontal period and frame rate are fixed to the value for this
mode. Pixels cropped by horizontal cropping setting are output with left justified and that extends the horizontal
blanking period.
Window cropping image is shown in the figure below.
Cropping position is set, regarding effective pixel start position as origin (0, 0) in all pixel scan mode.
Only vertical width can be set for OB (horizontal width is the same as the Window cropping width).

2 Ignored OB
WINWV_OB
WINWV_OB - 2 Vertical effective OB
RG
GB
(WINPH, WINPV) = (0, 0)

RG RG
Vertical scan direction (Normal)

GB GB
(WINPH, WINPV)

Horizontal dummy
WINWV

WINWH
3
RG RG
GB GB

VB Vertical blanking

Horizontal scan direction (Normal)

Image Drawing of Window Cropping Mode

Restrictions on Window cropping mode

The register settings should satisfy following conditions:

WINPH + WINWH ≤ 1944

368 ≤ WINWH
Set WINPH and WINWH to a multiple of 4.

VTTL (Number of lines per frame or VMAX) ≥ WINWV_OB + WINWV + 13

However,
6 ≤ WINWV_OB ≤ 12
WINPV + WINWV ≤ 1096
304 ≤ WINWV
OB_SIZE_V = WINWV_OB - 2 (In CSI-2 output)
Y_OUT_SIZE = WINWV (In CSI-2 output)

Frame rate on Window cropping mode

Frame rate [frame/s] = 1 / (VTTL × (1H period))

1H period (unit: [µs]) : Fix 1H time in a mode before cropping and calculate it by the value of "Number of INCK in
1H" in the table of "Operating Mode" and "List of Operation Modes and Output Rates".

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List of Setting Register for CMOS parallel / LVDS serial output

Address Initial CMOS LVDS serial
2
bit Register Name Remarks
4-wire IC Value parallel 2 ch 4 ch 8 ch
Chip ID: 02h
05h 3005h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
[0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
07h 3007h [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
[6:4] WINMODE 0h 4h Window cropping
2h
[1:0] FRSEL 2h N/A N/A 1h
09h 3009h
N/A N/A N/A 0h
[4] FDG_SEL 0h 0h / 1h 0: LCG mode, 1: HCG mode
12h 3012h [7:0] ― F0h 64h Initial setting
13h 3013h [7:0] ― 00h 00h Initial setting
18h 3018h [7:0]
19h 3019h [7:0] VMAX 465h VTTL See previous page.
1Ah 301Ah [1:0]
1130h : 30[frame/s] /
1Ch 301Ch [7:0] 1130h / 14A0h
14A0h : 25[frame/s]
0898h : 60[frame/s] /
HMAX 1130h N/A N/A 0898h / 0A50h
0A50h : 50[frame/s]
1Dh 301Dh [7:0]
044Ch / 044Ch : 120[frame/s] /
N/A N/A N/A
0528h 0528h : 100[frame/s]
[1:0] ODBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
46h 3046h
[7:4] OPORTSEL 0h 0h Dh Eh Fh I/F selection
5Ch 305Ch [7:0] INCKSEL1 0Ch 0Ch / 18h
5Dh 305Dh [7:0] INCKSEL2 00h 00h / 00h Set according to INCK
5Eh 305Eh [7:0] INCKSEL3 10h 10h / 20h 74.25/37.125 MHz
5Fh 305Fh [7:0] INCKSEL4 01h 01h / 01h
Chip ID = 03h
10bit : 1Dh
29h 3129h [7:0] ADBIT1 00h 1Dh / 00h
12bit : 00h
5Eh 315Eh [7:0] INCKSEL5 1Bh 1Bh / 1Ah INCK : 74.25 / 37.125 MHz
64h 3164h [7:0] INCKSEL6 1Bh 1Bh / 1Ah INCK : 74.25 / 37.125 MHz
10bit : 12h
7Ch 317Ch [7:0] ADBIT2 17h 12h / 00h
12bit : 00h
10bit :37h
ECh 31ECh [7:0] ADBIT3 0Eh 37h / 0Eh
12bit : 0Eh
Chip ID = 04h
00h 3200h [7:0]
to to to Set register value that described on item “Register map”.
FFh 32FFh [7:0]
ChipID = 05h
00h 3300h [7:0]
to to to Set register value that described on item “Register map”.
FFh 33FFh [7:0]
ChipID = 06h
00h 3400h [7:0]
to to to Changing the value is not necessary.
FFh 34FFh [7:0]

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List of Setting Register for CSI-2 serial output

CSI-2 serial
Address
Register Initial 2 lane 4 lane
bit Remarks
2 Name Value *1 *2 *1 *2 *3
4-wire IC
[frame /s] [frame /s] [frame /s] [frame /s] [frame /s]
Chip ID: 02h
05h 3005h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
[0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
07h 3007h [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
[6:4] WINMODE 0h 4h Window cropping
[1:0] FRSEL 2h 2h 1h 2h 1h 0h
09h 3009h 0: LCG mode,
[4] FDG_SEL 0h 0h / 1h
1: HCG mode
12h 3012h [7:0] ― F0h 64h Initial setting
13h 3013h [7:0] ― 00h 00h Initial setting
18h 3018h [7:0]
19h 3019h [7:0] VMAX 465h VTTL See previous page.
1Ah 301Ah [1:0]
1Ch 301Bh [7:0] 465h: 30 / 60 /120
1130h / 0898h / 1130h / 0898h / 044Ch / [frame / s] /
HMAX 1130h
1Dh 301Ch [7:0] 14A0h 0A50h 14A0h 0A50h 0528h 546h: 25 / 50 /100
[frame / s]
[1:0] ODBIT 1h 1h In CSI-2, fixed to “1h”.
46h 3046h
[7:4] OPORTSEL 0h 0h In CSI-2, fixed to “0h”.
5Ch 305Ch [7:0] INCKSEL1 0Ch 0Ch / 18h
5Dh 305Dh [7:0] INCKSEL2 00h 00h / 03h Set according to INCK
5Eh 305Eh [7:0] INCKSEL3 10h 10h / 20h 74.25/37.125 MHz
5Fh 305Fh [7:0] INCKSEL4 01h 01h / 01h
Chip ID = 03h
10bit : 1Dh
29h 3129h [7:0] ADBIT1 00h 1Dh / 00h
12bit : 00h
Set according to INCK
5Eh 315Eh [7:0] INCKSEL5 1Bh 1Bh / 1Ah
74.25 / 37.125 MHz
Set according to INCK
64h 3164h [7:0] INCKSEL6 1Bh 1Bh / 1Ah
74.25 / 37.125 MHz
10bit : 12h
7Ch 317Ch [7:0] ADBIT2 17h 12h / 00h
12bit : 00h
10bit :37h
ECh 31ECh [7:0] ADBIT3 0Eh 37h / 0Eh
12bit : 0Eh
Chip ID = 04h
00h 3200h [7:0]
to to to Set register value that described on item “Register map”.
FFh 32FFh [7:0]
Chip ID = 05h
00h 3300h [7:0]
to to to Set register value that described on item “Register map”.
FFh 33FFh [7:0]

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CSI-2 serial
Address
Register Initial 2 lane 4 lane
bit Remarks
2 Name Value *1 *2 *1 *2 *3
4-wire IC
[frame /s] [frame /s] [frame /s] [frame /s] [frame /s]
Chip ID = 06h
Data rate 445.5 891 222.75 445.5 891 [Mbps / Lane]
05h 3405h [5:4] REPETITION 2h 1h 0h 2h 1h 0h
PHYSICAL_
07h 3407h [1:0] 3h 1h 3h
LANE_NUM
14h 3414h [5:0] OPB_SIZE_V Ah Ah
18h 3418h [7:0]
Y_OUT_SIZE 0449h 0449h
19h 3419h [4:0]
41h 3441h [7:0] 0A0Ah: RAW10
CSI_DT_FMT 0C0Ch 0A0Ah / 0C0Ch
42h 3442h [7:0] 0C0Ch: RAW12
CSI_LANE_
43h 3443h [1:0] 3h 1h 3h
MODE

44h 3444h [7:0]

EXTCK_ 37.125 MHz : 2520h
4A40h Set according to INCK
FREQ 74.25 MHz : 4A40h
45h 3445h [7:0]

46h 3446h [7:0]

TCLKPOST 047h 057h 077h 047h 057h 077h Global timing
47h 3447h [0]
48h 3448h [7:0]
THSZERO 01Fh 037h 067h 01Fh 037h 067h Global timing
49h 3449h [0]
4Ah 344Ah [7:0]
THSPREPARE 017h 01Fh 047h 017h 01Fh 047h Global timing
4Bh 344Bh [0]
4Ch 344Ch [7:0]
TCLKTRAIL 00Fh 01Fh 037h 00Fh 01Fh 037h Global timing
4Dh 344Dh [0]
4Eh 344Eh [7:0]
THSTRAIL 017h 01Fh 03Fh 017h 01Fh 03Fh Global timing
4Fh 344Fh [0]
50h 3450h [7:0]
TCLKZERO 047h 077h 0FFh 047h 077h 0FFh Global timing
51h 3451h [0]
52h 3452h [7:0]
TCLKPREPARE 00Fh 01Fh 03Fh 00Fh 01Fh 03Fh Global timing
53h 3453h [0]
54h 3454h [7:0]
TLPX 00Fh 017h 037h 00Fh 017h 037h Global timing
55h 3455h [0]

72h 3472h [7:0]

X_OUT_SIZE 079Ch 079Ch
73h 3473h [4:0]

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The example of window cropping setting is shown below.

The frame rate is maximum setting as each image format. For adjust the frame rate, please extend the VMAX or
the number of lines per frame.

Example of Window cropping Mode Setting

Register setting
Number of
Output Frame [DEC]
Image INCK recording pixels
Resolution rate (HEX)
size [MHz]
[bit] [frame/s]
Horizontal Vertical FRSEL HMAX VMAX WINPH WINPV WINWH WINWV

4400d
10/12 64.9 2
(1130h)
37.125 2200d 520d 640d 300d 656d 496d
VGA 10/12 129.8 640 480 1
74.25 (898h) (208h) (280h) (12Ch) (290h) (1F0h)
1100d
10 259.6 0
(44Ch)
4400d
10/12 102.9 2
(1130h)
37.125 2200d 328d 784d 396d 368d 304d
CIF 10/12 205.8 352 288 1
74.25 (898h) (148h) (310h) (18Ch) (170h) (130h)
1100d
10 411.6 0
(44Ch)

* These settings are when the ignored OB line is 2 lines and effective OB line is 10 lines.
* When the CSI-2 output, set the value that is set to register WINWV_OB to register Y_OUT_SIZE.

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8 Vertical blanking period

1 Frame information line
XVS

2 Ignored OB
Vertical effective OB WINWV_OB - 2
RG RG RG RG
GB GB GB GB
Vertical scan direction (Normal)

Ignored area of effective

Ignored area of effective

(WINPH, WINPV)
Horizontal blanking

Horizontal blanking
Horizontal dummy
Recording pixel area
Sync code

Sync code
WINWV
pixel side

pixel side
+
Effective margin for color processing

SD 4 4 4 3 4 HB
WINWH

RG RG RG RG
GB GB GB GB
VB Vertical blanking

Horizontal scan direction (Normal)

XHS

Pixel Array Image Drawing in Window Cropping mode (Parallel CMOS output / Serial LVDS output)

XVS (1 Frame) 13 + WINWV_OB + WINWV + Vx [lines]

XHS
WINPV
Line No. during
1 2 3 12
normal operation WINPV
Line No. during
1 2 3 12
inverted operation
8 1 2 Vx
WINWV_OB - 2 WINWV (Arbitrary value)
WINWV_OB

XHS (1 Line) : 2200 [pixels]

CMOS DCK(SDR)
WINPH
DO during horizontal
normal operation WINPH
DO during horizontal
inverted operation
4 4 WINWH - 8 4 3 4
SD HB

WINWH

: Frame information line : Sync code

: Ineffective OB / Blanking : Effective pixel side ignored area
: Effective OB : Margin for color processing
: Dummy area : Recording pixel area

SD : System delay
HB : Horizontal blanking

Drive Timing Chart for Window Cropping mode (Parallel CMOS output)

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XVS (1 Frame) 9 + WINWV_OB + WINWV + Vx [lines]

XHS
WINPV
Line No. during
1 2 3 12
normal operation WINPV
Line No. during
1 2 3 12
inverted operation
8 1 2 Vx
WINWV_OB - 2 WINWV (Arbitrary value)
(Number of Data in 1 Line) : 10bit: 2640 [DATA] / 12bit: 2200 [DATA] WINWV_OB
* Number of data when 1ch output, 1/2 when 2ch output, 1/4 when 4ch output
and 1/8 when 8ch output (average)

WINPH
CH1 / DLOP/M D
2ch output

Normal
CH2 / DLOP/M E
WINPH
CH1 / DLOP/M D
Inverted
CH2 / DLOP/M E
4 2 (WINWH / 2) - 4 2 2 4
HB HB

WINWH / 2
WINWH / 2 + 10 DATA
WINPH
CH1 / DLOP/M D
Normal CH2 / DLOP/M E
4ch output

CH3 / DLOP/M C
CH4 / DLOP/M F
CH1 / DLOP/M D
Inverted CH2 / DLOP/M E WINPH
CH3 / DLOP/M C
CH4 / DLOP/M F
4 1 (WINWH / 4) - 2 1 1 4
HB HB

WINWH / 4
WINWH /4 + 9 DATA
WINPH
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
Normal CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
8ch output

CH8 / DLOP/M H
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
Inverted CH5 / DLOP/M B
CH6 / DLOP/M G WINPH
CH7 / DLOP/M A
CH8 / DLOP/M H
4 1 (WINWH / 8) - 1 1 1 4
HB HB

WINWH / 8
WINWH /8 + 9 DATA

DCK (DDR)
: Frame information line : Sync code
: Ineffective OB / Blanking : Effective pixel side ignored area
1st [9]

1st [8]

1st [7]

1st [6]

1st [5]

1st [4]

1st [3]

1st [2]

1st [1]

1st [0]

10 bit CHx
SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

Output (x = 1-4) : Effective OB : Margin for color processing

: Dummy area / Dummy data : Recording pixel area

DCK (DDR) HB : Horizontal blanking

1st [11]

1st [10]

1st [9]

1st [8]

1st [7]

1st [6]

1st [5]

1st [4]

1st [3]

1st [2]

1st [1]

1st [0]

12 bit CHx
SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

Output (x = 1-4)

Drive Timing Chart for Window Cropping mode (Serial LVDS output)

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FS 1
PH 1 EBD(Embedded data) PF
PH 1 NULL 0 PF
Vertical effective OB WINWV_OB - 2
RG RG RG RG
GB GB GB GB
Ignored area of effective

Ignored area of effective

(WINPH, WINPV)

Horizontal blanking
Horizontal dummy
PH Recording pixel area WINWV PF
pixel side

pixel side
+
Effective margin for color processing

4 4 3 HB
WINWH

RG RG RG RG
GB GB GB GB
FE
VB Vertical blanking

Pixel Array Image Drawing in Window Cropping mode (CSI-2 serial output)

XVS (1 Frame) 9 + WINWV_OB + WINWV + Vx [lines]

XHS
WINPV
Line No. during
3 12
normal operation WINPV
Line No. during
3 12
inverted operation
8 1 1 1 1 Vx
WINWV (Arbitrary value)
WINWV_OB - 2
(Number of Data in 1 Line) : 10bit: 2640 [DATA] / 12bit: 2200 [DATA]
* Number of data when 1Lane, 1/2 when 2Lane and 1/4 when 4Lane (average)

WINPH
Horizontal pixel output image
normal operation WINPH
Horizontal pixel output image
inverted operation
4 WINWH - 8 4 3
HB

WINWH
* It outputs in the format of RAW10 or RAW12.

: FS / FE : Packet header / Packet footer

: NULL : Effective pixel side ignored area
: Embedded data : Margin for color processing
: Ineffective OB / Blanking : Recording pixel area
: Effective OB : Dummy area
HB : Horizontal blanking

Drive Timing Chart for Window Cropping mode (CSI-2 serial output)

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HD720p mode
List of Setting Register for CMOS parallel / LVDS serial output
Address Initial CMOS LVDS serial
2 bit Register Name Remarks
4-wire IC Value parallel 2 ch 4 ch
Chip ID: 02h
05h 3005h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
[0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
07h 3007h [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted
[6:4] WINMODE 0h 1h HD 720p
2h 30 [frame/s]
[1:0] FRSEL 2h 1h 60 [frame/s]
09h 3009h
N/A N/A 0h 120 [Frame/s]
[4] FDG_SEL 0h 0h / 1h 0: LCG mode, 1: HCG mode
12h 3012h [7:0] ― F0h 64h Initial setting
13h 3013h [7:0] ― 00h 00h Initial setting
18h 3018h [7:0]
19h 3019h [7:0] VMAX 465h 2EEh 25 /30 / 50 / 60 / 100 / 120 [frame/s]
1Ah 301Ah [1:0]
19C8h : 30[frame/s] /
1Ch 301Ch [7:0] 19C8h / 1EF0h
1EF0h : 25[frame/s]
0CE4h : 60[frame/s] /
HMAX 1130h 0CE4h / 0F78h
0F78h : 50[frame/s]
1Dh 301Dh [7:0]
0672h / 0672h : 120[frame/s] /
N/A N/A
07BCh 07BCh : 100[frame/s]
[1:0] ODBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
46h 3046h
[7:4] OPORTSEL 0h 0h Dh Eh I/F selection
5Ch 305Ch [7:0] INCKSEL1 0Ch 10h / 20h
5Dh 305Dh [7:0] INCKSEL2 00h 00h / 00h Set according to INCK
5Eh 305Eh [7:0] INCKSEL3 10h 10h / 20h 74.25/37.125 MHz
5Fh 305Fh [7:0] INCKSEL4 01h 01h / 01h
Chip ID = 03h
10bit : 1Dh
29h 3129h [7:0] ADBIT1 00h 1Dh / 00h
12bit : 00h
5Eh 315Eh [7:0] INCKSEL5 1Bh 1Bh / 1Ah INCK : 74.25 / 37.125 MHz
64h 3164h [7:0] INCKSEL6 1Bh 1Bh / 1Ah INCK : 74.25 / 37.125 MHz
10bit : 12h
7Ch 317Ch [7:0] ADBIT2 17h 12h / 00h
12bit : 00h
10bit :37h
ECh 31ECh [7:0] ADBIT3 0Eh 37h / 0Eh
12bit : 0Eh
Chip ID = 04h
00h 3200h [7:0]
to to to Set register value that described on item “Register map”.
FFh 32FFh [7:0]
ChipID = 05h
00h 3300h [7:0]
to to to Set register value that described on item “Register map”.
FFh 33FFh [7:0]
ChipID = 06h
00h 3400h [7:0]
to to to Changing the value is not necessary.
FFh 34FFh [7:0]

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List of Setting Register for CSI-2 serial output

CSI-2 serial
Address
Register Initial 2 lane 4 lane
bit Remarks
2 Name Value 30 60 30 60 120
4-wire IC
[frame /s] [frame /s] [frame /s] [frame /s] [frame /s]
Chip ID: 02h
05h 3005h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit
0h / 1h 0: Normal,
[0] VREVERSE 0h
1: Inverted
07h 3007h 0h / 1h 0: Normal,
[1] HREVERSE 0h
1: Inverted
[6:4] WINMODE 0h 1h HD 720p
[1:0] FRSEL 2h 2h 1h 2h 1h 0h
09h 3009h 0: LCG mode,
[4] FDG_SEL 0h 0h / 1h
1: HCG mode
12h 3012h [7:0] ― F0h 64h Initial setting
13h 3013h [7:0] ― 00h 00h Initial setting
18h 3018h [7:0]
25 /30 / 50 / 60 / 100 / 120
19h 3019h [7:0] VMAX 465h 2EEh
[frame/s]
1Ah 301Ah [1:0]
1Ch 301Ch [7:0] 30 / 60 /120
19C8h / 0CE4h / 19C8h / 0CE4h / 0672h / [frame / s] /
HMAX 1130h
1Dh 301Dh [7:0] 1EF0h 0F78h 1EF0h 0F78h 07BCh 25 / 50 /100
[frame / s]
[1:0] ODBIT 1h 1h In CSI-2, fixed to “1h”.
46h 3046h
[7:4] OPORTSEL 0h 0h In CSI-2, fixed to “0h”.
5Ch 305Ch [7:0] INCKSEL1 0Ch 10h / 20h
5Dh 305Dh [7:0] INCKSEL2 00h 00h / 00h Set according to INCK
5Eh 305Eh [7:0] INCKSEL3 10h 10h / 20h 74.25/37.125 MHz
5Fh 305Fh [7:0] INCKSEL4 01h 01h / 01h
Chip ID = 03h
10bit : 1Dh
29h 3129h [7:0] ADBIT1 00h 1Dh / 00h
12bit : 00h
Set according to INCK
5Eh 315Eh [7:0] INCKSEL5 1Bh 1Bh / 1Ah
74.25 / 37.125 MHz
Set according to INCK
64h 3164h [7:0] INCKSEL6 1Bh 1Bh / 1Ah
74.25 / 37.125 MHz
10bit : 12h
7Ch 317Ch [7:0] ADBIT2 17h 12h / 00h
12bit : 00h
10bit :37h
ECh 31ECh [7:0] ADBIT3 0Eh 37h / 0Eh
12bit : 0Eh
Chip ID = 04h
00h 3200h [7:0]
to to to Set register value that described on item “Register map”.
FFh 32FFh [7:0]
Chip ID = 05h
00h 3300h [7:0]
to to to Set register value that described on item “Register map”.
FFh 33FFh [7:0]

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CSI-2 serial
Address
Register Initial 2 lane 4 lane
bit Remarks
2 Name Value 30 60 30 60 120
4-wire IC
[frame /s] [frame /s] [frame /s] [frame /s] [frame /s]
Chip ID = 06h
Data rate 297 594 148.5 297 594 [Mbps / Lane]
05h 3405h [5:4] REPETITION 2h 1h 0h 2h 1h 0h
PHYSICAL_
07h 3407h [1:0] 3h 1h 3h
LANE_NUM
14h 3414h [5:0] OPB_SIZE_V Ah 4h
18h 3418h [7:0]
Y_OUT_SIZE 0449h 2D9h
19h 3419h [4:0]
41h 3441h [7:0] 0A0Ah: RAW10
CSI_DT_FMT 0C0Ch 0A0Ah / 0C0Ch
42h 3442h [7:0] 0C0Ch: RAW12
CSI_LANE_
43h 3443h [1:0] 3h 1h 3h
MODE

44h 3444h [7:0]

37.125 MHz : 2520h Set according
EXTCK_FREQ 4A40h
74.25 MHz : 4A40h to INCK
45h 3445h [7:0]

46h 3446h [7:0]

TCLKPOST 047h 04Fh 067h 047h 04Fh 067h Global timing
47h 3447h [0]
48h 3448h [7:0]
THSZERO 01Fh 02Fh 057h 017h 02Fh 057h Global timing
49h 3449h [0]
4Ah 344Ah [7:0]
THSPREPARE 017h 017h 02Fh 00Fh 017h 02Fh Global timing
4Bh 344Bh [0]
4Ch 344Ch [7:0]
TCLKTRAIL 00Fh 017h 027h 00Fh 017h 027h Global timing
4Dh 344Dh [0]
4Eh 344Eh [7:0]
THSTRAIL 017h 017h 02Fh 00Fh 017h 02Fh Global timing
4Fh 344Fh [0]
50h 3450h [7:0]
TCLKZERO 047h 057h 0BFh 02Bh 057h 0BFh Global timing
51h 3451h [0]
52h 3452h [7:0]
TCLKPREPARE 00Fh 017h 02Fh 00Bh 017h 02Fh Global timing
53h 3453h [0]
54h 3454h [7:0]
TLPX 00Fh 017h 027h 00Fh 017h 027h Global timing
55h 3455h [0]

72h 3472h [7:0]

X_OUT_SIZE 079Ch 51Ch
73h 3473h [4:0]

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8 Vertical blanking period

1 Frame information line
XVS

2 Ignored OB
4 Vertical effective OB
RG RG GR GR
GB GB 4 Effective margin for color processing BG BG
RG RG
Vertical scan direction (Normal)

GB GB
Number of recommended
Ignored area of effective

Ignored area of effective

recording pixels: 1280 (H) × 720 (V) = 0.92 M pixel
Number of active pixels: 1297 (H) × 725 (V) = 0.94 M pixel
for color processing

for color processing

Horizontal blanking

Horizontal blanking
Number of effective pixels: 1305 (H) × 725 (V) = 0.95 M pixel

Horizontal dummy
Total number of pixels: 1312 (H) × 731 (V) = 0.96 M pixel
Effective margin

Effective margin
Sync code

Sync code
pixel side

pixel side
720
Recording pixel area

SD 4 4 8 1280 9 4 3 4 HB

RG RG
GB GB
GB GB BG BG
RG RG 5 Effective margin for color processing GR GR
6 Vertical blanking

Horizontal scan direction (Normal)

XHS

Pixel Array Image Drawing in HD720p mode (Parallel CMOS output / Serial LVDS output)

XVS (1 Frame) 30, 60 frame/s: 750 [lines]

XHS

Line No. during

1 2 3 6 197 198 199 200 201 920 921 922 923 924 925
normal operation
Line No. during
1 2 3 6 925 924 923 922 921 202 201 200 199 198 197
inverted operation
8 1 2 4 4 720 5 6

XHS (1 Line) : 1650 [pixels]

CMOS DLCKP(SDR)

DO during horizontal
321 324 325 332 333 1612 1613 1621 1622 1625
normal operation
DO during horizontal
1625 1622 1621 1614 1613 334 333 325 324 321
inverted operation
4 4 8 1280 9 4 3 4
SD HB

: Frame information line : Sync code

: Ineffective OB / Blanking : Effective pixel side ignored area
: Effective OB : Margin for color processing
: Dummy area : Recording pixel area

SD : System delay
HB : Horizontal blanking

Drive Timing Chart for HD720p mode (Parallel CMOS output)

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XVS (1 Frame) 30, 60, 120 frame/s: 750 [lines]

XHS

Line No. during

1 2 3 6 197 198 199 200 201 920 921 922 923 924 925
normal operation
Line No. during
1 2 3 6 925 924 923 922 921 202 201 200 199 198 197
inverted operation
8 1 2 4 4 720 5 6

(Number of Data in 1 Line) : 10bit: 2640 [DATA] / 12bit: 2200 [DATA]

* Number of data when 1ch output, 1/2 when 2ch output and 1/4 when 4ch output (average)

CH1 / DLOP/M D
2ch output

321 323 325 331 333 1611 1613 1619 1621 1623 1625
Normal 322 324 326 332 334 1612 1614 1620 1622 1624
CH2 / DLOP/M E
CH1 / DLOP/M D 1625 1623 1621 1615 1613 335 333 327 325 323 321
Inverted 1624 1622 1620 1614 1612 334 332 326 324 322
CH2 / DLOP/M E
4 2 4 640 4 2 2 4
HB HB
662 DATA

CH1 / DLOP/M D 321 325 329 333 1609 1613 1617 1621 1625

Normal CH2 / DLOP/M E 322 326 330 334 1610 1614 1618 1622
4ch output

CH3 / DLOP/M C 323 327 331 335 1611 1615 1619 1623
CH4 / DLOP/M F 324 328 332 336 1612 1616 1620 1624

CH1 / DLOP/M D 1625 1621 1617 1613 337 333 329 325 321

Inverted CH2 / DLOP/M E

1624 1620 1616 1612 336 332 328 324
CH3 / DLOP/M C 1623 1619 1615 1611 335 331 327 323
CH4 / DLOP/M F 1622 1618 1614 1610 334 330 326 322

4 1 2 320 2 1 1 4
HB HB
336 DATA

DLCK (DDR)
: Frame information line : Sync code
: Ineffective OB / Blanking : Effective pixel side ignored area
1st [9]

1st [8]

1st [7]

1st [6]

1st [5]

1st [4]

1st [3]

1st [2]

1st [1]

1st [0]

10 bit CHx
SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

Output (x = 1-4) : Effective OB : Margin for color processing

: Dummy area : Recording pixel area

DLCK (DDR) HB : Horizontal blanking

1st [11]

1st [10]

1st [9]

1st [8]

1st [7]

1st [6]

1st [5]

1st [4]

1st [3]

1st [2]

1st [1]

1st [0]

12 bit CHx
SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

SAV

Output (x = 1-4)

Drive Timing Chart for HD720p mode (Serial LVDS output)

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FS 1
PH 1 EBD(Embedded data) PF
PH 1 NULL 0 PF
4 Vertical effective OB
RG RG GR GR
GB GB 4 Effective margin for color processing BG BG
RG RG
GB GB
Ignored area of effective

Ignored area of effective

for color processing

for color processing

Horizontal blanking
Horizontal dummy
Effective margin

Effective margin
PH PF
pixel side

pixel side
720
Recording pixel area

4 8 1280 9 4 3 HB

RG RG
GB GB
GB GB BG BG
RG RG 5 Effective margin for color processing GR GR
FE
5 Vertical blanking

Pixel Array Image Drawing in HD720p mode (CSI-2 serial output)

XVS (1 Frame) 30, 60, 120 frame/s: 750 [lines]

XHS

Line No. during

3 6 197 200 201 920 921 925
normal operation
Line No. during
3 6 925 922 921 202 201 197
inverted operation
8 1 1 1 4 4 720 5 1 5

(Number of Data in 1 Line) : 10bit: 2640 [DATA] / 12bit: 2200 [DATA]

* Number of data when 1Lane, 1/2 when 2Lane and 1/4 when 4Lane (average)

Horizontal pixel output image

321 324 325 332 333 1612 1613 1621 1622 1625
normal operation
Horizontal pixel output image
1625 1622 1621 1614 1613 334 333 325 324 321
inverted operation
4 8 1280 9 4 3
HB
* It outputs in the format of RAW10 or RAW12.

: FS / FE : Packet header / Packet footer

: NULL : Effective pixel side ignored area
: Embedded data : Margin for color processing
: Ineffective OB / Blanking : Recording pixel area
: Effective OB : Dummy area
HB : Horizontal blanking

Drive Timing Chart for HD720p mode (CSI-2 serial output)

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Description of Various Function

Standby Mode
This sensor stops its operation and goes into standby mode which reduces the power consumption by writing “1” to
the standby control register STANDBY. Standby mode is also established after power-on or other system reset
operation.

List of Standby Mode Setting

Register details
Initial Setting
Register name Address Status Remarks
Register ChipID bit value value
2
():I C

1 Standby Register communication

00h
STANDBY ― 02h [0] 1 is executed in standby
(3000h)
0 Operating mode.

The serial communication registers hold the previous values. However, the address registers transmitted in standby
mode are overwritten. The serial communication block operates even in standby mode, so standby mode can be
canceled by setting the STANDBY register to “0”. Some time is required for sensor internal circuit stabilization after
standby mode is canceled. After standby mode is canceled, a normal image is output from the 9 frames after internal
regulator stabilization (TBD ms or more).

Initial regulator
Register Standby
stabilization period
initial settings cancel
(TBD ms)

XCE

XVS

Initialization period (8 frames) Normal image output

Sequence from Standby Cancel to Stable Image Output

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Slave Mode and Master Mode

The sensor can be switched between slave mode and master mode. The switching is made by the XMASTER pin.
Establish the XMASTER pin status before canceling the system reset. (Do not switch this pin status during
operation.)

Input a vertical sync signal to XVS and input a horizontal sync signal to XHS when a sensor is in slave mode.
For sync signal interval, input data lines to output for vertical sync signal and 1H period designated in each operating
mode for horizontal sync signal. See the section of "Operating mode" for the number of output data line and 1H
period.
Set the XMSTA register to “0” in order to start the operation after setting to master mode. In addition, set the count
number of sync signal in vertical direction by the VMAX [17:0] register and the clock number in horizontal direction by
the HMAX [13:0] register. See the description of Operation Mode for details of the section of “Operating Modes”.

List of Slave and Master Mode Setting

Pin name Pin processing Operating mode Remarks
Fixed to Low Master mode High: OVDD
XMASTER pin
Fixed to High Slave mode Low: GND

List of Register in Master Mode

Register details (Chip ID = 02h)
Initial
Register name Address Setting value Remarks
Register 2 bit value
():I C
02h 1: Master operation ready The master operation
XMSTA ― [0] 1
(3002h) 0: Master operation start starts by setting 0.
18h
VMAX [7:0] [7:0]
(3018h)
19h Line number per
VMAX [17:0] VMAX [15:8] [7:0] 00465h See the item of each drive mode.
(3019h) frame designated
1Ah
VMAX [17:16] [1:0]
(301Ah)
1Ch
HMAX [7:0] [7:0]
(301Ch) Clock number per line
HMAX [13:0] 1130h See the item of each drive mode.
1Dh designated
HMAX [15:8] [7:0]
(301Dh)
48h XVS low level pulse
XVSLNG [1:0] ― [5:4] 0h 0: 1H, 1: 2H, 2: 4H, 3: 8H
(3048h) width designated
49h 0: Min. to 3: Max. XHS low level pulse
XHSLNG [1:0] ― [5:4] 0h
(3049h) See the next width designated
0: Fixed to High
XVSOUTSEL [1:0] ― [1:0] 0h 2: VSYNC output
4Bh Others: Setting prohibited
(304Bh) 0: Fixed to High
XHSOUTSEL [1:0] ― [3:2] 0h 2: HSYNC output
Others: Setting prohibited

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XVS
XVSLNG = 0d: 1H width

XVSLNG = 1d: 2H width

XVS
XVSLNG = 2d: 4H width

XVSLNG = 3d: 8H width

XHS

XHS
XHSLNG = 0

XHSLNG = 1
XHS
XHSLNG = 2

XHSLNG = 3
System delay
DataOut SAV

XVS/XHS output waveform in sensor master mode

List of XHSLNG Register

CMOS parallel output LVDS serial output
74.25 37.125 594 297 148.5 445.5 222.75 111.375
DCK
[MHz] [MHz] [Mbps / ch] [Mbps / ch] [Mbps / ch] [Mbps / ch] [Mbps / ch] [Mbps / ch]
XHSLNG =0 8 clk 4 clk 64 bit 32 bit 16 bit 48 bit 24 bit 12 bit
XHSLNG =1 16 clk 8 clk 128 bit 64 bit 32 bit 96 bit 48 bit 24 bit
XHSLNG =2 32 clk 16 clk 256 bit 128 bit 64 bit 192 bit 96 bit 48 bit
XHSLNG =3 64 clk 32 clk 512 bit 256 bit 128 bit 384 bit 192 bit 96 bit

The XVS and XHS are output in timing that set 0 to the register XMSTA. If set 0 to XMSTA during standby, the XVS
and XHS are output just after standby is released. The XVS and XHS are output asynchronous with other input or
output signals. In addition, the output signals are output with a undefined latency time (system delay) relative to the
XHS. Therefore, refer to the sync codes output from the sensor and perform synchronization.

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Gain Adjustment Function

The Programmable Gain Control (PGC) of this device consists of the analog block and digital block. The total of
analog gain and digital gain can be set up to 72 dB by the GAIN [7:0] register setting. The same setting is applied in
all colors.

The value which is 10/3 times the gain is set to register. (0.3 dB step)

Example)
When set to 6 dB: 6 × 10/3 = 20d; GAIN [7:0] = 14h
When set to 12.6 dB: 12.6 × 10/3 = 42d; GAIN [7:0] = 2Ah

List of PGC Register

Setting
Register details (Chip ID = 02h)
Register Initial value
Remarks
name Address value Setting
Register 2 bit
():I C range

14h 00h-F0h Setting value: Gain [dB] × 10/3

GAIN [7:0] GAIN [7:0] [7:0] 00h
(3014h) (0d-240d) (0.3 dB step)

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The gain setting is reflected at the next frame that the communication is performed as shown below.

Communication period
Register Communication
Time base

GAIN = 00h GAIN = 14h GAIN = 00h

XVS

Output Signal Frame Frame Frame Frame Frame Frame Frame Frame

Gain 6dB
setting 0dB

Gain Reflection Timing

Black Level Adjustment Function

The black level offset (offset variable range: 000h to 1FFh) can be added relative to the data in which the digital gain
modulation was performed by the BLKLEVEL [8:0] register. When the BLKLEVEL setting is increased by 1 LSB, the
black level is increased by 1 LSB.

Use with values shown below is recommended.

10-bit output: 03Ch (60d)
12-bit output: 0F0h (240d)

List of Black Level Adjustment Register

Register details (Chip ID = 02h)

Initial
Register name Address Setting value
Register bit value
( ) : I 2C
0Ah
BLKLEVEL [7:0] [7:0]
(300Ah)
BLKLEVEL [8:0] 0F0h 000h to 1FFh
0Bh
BLKLEVEL [8] [0]
(300Bh)

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Normal Operation and Inverted Operation

The sensor readout direction (normal / inverted) in vertical direction can be switched by the VREVERSE register
setting and in horizontal direction can be switched by the HREVERSE register setting. See the section of “Operating
Modes” for the order of readout lines in normal and inverted modes. One invalid frame is generated when reading
immediately after the readout direction change in order to switch the normal operation and inversion between frames.

List of Drive Direction Setting Register

Register details (Chip ID = 02h)

Initial
Register name Address Setting value
Register 2 bit value
():I C
0: Normal (Initial value)
VREVERSE ― [0] 0h
07h 1: Vertical Inverted
(3007h) 0: Normal (Initial value)
HREVERSE ― [1] 0h
1: Horizontal Inverted

In normal mode In inverted mode

P1-Pin A1-Pin P1-Pin A1-Pin

V (+) V (+)

H (+) H (+)

P11-Pin A11-Pin P11-Pin A11-Pin

(Chip outline) (Chip outline)

Normal and Inverted Drive Outline in Vertical Direction (TOP VIEW)

In normal mode In inverted mode

P1-Pin A1-Pin P1-Pin A1-Pin

V (+) V (+)

H (+) H (+)

P11-Pin A11-Pin P11-Pin A11-Pin

(Chip outline) (Chip outline)

Normal and Inverted Drive Outline in Horizontal Direction (TOP VIEW)

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Shutter and Integration Time Settings

This sensor has a variable electronic shutter function that can control the integration time in line units. In addition, this
sensor performs rolling shutter operation in which electronic shutter and readout operation are performed
sequentially for each line.

Note) For integration time control, an image which reflects the setting is output from the frame after the setting
changes.

Example of Integration Time Setting

The sensor's integration time is obtained by the following formula.

Intefration time = 1 frame period - (SHS1 + 1) × (1H period)

*1 The frame period is determined by the input XVS when the sensor is operating in slave mode, or the register
VMAX value in master mode. The frame period is designated in 1H units, so the time is determined by
(Number of lines × 1H period).
*2 See “Operating Modes” for the 1H period.

In this section, the shutter operation and storage time are shown as in the figure below with the time sequence on the
horizontal axis and the vertical address on the vertical axis. For simplification, shutter and readout operation are
noted in line units.

FS (Frame Start) Shutter timing

FE (Frame End) Readout timing
Blanking Integration time
Embedded Data
Time base
XVS N frame N+1 frame

XHS
CSI-2
N frame N+1 frame
Packet
Chip top side
Last line
Last-1 line
Last-2 line

Sensor

4 line
3 line
2 line
1 line
Chip bottom side
Output
blanking effective signal blanking effective signal blanking

Image Drawing of Shutter Operation

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Normal Exposure Operation (Controlling the Integration Time in 1H Units)

The integration time can be controlled by varying the electronic shutter timing. In the electronic shutter settings, the
integration time is controlled by the SHS1 [17:0] register. Set SHS1 [17:0] to a value between 1 and (Number of lines
per frame - 1). When the sensor is operating in slave mode, the number of lines per frame is determined by the XVS
interval (number of lines), using the input XHS interval as the line unit.
When the sensor is operating in master mode, the number of lines per frame is determined by the VMAX register.
The number of lines per frame differs according to the operating mode.

Registers Used to Set the Integration Time in 1H Units

Register details (Chip ID = 02h)

Initial
Register name Address Setting value
Register bit value
( ) : I 2C

20h
SHS1 [7:0] [7:0]
(3020h)
Sets the shutter sweep time.
21h 1 to (Number of lines per frame - 2)
SHS1 [17:0] SHS1 [15:8] [7:0] 00000h
(3021h) * 0 and number of lines per frame -1
setting is prohibited
22h
SHS1 [17:16] [1:0]
(3022h)
18h
VMAX [7:0] [7:0]
(3018h)
Sets the number of lines per frame
19h
VMAX [17:0] VMAX [15:8] [7:0] 00465h (only in master mode). See “Operating
(3019h)
Modes” for the setting value in each mode.
1Ah
VMAX [17:16] [1:0]
(301Ah)

Readout timing Integration time FS (Frame Start) Embedded Data

Shutter timing Communication period FE (Frame End) Blanking

Time base

XVS
SHS1=α SHS1=β

XHS

CSI-2 Packet

α+1 Frame2
integration time
β+1 Frame3
integration time
β+1 Frame4
integration time
β+1 Frame5
integration time
…

Output timimg V-BLK Frame1 V-BLK Frame2 V-BLK Frame3 V-BLK Frame4 V-BLK Frame5

Image Drawing of Integration Time Control within a Frame

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Long Exposure Operation (Control by Expanding the Number of Lines per Frame)
Long exposure operation can be performed by lengthening the frame period.
When the sensor is operating in slave mode, this is done by lengthening the input vertical sync signal (XVS) pulse
interval.
When the sensor is operating in master mode, it is done by designating a larger register VMAX [17:0] value
compared to normal operation. When the integration time is extended by increasing the number of lines, the rear V
blanking increases by an equivalent amount.

Although the maximum value of long exposure operation changes in each modes, the maximum of long time
exposure is approximately 1 s.
When set to a number of V lines or more than that noted for each operating mode, the imaging characteristics are not
guaranteed during long exposure operation.

Time base

XVS VMAX = 1125d VMAX = 1600d

SHS1 = α SHS1 = α
Communication
XHS period

FS (Frame Start)

CSI-2 FE (Frame End)

Packet
mode Blanking
Embedded Data

α+1 Frame2 α+1 α+1 α+1 Readout timing

Frame3 Frame4
integration time integration time integration time ... Shutter timing
Integration time
Output timimg V-BLK Frame1 V-BLK Frame2 V-BLK Frame3 V-BLK Frame4 V-BLK

Image Drawing of Long Integration Time Control by Adjusting the Frame Period

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Example of Integration Time Settings

The example of register setting for controlling the storage time is shown below.

Example of Integration Time Settings (In Full HD 1080p)

Sensor setting (register)
Operation Integration time
VMAX* SHS1**
1123 1H

…
Normal frame rate 1125 N (1125 - (N + 1)) H

…
1 1123H

* In sensor master mode. In slave mode, the interval is the same as XVS input.
** The SHS1 setting value (N) is set between “1” and “the VMAX value (M) – 2”.

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Signal Output
Output Pin Settings
The output formats of this sensor support the following modes.

CMOS logic parallel SDR output

Low voltage LVDS serial (2 ch / 4 ch / 8 ch switching) DDR output
CSI-2 serial (2 Lane / 4 Lane, RAW10 / RAW12) output

The switching for serial interface is made by the OMODE pin. Establish the OMODE pin status before canceling
the system reset. (Do not switch this pin status during operation.) Each mode is set using the register OPORTSEL.
The table below shows the output format settings.

List of Interface Switching

Pin name Pin Interface Remarks
Fixed to Low CSI-2 serial
High: OVDD
OMODE pin CMOS parallel SDR
Fixed to High Low: GND
Low voltage LVDS serial

List of Output Interface Setting Register

Register details
(Chip ID = 02h) Initial Setting
Register name Description
Address value value
bit
( ) : I 2C
0h CMOS logic parallel SDR output
Dh Low voltage LVDS serial 2 ch DDR
OPORTSEL 46h Eh Low voltage LVDS serial 4 ch DDR
[7:4] 0h
[3:0] (3046h) Fh Low voltage LVDS serial 8 ch DDR
N/A CSI-2 serial 2Lane
N/A CSI-2 serial 4Lane

* In CMOS output, Clock is output from DLCKP pin. DLCKM pin is fixed to low level.
* In CSI-2 output, set registers that described in section “CSI-2 output setting”.

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Each output pin is shown in the table below when setting low-voltage LVDS serial 2 ch / 4 ch / 8 ch output.

Output Pins for Low LVDS Serial and CMOS parallel

CMOS logic Low voltage LVDS serial DDR output

DLOP/DLOM parallel SDR output
2 ch 4 ch 8 ch
10 bit 12 bit
DLOMH Low fixed Low fixed Hi-Z Hi-Z Ch8 / M
DLOPH Low fixed Low fixed Hi-Z Hi-Z Ch8 / P
DLOMG DO9 DO11 Hi-Z Hi-Z Ch6 / M
DLOPG DO8 DO10 Hi-Z Hi-Z Ch6 / P
DLOMF DO7 DO9 Hi-Z Ch4 / M Ch4 / M
DLOPF DO6 DO8 Hi-Z Ch4 / P Ch4 / P
DLOME DO5 DO7 Ch2 / M Ch2 / M Ch2 / M
DLOPE DO4 DO6 Ch2 / P Ch2 / P Ch2 / P
DLOMD DO3 DO5 Ch1 / M Ch1 / M Ch1 / M
DLOPD DO2 DO4 Ch1 / P Ch1 / P Ch1 / P
DLOMC DO1 DO3 Hi-Z Ch3 / M Ch3 / M
DLOPC DO0 DO2 Hi-Z Ch3 / P Ch3 / P
DLOMB Low fixed DO1 Hi-Z Hi-Z Ch5 / M
DLOPB Low fixed DO0 Hi-Z Hi-Z Ch5 / P
DLOMA Low fixed Low fixed Hi-Z Hi-Z Ch7 / M
DLOPA Low fixed Low fixed Hi-Z Hi-Z Ch7 / P

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Low-voltage LVDS serial 2 ch / 4 ch / 8 ch output format is shown in the figure below.

When setting 2 ch, after four data of SAV is output in the order of CH1 and CH2 pixel data is repeatedly output in
the same order and then four data of EAV is output in the same order to CH1 and CH2 respectively.
When setting 4 ch, after four data of SAV is output in the order of CH1, CH2, CH3 and CH4 pixel data is
repeatedly output in the same order and then four data of EAV is output in the same order to CH1, CH2, CH3 and
CH4 respectively.
When setting 8 ch, after four data of SAV is output in the order of CH1, CH2, CH3, CH4, CH5, CH6, CH7 and CH8
pixel data is repeatedly output in the same order and then four data of EAV is output in the same order to CH1,
CH2, CH3, CH4, CH5, CH6, CH7 and CH8 respectively.
Data is sent MSB first.
For details, see drive timing in each mode in the section of "Operation Mode".

DLCK

・・・

P 2n
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P0
3rd

3rd
4th

4th
1st

1st
CH1

2 ch

P 2n+1
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P1
3rd

3rd
4th

4th
1st

1st
CH2

DLCK

・・・

P 4n
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P0
3rd

3rd
4th

4th
1st

1st
CH1

P 4n+1
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P1
3rd

3rd
4th

4th
1st

1st
CH2

4 ch
P 4n+2
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P2
3rd

3rd
4th

4th
1st

1st

CH3
P 4n+3
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P3
3rd

3rd
4th

4th
1st

1st

CH4

DLCK
・・・

P 8n
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P0
3rd

3rd
4th

4th
1st

1st

CH1
P 8n+1
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P1
3rd

3rd
4th

4th
1st

1st

CH2
P 8n+2
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P2
3rd

3rd
4th

4th
1st

1st

CH3
P 8n+3
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P3
3rd

3rd
4th

4th
1st

1st

CH4
8 ch
P 8n+4
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P4
3rd

3rd
4th

4th
1st

1st

CH5
P 8n+5
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P5
3rd

3rd
4th

4th
1st

1st

CH6
P 8n+6
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P6
3rd

3rd
4th

4th
1st

1st

CH7
P 8n+7
・・・
SAV

SAV

SAV

SAV

EAV

EAV

EAV

EAV
2nd

2nd
P7
3rd

3rd
4th

4th
1st

1st

CH8

Output Format of Low voltage LVDS Serial 2 ch / 4 ch / 8 ch

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CSI-2 output
The output formats of this sensor support the following modes.

CSI-2 serial 2 Lane / 4 Lane, RAW10 / RAW12

The 2 Lane / 4 Lane serial signal output method using this sensor is described below.
Complied with the CSI-2, data is output using 2 Lane / 4 Lane. The image data is output from the CSI-2 output pin.
The DMO1P/DMO1N are called the Lane1 data signal, the DMO2P/DMO2N are called the Lane2 data signal, the
DMO3P/DMO3N are called the Lane3 data signal, the DMO4P/DMO4N are called the Lane4 data signal. In addition,
the clock signals are output from DMCKP/DMCKN of the CSI-2 pins.
In 2 Lane mode, data is output from Lane1 and Lane2. In 4 Lane mode, data is output from Lane1, Lane2, Lane3 and
Lane4. The bit rate maximum value is 891 Mbps / Lane.
The select of RAW10 / RAW12 is set by the register: CSI_DT_FMT [15:0] The number of output lanes is set by the
register: CSI_LANE_MODE [1:0] and the number of lanes physically connected is set by PHYSICAL_LANE_NUM
[1:0]. Unused lanes (when setting 2 lanes; DMO3P / DMO3N, DMO4P / DMO4N) are set to Hi-Z output by the setting.
When the number of lanes more than CSI_LANE_MODE is set by PHYSICAL_LANE_NUM, unused lanes output
signals conformed to MIPI standard.

Register details
(Chip ID = 06h) Initial Setting
Register name Description
Address value value
bit
( ) : I 2C
41h
[7:0] 0A0Ah RAW10
(3441h)
CSI_DT_FMT [15:0] 0C0Ch
42h
[7:0] 0C0Ch RAW12
(3442h)
0h Setting prohibited
PHYSICAL_LANE_NUM 07h 1h 2Lane
[1:0] 3h
[1:0] (3407h) 2h Setting prohibited
3h 4Lane
0h Setting prohibited
43h 1h 2Lane
CSI_LANE_MODE [1:0] [1:0] 3h
(3443h) 2h Setting prohibited
3h 4Lane

The formats of RAW12 and RAW10 are shown below.

P0 P1 P2 P3

→ RAW12 Format
P0 P0 P0 P0 P0 P0 P0 P0 P1 P1 P1 P1 P1 P1 P1 P1 P0 P0 P0 P0 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 P3 P3 P3 P3 P3 P3 P3 P3
[4] [5] [6] [7] [8] [9] [10] [11] [4] [5] [6] [7] [8] [9] [10] [11] [0] [1] [2] [3] [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [4] [5] [6] [7] [8] [9] [10] [11] …

→ RAW10 Format
P0 P0 P0 P0 P0 P0 P0 P0 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 P3 P3 P3 P3 P3 P3 P3 P3 P0 P0 P1 P1 P2 P2 P3 P3
[2] [3] [4] [5] [6] [7] [8] [9] [2] [3] [4] [5] [6] [7] [8] [9] [2] [3] [4] [5] [6] [7] [8] [9] [2] [3] [4] [5] [6] [7] [8] [9] [0] [1] [0] [1] [0] [1] [0] [1] …

The Example of Format of RAW12 / RAW10

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The each formal of 2 Lane and 4 Lane are shown below.

a) 2 Lane-RAW12
Sensor
DMO1P/DMO1N P1 P5
P0 [3:0] P3 P4 [3:0] P7
P0 P1 P2 P3 … PH [11:4] P0 [11:4] [11:4] P4 [11:4] …
[3:0] [3:0]
DMO2P/DMO2N P3 P7
P1 P2 [3:0] P5 P6 [3:0]
PH [11:4] [11:4] P2 [11:4] [11:4] P6 …
[3:0] [3:0]

b) 2 Lane-RAW10
Sensor
DMO1P/DMO1N P3[1:0]
P0 P2 P2[1:0] P5 P7 P8
P0 P1 P2 P3 … PH [9:2] [9:2] P1[1:0] [9:2] [9:2] [9:2] …
P0[1:0]
DMO2P/DMO2N P7[1:0]
P1 P3 P4 P6 P6[1:0] P9
PH [9:2] [9:2] [9:2] [9:2] P5[1:0] [9:2] …
P4[1:0]

c) 4 Lane-RAW12
Sensor
DMO1P/DMO1N P5 P13
P0 P3 [3:0] P8 P11 [3:0]
P0 P1 P2 P3 … PH [11:4] [11:4] P4 [11:4] [11:4] P12 …
[3:0] [3:0]
DMO2P/DMO2N P3 P11
P1 [3:0] P6 P9 [3:0] P14
PH [11:4] P2 [11:4] [11:4] P10 [11:4] …
[3:0] [3:0]
DMO3P/DMO3N P1 P9
[3:0] P4 P7 [3:0] P12 P15
PH P0 [11:4] [11:4] P8 [11:4] [11:4] …
[3:0] [3:0]
DMO4P/DMO4N P7 P15
P2 P5 [3:0] P10 P13 [3:0]
PH [11:4] [11:4] P6 [11:4] [11:4] P14 …
[3:0] [3:0]

d) 2 Lane-RAW10
Sensor
DMO1P/DMO1N P3[1:0]
P0 P2[1:0] P7 P10 P13 P16
P0 P1 P2 P3 … PH [9:2] P1[1:0] [9:2] [9:2] [9:2] [9:2] …
P0[1:0]
DMO2P/DMO2N P7[1:0]
P1 P4 P6[1:0] P11 P14 P17
PH [9:2] [9:2] P5[1:0] [9:2] [9:2] [9:2] …
P4[1:0]
DMO3P/DMO3N P11[1:0]
P2 P5 P8 P10[1:0] P15 P18
PH [9:2] [9:2] [9:2] P9[1:0] [9:2] [9:2] …
P8[1:0]
DMO4P/DMO4N P15[1:0]
P3 P6 P9 P12 P14[1:0] P19
PH [9:2] [9:2] [9:2] [9:2] P13[1:0] [9:2] …
P12[1:0]

2 Lane / 4 Lane Output Format

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MIPI Transmitter
Output pins (DMO1P, DMO1N, DMO2P, DMO2N, DMO3P, DMO3N, DMO4P, DMO4D, DMCKP, DMCKN) are
described in this section.

Sensor

DMO1P N6 +
Data Lane 1
DMO1N P6 -

DMO2P N8 +
Data Lane 2
DMO2N P8 -

DMO3P N5 +
Data Lane 3
DMO3N P5 -

DMO4P N9 +
Data Lane 4
DMO4N P9 -

DMCKP N7 +
Clock Lane
DMCKN P7 -

Relationship between Pin Name and MIPI Output Lane

The pixel signals are output by the CSI-2 High-speed serial interface.
See the MIPI Standard
・MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01.00
・MIPI Alliance Specification for D-PHY Version 1.00.00

The CSI-2 transfers one bit with a pair of differential signals. The transmitter outputs differential current signal after
converting pixel signals to it. Insert external resistance in differential pair in a series or use cells with a built-in
resistance on the Receiver side. When inserting an external resistor, as close as possible to the Receiver. The
differential signals maintain a constant interval and reach the receiver with the shortest wiring length possible to
avoid malfunction. The maximum bit rate of each Lane are 891 Mbps / Lane.

Dp
Clock
LP-Tx

Lane Control Dn
Data and Tx
Interface Logic
HS-Tx
Control

Protocol Side Line Side

Universal Lane Module Functions

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Output Pin Bit Width Selection

The output pin width can be selected from 10-bit or 12-bit output using the register ODBIT. In parallel output mode,
when ODBIT = 0 (10-bit output), the lower 2 bits are fixed to Low level in CMOS output mode. Therefore, when
using only 10 bits, the pins corresponding to the lower 2 bits can be left open on the board by setting ODBIT = 0.
When low-voltage LVDS serial output, continuous data is output MSB first by 10-bit and 12-bit output setting
respectively. 10-bits sync code are output when ODBIT = 0 (10-bit output), and 12-bit sync codes are output when
ODBIT = 1 (12-bit output).

Output Pin Bit Width Selection Setting Register

Register details (Chip ID = 02h)
Register Initial
Address Setting value
name Register 2 bit value
():I C
46h 0: 10 bit
ODBIT ― [0] 0h
(3046h) 1: 12 bit

ODBIT = 0 (CMOS Parallel 10 bit output)

Internal data bus D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

Chip output pins DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

*) The sync code is 10 bit. Fixed to Low

Bit Assignments in Parallel 10-bit Output Mode

ODBIT = 1 (CMOS Parallel 12 bit output)

Internal data bus D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

Chip output pins DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

*) The sync code is 12 bit.

Bit Assignments in Parallel 12-bit Output Mode

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ODBIT = 0 (Low voltage LVDS serial 10 bit output)

DLCK

・・・

・・・
CHx

P0

P1
(x = 1 - 4)

MSB First
DLCK

・・・
CHx
P0[9]

P0[8]

P0[7]

P0[6]

P0[5]

P0[4]

P0[3]

P0[2]

P0[1]

P0[0]

P1[9]

P1[8]

P1[7]

P1[6]

P1[5]

P1[4]

P1[3]

P1[2]

P1[1]

P1[0]
(x = 1 - 4)

Example of Data format in low-voltage LVDS serial 10-bit output

ODBIT = 1 (Low voltage LVDS serial 12 bit output)

DLCK
・・・

・・・

CHx
P0

P1

(x = 1 - 4)

MSB First

DLCK
P0 [11]

P1 [11]

・・・
P0[10]

P1[10]

CHx
P0[9]

P0[8]

P0[7]

P0[6]

P0[5]

P0[4]

P0[3]

P0[2]

P0[1]

P0[0]

P1[9]

P1[8]

P1[7]

P1[6]

P1[5]

P1[4]

P1[3]

P1[2]

P1[1]

P1[0]
(x = 1 - 4)

Example of Data format in low-voltage LVDS serial 12-bit output

Number of Internal A/D Conversion Bits Setting

The number of internal A/D conversion bits can be selected from 10 bits or 12 bits by the register ADBIT. See the
section of “Operating Modes” for the correspondence with each mode.

List of Bit Width Selection

Register details
*1 : Chip ID = 02h
Register *2 : Chip ID = 03h Initial value Setting value
name
Address
Register 2 bit
():I C
05h 0: 10 bit
ADBIT ― [0] 1h
(3005h) 1: 12 bit
29h *2 10bit : 1Dh
ADBIT1[7:0] ― [7:0] 00h
(3129h) 12bit : 00h
7Ch *2 10bit : 12h
ADBIT2[7:0] ― [7:0] 17h
(317Ch) 12bit : 00h
29h *2 10bit : 37h
ADBIT3[7:0] ― [7:0] 0Eh
(31ECh) 12bit : 0Eh

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Output Rate Setting

The sensor output rate is determined uniformly by the sensor operating mode and the output format. See the
section of “Operating Modes” for the relationship between each setting and the frame rate, data rate and data bit
rate. The registers related to mode setting are shown in the table below.

Related Registers for Setting Operation Mode

Register details (Chip ID = 02h)
Initial
Register name Address Setting value
Register 2 bit value
():I C
0: Full HD 1080p
07h
WINMODE [2:0] ― [6:4] 0h 1: 720 p
(3007h)
4: Window cropping from Full HD 1080p
0: 120 frame / s
09h 1: 60 frame / s
FRSEL [1:0] ― [1:0] 1h
(3009h) 2: 30 frame / s
3: Setting prohibited

Output Signal Range

In sub LVDS output and CMOS parallel output mode, the sensor output has 10 bit or 12 bit gray scale according to
the setting. The output is not performed at full range and the range is the values shown in the table below
See the item of “Sync Codes” in the section of “Operating Modes” for the sync codes.

Output Gradation and Output Range (Low voltage LVDS Output)

Output value
Output gradation
Min. Max.
10 bit 001h 3FEh
12 bit 001h FFEh

In CSI-2 output mode, the sensor output has either a 10 bit or 12 bit gradation, but output is not performed over the
full range, and the maximum output value is the 3FFh value (10 bit output) and the FFFh one (12 bit output).
The output range for each output gradation is shown in the table below.

Output Gradation and Output Range (CSI-2 Output)

Output value
Output gradation
Min. Max.
10 bit 000h 3FFh
12 bit 000h FFFh

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INCK Setting
The available operation mode varies according to INCK frequency. Input either 37.125 MHz or 74.25 MHz for
INCK frequency. The INCK setting register and the list of INCK setting are shown in the table below.

INCK Setting Register

Register details
*1 : Chip ID = 02h INCK = 37.125 MHz INCK = 74.25 MHz
Register *2 : Chip ID = 03h Initial
name value 1080p 1080p
Address 1080p 1080p
Register 2 bit CMOS 720p CMOS 720p
():I C CSI-2 CSI-2
LVDS LVDS
5Ch *1
INCKSEL1 ― [7:0] 0Ch 18h 18h 20h 0Ch 0Ch 10h
(305Ch)
5Dh *1
INCKSEL2 ― [7:0] 00h 00h 03h 00h 00h 03h 00h
(305Dh)
5Eh *1
INCKSEL3 ― [7:0] 10h 20h 20h 20h 10h 10h 10h
(305Eh)
5Fh *1
INCKSEL4 ― [7:0] 01h 01h 01h 01h 01h 01h 01h
(305Fh)
5Eh *2
INCKSEL5 ― [7:0] 1Bh 1Ah 1Ah 1Ah 1Bh 1Bh 1Bh
(315Eh)
64h *2
INCKSEL6 ― [7:0] 1Bh 1Ah 1Ah 1Ah 1Bh 1Bh 1Bh
(3164h)

Register Hold Setting

Register setting can be transmitted with divided to several frames and it can be reflected globally at a certain frame
by the register REGHOLD. Setting REGHOLD = 1 at the start of register communication period prevents the
registers that are set thereafter from reflecting at the frame reflection timing. The registers that are set when setting
REGHOLD = 1 are reflected globally by setting REGHOLD = 0 at the end of communication period of the desired
frame to reflect the register.

Register Hold Setting Register

Register details (Chip ID = 02h)

Register Initial
Address Setting value
name Register bit value
( ) : I 2C
01h 0: Invalid
REGHOLD ― [0] 0h
(3001h) 1: Valid (Register hold)

FS (frame start) Blanking

FE (frame end) Communication period

Embedded data Communication prohibited period Register reflection timing

XVS

Packet
(CSI-2)

lines 6H 6H 6H 6H

REGHOLD=1 REGHOLD=0
Register setting A Register setting B Register setting C Register setting D
Register A Register B Register C
is not reflected. is not reflected. is not reflected.
Register A
Register B
Register C
Register D
are reflected.

Register Hold Setting

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Software Reset (CMOS parallel / Low voltage LVDS serial only)

This function is prohibited in CSI-2 output mode.
Software reset can be performed by register setting using the register SW_RESET.Sensor reset is performed by
setting SW_RESET = 1. However, the communication to continuous address cannot use. The registers become
initial state and standby 500 ns after setting SW_RESET = 1. The SW_RESET signal returns to "0" automatically.
The DOPA-H/DOMA-H/DCKP/DCKM terminal will be in the standby state (GND) of the CMOS output.
The XVS and XHS output High in master mode. Input High to the XVS and XHS before setting SW_RESET = 1 in
slave mode. Follow the sequence in the item of "Standby Mode" to perform register initial setting and standby cancel
from standby state.

Software Reset Register Setting

Register details (Chip ID = 02h)
Register Initial value Setting value
Address
name Register bit
( ) : I 2C
03h 0: Normal Operation
SW_RESET ― [0] 0h
(3003h) 1: Reset

Software Reset
SW_RESET = 1 Write
*The register value
SW_RESET automatically returns to 0.
500[ns]

XCE

4-wire SCK High

SDI DATA [7:0] Invalid

SCL High
2
IC
SDA ACK DATA [7:0] ACK Invalid High

DOP / DOM DATA Invalid Standby (CMOS output: GND)

XVS / XHS
High
(Slave mode）

XVS / XHS
High Invalid High
(Master mode）

Software Reset

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Mode Transitions
When changing the operating mode during sensor drive operation, set via sensor standby. However, these
transitions that described below can be transitions without standby.

◆ Change the number of vertical lines (In sensor master mode, change the VMAX. In sensor slave mode, change
the period of XVS input.)
◆ Horizontal and vertical scan direction. (When the vertical scan direction is changed, an invalid frame generates
during transition.)
◆ Change the HCG mode and LCG mode.
◆ Change the mode between All-pixel scan and Window cropping. (However, It is case that transitions by not
changing register HMAX and FRSEL. In addition, an invalid frame generates during transition.)

When changing input INCK frequency (register INCKSEL1, INCKSEL2, INCKSEL3, INCKSEL4, INCKSEL5,and
INCKSEL6 change) or when operating mode transition that changes output bit width (register ODBIT) or output
format (register OPORTSEL [3:0]), always start the operation via sensor standby after changing mode during
standby following the standby cancel sequence.

When changing input INCK frequency, care should be taken not to be input pulses whose width are shorter than the
High / Low level width in front and behind of the INCK pulse at the frequency change. If the pulses above generate at
the frequency change, change INCK frequency during system reset in the state of XCLR = Low, and then perform
system clear in the state of XCLR = High following the item of "Power on sequence" in the section of "Power on / off
sequence". Execute initial setting again because the register settings become default state after system clear.

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Power-on and Power-off Sequence

Power-on sequence
1. Turn On the power supplies so that the power supplies rise in order of 1.2 V power supply (DV DD) →1.8 V power
supply (OVDD) → 2.9 V power supply (AVDD). In addition, all power supplies should finish rising within 200 ms.
2. Start master clock (INCK) input after turning On the power supplies.
3. The register values are undefined immediately after power-on, so the system must be cleared. Hold XCLR at Low
level for 500 ns or more after all the power supplies have finished rising. (The register values after a system clear
are the default values.) In addition, hold XCE to High level during this period. Rise XCE after 1.8 V power supply
(OVDD).
4. The system clear is applied by setting XCLR to High level. However, the maser clock needs to stabilize before
setting the XCLR pin to High level.
5. Make the sensor setting by register communication after the system clear. A period of 20 µs or more should be
provided after setting XCLR High before inputting the communication enable signal XCE. In I2C communication,
XCE is fixed to High.

T2 2.9 V power supply (AVDD)

T0 T1
1.8 V power supply (OVDD)

1.2 V power supply (DVDD)

Input before power-On

INCK
is available.

Wait for the clock to stabilize

XCLR before setting XCLR High.

TLOW Standby mode cancel

I2C SDA Depend on the rising of Initial setting

SCL 1.8V power supply
TXCE Standby mode cancel
SDI Rise up after Initial setting
1.8V power is supplied
SCK
4-wire
Rise up after
XCE 1.8V power is supplied

In slave mode, hold the high impedance state until the power supplies have finished rising.
XVS
Hi-Z
XHS TSYNC

LP00 LP10 LP11 LP01 LP00 SoT

Streaming
Clock Lane
CSI-2
Output Data Lane LP00 LP10 LP11 LP01 LP00 SoT
2/4 LANE
ULPS INIT
ULPS
exit Master

Power-on Sequence

Item Symbol Min. Max. Unit

1.2 V power supply rising → 1.8 V power supply rising T0 0 ― ns
1.8 V power supply rising → 2.9 V power supply rising T1 0 ― ns
Rising time of all power supply T2 ― 200 ms
INCK active → Clear OFF TLOW 500 ― ns
Clear OFF → Communication start TXCE 20 ― µs
Standby OFF (communication)
TSYNC 20 ― ms
→ External input XHS,XVS (slave mode only)

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Power-off sequence
Turn Off the power supplies so that the power supplies fall in order of 2.9 V power supply (AVDD) → 1.8 V power
supply (OVDD) → 1.2 V power supply (DVDD). In addition, all power supplies should falling within 200 ms. Set each
digital input pin (INCK, XCE, SCK, SDI, XCLR, XMASTER, OMODE, XVS, XHS) to 0 V before the 1.8 V power
supply (OVDD) falls.

T6
2.9 V power supply (AVDD)
T4 T5
1.8 V power supply (OVDD)

1.2 V power supply (DVDD)

INCK

Fixed to the high impedance state or 0 before

XCLR the power supplies have finished fowling.
TCLR

SDA Depend on the falling of

I2C Standby-On 1.8V power supply
SCL TSTB
SDI
Standby-On
SCK
4-wire
XCE

XVS Fixed to 0 before

XHS the power supplies have finished fowling.

Streaming
Clock Lane LP11 ULPS LP00

Data Lane LP11 ULPS LP00

2/4 LANE

Power-off Sequence

Item Symbol Min. Max. Unit

Standby ON (communication) → LP11 mode start TSTB Until FE ―
LP00 → XCLR falling TCLR 128 ― cycle
2.9 V power shut down → 1.8 V power shut down T4 0 ― ns
1.8 V power shut down → 1.2 V power shut down T5 0 ― ns
Shut down time of all power supply T6 ― 200 ms

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Sensor Setting Flow

Setting Flow in Sensor Slave Mode
The figure below shows operating flow in sensor slave mode.
For details of "Power-on" to "Reset cancel", see the item of "Power-on sequence" in this section.
For details of “Standby cancel" until "Wait for image stabilization", see the item of "Standby mode".
“Standby setting (power save mode) can be made by setting the STANDBY register to “1” during “Operation”.

Start

Pin settings

Power-on
INCK input before
power-on is available.
INCK input

System clear
XCLR pin : Low High

Change to settings
after standby release Register settings

Standby cancel
STANDBY=0 Standby setting
(power save mode)
Wait for internal regulator stabilization STANDBY=1

XVS and XHS input start

XVS and XHS input
Wait for image stabilization stop

Register changes
Shutter
Gain Operation
Other

Sensor Setting Flow (Sensor Slave Mode)

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Setting Flow in Sensor Master Mode

The figure below shows operating flow in sensor master mode.
For details of "Power-on" to "Reset cancel", see the item of "Power on sequence" in this section.
For details of “Standby cancel" until "Wait for image stabilization", see the item of "Standby mode".
In master mode, “Master mode start” by setting register XMSTA to “0” after “Waiting for internal regulator
stabilization”
“Standby setting (power save mode) can be made by setting the STANDBY register to “1” during “Operation”. This
time, set "master mode stop" by setting XMSTA to "1".

Start

Pin settings

Power-on
INCK input before
power-on is available. INCK input

System clear
XCLR pin : Low High

change to settings Register settings

after standby release

Standby cancel
STANDBY=0
Master mode stop
Wait for internal regulator stabilization XMSTA=1

Master mode start

XMSTA=0
Standby setting
XVS and XHS output start (power save mode)
STANDBY=1
Wait for image stabilization
Register changes
Shutter
Gain Operation
Other

Sensor Setting Flow (Sensor Master Mode)

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Peripheral Circuit

Analog 2.9V Digital 1.2V Digital 1.8V

0.01µF / 4.7µF
0.01µF / 1.0µF

0.01µF / 1.0µF
0.1µF / 1.0µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF

0.1µF / 4.7µF
A7 A9 A4 A8 A6 M11 D11 K8 K5 E8 E4 K7 K6 M1

VDDMIF
VDDHCP

VDDHAN

VDDHAN

VDDHPX

VDDHPX

VDDLCN

VDDLCN

VDDLSC

VDDLSC

VDDLSC

VDDLSC

VDDLIF

VDDLIF

DLOPx/DLOMx
PLL LVDS/CMOS
V
Pixel
Ramp Scan

DMOxP/DMOxN
Comp Counter
BIAS Logic

D-PHY
Digital
I/F
CP
VSSHCP

VSSHAN
VSSHAN

VLOADLM
VSSHPX
VSSHPX
VSSHPX

VSSLCN
VSSLCN

VSSLSC
VSSLSC
VSSLSC
VSSLSC
VSSLSC
VSSLSC
VSSLSC

VSSMIF
VSSMIF
VSSMIF
VSSMIF
VSSMIF
VSSMIF
VSSMIF
VSSLIF
VSSLIF
VSSLIF
VSSLIF
VSSLIF
VSSLIF
VSSLIF
VRLFR
VRLST

VBGR

INCK
B7 A5 B5 B9 B4 C11 B8 B6 B3 A3 M10 D10 N3 L11 L8 L5 E10 D8 D4 P3 M9 M8 M7 M6 M5 L7 L6 M3 M2 L3 K3 E3 D3 C3
0.22µF

1.0µF
1µF

1µF

Common GND
Digital 1.8V
CMOS parallel output LVDS serial output CSI-2 serial output

C2 DLOPA OPEN C2 DLOPA +

100Ω
7ch
2
C1 DLOMA OPEN C1 DLOMA -
I C serial XCE G11
1kΩ

1kΩ

communication D2 DLOPB DO0 D2 DLOPB + N5 DMOPC +

100Ω
SCK G10 5ch MIPI 3Lane
D1 DLOMB DO1 D1 DLOMB - P5 DMOMC -

SDI H10 OPEN

F10 SDO
E2 DLOPC DO2 E2 DLOPC + N6 DMOPA +

100Ω
3ch MIPI 1Lane
E1 DLOMC DO3 E1 DLOMC - P6 DMOMA -

XCE G11
4-wire serial F2 DLOPD DO4 F2 DLOPD + N7 DMCKP +
100Ω

communication SCK G10 1ch Clock lane

F1 DLOMD DO5 F1 DLOMD - P7 DMCKM -

SDI H10 F10 SDO

G2 DLCKP DLCKP G2 DLCKP + N8 DMOPB +
100Ω

Clock MIPI 2Lane

Digital
I/F G1 DLCKM OPEN G1 DLCKM -
P8 DMOMB -
XHS L10 J11 TOUT OPEN

H2 DLOPE DO6 H2 DLOPE + N9 DMOPD +

XVS H11
100Ω

C10 TAMON
OPEN 2ch MIPI 4Lane
H1 DLOME DO7 H1 DLOME -
P9 DMOMD -

OMODE J10
J2 DLOPF DO8 J2 DLOPF +
100Ω

XMASTER F11 4ch

J1 DLOMF DO9 J1 DLOMF -

XTRIG K11
K2 DLOPG DO10 K2 DLOPG +
100Ω

XCLR K10 6ch

K1 DLOMG DO11 K1 DLOMG -

TENABLE E11
OPEN L2 DLOPH OPEN L2 DLOPH +
100Ω

8ch
L1 DLOMH OPEN L1 DLOMH -

Terminal resistance: 100 Ω

Isometric wiring of differential signal

Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits or for
any infringement of third party and other right due to same.

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Spot Pixel Specifications

(AVDD = 2.9 V, OVDD = 1.8 V, DVDD = 1.2 V, Tj = 60 ˚C, 30 frame/s, Gain: 0 dB)

Maximum distorted pixels in each zone Measurement

Type of distortion Level Effective Ineffective Remarks
0 to II' III method
OB OB
Black or white No evaluation
30 % < D 15 1
pixels at high light criteria applied

White pixels No evaluation

5.6 mV < D 150 2 1/30 s storage
in the dark criteria applied

Black pixels at No evaluation

D < 730 mV 0 3
signal saturated criteria applied

Note) 1. Zone is specified based on all-pixel drive mode

2. D Spot pixel level
3. See the Spot Pixel Pattern Specifications for the specifications in which pixel and black pixel are close.

Zone Definition
TBD

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Notice on White Pixels Specifications

After delivery inspection of CMOS image sensors, cosmic radiation may distort pixels of CMOS image sensors,
and then distorted pixels may cause white point effects in dark signals in picture images. (Such white point
effects shall be hereinafter referred to as "White Pixels".) Unfortunately, it is not possible with current scientific
technology for CMOS image sensors to prevent such White Pixels. It is recommended that when you use CMOS
image sensors, you should consider taking measures against such White Pixels, such as adoption of automatic
compensation systems for White Pixels in dark signals and establishment of quality assurance standards.
Unless the Seller's liability for White Pixels is otherwise set forth in an agreement between you and the Seller,
Sony Corporation or its distributors (hereinafter collectively referred to as the "Seller") will, at the Seller's
expense, replace such CMOS image sensors, in the event the CMOS image sensors delivered by the Seller
are found to be to the Seller's satisfaction, to have over the allowable range of White Pixels as set forth as set
forth above under the heading "Spot Pixels Specifications", within the period of three months after the delivery
date of such CMOS image sensors from the Seller to you; provided that the Seller disclaims and will not
assume any liability after if you have incorporated such CMOS image sensors into other products.
Please be aware that Seller disclaims and will not assume any liability for (1) CMOS image sensors fabricated,
altered or modified after delivery to you, (2) CMOS image sensors incorporated into other products, (3) CMOS
image sensors shipped to a third party in any form whatsoever, or (4) CMOS image sensors delivered to you
over three months ago. Except the above mentioned replacement by Seller, neither Sony Corporation nor its
distributors will assume any liability for White Pixels. Please resolve any problem or trouble arising from or in
connection with White Pixels at your costs and expenses.

[For Your Reference] The Annual Number of White Pixels Occurrence

The chart below shows the predictable data on the annual number of White Pixels occurrence in a single-story
building in Tokyo at an altitude of 0 meters. It is recommended that you should consider taking measures against
the annual White Pixels, such as adoption of automatic compensation systems appropriate for each annual
number of White Pixels occurrence.
The data in the chart is based on records of past field tests, and signifies estimated number of White Pixels
calculated according to structures and electrical properties of each device. Moreover, the data in the chart is
for your reference purpose only, and is not to be used as part of any CMOS image sensor specifications.

Example of Annual Number of Occurrence

White Pixel Level (in case of integration time = 1/30 s)
Annual number of occurrence
(Tj = 60 ℃)

5.6 mV or higher TBD pcs

10.0 mV or higher TBD pcs
24.0 mV or higher TBD pcs
50.0 mV or higher TBD pcs
72.0 mV or higher TBD pcs

Note 1) The above data indicates the number of White Pixels occurrence when a CMOS image sensor is left
for a year.
Note 2) The annual number of White Pixels occurrence fluctuates depending on the CMOS image sensor storage
environment (such as altitude, geomagnetic latitude and building structure), time (solar activity effects)
and so on. Moreover, there may be statistic errors. Please take notice and understand that this is an
example of test data with experiments that have being conducted over a specific time period and in
a specific environment.
Note 3) This data does not guarantee the upper limits of the number of White Pixels occurrence.

For Your Reference:

The annual number of White Pixels occurrence at an altitude of 3,000 meters is from 5 to 10 times more than that
at an altitude of 0 meters because of the density of the cosmic rays. In addition, in high latitude geographical areas
such as London and New York, the density of cosmic rays increases due to a difference in the geomagnetic
density, so the annual number of White Pixels occurrence in such areas approximately doubles when compared
with that in Tokyo.

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Measurement Method for Spot Pixels

After setting to standard imaging condition II, and the device driver should be set to meet bias and clock voltage
conditions. Configure the drive circuit according to the example and measure.

1. Black or white pixels at high light

After adjusting the luminous intensity so that the average value VG of the Gb / Gr signal outputs is 650 mV,
measure the local dip point (black pixel at high light, ViB) and peak point (white pixel at high light, ViK) in the Gr /
Gb / R / B signal output Vi (i = Gr / Gb / R / B), and substitute the value into the following formula.

Spot pixel level D = ((ViB or ViK) / Average value of Vi) × 100 [%]

White pixel
ViB
ViK
Vi (i = R, G, B, VG = 650 mV )
Black pixel

Signal output waveform of R / G / B channel

2. White pixels in the dark

Set the device to a dark setting and measure the local peak point of the signal output waveform, using the
average value of the dark signal output as a reference.

3. Black pixels at signal saturated

Set the device to operate in saturation and measure the local dip point, using the OB output as a reference.

Level D Black pixel Vsat (Min = 914 mV )

OB output

Signal output waveform of R/G/B channel

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Spot Pixel Pattern Specification

White Pixel, Black Pixel and Bright Pixel are judged from the pattern whether they are allowed or rejected, and
counted.

List of White Pixel, Black Pixel and Bright Pixel Pattern

R G
White pixel
It provides by color filter
No. Pattern Black pixel
G B array described in the left.
Bright pixel

1 ● ● Same color Rejected

●
2 Same color Rejected
●

Note) 1.”●” shows the position of white pixel, black pixel and bright pixel.
White pixel, black pixel and bright pixel are specified separately according the pattern.
(Example: If a black pixel and a white pixel is in the pattern No.1 respectively, they are not judged to
be rejected.)
2. When one or more spot pixels indicated “Rejected” is selected and removed.
3. Spot pixels other than described in the table above are all counted including the number of allowable
spot pixels by zone.

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Marking (Tentative)

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Notes On Handling

1. Static charge prevention

Image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
(1) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
(2) Use a wrist strap when handling directly.
(3) Install grounded conductive mats on the floor and working table to prevent the generation of static
electricity.
(4) Ionized air is recommended for discharge when handling image sensors.
(5) For the shipment of mounted boards, use boxes treated for the prevention of static charges.

2. Protection from dust and dirt

Image sensors are packed and delivered with care taken to protect the element glass surfaces from
harmful dust and dirt. Clean glass surfaces with the following operations as required before use.
(1) Perform all lens assembly and other work in a clean environment (class 1000 or less).
(2) Do not touch the glass surface with hand and make any object contact with it.
If dust or other is stuck to a glass surface, blow it off with an air blower.
(For dust stuck through static electricity, ionized air is recommended.)
(3) Clean with a cotton swab with ethyl alcohol if grease stained. Be careful not to scratch the glass.
(4) Keep in a dedicated case to protect from dust and dirt. To prevent dew condensation, preheat or
precool when moving to a room with great temperature differences.
(5) When a protective tape is applied before shipping, remove the tape applied for electrostatic
protection just before use. Do not reuse the tape.

3. Installing (attaching)
(1) If a load is applied to the entire surface by a hard component, bending stress may be generated
and the package may fracture, etc., depending on the flatness of the bottom of the package.
Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.
(2) The adhesive may cause the marking on the rear surface to disappear.
(3) If metal, etc., clash or rub against the package surface, the package may chip or fragment and
generate dust.
(4) Acrylate anaerobic adhesives are generally used to attach this product. In addition, cyanoacrylate
instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives to hold
the product in place until the adhesive completely hardens. (Reference)
(5) Note that the sensor may be damaged when using ultraviolet ray and infrared laser for mounting it.

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4. Recommended reflow soldering conditions

The following items should be observed for reflow soldering.
(1) Temperature profile for reflow soldering
Control item Profile (at part side surface)
150 to 180 °C
1. Preheating
60 to 120 s
2. Temperature up (down) +4 °C/s or less (– 6 °C/s or less)
Over 230 °C
3. Reflow temperature 10 to 30 s
Max. 5 °C/s
4. Peak temperature Max. 240 ± 5 °C

Temperature

Peak 240 ± 5 °C

230 °C
Max. 5 °C/s
180 °C – 6 °C/s or less
10 to 30 s
150 °C
+4 °C/s
or less 60 to 120 s

Preheating Reflow
Time

(2) Reflow conditions

(a) Make sure the temperature of the upper surface of the seal glass resin adhesive portion of the
package does not exceed 245 °C.
(b) Perform the reflow soldering only one time.
(c) Finish reflow soldering within 72 h after unsealing the degassed packing.
Store the products under the condition of temperature of 30 °C or less and humidity of
70 % RH or less after unsealing the package.
(d) Perform re-baking only one time under the condition at 125 °C for 24 h.
(3) Others
(a) Carry out evaluation for the solder joint reliability in your company.
(b) After the reflow, the paste residue of protective tape may remain around the seal glass.
(The paste residue of protective tape should be ignored except remarkable one.)
(c) Note that X-ray inspection may damage characteristics of the sensor.

5. Others
(1) Do not expose to strong light (sun rays) for long periods, as the color filters of color devices will
be discolored.
(2) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage
or use in such conditions.
(3) This product is precision optical parts, so care should be taken not to apply excessive mechanical
shocks or force.
(4) Note that imaging characteristics of the sensor may be affected when approaching strong
electromagnetic wave or magnetic field during operation.
(5) Note that image may be affected by the light leaked to optical black when using an infrared cut
filter that has transparency in near infrared ray area during shooting subjects with high luminance.

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Package Outline (Tentative)

(Unit: mm)

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List of Trademark Logos and Definition Statements

* Exmor R is a trademark of Sony Corporation. The Exmor R is a Sony's CMOS image sensor with significantly enhanced imaging
TM
characteristics including sensitivity and low noise by changing fundamental structure of Exmor pixel adopted column parallel A/D converter
to back-illuminated type.

* STARVIS is a trademark of Sony Corporation. The STARVIS is back-illuminated pixel technology used in CMOS image sensors
2
for surveillance camera applications. It features a sensitivity of 2000 mV or more per 1 μm (color product, when imaging
2
with a 706 cd/m light source, F5.6 in 1 s accumulation equivalent), and realizes high picture quality in the visible-light and
near infrared light regions.

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Revision History

Date of Revision Page Contain of Change

change
5-Sep-14 0.1 - First edition
24-Sep-14 0.2 1 Updated “Features”
8,12,14,
15,17,22,
41,50,51
56,63,70
24-Sep-14 0.2 correction of errors
77,83,84
86,89,90
94,95,96,
100,101,
30-Oct-14 0.3 35 to 48 Updated “Register Map”
56 to 58
30-Oct-14 0.3 63 to 65 correction of errors
70 to 72
30-Oct-14 0.3 80 Added Figure “Gain Reflection Timing”
12-Nov-14 0.4 102 Updated “Peripheral Circuit”
2-Feb-15 0.5 1 Updated “Features “
2-Feb-15 0.5 15 Updated “Current Consumption “
2-Feb-15 0.5 23 Updated “Spectral Sensitivity Characteristics “
2-Feb-15 0.5 24 Updated “Image Sensor Characteristics “
2-Feb-15 0.5 26 Updated “Measurement Method “
2-Feb-15 0.5 35 to 49 Updated “Register Map “
2-Feb-15 0.5 61 Updated “Drive Timing Chart “
2-Feb-15 0.5 57,58,64,65,71,72 Updated “List of Setting Register “
2-Feb-15 0.5 80 Updated “Gain Adjustment Function “
2-Feb-15 0.5 86 Updated “Example of Integration Time Settings “
2-Feb-15 0.5 104 Updated “Spot Pixel Specifications “
2-Feb-15 0.5 106 Updated “Measurement Method for Spot Pixels “

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