337(S)

December 2019

COMPUTER ORGANISATION
& ARCHITECTURE
Time Allowed: 3 Hours Full Marks: 70
Answer to Question No.1 is compulsory
This answer is to be made in separate and to be answered iirst.
loose script(s) provided for the purpose
Maximum time allowed is 45 minutes, after nd
which the loose answer scripts will be coleccted
fresh answer scripts for answering the remaining
part of the question will be proviat
On early submission of answer scripts of Question No.l,
a student will get the remaining script earlier.
Answer any fivequestions from the rest.
1. A Choose the correct answer from the given alternatives (any
ten):
10xl

Which of the following comment about the IR is true? -a) It is used to count the number
of instructions, b) It is a cell in ROM, c) During execution of the current instruction, ls
content changes, d) Opcode fetched from memory stored in IR

ii) The speed imbalance between memory access & CPU operation can be reduccd by
a) Cache memory, b) memory interleaving, c) reducing memory size, d) virtual memory.

ii) The sequence of cvents that happen during a typical fetch operation is
a) PC-MDR-Memory-IR, b) PCMARMEMORY-MDR--IR, c)
PC--MEMORY-IR, d) MAR-MDR-IR.
iv) Negative numbers can be represented in - a) Sign-magnitude form, b) 1's complemented
form, c) 2's complemented form, d) all of the above.

v) The instruction ADD is address instruction. -a) 0, b) 1, c) 2, d) 3.

vi) The exponent of a floating point number is represented in excess-N code (biased) sothat
a) the dynamic range is large, b) the precision is high, c) the smallest number is
represented by all zeroes, d) overflow is avoided.

vii) If negative numbers are stored in 2's complemented form, the range of numbers that can
be stored in 8 bits is-a) -128 to +128, b) -128 to +127, c)-127 to +128, d) -127 to +127.

viii) The three main components of a digital computer system are - a) Memory, I0, DMA,
b) ALU, CPU, Memory, c) CPU, Memory, 10, d) Control Unit, ALU, Register.

ix) The cost of storing a bit is minimum in -

a) Cache memory, b) Register, c) RAM, d) Hard
disk.

X) Which of the following statement(s) is true? a) ROM is a read/write memory, b) PC

-

points to the last instruction that was executed, c) Stack works on the principle of FIFO,
d) RAM is a Read/Write memory.

xi) Tera is 2 to the power of-a) 9, b) 20, c) 30, d) 40.

xii) In immediate addressing the operand is placed-a) in the CPU register, b) after OP code in
the instruction, c) in memory, d) in stack.

B. Answer the following questions (any five): 5x2

1) What is write through policy?

ii) What is supercomputer?
 iin) What is TLB?
interrupt?
iv) What do you mean by vectored
is the function of 1O
processor?
v) What
Buffer?
vi) What do you mean by Loop
Replacement Algorithm?
vin) What do you mean by

suitable example.
2. Describe the following addressing modes with 10
addressing mode, (11) Indexed addressing mode
ode, (iv) Based
1) Direct addressing mode, (ii) Indirect
addressing mode, (v) Implied addressing mode.
architectural diagram.
3 ) Describe Booth's algorithm with suitable
implemented?
b) Explain how priority of interrupt will be 6+4

diVision of integer numbers

a) Write down the flowchart of both restoring and non-restoring
b) Write down the features of RISC architecture. 6+4

memory.
5. a) Explain different types of mapping technique used in cache
b) How hit ratio depends on different types of mapping. 6+4

6. a) Explain the representation of floating point number in computer. Describe the IEEE fomat also
) What is NaN in floating point number representation? Give example. 4+3+3

a) Explain the difference between Hardwired Control and Micro-programmed control.

b) Explain the organization of control memory in Micro-programmed control with diagram. 4+6

8. a) Describe DMA mode of data transfer in details with suitable diagram.

b) RISC architecture is more suitable for pipcline implementation-explain. 5+5

9. a) Discuss Flynn's classification in details.

b) Explain instruction pipeline with suitable example and diagram. S+5

10 Write short notes on the followings (any two): 5+5

a) Generations of computer
b) Space time diagram
Array processor
d) Virtual memory

2
 December 2018 337(S)

COMPUTER ORGANISATION
& ARCHITECTURE
Time Allowed: 3 Hours
Full Marks: 70
Answer to Question No.1 is
This answer is to be made in compulsory and to be answered first.
separate loose script(s) provided purpose.
Maximum time allowed is 45 minutes, for
answer after which the loose answer scripts the
fresh scripts for answering the will be collected and
remaining
On early submission of answer part of the question will be provided.
a student will get the scripts of Question No.l,
remaining seript earlier.
Answer any fivequestions from
the rest.
1. A. Choose the correct answer from
the given alternatives (any ten):
Ix10 10
i) A typical modern computer
uses (a) LSI chip (b) VLSI chip (c) valves (d) vacuum tube.
ii) A Subtractor is not usually
present in a computer because (a) it is expensive (b) it is not
possible to design it (c) the adder will
take care of subtraction (d) none of the above.
iii) The instruction 0101 111100001100 is
a (a) direct memory reference instruction
() indirect memory reference instruction (c) register reference instruction (d) input output
instruction.

iv) In auto increment addressing mode,

the value of the register is incremented by 1
.
the execution of the instruction. (a) before (b)
after (c) during (d) not in the Iist.
01110010 represents (a) 0 (b) NaN (¢) +co (d) -o

vi) If we want an addition/subtraction circuit to do subtraction, the initial value of carry in

should be (a) -1 (b) 0 (c) 1 (d) 2.

vii) Virtual memory is(a) primary memory (b) secondary memory (c) both a & b (d) none of
these.

viii) Direct mapping is (a) one to one mapping (b) many to many mapping (c) many to one
mapping (d) all of these.

ix) In associative mapping technique, number of comparators required is (a) 1 (6) 2 (c) equal
to the number of blocks in main memory (d) equal to the number of lines in cache
memory.

In which addressing mode is operand specified in the instruction itself?a) Register mode
b) Immediate mode c) Direct Address mode d) Index Addressing mode.

xi) In Booth's algorithm, if the multiplier has n bits then the multiplicand should have (a) 1
bit
(b) n bits (c) n+1 bits (d) 2n bits.

B. Answer any five questions: Sx2=10

i) Write the IEEE format for single precision number.

ii) Why is biased exponent used in computation?
iii) What is Program Counter?
iv) What is L2 cache?
v) What is Opcode?
vi) What is the minimization of pipeline?
 o
2. a) Draw the block diagram of Von Ncumann computer arclhiteclure and explain the function of ca-
part.
b) Write short note on ALU.

3 a) What is the One address instruction?

b) Write one address instruction code to execute X=(A+B)*(C+D)
3+

4. 2) What is addressing mode?

b) Explain the different addressing modes?
. a) Convert and represent the decimal number 0.5624 in loating point representation using 8 bits.
O) Draw the Addition-Subtraction unit block diagram. 6+-

6. a) Divide Q11010 (dividend) by M=110 (divisor) using restoring division method.

) Show the steps of multiplication performed by using Booth's algorithm of 1011x10011.

7. a) What is hit ratio? If numbers of hits are cqual to 10 & if numbers of misses are equal to 4 then
the hit ratio? i
b) "Hit ratio is better in set-ass ociative mapping than in direct mapping of cache" Is it corce
Explain. (2+3)+-

8. a) Write a short note on RISC pipeline.

b) Write a short note on Vector processing.
 337(S)
December 2017

CoMPUTER OrGANISATION & ArCHITECTURE

Time Allowed: 3 Hours Full Marks: 70

Answer to Question No.1 is compulsory and to be answered first.

This answer is to be made in separate loose script(s) provided for the purpose.
Maximum time allowed is 45 minutes, after which the loose answer seripts will be collected and
fresh answer scripts for answering the remaining part of the question will be provided.
On early submission of answer scripts of Question No.1,
a student will get the remaining script earlier.

Answer any five questions from the rest.

1. A. Choose the correct answer from the given alternatives (any ten): 1x10

The three main components of a digital computer system are (a) Memory, 10, DMA
(b) ALU, CPU, Memory (c) CU, ALU, Register (d) CPU, Memory, IO.

11) The second generation of computer used (a) transistors (b) IC (¢) vacuum tube (d) LS.

iii) Processors of all computers, whether micro, mini or mainframe must have a) ALU
(6) Primary storage (c) Control Unit (d) all of these.

iv) In Which addressing mode is operand specified in the instruction itself? (a) Register mode
(b) Immediate mode (c) Direct Address mode (d) Index Addressing mode.

v The instruction LOAD is a (a) zero-address instruction (b) one-address instruction (c) two0-
address instruction (d) three-address instruction.

vi) The number of fetch operation to execute instruction inimm

immediate mode is (a) 0 (6) 1 (c) 2
(d) none of these.

vii) The instruction 1111 I11100001100 is a (a) direct memory reference instruction
b) indirect memory reference instruction (e) register reference instruction (d) input output
instruction.

vii) 01110000 represents (a) 0 (b) NaN (¢) +o (d) -oo,

ix) The largest floating point number that can be represented by 8 bit is (a) 01111111
(b) 11111111 (c) 01101111 (d) 01111110.

If n is number of bits in exponent, the bias number can be calculated as (a) 2-1 (b) 2"
(c) 2 (d) 2-1.
xi) In Booth's algorithm, if the multiplier has n bits then the multiplicand should have (a) 1
bit
(b) n bits (c) n+1 bits (d) 2n bits.

xii) k-way set associative means (a) k blocks are present in a set (b) k sets are present in a
block (c) k sets are present in the cache (d) none of these.

B. Answer the following questions (any five): 5x2

) What is a super computer?

How does a computer differ from a calculator?
 iii) What is bus?
iv) What do you mean by Effective Address7
What is Program Counter?
vi) What is 10 processor?
vii) Write full form of RISC and CISC.

fiunctin
Draw a block diagram of
CPU and explain the function of cach part. What are the ess bus,
data bus and control bus? 6+4
by Instruction Format? Write two address instruction cod
What do you understandAccumulator?
X=(A+B) °(C+D). What is 3+5+2

. what is biased exponent? Represent

indirect addresses?
0.l2 in tloating point representation using 8 bit. What are
dircct &
2+5+3
the steps of multiplication performed h
for Booth's Algorithm. Show
Draw and explain the flow chart
using Booth's algorithm of-6x7. S+5

process. Show the restoring division steps of 12/3.

6. Write the algorithm of Restoring Division 5+5

of cache direct mapping? If in a byte addressable system

What is Cache memory? What is the advantage memory block size is KB. find 1
size is 32 KB and main
the main memory size is 32 GB, associative cache
the number of tag bits in the physical address. 2+2+6

control. What is horizontal

S. Differentiate between hardwired control and micro programmed
microprogramming? Explain the functions of control memory. 2+3

Explain it
9. Explain Flynn's classification of computers. What is instruction pipeline? with the
5+5
flowchart
 337(S)
December 2016

COMPUTER OrGANISATION & ARCHITECTURE

Time
Allowved: 3 Hours Full Marks: 70

Answer to Question No.1 is compulsory and to be answered

This answer is to be made in separate irst.
loose seript(s) provided for the purpose
Maximum time allowed is 45 minutes, after which the loose answer
scripts willDE
fresh answer seripts for answering the remaining part of the question will be provided.
On early submission of answer scripts
of Question No.l,
a student will get the remaining seript earlier.
Answer any five questions from the rest.

1. A. Choose the correct answer from the given alternatives: 10x

i) Which of the following statement is true about cache memory? (a) It is used to increase
-

the memory size, (b) It is used to decrease the memory size, (c) It decreases the overal
pertormance of the CPU, (d) It minimizes the speed gap between CPU and main memory

i) MAR stands for (a) Memory Access Register, (b) Memory Address Register,
(c) Memory Access Reference, (d) Memory Address Reterence.

ii) Exponent in floating point number can be represented by (a) Sign-magnitude torm,
(D)'s complemented form, (c) 2's complemented form, (d) biased form.

iv) Which of the following has least number of instructíons? - (a) RISC, (b) CISC, () Both a
and b, (d) XISC.

v In this mode, the address of the operand is not specified explicitly

(b) Indirect, (c) Relative, (d) Stack.
- (a) Indexed,

vi) The start/stop bit combination is used in (a) Synchronous Transmission,

(6) Asynchronous Transmission, (c) Both a and b, (d) Handshake mode.

vii) If negative numbers are stored in 2's complemented form, the range of numbers that can
be stored in 16 bits is -(a) -128 to +128, (b)-128 to +127, (c) -127 to +127, (d)-32768
to +32767.

viii) Which one is fastest?- (a) Cache memory, (6) CPU Registers, (c) RAM, (d) Hard disk
drive.

ix) Cache memory uses - (a) SRAM, (b) DRAM, (0) EEPROM, (d) EPROM.

Replacement algorithm is not necessary 1s-(a) Associative mapping, (b) Set associative
mapping, (c) Direct mapping, (d) All of the above.

B. Answer the following questions (any five): 5x2

What is vectored interrupt?

1) What is Flynn's Classification?
iin) What is paging
V) Write down the instruction format.
) What is Hit Ratio?
V1) What is the function of TLB?
VIi) What do you mean by effective address?
 Describe the following addressing modes with suitable example: Sx2

) Register addressing mode

ii) Indirect addressing mode
iin) Indexed addressing mode
IV) Base addressing mode
v) Immediate addressing mode

3. and flowchart.
a)
b)
escrbe Booth's algorithm with suitable block diagram
Booth's algorithm of 7X -5. 6+4
Snow the steps of multiplication performed by using
d)
Xplan the difference between Hardwired Control and Microprogrammed control.
b) do you mean by horizontal and vertical microprogramming?
compare these two ways of
wat
microprogramming. S+5

. a)
b)
Explain different types of mapping technique used in cache memory
6+4
Differentiate virtual memory and cache memory.

6. What do you mean by pipeline hazards/conflicts? Discuss the different types ot hazards being observed
and also explain the possible solutions. 2+8

) What are the major charact istics of RISC architecture?

b) What do you mean by speedup ratio? What are the reasons for which theoretical maximum
speedup cannot be obtained in reality? 2+3

8. Differentiate programmed IO and Interrupt briefly.

Describe DMA mode of data transfer in details with suitable diagram. 4+6

9. Write short notes on the followings (any two): 5+5

a) 1O processor
b) Vector Processing
C) Memory Interleavng
d) Loop Buffer

2
 337(S)
December 2015

COMPUTER OrGANIZATION & ARCHITECTURE

Time Allowved: 3 Hours Full Marks: 70

Answer to Question No.l is compulsory and to be answered first.
This answer is to be made in separate loose script(s) provided for the purpose.
Maximum time allowed is 45 minutes, after which the loose answer scripts will be collected and
fresh answer scripts for answering the remaining part of the question will be provided.
On early submission of answer scripts of Question No.l,
a student will get the remaining seript earlier.
Answer any five questions from the rest.
. Choose the correct answer (any twenty): 20x1

Which of the following comment about the program counter is true?- (a) It is used to count the no
ot instructions, (6) It is a cell in ROM, (c) During execution of the current instruction, its content
changes, (d) None of the above.

11) he speed imbalance between memory access & CPU operation can be reduced by -
(a) Cache
memory, (b) memory interleaving, (c) reducing memory size, (d) none of the above.

iii)
ne Sequence of events that happen during a typical fetch operation is (a)
PCMDR-Memory-IR, (b) PC-MAR--MEMORY-MDR-IR, (¢) PC--MEMORY-IR,
MARMDR--IR
d)

iv) Negative numbers cannot be represented in a) Sign-magnitude form b) 1's complemented form
c) 2's complemented form none of the above.

N) The addressing mode used in an instruction of the form ADD X,Y is a) absolute register b)
immediate c) indirect d) index.

Vi) Any instruction should have at least a) 3 operands b) 2 operands c)1 operand d)none of the
above.

vii) Which of the followi rule(s) regarding the addition of 2 given numbers in 2's complement is
Correct a) Add sign bit and discard carry, if any b}Add sign bit and add carry, if any C)
don't Add sign bit and discard carry, if any d) Don't Add sign bit and add carry, if any.

viii) The exponent of a floating point number is represented in excess-N code (biased) so that a)
the dynamic range is large b) the precision is high c) the smallest number is represented by all
zeroes d) overflow is avoided.

IX) If negative numbers are stored in 2's complemented form, the range of numbers that can be stored
in 8 bits is a) -128 to +128 b)-128 to +127 c-127 to + 128 d)-127 to + 127.

X) The three main components of a digital computer system are a) Memory, 1o, DMA b) ALU,
CPU, Memory c) CPU, Memory, I10 d) Control Unit, ALU, Register.

Ki) A subtractor is not usually present in a computer because a) it is expensive b) it is not possible
to design it c)the adder will take care of subtraction d) none of the above.

xii) The cost of storing a bit is minimum in a) Cache memory b) Register c) RAM d) Tape.

xii) Which of the following statement(s) is true'? a) ROM is a read/write memory b) PC points to
the last instruction that was executed c) Stack works on the principle of LIFO d) RAM is a
Rcad/Write memory.
 xiv) Giga is 2 to the power of a) 10 b) 20 c)30 d)40
in the CPU register,
(b) after OP code in
placed (a) the
s

xv) in immediateaddressing the operand is

instruction, (c) memory,
in (d) in stack.

mini or mainirame must have (a) ALL ime Allc

xvi) Processors of all computers, whcther micro,
(6) Registers, (c) Control unit, (d) All of above.

xV11)nstruction incomputer languages consists of

- (a) OPCODE, (6) OPERAND, (c) Both of abou
oove,
M
(d) Nonc of above.
- (a) Cache memory, (b) Virtual memory, (C) Primary memory, (d) All ot
XVin) TLB is associated with
the above.
(5) CISC architecture, (c) Hybrid
xix) Pipeline architecture is more suitable for- (a) RISC architecture,
architecture, (d) All of the above.
device, (c) both (a
xx) As per CPU concern Hard disk drive is - (a) type of Memory, (b) peripheral
and (b), (d) none of the above.

xxi) Exponent in floating point number can be represented by (a) Sign-magnitude form, (b) 1's
-

complemented form, (c) 2's complemented form, (d) biased form.

2 Draw the block diagram of CPU and explain the execution of typical instruction through different section
of CPU. 4+6

10
3. Describe the following addressing modes with suitable example.
(a) Direct addressing mode, (b) Indirect addressing mode, (c) Indexed addressing mode, (d) Base
addressing mode, (e) Implied addressing mode.

4. a) Describe mapping techniques of cache memory.

b) How hit ratio depends on different types of mapping? 7+3

5. a) Describe Booth's algorithm with suitable architectural diagram.

b) Show the steps of multiplication performed by using Booth's algorithm of -7 X 5. 5+5

6. a) Write down the flowchart of both restoring and non-restoring division of integer numbers
b) Show the non-restoring division steps of 11+3. 6+4

7. a) Describe the different generation of computer

b) Discuss the IEEE format for representing floating point numbers 6+4

8. a Discuss the DMA data transfer mechanism.

b) Describe the virtual memory technique in details. 4+6

9 a) Differentiate the following i) Hardware and software interrupt ii) maskable and non-maskable
-

interrupt ii) vectored and non-vectored interrupt.

b) Differentiate virtual memory and cache memory. 7+3

10. a) Write down the characteristic features of RISC.

b) Explain the Flynn's classification. 6+4

11. a) Explain different pipeline hazards and their possible solution.

b) Why biased exponent is used in representation of floating point numbers? 7+3

12. Write a short note on (any two): 5+5

(a) Array Processor, (6) Super computer, (c) 0,1,2,3 address instruction, (d) Priority
interupt