CXL Consortium™ Webinar

An Introduction to
Compute Express Link™ (CXL) Technology

Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Agenda
• Presenter Introductions
• Introduction to Compute Express Link™
• Industry Landscape
• CXL Overview
• CXL Features & Benefits
• CXL Use Cases
• Introducing CXL Consortium™
• CXL Consortium™ Origin & Incorporation
• Membership Information
• Q&A

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Today’s Presenters
Kurtis Bowman
CXL Consortium Board Member – Secretary
Director of Server Architecture and Technologies - Server Office of CTO at Dell EMC

Dr. Debendra Das Sharma

Fellow and Director of I/O Technology and Standards at Intel

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Industry Landscape
Industry mega-trends are driving demand for faster data processing
and next-generation data center performance
Proliferation of Growth of Cloudification of the
Cloud Computing AI & Analytics Network & Edge

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 Why the need for a new class of interconnect?
Extend PCIe® for heterogenous computing and disaggregation usages

• Need a new class of interconnect for

heterogenous computing and disaggregation
usages:
• Efficient resource sharing
• Shared memory pools with efficient access
mechanisms
Today’s Environment
• Enhanced movement of operands and results
between accelerators and target devices
Memory
• Significant latency reduction to enable Load/Store

disaggregated memory

• The industry needs open standards that can

comprehensively address next-gen interconnect Writeback PCIe DMA
Memory
challenges
CXL Enabled Environment
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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Overview of Compute Express Link™

Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
CXL Overview
• New breakthrough high-speed CPU-to-Device interconnect
• Enables a high-speed, efficient interconnect between the CPU and platform
enhancements and workload accelerators
• Builds upon PCI Express® infrastructure, leveraging the PCIe® 5.0 physical and
electrical interface
• Maintains memory coherency between the CPU memory space and memory on
attached devices
• Allows resource sharing for higher performance
• Reduced complexity and lower overall system cost
• Permits users to focus on target workloads as opposed to redundant memory management
• Delivered as an open industry standard
• CXL Specification 1.1 is available now
• Future CXL Specification generations will continue to innovate to meet industry
needs

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Introducing CXL
• Processor Interconnect:
• Open industry standard
• High-bandwidth, low-latency
• Coherent interface A new class of
• Leverages PCI Express® interconnect
for device
• Targets high-performance connectivity
computational workloads
• Artificial Intelligence
• Machine Learning
• HPC
• Comms

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 What is CXL?
x16 PCIe x16 CXL
Card Card

• Alternate protocol that runs across

the standard PCIe physical layer X16 Connector

• Uses a flexible processor port that can PCIe channel

auto-negotiate to either the standard
SERDES
Connector
etc.
PCIe transaction protocol or the
alternate CXL transaction protocols
• First generation CXL aligns to Processor
32 Gbps PCIe 5.0
• CXL usages expected to be key driver
for an aggressive timeline to PCIe 6.0
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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 CXL Protocols
The CXL transaction layer is comprised of three dynamically multiplexed sub-
protocols on a single link:

CXL.io
Discovery, configuration, register
access, interrupts, etc.

CXL.cache
Device access to processor
memory

CXL.Memory
Processor access to device
attached memory

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
CXL Features and Benefits

Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 CXL Stack – Designed for Low Latency
CXL Stack – Alternate Stack –
Low latency Cache and Mem Transactions for contrast
• All 3 representative usages have
latency critical elements:
PCIe CXL PCIe
• CXL.cache Transaction
Transaction Transaction
• CXL.memory Layer Layer CXL.cache/CXL.mem Layer Alternate Link
• CXL.io Transaction Layer Transaction Layer

• CXL cache and memory stack is Dynamic Mux

optimized for latency:
• Separate transaction and link layer PCIe CXL
from IO Link Link
Layer Layer CXL.cache/CXL.mem
• Fixed message framing Link Layer PCIe
Link
Layer
• CXL io flows pass through a stack
that is largely identical a standard CXL Dynamic Mux

PCIe stack:
• Dynamic framing Static Mux
• Transaction Layer Packet (TLP)/Data
Link Layer Packet (DLLP) encapsulated PCIe/CXL Logical Phy PCIe Logical Phy
in CXL flits
PCIe/CXL Analog Phy PCIe Analog Phy

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 CXL Stack – Designed for Low Latency
CXL Stack –
Low latency Cache and Mem Transactions
• All 3 representative usages have
latency critical elements:
• CXL.cache PCIe CXL
Transaction Transaction
• CXL.memory Layer Layer CXL.cache/CXL.mem
• CXL.io Transaction Layer

• CXL cache and memory stack is

optimized for latency:
• Separate transaction and link layer PCIe CXL
from IO Link Link
Layer Layer CXL.cache/CXL.mem
• Fixed message framing Link Layer

• CXL io flows pass through a stack

that is largely identical a standard CXL Dynamic Mux

PCIe stack:
• Dynamic framing Static Mux
• Transaction Layer Packet (TLP)/Data
Link Layer Packet (DLLP) encapsulated PCIe/CXL Logical Phy
in CXL flits
PCIe/CXL Analog Phy

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 Asymmetric Complexity
CXL Model – Asymmetric Protocol
CCI* Model – Symmetric CCI Protocol Accelerator CPU
Accelerator CPU Core Core Core Core
Accelerator Engine Core Core Core Core Accelerator Engine
CXL
Cache CXL/CCI Caching Agent
Accelerator Caching Agent CCI Caching Agent Biased
CCI Coherence
Bypass
Accelerator Home Agent CCI Home Agent
CXL/CCI Home Agent
CXL
Memory Agent Memory Agent
Memory Agent Memory Agent

*Cache Coherent Interface

CXL Key Advantages:
• Avoid protocol interoperability hurdles/roadblocks
• Enable devices across multiple segments (e.g. client / server)
• Enable Memory buffer with no coherency burden
• Simpler, processor independent device development
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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 CXL’s Coherence Bias
Device Bias Host Bias
Accelerator CPU
Accelerator CPU + IO Accelerator CPU + IO
Core Core Core Core
Accelerator Engine
Coherence Uncached
Cache CA + HA Flow Cache Coherence
CA + HA
CXL/CCI Caching Agent Cache
Biased
Coherence
Bypass
CXL/CCI Home Agent

Accelerator Local Memory Agent Memory Agent Accelerator Local

Memory Host Memory Memory Host Memory

Critical access class “Coherence Bias” allows a Two driver managed Both biases guaranteed
for accelerators is device engine to access its modes or “Biases” correct/coherent
“device engine to memory coherently without HOST BIAS: pages being used by the host or Guarantee applies even when software bugs or
shared between host and device
device memory” visiting the processor DEVICE BIAS: pages being used exclusively by
speculative accesses unexpectedly access device
memory in the “Device Bias” state.
the device

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
CXL Use Cases

Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 Representative CXL Usages
Caching Devices / Accelerators with Memory Buffers
Accelerators Memory Usages:
• Memory BW expansion
Usages: Usages: • Memory capacity expansion
• PGAS NIC • GPU
• Storage Class Memory
• NIC atomics • Dense Computation
Protocols:
Protocols: Protocols: • CXL.io
• CXL.io Accelerator • CXL.io

HBM
• CXL.mem
• CXL.cache • CXL.cache
NIC
• CXL.memory Accelerator Memory

Memory

Memory

Memory

Memory
Cache

HBM
Cache Buffer

C X L C X L C X L

DDR

DDR
DDR

Processor Processor Processor

DDR

DDR
DDR

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 Heterogeneous Computing Revisited – with CXL
CXL enables a more fluid and flexible memory model
Single, common, memory address space across processors and devices

• More efficient population and CPU-attached Memory

update of operands (OS Managed)
Writeback
PCIe DMA
• More efficient extraction of Memory Memory
results Load/Store

• Memory resource “borrowing” CPU CPU GPU FPGA AI NIC NIC

• User/Kernel level data access and … … …

data movement
• Low latency to memory, host to Memory Load/Store
device and device to host Writeback PCIe DMA
Memory Accelerator-Attached Memory
(Runtime managed cache)

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 CXL Summary
CXL has the right features and architecture to enable a broad, open
ecosystem for heterogeneous computing and server disaggregation:

Coherent Interface: Low Latency: Asymmetric Complexity: Open Industry Standard:

With growing broad industry
Leverages PCIe® with 3 .Cache and .Mem Eases burdens of cache support
mix-and-match protocols targeted at near CPU coherent interface designs
cache coherent latency
Introducing CXL Consortium™

Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Introducing CXL Consortium™
• Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel
Corporation and Microsoft announced their intent to incorporate in March 2019
• This core group announced incorporation of the Compute Express Link (CXL) Consortium
on September 17, 2019 and unveiled the names of its Board of Directors:

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Membership Overview
• CXL Consortium™ boasts 90+ member companies to date and is growing
rapidly
• Current membership ranks reflects the required industry expertise to create a robust,
vibrant CXL ecosystem

• Two levels of membership are available for participation in CXL

• Adopter memberships are free and allow your company to:
• Access the final specification releases
• Gain IP protection as outlined in the IPR Policy and Membership Agreements
• Contributor membership are $20K for the first year and $10K per year each
subsequent year with the following added benefits:
• Participate in the CXL workgroups
• Influence the direction of the technology
• Access the intermediate specifications (dot level releases)

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
Membership Overview
• Members have access to the CXL Specification 1.1
• Both the Host and Target side of the interface is published
• All members can implement the spec under the Consortium’s IP protection policy
• An evaluation copy of the 1.1 Spec is available at computeexpresslink.org
• The CXL Consortium will deliver future generations of the Specification
• Contributor members can participate in the definition and promotion of future
specifications in the CXL Working Groups:
• Compliance WG
• Marketing WG
• Memory System WG
• PHY WG
• Protocol WG
• Software & Systems WG
• CXL maintains backwards compatibility to protect member investments
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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 Join Today!
www.computeexpresslink.org/join

Follow Us on Social Media

@ComputeExLink

www.linkedin.com/company/cxl-consortium/

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.
 Q&A

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Compute Express Link™ and CXL Consortium™ are trademarks of the Compute Express Link Consortium.