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MSP430F673xA, MSP430F672xA Mixed-Signal Microcontrollers: 1 Device Overview

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14 views164 pages

MSP430F673xA, MSP430F672xA Mixed-Signal Microcontrollers: 1 Device Overview

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Product Order Technical Tools & Support &

Folder Now Documents Software Community

MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A

MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

MSP430F673xA, MSP430F672xA Mixed-Signal Microcontrollers

1 Device Overview

1.1
1
Features
• Low Supply-Voltage Range: • Three 16-Bit Timers With Two Capture/Compare
3.6 V Down to 1.8 V Registers Each
• Ultra-Low Power Consumption • Enhanced Universal Serial Communication
– Active Mode (AM): Interfaces (eUSCIs)
All System Clocks Active – eUSCI_A0, eUSCI_A1, and eUSCI_A2
265 µA/MHz at 8 MHz, 3.0 V, Flash Program – Enhanced UART Supports Automatic Baud-
Execution (Typical) Rate Detection
140 µA/MHz at 8 MHz, 3.0 V, RAM Program – IrDA Encoder and Decoder
Execution (Typical)
– Synchronous SPI
– Standby Mode (LPM3):
– eUSCI_B0
Real-Time Clock (RTC) With Crystal, Watchdog,
and Supply Supervisor Operational, Full RAM – I2C With Multiple Slave Addressing
Retention, Fast Wake up: – Synchronous SPI
1.7 µA at 2.2 V, 2.5 µA at 3.0 V (Typical) • Password-Protected RTC With Crystal Offset
– Off Mode (LPM4): Calibration and Temperature Compensation
Full RAM Retention, Supply Supervisor • Separate Voltage Supply for Backup Subsystem
Operational, Fast Wake up: – 32-kHz Low-Frequency Oscillator (XT1)
1.6 µA at 3.0 V (Typical) – Real-Time Clock
– Shutdown RTC Mode (LPM3.5): – Backup Memory (4 × 16 Bits)
Shutdown Mode, Active RTC With Crystal: • Three 24-Bit Sigma-Delta Analog-to-Digital
1.24 µA at 3.0 V (Typical) Converters (ADCs) With Differential PGA Inputs
– Shutdown Mode (LPM4.5): • Integrated LCD Driver With Contrast Control for up
0.78 µA at 3.0 V (Typical) to 320 Segments in 8-Mux Mode
• Wake up From Standby Mode in 3 µs (Typical) • Hardware Multiplier Supports 32-Bit Operations
• 16-Bit RISC Architecture, Extended Memory, up to • 10-Bit 200-ksps ADC
25-MHz System Clock
– Internal Reference
• Flexible Power-Management System
– Sample-and-Hold, Autoscan Feature
– Fully Integrated LDO With Programmable
– Up to Six External Channels and Two Internal
Regulated Core Supply Voltage
Channels, Including Temperature Sensor
– Supply Voltage Supervision, Monitoring, and
• Three-Channel Internal DMA
Brownout
• Serial Onboard Programming, No External
– System Operation From up to Two Auxiliary
Programming Voltage Needed
Power Supplies
• Device Comparison Summarizes the Available
• Unified Clock System
Family Members
– FLL Control Loop for Frequency Stabilization
• Available in 100-Pin and 80-Pin LQFP Packages
– Low-Power Low-Frequency Internal Clock
• Single-Phase Electronic Watt-Hour Meter
Source (VLO)
Development Tool (Also See Tools and Software)
– Low-Frequency Trimmed Internal Reference
– EVM430-F6736 - MSP430F6736 EVM for
Source (REFO)
Metering
– 32-kHz Crystals (XT1)
– Energy Measurement Design Center for
• One 16-Bit Timer With Three Capture/Compare MSP430™ MCUs
Registers

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

1.2 Applications
• Single-Phase Electronic Watt-Hour Meters • Utility Metering
• Energy Monitoring

1.3 Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets
of peripherals targeted for various applications. The architecture, combined with extensive low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The DCO allows the device to wake up from low-power modes to active mode
in 3 µs (typical).
The MSP430F673xA and MSP430F672xA devices are microcontrollers with high-performance 24-bit
sigma-delta ADCs (three ADCs in MSP430F673xA and two ADCs in MSP430F672xA), a 10-bit ADC, four
eUSCIs (three eUSCI_A modules and one eUSCI_B module), four 16-bit timers, a hardware multiplier, a
DMA module, an RTC module with alarm capabilities, an LCD driver with integrated contrast control, an
auxiliary supply system, and up to 72 I/O pins in the 100‑pin devices and 52 I/O pins in the 80‑pin devices.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.

Device Information (1)

PART NUMBER PACKAGE BODY SIZE (2)
MSP430F6736AIPZ LQFP (100) 14 mm × 14 mm
MSP430F6736AIPN LQFP (80) 12 mm × 12 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.

2 Device Overview Copyright © 2015–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram for all device variants in the PZ package.

XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI PA PB PC PD PE
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
(32 kHz)

ACLK I/O Ports

SYS I/O Ports I/O Ports I/O Ports I/O Ports
Unified 8KB P1, P2 P3, P4
128KB P5, P6 P7, P8 P9
Clock 4KB 2×8 I/Os 2×8 I/Os
96KB Watchdog 2×8 I/Os 2×8 I/Os 1×4 I/O
System 2KB Interrupt,
64KB
SMCLK 1KB CRC16 MPY32 Wakeup
32KB Port
16KB Mapping
MCLK Controller PA PB PC PD PE
Flash RAM 1×16 I/Os 1×16 I/Os 1×16 I/Os 1×16 I/Os 1×4 I/O

CPUXV2
and
Working
Registers
(25 MHz)

EEM
(S: 3+1)

PMM TA1 eUSCI_A0

Auxiliary SD24_B ADC10_A LCD_C REF
TA0 TA2 eUSCI_A1 eUSCI_B0 DMA
JTAG, Supplies TA3 eUSCI_A2
SBW RTC_C
Interface LDO 3 Channel 10 Bit 8-mux Reference 2 3 Channel
200 ksps Up to 320 1.5 V, 2.0 V, Timer_A Timer_A (UART, (SPI, I C)
SVM, SVS 2 Channel
Segments 2.5 V 3 CC 2 CC IrDA,SPI)
Port PJ BOR Registers Registers
PJ.x

Copyright © 2016, Texas Instruments Incorporated

Figure 1-1. Functional Block Diagram - MSP430F673xAIPZ and MSP430F672xAIPZ

Figure 1-2 shows the functional block diagram for all device variants in the PN package.

XIN XOUT DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI PA PB PC
P1.x P2.x P3.x P4.x P5.x P6.x
(32 kHz)

ACLK I/O Ports

SYS I/O Ports I/O Ports
Unified 128KB 8KB P1, P2 P3, P4 P5, P6
Clock 96KB 4KB 2×8 I/Os 2×8 I/Os
DMA Watchdog 2×8 I/Os
System 64KB 2KB Interrupt,
SMCLK 32KB 1KB CRC16 MPY32 Wakeup
16KB 3 Channel Port
Mapping
MCLK Controller PA PB PC
Flash RAM 1×16 I/Os 1×16 I/Os 1×16 I/Os

CPUXV2
and
Working
Registers
(25 MHz)

EEM
(S: 3+1)

PMM TA1 eUSCI_A0

Auxiliary SD24_B ADC10_A LCD_C REF TA0 TA2 eUSCI_A1 eUSCI_B0
JTAG, Supplies TA3 eUSCI_A2
SBW RTC_C
Interface LDO 3 Channel 10 Bit 8 mux Reference Timer_A Timer_A (UART, (SPI, I2C)
SVM, SVS 2 Channel 200 ksps Up to 320 1.5 V, 2.0 V, 3 CC 2 CC IrDA, SPI)
Port PJ BOR Segments 2.5 V Registers Registers
PJ.x

Copyright © 2016, Texas Instruments Incorporated

Figure 1-2. Functional Block Diagram - MSP430F673xAIPN and MSP430F672xAIPN

Copyright © 2015–2018, Texas Instruments Incorporated Device Overview 3

Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table of Contents
1 Device Overview ......................................... 1 6.2 CPU ................................................. 75
1.1 Features .............................................. 1 6.3 Instruction Set ....................................... 76
1.2 Applications ........................................... 2 6.4 Operating Modes .................................... 77
1.3 Description ............................................ 2 6.5 Interrupt Vector Addresses.......................... 78
1.4 Functional Block Diagrams ........................... 3 6.6 Bootloader (BSL) .................................... 79
2 Revision History ......................................... 5 6.7 JTAG Operation ..................................... 79
3 Device Comparison ..................................... 6 6.8 Flash Memory ....................................... 80
3.1 Related Products ..................................... 7 6.9 RAM ................................................. 80
4 Terminal Configuration and Functions .............. 8 6.10 Backup RAM ........................................ 80
4.1 Pin Diagrams ......................................... 8 6.11 Peripherals .......................................... 81
4.2 Pin Attributes ........................................ 12 6.12 Input/Output Diagrams .............................. 91
4.3 Signal Descriptions .................................. 22 6.13 Device Descriptors (TLV) .......................... 123
4.4 Pin Multiplexing ..................................... 33 6.14 Memory ............................................ 125
4.5 Buffer Type .......................................... 33 6.15 Identification........................................ 140
4.6 Connection of Unused Pins ......................... 33 7 Applications, Implementation, and Layout ...... 141
5 Specifications ........................................... 34 8 Device and Documentation Support .............. 142
5.1 Absolute Maximum Ratings ........................ 34 8.1 Getting Started and Next Steps ................... 142
5.2 ........................................
ESD Ratings 34 8.2 Device Nomenclature .............................. 142
5.3 Recommended Operating Conditions ............... 34 8.3 Tools and Software ................................ 144
5.4 Active Mode Supply Current Into VCC Excluding 8.4 Documentation Support ............................ 146
External Current ..................................... 36 8.5 Related Links ...................................... 148
5.5 Low-Power Mode Supply Currents (Into VCC)
8.6 Community Resources............................. 148
Excluding External Current.......................... 37
8.7 Trademarks ........................................ 148
5.6 Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current .................... 38 8.8 Electrostatic Discharge Caution ................... 149
5.7 Thermal Resistance Characteristics ................ 39 8.9 Export Control Notice .............................. 149
5.8 Timing and Switching Characteristics ............... 40 8.10 Glossary............................................ 149
6 Detailed Description ................................... 75 9 Mechanical, Packaging, and Orderable
Information ............................................. 149
6.1 Overview ............................................ 75

4 Table of Contents Copyright © 2015–2018, Texas Instruments Incorporated

2 Revision History
Changes from February 25, 2015 to October 3, 2018 Page

• Added links to development tool and design center in , Features ............................................................. 1

• Added Section 3.1, Related Products ............................................................................................. 7
• Added Section 4.5, Buffer Type ................................................................................................... 33
• Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 34
• Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and
added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings ..... 34
• Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 39
• Corrected nonvolatile memory type (changed "FRAM" to "flash") in Section 5.8.1, Power Supply Sequencing ....... 40
• Updated notes (1) and (2) and added note (3) in Table 5-1, Wake-up Times From Low-Power Modes and Reset .. 40
• Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Table 5-12, PMM, Brownout
Reset (BOR) ......................................................................................................................... 50
• Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-33, LCD_C Operating
Conditions ............................................................................................................................ 62
• Removed ADC10DIV from the formula for the TYP value in the second row for tCONVERT in Table 5-44, 10-Bit
ADC, Timing Parameters, because fADC10CLK is after division ................................................................. 71
• Updated Test Conditions for all parameters in Table 5-45, 10-Bit ADC, Linearity Parameters: changed from
"(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to "1.4 V ≤ (VeREF+ – VeREF–)" in all cases ....................................... 72
• Added "CVeREF+ = 20 pF" to EI Test Conditions.................................................................................. 72
• Changed all instances of "bootloader" to "bootloader" ......................................................................... 79
• Corrected spelling of NMIIFG in Table 6-9, System Module Interrupt Vector Registers ................................... 85
• Corrected port number in title of Table 6-21, Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxAIPZ Only) .... 96
• Replaced former section Development Tools Support with Section 8.3, Tools and Software .......................... 144
• Changed the format in and added content to Section 8.4, Documentation Support ...................................... 146

Copyright © 2015–2018, Texas Instruments Incorporated Revision History 5

Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

3 Device Comparison
Table 3-1 summarizes the available family members.

Table 3-1. Device Comparison (1) (2)

eUSCI_A:
FLASH SRAM SD24_B ADC10_A eUSCI_B:
DEVICE Timer_A (3) UART, IrDA, I/Os PACKAGE
(KB) (KB) CONVERTERS CHANNELS SPI, I2C
SPI
MSP430F6736AIPZ 128 8 3 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6735AIPZ 128 4 3 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6734AIPZ 96 4 3 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6733AIPZ 64 4 3 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6731AIPZ 32 2 3 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6730AIPZ 16 1 3 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6726AIPZ 128 8 2 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6725AIPZ 128 4 2 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6724AIPZ 96 4 2 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6723AIPZ 64 4 2 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6721AIPZ 32 2 2 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6720AIPZ 16 1 2 6 ext, 2 int 3, 2, 2, 2 3 1 72 100 PZ
MSP430F6736AIPN 128 8 3 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6735AIPN 128 4 3 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6734AIPN 96 4 3 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6733AIPN 64 4 3 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6731AIPN 32 2 3 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6730AIPN 16 1 3 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6726AIPN 128 8 2 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6725AIPN 128 4 2 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6724AIPN 96 4 2 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6723AIPN 64 4 2 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6721AIPN 32 2 2 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN
MSP430F6720AIPN 16 1 2 3 ext, 2 int 3, 2, 2, 2 3 1 52 80 PN

(1) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at
www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

6 Device Comparison Copyright © 2015–2018, Texas Instruments Incorporated

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless
connectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless
possibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F6736A Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430F6736A The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market.

Copyright © 2015–2018, Texas Instruments Incorporated Device Comparison 7

Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

4 Terminal Configuration and Functions

4.1 Pin Diagrams
Figure 4-1 shows the pinout for the 100-pin PZ package. See Table 4-1 for differences between the
MSP430F673xA and MSP430F672xA devices in this package.

PJ.2/ADC10CLK/TMS
PJ.1/MCLK/TDI/TCLK
RST/NMI/SBWTDIO

PJ.0/SMCLK/TDO
PJ.3/ACLK/TCK

TEST/SBWTCK

P7.1/S10

P6.7/S12
P6.6/S13
P6.5/S14
P6.4/S15
P6.3/S16
P6.2/S17
P6.1/S18
P7.0/S11
P8.3/S0
P8.2/S1
P8.1/S2
P8.0/S3
P7.7/S4
P7.6/S5
P7.5/S6
P7.4/S7
P7.3/S8
P7.2/S9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SD0P0 1 75 DVSS
SD0N0 2 74 DVSYS
SD1P0 3 73 P6.0/S19
SD1N0 4 72 P5.7/S20
SD2P0 5 71 P5.6/S21
SD2N0 6 70 P5.5/S22
VREF 7 69 P5.4/S23
AVSS 8 68 P5.3/S24
AVCC 9 67 P5.2/S25
VASYS 10 66 P5.1/S26
P9.1/A5 11 65 P5.0/S27
P9.2/A4 12 64 P4.7/S28
P9.3/A3 13 63 P4.6/S29
P1.0/PM_TA0.0/VeREF-/A2 14 62 P4.5/S30
P1.1/PM_TA0.1/VeREF+/A1 15 61 P4.4/S31
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 16 60 P4.3/S32
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 17 59 P4.2/S33
AUXVCC2 18 58 P4.1/S34
AUXVCC1 19 57 P4.0/S35
VDSYS 20 56 P3.7/PM_SD2DIO/S36
DVCC 21 55 P3.6/PM_SD1DIO/S37
DVSS 22 54 P3.5/PM_SD0DIO/S38
VCORE 23 53 P3.4/PM_SDCLK/S39
XIN 24 52 P3.3/PM_TA0.2
XOUT 25 51 P3.2/PM_TACLK/PM_RTCCLK
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AUXVCC3

COM0
COM1
COM2
COM3
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
LCDCAP/R33
P8.4/TA1.0
P8.5/TA1.1

P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
P8.6/TA2.0
P8.7/TA2.1
P9.0/TACLK/RTCCLK
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
P3.0/PM_TA2.0/BSL_TX
P3.1/PM_TA2.1/BSL_RX

NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See Section 6.11.6 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.

Figure 4-1. 100-Pin PZ Package (Top View)

8 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-1. Pinout Differences Between MSP430F673xAIPZ and

MSP430F672xAIPZ (1)
PIN NAME
PIN NUMBER
MSP430F673xAIPZ MSP430F672xAIPZ
1 SD0P0 SD0P0
2 SD0N0 SD0N0
3 SD1P0 SD1P0
4 SD1N0 SD1N0
5 SD2P0 NC
6 SD2N0 NC
7 VREF VREF
53 P3.4/PM_SDCLK/S39 P3.4/PM_SDCLK/S39
54 P3.5/PM_SD0DIO/S38 P3.5/PM_SD0DIO/S38
55 P3.6/PM_SD1DIO/S37 P3.6/PM_SD1DIO/S37
56 P3.7/PM_SD2DIO/S36 P3.7/PM_NONE/S36
(1) Signal names that differ between devices are indicated by italic typeface.

Copyright © 2015–2018, Texas Instruments Incorporated Terminal Configuration and Functions 9

Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Figure 4-2 shows the pinout for the 80-pin PN package. See Table 4-2 for differences between the
MSP430F673xA and MSP430F672xA devices in this package.

PJ.2/ADC10CLK/TMS
PJ.1/MCLK/TDI/TCLK
RST/NMI/SBWTDIO

PJ.0/SMCLK/TDO
PJ.3/ACLK/TCK

TEST/SBWTCK

P5.5/S10

P5.3/S12
P5.2/S13
P5.4/S11
P6.7/S0
P6.6/S1
P6.5/S2
P6.4/S3
P6.3/S4
P6.2/S5
P6.1/S6
P6.0/S7
P5.7/S8
P5.6/S9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SD0P0 1 60 DVSS
SD0N0 2 59 DVSYS
SD1P0 3 58 P5.1/S14
SD1N0 4 57 P5.0/S15
SD2P0 5 56 P4.7/S16
SD2N0 6 55 P4.6/S17
VREF 7 54 P4.5/S18
AVSS 8 53 P4.4/S19
AVCC 9 52 P4.3/S20
VASYS 10 51 P4.2/S21
P1.0/PM_TA0.0/VeREF-/A2 11 50 P4.1/S22
P1.1/PM_TA0.1/VeREF+/A1 12 49 P4.0/S23
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 13 48 P3.7/PM_SD2DIO/S24
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 14 47 P3.6/PM_SD1DIO/S25
AUXVCC2 15 46 P3.5/PM_SD0DIO/S26
AUXVCC1 16 45 P3.4/PM_SDCLK/S27
VDSYS 17 44 P3.3/PM_TA0.2/S28
DVCC 18 43 P3.2/PM_TACLK/PM_RTCCLK/S29
DVSS 19 42 P3.1/PM_TA2.1/S30/BSL_RX
VCORE 20 41 P3.0/PM_TA2.0/S31/BSL_TX
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
XIN
XOUT
AUXVCC3

COM1
COM2
COM3
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
LCDCAP/R33
COM0

P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32

Figure 4-2. 80-Pin PN Package (Top View)

10 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-2. Pinout Differences Between MSP430F673xAIPN and

MSP430F672xAIPN (1)
PIN NAME
PIN NUMBER
MSP430F673xAIPN MSP430F672xAIPN
1 SD0P0 SD0P0
2 SD0N0 SD0N0
3 SD1P0 SD1P0
4 SD1N0 SD1N0
5 SD2P0 NC
6 SD2N0 NC
7 VREF VREF
45 P3.4/PM_SDCLK/S27 P3.4/PM_SDCLK/S27
46 P3.5/PM_SD0DIO/S26 P3.5/PM_SD0DIO/S26
47 P3.6/PM_SD1DIO/S25 P3.6/PM_SD1DIO/S25
48 P3.7/PM_SD2DIO/S24 P3.7/PM_NONE/S24
(1) Signal names that differ between devices are indicated by italic typeface.

Copyright © 2015–2018, Texas Instruments Incorporated Terminal Configuration and Functions 11

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

4.2 Pin Attributes

Table 4-3 lists the pin attributes for all device variants in the PZ package. For the PN package, see
Table 4-4.

Table 4-3. Pin Attributes, PZ Package

(1) (2) (3) (4) RESET STATE AFTER
PIN NO. SIGNAL NAME SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
1 SD0P0 I Analog AVCC OFF
2 SD0N0 I Analog AVCC OFF
3 SD1P0 I Analog AVCC OFF
4 SD1N0 I Analog AVCC OFF
5 SD2P0 I Analog AVCC OFF
6 SD2N0 I Analog AVCC OFF
7 VREF I Analog – OFF
8 AVSS P Power – N/A
9 AVCC P Power – N/A
10 VASYS P Power – N/A
P9.1 I/O LVCMOS DVCC OFF
11
A5 I Analog AVCC –
P9.2 I/O LVCMOS DVCC OFF
12
A4 I Analog AVCC –
P9.3 I/O LVCMOS DVCC OFF
13
A3 I Analog AVCC –
P1.0 I/O LVCMOS DVCC OFF
PM_TA0.0 I/O LVCMOS DVCC –
14
VeREF- I Power – N/A
A2 I Analog AVCC –
P1.1 I/O LVCMOS DVCC OFF
PM_TA0.1 I/O LVCMOS DVCC –
15
VeREF+ I Power – N/A
A1 I Analog AVCC –
P1.2 I/O LVCMOS DVCC OFF
PM_UCA0RXD I LVCMOS DVCC –
16
PM_UCA0SOMI I/O LVCMOS DVCC –
A0 I Analog AVCC –
P1.3 I/O LVCMOS DVCC OFF
PM_UCA0TXD O LVCMOS DVCC –
17
PM_UCA0SIMO I/O LVCMOS DVCC –
R03 I/O Analog AVCC –
18 AUXVCC2 P Power – N/A
19 AUXVCC1 P Power – N/A
20 VDSYS P Power – N/A
21 DVCC P Power – N/A
22 DVSS P Power – N/A

(1) For each multiplexed pin, the signal that is listed first in this table is the default after reset.
(2) To determine the pin mux encodings for each pin, refer to Section 6.12, Input/Output Diagrams.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output.
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-7, Buffer Type)
(5) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
12 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

Table 4-3. Pin Attributes, PZ Package (continued)

(1) (2) (3) (4) RESET STATE AFTER
PIN NO. SIGNAL NAME SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
23 VCORE P Power – N/A
24 XIN I LVCMOS DVCC OFF
25 XOUT O LVCMOS DVCC OFF
26 AUXVCC3 P Power – N/A
P1.4 I/O LVCMOS DVCC OFF
PM_UCA1RXD I LVCMOS DVCC –
27 PM_UCA1SOMI I/O LVCMOS DVCC –
LCDREF I Analog AVCC –
R13 I/O Analog AVCC –
P1.5 I/O LVCMOS DVCC OFF
PM_UCA1TXD O LVCMOS DVCC –
28
PM_UCA1SIMO I/O LVCMOS DVCC –
R23 I/O Analog AVCC –
LCDCAP I/O Analog AVCC OFF
29
R33 I/O Analog AVCC –
P8.4 I/O LVCMOS DVCC OFF
30
TA1.0 I/O LVCMOS DVCC –
P8.5 I/O LVCMOS DVCC OFF
31
TA1.1 I/O LVCMOS DVCC –
32 COM0 O LVCMOS DVCC OFF
33 COM1 O LVCMOS DVCC OFF
34 COM2 O LVCMOS DVCC OFF
35 COM3 O LVCMOS DVCC OFF
P1.6 I/O LVCMOS DVCC OFF
36 PM_UCA0CLK I/O LVCMOS DVCC –
COM4 O LVCMOS DVCC –
P1.7 I/O LVCMOS DVCC OFF
37 PM_UCB0CLK I/O LVCMOS DVCC –
COM5 O LVCMOS DVCC –
P2.0 I/O LVCMOS DVCC OFF
PM_UCB0SOMI I/O LVCMOS DVCC –
38
PM_UCB0SCL I/O LVCMOS DVCC –
COM6 O LVCMOS DVCC –
P2.1 I/O LVCMOS DVCC OFF
PM_UCB0SIMO I/O LVCMOS DVCC –
39
PM_UCB0SDA I/O LVCMOS DVCC –
COM7 O LVCMOS DVCC –
P8.6 I/O LVCMOS DVCC OFF
40
TA2.0 I/O LVCMOS DVCC –
P8.7 I/O LVCMOS DVCC OFF
41
TA2.1 I/O LVCMOS DVCC –
P9.0 I/O LVCMOS DVCC OFF
42 TACLK I LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
P2.2 I/O LVCMOS DVCC OFF
43 PM_UCA2RXD I LVCMOS DVCC –
PM_UCA2SOMI I/O LVCMOS DVCC –

Copyright © 2015–2018, Texas Instruments Incorporated Terminal Configuration and Functions 13

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-3. Pin Attributes, PZ Package (continued)

(1) (2) (3) (4) RESET STATE AFTER
PIN NO. SIGNAL NAME SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
P2.3 I/O LVCMOS DVCC OFF
44 PM_UCA2TXD O LVCMOS DVCC –
PM_UCA2SIMO I/O LVCMOS DVCC –
P2.4 I/O LVCMOS DVCC OFF
45
PM_UCA1CLK I/O LVCMOS DVCC –
P2.5 I/O LVCMOS DVCC OFF
46
PM_UCA2CLK I/O LVCMOS DVCC –
P2.6 I/O LVCMOS DVCC OFF
47
PM_TA1.0 I/O LVCMOS DVCC –
P2.7 I/O LVCMOS DVCC OFF
48
PM_TA1.1 I/O LVCMOS DVCC –
P3.0 I/O LVCMOS DVCC OFF
49 PM_TA2.0 I/O LVCMOS DVCC –
BSL_TX O LVCMOS DVCC –
P3.1 I/O LVCMOS DVCC OFF
50 PM_TA2.1 I/O LVCMOS DVCC –
BSL_RX I LVCMOS DVCC –
P3.2 I/O LVCMOS DVCC OFF
51 PM_TACLK I LVCMOS DVCC –
PM_RTCCLK O LVCMOS DVCC –
P3.3 I/O LVCMOS DVCC OFF
52
PM_TA0.2 I/O LVCMOS DVCC –
P3.4 I/O LVCMOS DVCC OFF
53 PM_SDCLK I/O LVCMOS DVCC –
S39 O LVCMOS DVCC –
P3.5 I/O LVCMOS DVCC OFF
54 PM_SD0DIO I/O Analog AVCC –
S38 O LVCMOS DVCC –
P3.6 I/O LVCMOS DVCC OFF
55 PM_SD1DIO I/O Analog AVCC –
S37 O LVCMOS DVCC –
P3.7 I/O LVCMOS DVCC OFF
56 PM_SD2DIO I/O LVCMOS DVCC –
S36 O LVCMOS DVCC –
P4.0 I/O LVCMOS DVCC OFF
57
S35 O LVCMOS DVCC –
P4.1 I/O LVCMOS DVCC OFF
58
S34 O LVCMOS DVCC –
P4.2 I/O LVCMOS DVCC OFF
59
S33 O LVCMOS DVCC –
P4.3 I/O LVCMOS DVCC OFF
60
S32 O LVCMOS DVCC –
P4.4 I/O LVCMOS DVCC OFF
61
S31 O LVCMOS DVCC –
P4.5 I/O LVCMOS DVCC OFF
62
S30 O LVCMOS DVCC –

14 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-3. Pin Attributes, PZ Package (continued)

(1) (2) (3) (4) RESET STATE AFTER
PIN NO. SIGNAL NAME SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
P4.6 I/O LVCMOS DVCC OFF
63
S29 O LVCMOS DVCC –
P4.7 I/O LVCMOS DVCC OFF
64
S28 O LVCMOS DVCC –
P5.0 I/O LVCMOS DVCC OFF
65
S27 O LVCMOS DVCC –
P5.1 I/O LVCMOS DVCC OFF
66
S26 O LVCMOS DVCC –
P5.2 I/O LVCMOS DVCC OFF
67
S25 O LVCMOS DVCC –
P5.3 I/O LVCMOS DVCC OFF
68
S24 O LVCMOS DVCC –
P5.4 I/O LVCMOS DVCC OFF
69
S23 O LVCMOS DVCC –
P5.5 I/O LVCMOS DVCC OFF
70
S22 O LVCMOS DVCC –
P5.6 I/O LVCMOS DVCC OFF
71
S21 O LVCMOS DVCC –
P5.7 I/O LVCMOS DVCC OFF
72
S20 O LVCMOS DVCC –
P6.0 I/O LVCMOS DVCC OFF
73
S19 O LVCMOS DVCC –
74 DVSYS P Power – N/A
75 DVSS P Power – N/A
P6.1 I/O LVCMOS DVCC OFF
76
S18 O LVCMOS DVCC –
P6.2 I/O LVCMOS DVCC OFF
77
S17 O LVCMOS DVCC –
P6.3 I/O LVCMOS DVCC OFF
78
S16 O LVCMOS DVCC –
P6.4 I/O LVCMOS DVCC OFF
79
S15 O LVCMOS DVCC –
P6.5 I/O LVCMOS DVCC OFF
80
S14 O LVCMOS DVCC –
P6.6 I/O LVCMOS DVCC OFF
81
S13 O LVCMOS DVCC –
P6.7 I/O LVCMOS DVCC OFF
82
S12 O LVCMOS DVCC –
P7.0 I/O LVCMOS DVCC OFF
83
S11 O LVCMOS DVCC –
P7.1 I/O LVCMOS DVCC OFF
84
S10 O LVCMOS DVCC –
P7.2 I/O LVCMOS DVCC OFF
85
S9 O LVCMOS DVCC –
P7.3 I/O LVCMOS DVCC OFF
86
S8 O LVCMOS DVCC –

Copyright © 2015–2018, Texas Instruments Incorporated Terminal Configuration and Functions 15

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-3. Pin Attributes, PZ Package (continued)

(1) (2) (3) (4) RESET STATE AFTER
PIN NO. SIGNAL NAME SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
P7.4 I/O LVCMOS DVCC OFF
87
S7 O LVCMOS DVCC –
P7.5 I/O LVCMOS DVCC OFF
88
S6 O LVCMOS DVCC –
P7.6 I/O LVCMOS DVCC OFF
89
S5 O LVCMOS DVCC –
P7.7 I/O LVCMOS DVCC OFF
90
S4 O LVCMOS DVCC –
P8.0 I/O LVCMOS DVCC OFF
91
S3 O LVCMOS DVCC –
P8.1 I/O LVCMOS DVCC OFF
92
S2 O LVCMOS DVCC –
P8.2 I/O LVCMOS DVCC OFF
93
S1 O LVCMOS DVCC –
P8.3 I/O LVCMOS DVCC OFF
94
S0 O LVCMOS DVCC –
TEST I LVCMOS DVCC OFF
95
SBWTCK I LVCMOS DVCC –
PJ.0 I/O LVCMOS DVCC OFF
96 SMCLK O LVCMOS DVCC –
TDO O LVCMOS DVCC –
PJ.1 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC –
97
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
PJ.2 I/O LVCMOS DVCC OFF
98 ADC10CLK O LVCMOS DVCC –
TMS I LVCMOS DVCC –
PJ.3 I/O LVCMOS DVCC OFF
99 ACLK O LVCMOS DVCC –
TCK I LVCMOS DVCC –
RST I LVCMOS DVCC PU
100 NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –

16 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-4 lists the pin attributes for all device variants in the PN package. For the PZ package, see
Table 4-3.

Table 4-4. Pin Attributes, PN Package

(1)
SIGNAL NAME (3) (4) RESET STATE AFTER
PIN NO. (2) SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
1 SD0P0 I Analog AVCC OFF
2 SD0N0 I Analog AVCC OFF
3 SD1P0 I Analog AVCC OFF
4 SD1N0 I Analog AVCC OFF
5 SD2P0 I Analog AVCC OFF
6 SD2N0 I Analog AVCC OFF
7 VREF I Power – N/A
8 AVSS P Power – N/A
9 AVCC P Power – N/A
10 VASYS P Power – N/A
P1.0 I/O LVCMOS DVCC OFF
PM_TA0.0 I/O LVCMOS DVCC –
11
VeREF- I Power – –
A2 I Analog AVCC –
P1.1 I/O LVCMOS DVCC OFF
PM_TA0.1 I/O LVCMOS DVCC –
12
VeREF+ I Power – –
A1 I Analog AVCC –
P1.2 I/O LVCMOS DVCC OFF
PM_UCA0RXD I LVCMOS DVCC –
13
PM_UCA0SOMI I/O LVCMOS DVCC –
A0 I Analog AVCC –
P1.3 I/O LVCMOS DVCC OFF
PM_UCA0TXD O LVCMOS DVCC –
14
PM_UCA0SIMO I/O LVCMOS DVCC –
R03 I/O Analog AVCC –
15 AUXVCC2 P Power – N/A
16 AUXVCC1 P Power – N/A
17 VDSYS P Power – N/A
18 DVCC P Power – N/A
19 DVSS P Power – N/A
20 VCORE P Power – N/A
21 XIN I LVCMOS DVCC OFF
22 XOUT O LVCMOS DVCC OFF
23 AUXVCC3 P Power – N/A

(1) For each multiplexed pin, the signal that is listed first in this table is the default after reset.
(2) To determine the pin mux encodings for each pin, refer to Section 6.12, Input/Output Diagrams.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output.
(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-7, Buffer Type)
(5) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
Copyright © 2015–2018, Texas Instruments Incorporated Terminal Configuration and Functions 17
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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-4. Pin Attributes, PN Package (continued)

(1)
SIGNAL NAME (3) (4) RESET STATE AFTER
PIN NO. (2) SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
P1.4 I/O LVCMOS DVCC OFF
PM_UCA1RXD I LVCMOS DVCC –
24 PM_UCA1SOMI I/O LVCMOS DVCC –
LCDREF I Analog AVCC –
R13 I/O Analog AVCC –
P1.5 I/O LVCMOS DVCC OFF
PM_UCA1TXD O LVCMOS DVCC –
25
PM_UCA1SIMO I/O LVCMOS DVCC –
R23 I/O Analog AVCC –
LCDCAP I/O Analog AVCC OFF
26
R33 I/O Analog AVCC OFF
27 COM0 O LVCMOS DVCC OFF
28 COM1 O LVCMOS DVCC OFF
29 COM2 O LVCMOS DVCC OFF
30 COM3 O LVCMOS DVCC OFF
P1.6 I/O LVCMOS DVCC OFF
31 PM_UCA0CLK I/O LVCMOS DVCC –
COM4 O LVCMOS DVCC –
P1.7 I/O LVCMOS DVCC OFF
32 PM_UCB0CLK I/O LVCMOS DVCC –
COM5 O LVCMOS DVCC –
P2.0 I/O LVCMOS DVCC OFF
PM_UCB0SOMI I/O LVCMOS DVCC –
33 PM_UCB0SCL I/O LVCMOS DVCC –
COM6 O LVCMOS DVCC –
S39 O LVCMOS DVCC –
P2.1 I/O LVCMOS DVCC OFF
PM_UCB0SIMO I/O LVCMOS DVCC –
34 PM_UCB0SDA I/O LVCMOS DVCC –
COM7 O LVCMOS DVCC –
S38 O LVCMOS DVCC –
P2.2 I/O LVCMOS DVCC OFF
PM_UCA2RXD I LVCMOS DVCC –
35
PM_UCA2SOMI I/O LVCMOS DVCC –
S37 O LVCMOS DVCC –
P2.3 I/O LVCMOS DVCC OFF
PM_UCA2TXD O LVCMOS DVCC –
36
PM_UCA2SIMO I/O LVCMOS DVCC –
S36 O LVCMOS DVCC –
P2.4 I/O LVCMOS DVCC OFF
37 PM_UCA1CLK I/O LVCMOS DVCC –
S35 O LVCMOS DVCC –
P2.5 I/O LVCMOS DVCC OFF
38 PM_UCA2CLK I/O LVCMOS DVCC –
S34 O LVCMOS DVCC –

18 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-4. Pin Attributes, PN Package (continued)

(1)
SIGNAL NAME (3) (4) RESET STATE AFTER
PIN NO. (2) SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
P2.6 I/O LVCMOS DVCC OFF
39 PM_TA1.0 I/O LVCMOS DVCC –
S33 O LVCMOS DVCC –
P2.7 I/O LVCMOS DVCC OFF
40 PM_TA1.1 I/O LVCMOS DVCC –
S32 O LVCMOS DVCC –
P3.0 I/O LVCMOS DVCC OFF
PM_TA2.0 I/O LVCMOS DVCC –
41
S31 O LVCMOS DVCC –
BSL_TX O LVCMOS DVCC –
P3.1 I/O LVCMOS DVCC OFF
PM_TA2.1 I/O LVCMOS DVCC –
42
S30 O LVCMOS DVCC –
BSL_RX I LVCMOS DVCC –
P3.2 I/O LVCMOS DVCC OFF
PM_TACLK I LVCMOS DVCC –
43
PM_RTCCLK O LVCMOS DVCC –
S29 O LVCMOS DVCC –
P3.3 I/O LVCMOS DVCC OFF
44 PM_TA0.2 I/O LVCMOS DVCC –
S28 O LVCMOS DVCC –
P3.4 I/O LVCMOS DVCC OFF
45 PM_SDCLK I/O LVCMOS DVCC –
S27 O LVCMOS DVCC –
P3.5 I/O LVCMOS DVCC OFF
46 PM_SD0DIO I/O LVCMOS DVCC –
S26 O LVCMOS DVCC –
P3.6 I/O LVCMOS DVCC OFF
47 PM_SD1DIO I/O LVCMOS DVCC –
S25 O LVCMOS DVCC –
P3.7 I/O LVCMOS DVCC OFF
48 PM_SD2DIO I/O LVCMOS DVCC –
S24 O LVCMOS DVCC –
P4.0 I/O LVCMOS DVCC OFF
49
S23 O LVCMOS DVCC –
P4.1 I/O LVCMOS DVCC OFF
50
S22 O LVCMOS DVCC –
P4.2 I/O LVCMOS DVCC OFF
51
S21 O LVCMOS DVCC –
P4.3 I/O LVCMOS DVCC OFF
52
S20 O LVCMOS DVCC –
P4.4 I/O LVCMOS DVCC OFF
53
S19 O LVCMOS DVCC –
P4.5 I/O LVCMOS DVCC OFF
54
S18 O LVCMOS DVCC –
P4.6 I/O LVCMOS DVCC OFF
55
S17 O LVCMOS DVCC –

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-4. Pin Attributes, PN Package (continued)

(1)
SIGNAL NAME (3) (4) RESET STATE AFTER
PIN NO. (2) SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
P4.7 I/O LVCMOS DVCC OFF
56
S16 O LVCMOS DVCC –
P5.0 I/O LVCMOS DVCC OFF
57
S15 O LVCMOS DVCC –
P5.1 I/O LVCMOS DVCC OFF
58
S14 O LVCMOS DVCC –
59 DVSYS P Power – N/A
60 DVSS P Power – N/A
P5.2 I/O LVCMOS DVCC OFF
61
S13 O LVCMOS DVCC –
P5.3 I/O LVCMOS DVCC OFF
62
S12 O LVCMOS DVCC –
P5.4 I/O LVCMOS DVCC OFF
63
S11 O LVCMOS DVCC –
P5.5 I/O LVCMOS DVCC OFF
64
S10 O LVCMOS DVCC –
P5.6 I/O LVCMOS DVCC OFF
65
S9 O LVCMOS DVCC –
P5.7 I/O LVCMOS DVCC OFF
66
S8 O LVCMOS DVCC –
P6.0 I/O LVCMOS DVCC OFF
67
S7 O LVCMOS DVCC –
P6.1 I/O LVCMOS DVCC OFF
68
S6 O LVCMOS DVCC –
P6.2 I/O LVCMOS DVCC OFF
69
S5 O LVCMOS DVCC –
P6.3 I/O LVCMOS DVCC OFF
70
S4 O LVCMOS DVCC –
P6.4 I/O LVCMOS DVCC OFF
71
S3 O LVCMOS DVCC –
P6.5 I/O LVCMOS DVCC OFF
72
S2 O LVCMOS DVCC –
P6.6 I/O LVCMOS DVCC OFF
73
S1 O LVCMOS DVCC –
P6.7 I/O LVCMOS DVCC OFF
74
S0 O LVCMOS DVCC –
TEST I LVCMOS DVCC OFF
75
SBWTCK I LVCMOS DVCC –
PJ.0 I/O LVCMOS DVCC OFF
76 SMCLK O LVCMOS DVCC –
TDO O LVCMOS DVCC –
PJ.1 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC –
77
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –

20 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-4. Pin Attributes, PN Package (continued)

(1)
SIGNAL NAME (3) (4) RESET STATE AFTER
PIN NO. (2) SIGNAL TYPE BUFFER TYPE POWER SOURCE
BOR (5)
PJ.2 I/O LVCMOS DVCC OFF
78 ADC10CLK O LVCMOS DVCC –
TMS I LVCMOS DVCC –
PJ.3 I/O LVCMOS DVCC OFF
79 ACLK O LVCMOS DVCC –
TCK I LVCMOS DVCC –
RST I/O LVCMOS DVCC PU
80 NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

4.3 Signal Descriptions

Table 4-5 describes the signals for all device variants in the PZ package. See Table 4-6 for signal
descriptions in the PN package.

Table 4-5. Signal Descriptions, PZ Package

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE
A0 16 I Analog input A0 for 10-bit ADC
A1 15 I Analog input A1 for 10-bit ADC
A2 14 I Analog input A2 for 10-bit ADC
A3 13 I Analog input A3 for 10-bit ADC
A4 12 I Analog input A4 for 10-bit ADC
ADC10
A5 11 I Analog input A5 for 10-bit ADC
ADC10CLK 98 O ADC10_A clock output
Positive terminal for the ADC reference voltage for an external applied
VeREF+ 15 I
reference voltage
Negative terminal for the ADC reference voltage for an external applied
VeREF- 14 I
reference voltage
BSL_RX 50 I Bootloader data receive
BSL
BSL_TX 49 O Bootloader data transmit
ACLK 99 O ACLK clock output
MCLK 97 O MCLK clock output
PM_RTCCLK 51 O Default mapping: RTCCLK clock output
Clock RTCCLK 42 O RTCCLK clock output
SMCLK 96 O SMCLK clock output
XIN 24 I Input terminal for crystal oscillator
XOUT 25 O Output terminal for crystal oscillator
SBWTCK 95 I Spy-Bi-Wire input clock
SBWTDIO 100 I/O Spy-Bi-Wire data input/output
TCK 99 I Test clock
TCLK 97 I Test clock input
Debug
TDI 97 I Test data input
TDO 96 O Test data output
TEST 95 I Test mode pin – select digital I/O on JTAG pins
TMS 98 I Test mode select
General-purpose digital I/O with port interrupt and mappable secondary
P1.0 14 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P1.1 15 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P1.2 16 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P1.3 17 I/O
function
GPIO
General-purpose digital I/O with port interrupt and mappable secondary
P1.4 27 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P1.5 28 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P1.6 36 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P1.7 37 I/O
function

22 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-5. Signal Descriptions, PZ Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE
General-purpose digital I/O with port interrupt and mappable secondary
P2.0 38 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.1 39 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.2 43 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.3 44 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.4 45 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.5 46 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.6 47 I/O
function
General-purpose digital I/O with port interrupt and mappable secondary
P2.7 48 I/O
function
P3.0 49 I/O General-purpose digital I/O with mappable secondary function
P3.1 50 I/O General-purpose digital I/O with mappable secondary function
P3.2 51 I/O General-purpose digital I/O with mappable secondary function
P3.3 52 I/O General-purpose digital I/O with mappable secondary function
P3.4 53 I/O General-purpose digital I/O with mappable secondary function
P3.5 54 I/O General-purpose digital I/O with mappable secondary function
P3.6 55 I/O General-purpose digital I/O with mappable secondary function
P3.7 56 I/O General-purpose digital I/O with mappable secondary function
P4.0 57 I/O General-purpose digital I/O
GPIO P4.1 58 I/O General-purpose digital I/O
P4.2 59 I/O General-purpose digital I/O
P4.3 60 I/O General-purpose digital I/O
P4.4 61 I/O General-purpose digital I/O
P4.5 62 I/O General-purpose digital I/O
P4.6 63 I/O General-purpose digital I/O
P4.7 64 I/O General-purpose digital I/O
P5.0 65 I/O General-purpose digital I/O
P5.1 66 I/O General-purpose digital I/O
P5.2 67 I/O General-purpose digital I/O
P5.3 68 I/O General-purpose digital I/O
P5.4 69 I/O General-purpose digital I/O
P5.5 70 I/O General-purpose digital I/O
P5.6 71 I/O General-purpose digital I/O
P5.7 72 I/O General-purpose digital I/O
P6.0 73 I/O General-purpose digital I/O
P6.1 76 I/O General-purpose digital I/O
P6.2 77 I/O General-purpose digital I/O
P6.3 78 I/O General-purpose digital I/O
P6.4 79 I/O General-purpose digital I/O
P6.5 80 I/O General-purpose digital I/O
P6.6 81 I/O General-purpose digital I/O
P6.7 82 I/O General-purpose digital I/O

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-5. Signal Descriptions, PZ Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE
P7.0 83 I/O General-purpose digital I/O
P7.1 84 I/O General-purpose digital I/O
P7.2 85 I/O General-purpose digital I/O
P7.3 86 I/O General-purpose digital I/O
P7.4 87 I/O General-purpose digital I/O
P7.5 88 I/O General-purpose digital I/O
P7.6 89 I/O General-purpose digital I/O
P7.7 90 I/O General-purpose digital I/O
P8.0 91 I/O General-purpose digital I/O
P8.1 92 I/O General-purpose digital I/O
P8.2 93 I/O General-purpose digital I/O
P8.3 94 I/O General-purpose digital I/O
GPIO
P8.4 30 I/O General-purpose digital I/O
P8.5 31 I/O General-purpose digital I/O
P8.6 40 I/O General-purpose digital I/O
P8.7 41 I/O General-purpose digital I/O
P9.0 42 I/O General-purpose digital I/O
P9.1 11 I/O General-purpose digital I/O
P9.2 12 I/O General-purpose digital I/O
P9.3 13 I/O General-purpose digital I/O
PJ.0 96 I/O General-purpose digital I/O
PJ.1 97 I/O General-purpose digital I/O
PJ.2 98 I/O General-purpose digital I/O
PJ.3 99 I/O General-purpose digital I/O
PM_UCB0SCL 38 I/O Default mapping: eUSCI_B0 I2C clock
I2C
PM_UCB0SDA 39 I/O Default mapping: eUSCI_B0 I2C data
COM0 32 O LCD common output COM0 for LCD backplane
COM1 33 O LCD common output COM1 for LCD backplane
COM2 34 O LCD common output COM2 for LCD backplane
COM3 35 O LCD common output COM3 for LCD backplane
COM4 36 O LCD common output COM4 for LCD backplane
COM5 37 O LCD common output COM5 for LCD backplane
COM6 38 O LCD common output COM6 for LCD backplane
LCD COM7 39 O LCD common output COM7 for LCD backplane
LCD capacitor connection
LCDCAP 29 I/O
CAUTION: This pin must be connected to DVSS if not used.
LCDREF 27 I External reference voltage input for regulated LCD voltage
R03 17 I/O Input/output port of lowest analog LCD voltage (V5)
R13 27 I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 28 I/O Input/output port of second most positive analog LCD voltage (V2)
Input/output port of most positive analog LCD voltage (V1)
R33 29 I/O
CAUTION: This pin must be connected to DVSS if not used.

24 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-5. Signal Descriptions, PZ Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE
S0 94 O LCD segment output S0
S1 93 O LCD segment output S1
S2 92 O LCD segment output S2
S3 91 O LCD segment output S3
S4 90 O LCD segment output S4
S5 89 O LCD segment output S5
S6 88 O LCD segment output S6
S7 87 O LCD segment output S7
S8 86 O LCD segment output S8
S9 85 O LCD segment output S9
S10 84 O LCD segment output S10
S11 83 O LCD segment output S11
S12 82 O LCD segment output S12
S13 81 O LCD segment output S13
S14 80 O LCD segment output S14
S15 79 O LCD segment output S15
S16 78 O LCD segment output S16
S17 77 O LCD segment output S17
S18 76 O LCD segment output S18
S19 73 O LCD segment output S19
LCD
S20 72 O LCD segment output S20
S21 71 O LCD segment output S21
S22 70 O LCD segment output S22
S23 69 O LCD segment output S23
S24 68 O LCD segment output S24
S25 67 O LCD segment output S25
S26 66 O LCD segment output S26
S27 65 O LCD segment output S27
S28 64 O LCD segment output S28
S29 63 O LCD segment output S29
S30 62 O LCD segment output S30
S31 61 O LCD segment output S31
S32 60 O LCD segment output S32
S33 59 O LCD segment output S33
S34 58 O LCD segment output S34
S35 57 O LCD segment output S35
S36 56 O LCD segment output S36
S37 55 O LCD segment output S37
S38 54 O LCD segment output S38
S39 53 O LCD segment output S39

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-5. Signal Descriptions, PZ Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE
AUXVCC1 19 P Auxiliary power supply AUXVCC1
AUXVCC2 18 P Auxiliary power supply AUXVCC2
AUXVCC3 26 P Auxiliary power supply AUXVCC3 for back up subsystem
AVCC 9 P Analog power supply
AVSS 8 P Analog ground supply
DVCC 21 P Digital power supply
22
Power DVSS P Digital ground supply
75
(1)
DVSYS 74 P Digital power supply for I/Os
Analog power supply selected among AVCC, AUXVCC1, AUXVCC2.
VASYS 10 P
Connect recommended capacitor value of CVSYS (see Table 5-18).
Regulated core power supply (internal use only, no external current
VCORE (2) 23 P
loading)
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2.
VDSYS (1) 20 P
Connect recommended capacitor value of CVSYS (see Table 5-18).
PM_SD0DIO 54 I/O Default mapping: SD24_B converter 0 bit stream data input/output
PM_SD1DIO 55 I/O Default mapping: SD24_B converter 1 bit stream data input/output
Default mapping: SD24_B converter 2 bit stream data input/output (not
PM_SD2DIO 56 I/O
available on F672xA devices)
PM_SDCLK 53 I/O Default mapping: SD24_B bit stream clock input/output
SD0N0 2 I SD24_B negative analog input for converter 0 (3)
SD0P0 1 I SD24_B positive analog input for converter 0 (3)
SD24
SD1N0 4 I SD24_B negative analog input for converter 1 (3)
SD1P0 3 I SD24_B positive analog input for converter 1 (3)
SD24_B negative analog input for converter 2 (3) (not available on F672xA
SD2N0 6 I
devices)
SD24_B positive analog input for converter 2 (3) (not available on F672xA
SD2P0 5 I
devices)
VREF 7 O SD24_B external reference voltage
PM_UCA0CLK 36 I/O Default mapping: eUSCI_A0 clock input/output
PM_UCA0SIMO 17 I/O Default mapping: eUSCI_A0 SPI slave in/master out
PM_UCA0SOMI 16 I/O Default mapping: eUSCI_A0 SPI slave out/master in
PM_UCA1CLK 45 I/O Default mapping: eUSCI_A1 clock input/output
PM_UCA1SIMO 28 I/O Default mapping: eUSCI_A1 SPI slave in/master out
PM_UCA1SOMI 27 I/O Default mapping: eUSCI_A1 SPI slave out/master in
SPI
PM_UCA2CLK 46 I/O Default mapping: eUSCI_A2 clock input/output
PM_UCA2SIMO 44 I/O Default mapping: eUSCI_A2 SPI slave in/master out
PM_UCA2SOMI 43 I/O Default mapping: eUSCI_A2 SPI slave out/master in
PM_UCB0CLK 37 I/O Default mapping: eUSCI_B0 clock input/output
PM_UCB0SIMO 39 I/O Default mapping: eUSCI_B0 SPI slave in/master out
PM_UCB0SOMI 38 I/O Default mapping: eUSCI_B0 SPI slave out/master in
NMI 100 I Nonmaskable interrupt input
System
RST 100 I Reset input active low (4)

(1) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
(3) TI recommends shorting unused analog input pairs and connect them to analog ground.
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

Table 4-5. Signal Descriptions, PZ Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0
PM_TA0.0 14 I/O
output
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1
PM_TA0.1 15 I/O
output
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2
PM_TA0.2 52 I/O
output
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0
PM_TA1.0 47 I/O
output
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1
PM_TA1.1 48 I/O
output
Timer_A Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0
PM_TA2.0 49 I/O
output
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1
PM_TA2.1 50 I/O
output
PM_TACLK 51 I Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3
TA1.0 30 I/O Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
TA1.1 31 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
TA2.0 40 I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
TA2.1 41 I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
TACLK 42 I Timer clock input TACLK for TA0, TA1, TA2, TA3
PM_UCA0RXD 16 I Default mapping: eUSCI_A0 UART receive data
PM_UCA0TXD 17 O Default mapping: eUSCI_A0 UART transmit data
PM_UCA1RXD 27 I Default mapping: eUSCI_A1 UART receive data
UART
PM_UCA1TXD 28 O Default mapping: eUSCI_A1 UART transmit data
PM_UCA2RXD 43 I Default mapping: eUSCI_A2 UART receive data
PM_UCA2TXD 44 O Default mapping: eUSCI_A2 UART transmit data

Copyright © 2015–2018, Texas Instruments Incorporated Terminal Configuration and Functions 27

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 4-6 describes the signals for all device variants in the PN package. See Table 4-5 for signal
descriptions in the PZ package.

Table 4-6. Signal Descriptions, PN Package

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE (1)
A0 13 I Analog input A0 for 10-bit ADC
A1 12 I Analog input A1 for 10-bit ADC
A2 11 I Analog input A2 for 10-bit ADC
ADC10 ADC10CLK 78 O ADC10_A clock output
Positive terminal for the ADC reference voltage for an external
VeREF+ 12 I
applied reference voltage
Negative terminal for the ADC reference voltage for an external
VeREF- 11 I
applied reference voltage
BSL_RX 42 I Bootloader data receive
BSL
BSL_TX 41 O Bootloader data transmit
ACLK 79 O ACLK clock output
MCLK 77 O MCLK clock output
PM_RTCCLK 43 O Default mapping: RTCCLK clock output
Clock
SMCLK 76 O SMCLK clock output
XIN 21 I Input terminal for crystal oscillator
XOUT 22 O Output terminal for crystal oscillator
SBWTCK 75 I Spy-Bi-Wire input clock
SBWTDIO 80 I/O Spy-Bi-Wire data input/output
TCK 79 I Test clock
TCLK 77 I Test clock input
Debug
TDI 77 I Test data input
TDO 76 O Test data output
TEST 75 I Test mode pin – select digital I/O on JTAG pins
TMS 78 I Test mode select
General-purpose digital I/O with port interrupt and mappable
P1.0 11 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P1.1 12 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P1.2 13 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P1.3 14 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P1.4 24 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P1.5 25 I/O
secondary function
GPIO
General-purpose digital I/O with port interrupt and mappable
P1.6 31 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P1.7 32 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.0 33 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.1 34 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.2 35 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.3 36 I/O
secondary function
(1) I = input, O = output
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

Table 4-6. Signal Descriptions, PN Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE (1)
General-purpose digital I/O with port interrupt and mappable
P2.4 37 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.5 38 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.6 39 I/O
secondary function
General-purpose digital I/O with port interrupt and mappable
P2.7 40 I/O
secondary function
P3.0 41 I/O General-purpose digital I/O with mappable secondary function
P3.1 42 I/O General-purpose digital I/O with mappable secondary function
P3.2 43 I/O General-purpose digital I/O with mappable secondary function
P3.3 44 I/O General-purpose digital I/O with mappable secondary function
P3.4 45 I/O General-purpose digital I/O with mappable secondary function
P3.5 46 I/O General-purpose digital I/O with mappable secondary function
P3.6 47 I/O General-purpose digital I/O with mappable secondary function
P3.7 48 I/O General-purpose digital I/O with mappable secondary function
P4.0 49 I/O General-purpose digital I/O
P4.1 50 I/O General-purpose digital I/O
P4.2 51 I/O General-purpose digital I/O
P4.3 52 I/O General-purpose digital I/O
P4.4 53 I/O General-purpose digital I/O
P4.5 54 I/O General-purpose digital I/O
GPIO P4.6 55 I/O General-purpose digital I/O
P4.7 56 I/O General-purpose digital I/O
P5.0 57 I/O General-purpose digital I/O
P5.1 58 I/O General-purpose digital I/O
P5.2 61 I/O General-purpose digital I/O
P5.3 62 I/O General-purpose digital I/O
P5.4 63 I/O General-purpose digital I/O
P5.5 64 I/O General-purpose digital I/O
P5.6 65 I/O General-purpose digital I/O
P5.7 66 I/O General-purpose digital I/O
P6.0 67 I/O General-purpose digital I/O
P6.1 68 I/O General-purpose digital I/O
P6.2 69 I/O General-purpose digital I/O
P6.3 70 I/O General-purpose digital I/O
P6.4 71 I/O General-purpose digital I/O
P6.5 72 I/O General-purpose digital I/O
P6.6 73 I/O General-purpose digital I/O
P6.7 74 I/O General-purpose digital I/O
PJ.0 76 I/O General-purpose digital I/O
PJ.1 77 I/O General-purpose digital I/O
PJ.2 78 I/O General-purpose digital I/O
PJ.3 79 I/O General-purpose digital I/O
PM_UCB0SCL 33 I/O Default mapping: eUSCI_B0 I2C clock
I2C
PM_UCB0SDA 34 I/O Default mapping: eUSCI_B0 I2C data

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Table 4-6. Signal Descriptions, PN Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE (1)
COM0 27 O LCD common output COM0 for LCD backplane
COM1 28 O LCD common output COM1 for LCD backplane
COM2 29 O LCD common output COM2 for LCD backplane
COM3 30 O LCD common output COM3 for LCD backplane
COM4 31 O LCD common output COM4 for LCD backplane
COM5 32 O LCD common output COM5 for LCD backplane
COM6 33 O LCD common output COM6 for LCD backplane
COM7 34 O LCD common output COM7 for LCD backplane
LCD capacitor connection
LCDCAP 26 I/O
CAUTION: This pin must be connected to DVSS if not used.
LCDREF 24 I External reference voltage input for regulated LCD voltage
R03 14 I/O Input/output port of lowest analog LCD voltage (V5)
Input/output port of third most positive analog LCD voltage (V3 or
R13 24 I/O
V4)
R23 25 I/O Input/output port of second most positive analog LCD voltage (V2)
Input/output port of most positive analog LCD voltage (V1)
R33 26 I/O
CAUTION: This pin must be connected to DVSS if not used.
S0 74 O LCD segment output S0
S1 73 O LCD segment output S1
S2 72 O LCD segment output S2
S3 71 O LCD segment output S3
S4 70 O LCD segment output S4
LCD S5 69 O LCD segment output S5
S6 68 O LCD segment output S6
S7 67 O LCD segment output S7
S8 66 O LCD segment output S8
S9 65 O LCD segment output S9
S10 64 O LCD segment output S10
S11 63 O LCD segment output S11
S12 62 O LCD segment output S12
S13 61 O LCD segment output S13
S14 58 O LCD segment output S14
S15 57 O LCD segment output S15
S16 56 O LCD segment output S16
S17 55 O LCD segment output S17
S18 54 O LCD segment output S18
S19 53 O LCD segment output S19
S20 52 O LCD segment output S20
S21 51 O LCD segment output S21
S22 50 O LCD segment output S22
S23 49 O LCD segment output S23
S24 48 O LCD segment output S24
S25 47 O LCD segment output S25
S26 46 O LCD segment output S26

30 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Table 4-6. Signal Descriptions, PN Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE (1)
S27 45 O LCD segment output S27
S28 44 O LCD segment output S28
S29 43 O LCD segment output S29
S30 42 O LCD segment output S30
S31 41 O LCD segment output S31
S32 40 O LCD segment output S32
LCD S33 39 O LCD segment output S33
S34 38 O LCD segment output S34
S35 37 O LCD segment output S35
S36 36 O LCD segment output S36
S37 35 O LCD segment output S37
S38 34 O LCD segment output S38
S39 33 O LCD segment output S39
AUXVCC1 16 P Auxiliary power supply AUXVCC1
AUXVCC2 15 P Auxiliary power supply AUXVCC2
AUXVCC3 23 P Auxiliary power supply AUXVCC3 for backup subsystem
AVCC 9 P Analog power supply
AVSS 8 P Analog ground supply
DVCC 18 P Digital power supply
DVSS 19 P Digital ground supply
Power DVSS 60 P Digital ground supply
DVSYS (2) 59 P Digital power supply for I/Os
Analog power supply selected between AVCC, AUXVCC1,
VASYS 10 P AUXVCC2. Connect recommended capacitor value of CVSYS (see
Table 5-18).
Regulated core power supply (internal use only, no external current
VCORE (3) 20 P
loading)
Digital power supply selected between DVCC, AUXVCC1,
VDSYS (2) 17 P AUXVCC2. Connect recommended capacitor value of CVSYS (see
Table 5-18).
PM_SD0DIO 46 I/O Default mapping: SD24_B converter 0 bit stream data input/output
PM_SD1DIO 47 I/O Default mapping: SD24_B converter 1 bit stream data input/output
Default mapping: SD24_B converter 2 bit stream data input/output
PM_SD2DIO 48 I/O
(not available on F672xA devices)
PM_SDCLK 45 I/O Default mapping: SD24_B bit stream clock input/output
SD0N0 2 I SD24_B negative analog input for converter 0 (4)
SD0P0 1 I SD24_B positive analog input for converter 0 (4)
SD24
SD1N0 4 I SD24_B negative analog input for converter 1 (4)
SD1P0 3 I SD24_B positive analog input for converter 1 (4)
SD24_B negative analog input for converter 2 (4) (not available on
SD2N0 6 I
F672xA devices)
SD24_B positive analog input for converter 2 (4) (not available on
SD2P0 5 I
F672xA devices)
VREF 7 I SD24_B external reference voltage

(2) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
(4) TI recommends shorting unused analog input pairs and connect them to analog ground.
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MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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Table 4-6. Signal Descriptions, PN Package (continued)

SIGNAL
FUNCTION SIGNAL NAME PIN NO. DESCRIPTION
TYPE (1)
PM_UCA0CLK 31 I/O Default mapping: eUSCI_A0 clock input/output
PM_UCA0SIMO 14 I/O Default mapping: eUSCI_A0 SPI slave in/master out
PM_UCA0SOMI 13 I/O Default mapping: eUSCI_A0 SPI slave out/master in
PM_UCA1CLK 37 I/O Default mapping: eUSCI_A1 clock input/output
PM_UCA1SIMO 25 I/O Default mapping: eUSCI_A1 SPI slave in/master out
PM_UCA1SOMI 24 I/O Default mapping: eUSCI_A1 SPI slave out/master in
SPI
PM_UCA2CLK 38 I/O Default mapping: eUSCI_A2 clock input/output
PM_UCA2SIMO 36 I/O Default mapping: eUSCI_A2 SPI slave in/master out
PM_UCA2SOMI 35 I/O Default mapping: eUSCI_A2 SPI slave out/master in
PM_UCB0CLK 32 I/O Default mapping: eUSCI_B0 clock input/output
PM_UCB0SIMO 34 I/O Default mapping: eUSCI_B0 SPI slave in/master out
PM_UCB0SOMI 33 I/O Default mapping: eUSCI_B0 SPI slave out/master in
NMI 80 I Nonmaskable interrupt input
System
RST 80 I/O Reset input active low (5)
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare:
PM_TA0.0 11 I/O
Out0 output
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare:
PM_TA0.1 12 I/O
Out1 output
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare:
PM_TA0.2 44 I/O
Out2 output
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare:
PM_TA1.0 39 I/O
Timer_A Out0 output
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare:
PM_TA1.1 40 I/O
Out1 output
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare:
PM_TA2.0 41 I/O
Out0 output
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare:
PM_TA2.1 42 I/O
Out1 output
PM_TACLK 43 I Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3
PM_UCA0RXD 13 I Default mapping: eUSCI_A0 UART receive data
PM_UCA0TXD 14 O Default mapping: eUSCI_A0 UART transmit data
PM_UCA1RXD 24 I Default mapping: eUSCI_A1 UART receive data
UART
PM_UCA1TXD 25 O Default mapping: eUSCI_A1 UART transmit data
PM_UCA2RXD 35 I Default mapping: eUSCI_A2 UART receive data
PM_UCA2TXD 36 O Default mapping: eUSCI_A2 UART transmit data
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.

32 Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

4.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.12.

4.5 Buffer Type

Table 4-7 describes the buffer types that are referenced in Table 4-3 and Table 4-4.

Table 4-7. Buffer Type

NOMINAL OUTPUT
BUFFER TYPE NOMINAL PU OR PD DRIVE OTHER
HYSTERESIS PU OR PD
(STANDARD) VOLTAGE STRENGTH STRENGTH CHARACTERISTICS
(µA) (mA)
See See
LVCMOS 3.0 V Y Programmable Section 5.8.4 Section 5.8.4
Digital I/O Ports Digital I/O Ports
See analog modules in
Analog 3.0 V N N/A N/A N/A Section 5, Specifications,
for details.
Power 3.0 V Y with SVS on N/A N/A N/A

4.6 Connection of Unused Pins

Table 4-8 lists the correct termination of unused pins.

Table 4-8. Connection of Unused Pins (1)

PIN POTENTIAL COMMENT
AVCC DVCC
AVSS DVSS
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y
Px.y Open
of port x (for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)
For dedicated XIN pins only. XIN pins with shared GPIO functions should be
XIN DVSS
programmed to GPIO and follow Px.y recommendations.
For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be
XOUT Open
programmed to GPIO and follow Px.y recommendations.
LCDCAP DVSS
RST/NMI DVCC or VCC 47-kΩ pullup or internal pullup selected with 10-nF (2.2-nF) pulldown (2)
PJ.0/TDO
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used,
PJ.1/TDI
Open these should be switched to port function, output direction (PJDIR.n = 1). When used as
PJ.2/TMS
JTAG pins, these pins should remain open.
PJ.3/TCK
TEST Open This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with a general-purpose I/O must follow the Px.y unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools such as FET interfaces or GANG programmers.

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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage applied at DVCC to DVSS –0.3 4.1 V
(3) (4)
All pins except VCORE , SD24_B input pins (SDxN0, SDxP0) ,
Voltage applied to pins (2) –0.3 VCC + 0.3 V
AUXVCC1, AUXVCC2, and AUXVCC3 (5)
All pins except SD24_B input pins (SDxN0, SDxP0) ±2
Diode current at pins mA
SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0 (6) 2
Maximum junction temperature, TJ 95 °C
Storage temperature, Tstg (7) –55 105 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS = VDVSS = VAVSS.
(3) VCORE is for internal device use only. No external DC loading or voltage should be applied.
(4) See Table 5-35 for SD24_B specifications.
(5) See Table 5-18 for AUX specifications.
(6) A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS.
(7) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6
Supply voltage during program execution and flash PMMCOREVx = 0, 1 2.0 3.6
VCC V
programming. V(AVCC) = V(DVCC) = VCC (1) (2) PMMCOREVx = 0, 1, 2 2.2 3.6
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
VSS Supply voltage V(AVSS) = V(DVSS) = VSS 0 V
TA Operating free-air temperature I version –40 85 °C
TJ Operating junction temperature I version –40 85 °C
(3)
CVCORE Recommended capacitor at VCORE 470 nF
CDVCC /
Capacitor ratio of DVCC to VCORE 10
CVCORE

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can
be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-14 threshold parameters for
the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
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MSP430F6720A
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Recommended Operating Conditions (continued)

MIN NOM MAX UNIT
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V 0 8.0
(default condition)
PMMCOREVx = 1,
Processor frequency (maximum MCLK frequency) (4) (5) 0 12.0
fSYSTEM 2.0 V ≤ VCC ≤ 3.6 V MHz
(see Figure 5-1)
PMMCOREVx = 2,
0 20.0
2.2 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 3,
0 25.0
2.4 V ≤ VCC ≤ 3.6 V
Maximum load current that can be drawn from DVCC for core and IO
ILOAD, DVCCD 20 mA
(ILOAD = ICORE + IIO)
Maximum load current that can be drawn from AUXVCC1 for core and IO
ILOAD, AUX1D 20 mA
(ILOAD = ICORE + IIO)
Maximum load current that can be drawn from AUXVCC2 for core and IO
ILOAD, AUX2D 20 mA
(ILOAD = ICORE + IIO)
Maximum load current that can be drawn from AVCC for analog modules
ILOAD, AVCCA 10 mA
(ILOAD = IModules)
Maximum load current that can be drawn from AUXVCC1 for analog modules
ILOAD, AUX1A 5 mA
(ILOAD = IModules)
Maximum load current that can be drawn from AUXVCC2 for analog modules
ILOAD, AUX2A 5 mA
(ILOAD = IModules)
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

20
System Frequency - MHz

2 2, 3

1 1, 2 1, 2, 3

0 0, 1 0, 1, 2 0, 1, 2, 3

0
1.8 2.0 2.2 2.4 3.6

Supply Voltage - V

The numbers within the fields denote the supported PMMCOREVx settings.

Figure 5-1. Maximum System Frequency

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MSP430F6720A
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MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
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5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)

FREQUENCY (fDCO = fMCLK = fSMCLK)

EXECUTION
PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNIT
MEMORY
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
0 0.32 0.36 2.10 2.30

(4)
1 0.36 2.39 3.54 3.90
IAM, Flash Flash 3.0 V mA
2 0.39 2.65 3.94 6.54 7.23
3 0.42 2.82 4.20 6.96 8.65 9.54
0 0.20 0.22 1.10 1.22

(5)
1 0.22 1.30 1.90 2.10
IAM, RAM RAM 3.0 V mA
2 0.24 1.45 2.15 3.55 4.0
3 0.26 1.55 2.30 3.80 4.70 5.30

(1) All inputs are tied to 0 or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.
(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.

36 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)

TEMPERATURE (TA)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 0 75 78 87 81 84 96
ILPM0,1MHz Low-power mode 0 (3) (4)
µA
3.0 V 3 85 89 99 93 98 110
2.2 V 0 5.9 6.2 9 6.9 9.4 17
ILPM2 Low-power mode 2 (5) (4)
µA
3.0 V 3 6.9 7.4 10 8.4 11 19
0 1.4 1.7 2.5 4.9
Low-power mode 3, crystal
ILPM3,XT1LF 2.2 V 1 1.5 1.9 2.7 5.2 µA
mode (6) (4)
2 1.7 2.0 2.9 5.5
0 2.2 2.5 3.1 3.3 5.5 12.7

Low-power mode 3, crystal 1 2.3 2.7 3.5 5.8

ILPM3,XT1LF 3.0 V µA
mode (6) (4) 2 2.5 2.9 3.7 6.1
3 2.5 2.9 3.5 3.7 6.1 14.0
0 1.4 1.7 2.2 2.4 4.5 11.5

Low-power mode 3, 1 1.5 1.8 2.5 4.7

ILPM3,VLO 3.0 V µA
VLO mode (7) (4) 2 1.6 1.9 2.7 4.9
3 1.6 1.9 2.4 2.7 5.0 12.7
0 1.3 1.6 2.0 2.3 4.4 11.1
1 1.4 1.6 2.4 4.5
ILPM4 Low-power mode 4 (8) (4)
3.0 V µA
2 1.4 1.7 2.5 4.8
3 1.4 1.7 2.2 2.5 4.8 12.2

Low-power mode 3.5, RTC 2.2 V 0.65 0.80 0.90 1.30

ILPM3.5 µA
active on AUXVCC3 (9) 3.0 V 1.16 1.24 2.05 1.43 1.87 2.71
(10)
ILPM4.5 Low-power mode 4.5 3.0 V 0.70 0.78 1.05 0.90 1.20 1.85 µA

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting
= 1-MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer clocked by ACLK included. RTC is disabled (RTCHOLD=1). ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1

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5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)

TEMPERATURE (TA)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
Low-power mode 3 0 2.4 2.9 3.6 3.8 5.8 12.2
ILPM3 (LPM3) current, LCD 4-
1 2.5 3.1 4.0 6.0
LCD, mux mode, internal 2.2 V µA
int. bias biasing, charge pump
2 2.6 3.3 3.9 4.2 6.3 13.4
disabled (3) (4)
Low-power mode 3 0 2.8 3.2 3.9 4.1 6.4 13.3
ILPM3 (LPM3) current, LCD 4- 1 2.9 3.4 4.3 6.7
LCD, mux mode, internal 3.0 V µA
int. bias biasing, charge pump 2 3.1 3.6 4.5 7.0
disabled (3) (4) 3 3.1 3.6 4.5 4.5 7.0 14.7
0 3.8
2.2 V 1 3.9
Low-power mode 3
2 4.0
(LPM3) current, LCD 4-
ILPM3
mux mode, internal 0 4.0 µA
LCD,CP
biasing, charge pump
1 4.1
enabled (3) (5) 3.0 V
2 4.2
3 4.2
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.

38 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

5.7 Thermal Resistance Characteristics

THERMAL METRIC (1) (2)
VALUE UNIT
LQFP 80 (PN) 46.3
RθJA Junction-to-ambient thermal resistance, still air °C/W
LQFP 100 (PZ) 45.6
LQFP 80 (PN) 11.5
RθJC(TOP) Junction-to-case (top) thermal resistance °C/W
LQFP 100 (PZ) 11.0
LQFP 80 (PN) N/A (3)
RθJC(BOTTOM) Junction-to-case (bottom) thermal resistance °C/W
LQFP 100 (PZ) N/A
LQFP 80 (PN) 21.9
RθJB Junction-to-board thermal resistance °C/W
LQFP 100 (PZ) 23.4
LQFP 80 (PN) 0.5
ΨJT Junction-to-package-top thermal characterization parameter °C/W
LQFP 100 (PZ) 0.4
LQFP 80 (PN) 21.6
ΨJB Junction-to-board thermal characterization parameter °C/W
LQFP 100 (PZ) 23.0
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = not applicable

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5.8 Timing and Switching Characteristics

5.8.1 Power Supply Sequencing

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and flash.

5.8.2 Reset Timing

Table 5-1 lists the device wake-up times.

Table 5-1. Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PMMCOREV = SVSMLRRL = n fMCLK ≥ 4 MHz 3 5
Wake-up time from LPM2, LPM3,
tWAKE-UP-FAST (where n = 0, 1, 2, or 3), 1 MHz < fMCLK < µs
or LPM4 to active mode (1) 4 6
SVSLFP = 1 4 MHz
PMMCOREV = SVSMLRRL = n
Wake-up time from LPM2, LPM3,
tWAKE-UP-SLOW (where n = 0, 1, 2, or 3), 150 160 µs
or LPM4 to active mode (2) (3)
SVSLFP = 0
Wake-up time from LPM4.5 to
tWAKE-UP-LPM4.5 2 3 ms
active mode (4)
Wake-up time from RST or BOR
tWAKE-UP-RESET 2 3 ms
event to active mode (4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the
Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the
performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.

40 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

5.8.3 Clock Specifications

Table 5-2 lists the characteristics of the crystal oscillator in low-frequency mode.

Table 5-2. Crystal Oscillator, XT1, Low-Frequency Mode (1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
0.075
XT1DRIVEx = 1, TA = 25°C
Differential XT1 oscillator
crystal current consumption fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
ΔIDVCC.LF 3.0 V 0.170 µA
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C
mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
0.290
XT1DRIVEx = 3, TA = 25°C
XT1 oscillator crystal
fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 Hz
frequency, LF mode
XT1 oscillator logic-level
fXT1,LF,SW square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2) (3)
10 32.768 50 kHz
LF mode
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
210
Oscillation allowance for fXT1,LF = 32768 Hz, CL,eff = 6 pF
OALF kΩ
LF crystals (4) XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
300
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 (6) 1
Integrated effective load XTS = 0, XCAPx = 1 5.5
CL,eff pF
capacitance, LF mode (5) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
XTS = 0, Measured at ACLK,
Duty cycle, LF mode 30% 70%
fXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0 (8) 10 10000 Hz
LF mode (7)
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
1000
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
tSTART,LF Start-up time, LF mode 3.0 V ms
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
500
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-Trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.

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Table 5-3 lists the characteristics of the VLO.

Table 5-3. Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 15 kHz
(1)
dfVLO/dT VLO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 30% 70%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-4 lists the characteristics of the REFO.

Table 5-4. Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
REFO oscillator current
IREFO TA = 25°C 1.8 V to 3.6 V 3 µA
consumption
REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
fREFO Full temperature range 1.8 V to 3.6 V ±3.5%
REFO absolute tolerance calibrated
TA = 25°C 3V ±1.5%
(1)
dfREFO/dT REFO frequency temperature drift Measured at ACLK 1.8 V to 3.6 V 0.01 %/°C
dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 1.0 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
tSTART REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

42 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-5 lists the DCO frequencies.

Table 5-5. DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fDCO(0,0) DCO frequency (0, 0) (1) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
(1)
fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz
fDCO(1,31) DCO frequency (1, 31) (1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz
fDCO(2,0) DCO frequency (2, 0) (1) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz
(1)
fDCO(2,31) DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz
fDCO(3,0) DCO frequency (3, 0) (1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz
fDCO(3,31) DCO frequency (3, 31) (1) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz
(1)
fDCO(4,0) DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz
fDCO(4,31) DCO frequency (4, 31) (1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz
fDCO(5,0) DCO frequency (5, 0) (1) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz
(1)
fDCO(5,31) DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz
fDCO(6,0) DCO frequency (6, 0) (1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz
fDCO(6,31) DCO frequency (6, 31) (1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz
fDCO(7,0) DCO frequency (7, 0) (1) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz
(1)
fDCO(7,31) DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
Frequency step between range
SDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
DCORSEL and DCORSEL + 1
Frequency step between tap
SDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
DCO and DCO + 1
Duty cycle Measured at SMCLK 40% 50% 60%
dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz 0.1 %/°C
dfDCO/dVCORE DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCOfrequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.

100
VCC = 3.0 V
TA = 25°C

10
fDCO – MHz

DCOx = 31
1

DCOx = 0
0.1
0 1 2 3 4 5 6 7
DCORSEL

Figure 5-2. Typical DCO Frequency

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5.8.4 Digital I/O Ports

Table 5-6 lists the characteristics of the GPIOs.

Table 5-6. Schmitt-Trigger Inputs, General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.80 1.40
VIT+ Positive-going input threshold voltage V
3V 1.50 2.10
1.8 V 0.45 1.00
VIT– Negative-going input threshold voltage V
3V 0.75 1.65
1.8 V 0.3 0.85
Vhys Input voltage hysteresis (VIT+ – VIT–) V
3V 0.4 1.0
For pullup: VIN = VSS
RPull Pullup or pulldown resistor (1) 20 35 50 kΩ
For pulldown: VIN = VCC
CI Input capacitance VIN = VSS or VCC 5 pF
(1) Also applies to RST pin when pullup or pulldown resistor is enabled.

Table 5-7 lists the characteristics of the P1 and P2 inputs.

Table 5-7. Inputs, Ports P1 and P2 (1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse duration
t(int) External interrupt timing (2) 2.2 V, 3 V 20 ns
to set interrupt flag
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It might be set by trigger signals
shorter than t(int).

Table 5-8 lists the leakage currents of the GPIOs.

Table 5-8. Leakage Current, General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
(1) (2)
Ilkg(Px.y) High-impedance leakage current See 1.8 V, 3 V ±50 nA
(1) The leakage current is measured with VSSor VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.

44 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-9 lists the output characteristics of the GPIOs in full drive strength mode. Also see Figure 5-3
through Figure 5-6.

Table 5-9. Outputs, General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = –3 mA (1) VCC – 0.25 VCC
1.8 V
I(OHmax) = –10 mA (1) VCC – 0.60 VCC
VOH High-level output voltage V
I(OHmax) = –5 mA (1) VCC – 0.25 VCC
3V
I(OHmax) = –15 mA (1) VCC – 0.60 VCC
I(OLmax) = 3 mA (2) VSS VSS + 0.25
1.8 V
I(OLmax) = 10 mA (3) VSS VSS + 0.60
VOL Low-level output voltage V
I(OLmax) = 5 mA (2) VSS VSS + 0.25
3V
I(OLmax) = 15 mA (3) VSS VSS + 0.60
(1) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(2) The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
(3) The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

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5.8.4.1 Typical Characteristics, General-Purpose I/O (Full Drive Strength)

0 0

-10
-5
IOH – High-Level Output Current – mA

IOH – High-Level Output Current – mA

-20
-10

-30

-15
TA = 85°C -40

TA = 85°C
-20
-50
TA = 25°C

TA = 25°C
-25 -60
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3
VOH – High-Level Output Voltage – V VOH – High-Level Output Voltage – V
VCC = 1.8 V Full Drive Strength VCC = 3 V Full Drive Strength
Figure 5-3. High-Level Output Current vs High-Level Output Figure 5-4. High-Level Output Current vs High-Level Output
Voltage Voltage

25 60

50
20
IOL – Low-Level Output Current – mA

IOL – Low-Level Output Current – mA

TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C 40
15

10
20

5
10

0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3
VOL – Low-Level Output Voltage – V VOL – Low-Level Output Voltage – V
VCC = 1.8 V Full Drive Strength VCC = 3 V Full Drive Strength
Figure 5-5. Low-Level Output Current vs Low-Level Output Figure 5-6. Low-Level Output Current vs Low-Level Output
Voltage Voltage

46 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-10 lists the output characteristics of the GPIOs in reduced drive strength mode. Also see Figure 5-
7 through Figure 5-10.

Table 5-10. Outputs, General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = –1 mA (2) VCC – 0.25 VCC
1.8 V
I(OHmax) = –3 mA (2) VCC – 0.60 VCC
VOH High-level output voltage V
I(OHmax) = –2 mA (2) VCC – 0.25 VCC
3.0 V
I(OHmax) = –6 mA (2) VCC – 0.60 VCC
I(OLmax) = 1 mA (3) VSS VSS + 0.25
1.8 V
I(OLmax) = 3 mA (4) VSS VSS + 0.60
VOL Low-level output voltage V
I(OLmax) = 2 mA (3) VSS VSS + 0.25
3.0 V
I(OLmax) = 6 mA (4) VSS VSS + 0.60
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
(3) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(4) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.

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5.8.4.2 Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)

0 0

-1

-5
IOH – High-Level Output Current – mA

IOH – High-Level Output Current – mA

-2

-3
-10

-4

-15
-5
TA = 85°C
TA = 85°C
-6
-20

-7 TA = 25°C
TA = 25°C
-8 -25
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3
VOH – High-Level Output Voltage – V VOH – High-Level Output Voltage – V
VCC = 1.8 V Reduced Drive Strength VCC = 3 V Reduced Drive Strength
Figure 5-7. High-Level Output Current vs High-Level Output Figure 5-8. High-Level Output Current vs High-Level Output
Voltage Voltage

8 20

18
7 TA = 25°C
TA = 25°C 16
IOL – Low-Level Output Current – mA

IOL – Low-Level Output Current – mA

6 TA = 85°C
14
TA = 85°C
5
12

4 10

8
3
6
2
4

1
2

0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3
VOL – Low-Level Output Voltage – V VOL – Low-Level Output Voltage – V
VCC = 1.8 V Reduced Drive Strength VCC = 3 V Reduced Drive Strength
Figure 5-9. Low-Level Output Current vs Low-Level Output Figure 5-10. Low-Level Output Current vs Low-Level Output
Voltage Voltage

48 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-11 lists the output frequencies of the GPIOs.

Table 5-11. Output Frequency, General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 1.8 V,
16
PMMCOREVx = 0
fPx.y Port output frequency (with load) See (1) (2)
MHz
VCC = 3 V,
25
PMMCOREVx = 3
VCC = 1.8 V,
16
ACLK, SMCLK, MCLK, PMMCOREVx = 0
fPort_CLK Clock output frequency MHz
CL = 20 pF (2) VCC = 3 V,
25
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

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5.8.5 Power-Management Module (PMM)

Table 5-12 lists the characteristics of the BOR.

Table 5-12. PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s 1.45 V
V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s 0.80 1.30 1.50 V
V(DVCC_BOR_hys) BORH hysteresis 50 250 mV
(1) Pulse duration required at RST/NMI pin to
tRESET 2 µs
accept a reset
(1) Pulse shorter than 2 µs might trigger reset.

Table 5-13 lists the characteristics of the PMM core voltage.

Table 5-13. PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.93 V
VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.83 V
VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.62 V
VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.42 V
VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.96 V
VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.94 V
VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.74 V
VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.54 V

50 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-14 lists the characteristics of the high-side SVS.

Table 5-14. PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSHE = 0, DVCC = 3.6 V 0
nA
I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA
SVSHE = 1, SVSHRVL = 0 1.60 1.65 1.70
SVSHE = 1, SVSHRVL = 1 1.77 1.84 1.90
V(SVSH_IT–) SVSH on voltage level (1) V
SVSHE = 1, SVSHRVL = 2 1.97 2.04 2.10
SVSHE = 1, SVSHRVL = 3 2.09 2.16 2.23
SVSHE = 1, SVSMHRRL = 0 1.68 1.74 1.80
SVSHE = 1, SVSMHRRL = 1 1.89 1.95 2.01
SVSHE = 1, SVSMHRRL = 2 2.08 2.14 2.21
SVSHE = 1, SVSMHRRL = 3 2.21 2.27 2.34
V(SVSH_IT+) SVSH off voltage level (1) V
SVSHE = 1, SVSMHRRL = 4 2.35 2.41 2.49
SVSHE = 1, SVSMHRRL = 5 2.65 2.72 2.80
SVSHE = 1, SVSMHRRL = 6 2.96 3.04 3.13
SVSHE = 1, SVSMHRRL = 7 2.96 3.04 3.13
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5
tpd(SVSH) SVSH propagation delay µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20
SVSHE = 0 → 1, SVSHFP = 1 12.5
t(SVSH) SVSH on or off delay time µs
SVSHE = 0 → 1, SVSHFP = 0 100
dVDVCC/dt DVCC rise time 0 1000 V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.

Table 5-15 lists the characteristics of the high-side SVM.

Table 5-15. PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMHE = 0, DVCC = 3.6 V 0
nA
I(SVMH) SVMH current consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA
SVMHE = 1, SVSMHRRL = 0 1.68 1.74 1.80
SVMHE = 1, SVSMHRRL = 1 1.89 1.95 2.01
SVMHE = 1, SVSMHRRL = 2 2.08 2.14 2.21
SVMHE = 1, SVSMHRRL = 3 2.21 2.27 2.34
V(SVMH) SVMH on or off voltage level (1) SVMHE = 1, SVSMHRRL = 4 2.35 2.41 2.49 V
SVMHE = 1, SVSMHRRL = 5 2.65 2.72 2.80
SVMHE = 1, SVSMHRRL = 6 2.96 3.04 3.13
SVMHE = 1, SVSMHRRL = 7 2.96 3.04 3.13
SVMHE = 1, SVMHOVPE = 1 3.79
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5
tpd(SVMH) SVMH propagation delay µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20
SVMHE = 0 → 1, SVMHFP = 1 12.5
t(SVMH) SVMH on or off delay time µs
SVMHE = 0 → 1, SVMHFP = 0 100
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.

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Table 5-16 lists the characteristics of the low-side SVS.

Table 5-16. PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSLE = 0, PMMCOREV = 2 0
nA
I(SVSL) SVSL current consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5
tpd(SVSL) SVSL propagation delay µs
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20
SVSLE = 0 → 1, SVSLFP = 1 12.5
t(SVSL) SVSL on or off delay time µs
SVSLE = 0 → 1, SVSLFP = 0 100

Table 5-17 lists the characteristics of the low-side SVM.

Table 5-17. PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMLE = 0, PMMCOREV = 2 0
nA
I(SVML) SVML current consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5
tpd(SVML) SVML propagation delay µs
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20
SVMLE = 0 → 1, SVMLFP = 1 12.5
t(SVML) SVML on or off delay time µs
SVMLE = 0 → 1, SVMLFP = 0 100

52 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

5.8.6 Auxiliary Supplies Module

Table 5-18 lists the recommended operating conditions of the auxiliary supplies.

Table 5-18. Auxiliary Supplies, Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage for all supplies at pins DVCC, AVCC, AUX1, AUX2, AUX3 1.8 3.6 V
PMMCOREVx = 0 1.8 3.6
Digital system supply voltage range, PMMCOREVx = 1 2.0 3.6
VDSYS V
VDSYS = VCC – RON × ILOAD PMMCOREVx = 2 2.2 3.6
PMMCOREVx = 3 2.4 3.6
VASYS Analog system supply voltage range, VASYS = VCC - RON × ILOAD Refer to modules V
CVCC,
Recommended capacitor at pins DVCC, AVCC, AUX1, AUX2 4.7 µF
CAUX1/2
CVSYS Recommended capacitor at pins VDSYS and VASYS 4.7 µF
CVCORE Recommended capacitance at pin VCORE 0.47 µF
CAUX3 Recommended capacitor at pin AUX3 0.47 µF

Table 5-19 lists the current consumption of AUX3.

Table 5-19. Auxiliary Supplies, AUX3 (Backup Subsystem) Currents

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TA MIN MAX UNIT
RTC and 32-kHz oscillator in 25°C 0.83
IAUX3,RTCon AUX3 current with RTC enabled 3V µA
backup subsystem enabled 85°C 0.95
RTC and 32-kHz oscillator in 25°C 110
IAUX3,RTCoff AUX3 current with RTC disabled 3V nA
backup subsystem disabled 85°C 165

Table 5-20 lists the characteristics of the auxiliary supply monitor.

Table 5-20. Auxiliary Supplies, Auxiliary Supply Monitor

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
LOCKAUX = 0, AUXMRx = 0,
Average supply current for
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
ICC,Monitor monitoring circuitry drawn from 3V 0.70 µA
VDSYS = DVCC, VASYS = AVCC,
VDSYS (also see Figure 5-11)
Current measured at VDSYS pin
LOCKAUX = 0, AUXMRx = 0,
Average current drawn from
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
monitored supply during
IMeas,Monitor VDSYS = DVCC, VASYS = AVCC, 0.11 µA
measurement cycle (also see
AUXVCC1 = 3 V,
Figure 5-12)
Current measured at AUXVCC1 pin
AUXLVLx = 0 1.67 1.74 1.80
AUXLVLx = 1 1.87 1.95 2.01
AUXLVLx = 2 2.06 2.14 2.21
AUXLVLx = 3 2.19 2.27 2.33
VMonitor Auxiliary supply threshold level V
AUXLVLx = 4 2.33 2.41 2.48
AUXLVLx = 5 2.63 2.72 2.79
AUXLVLx = 6 2.91 3.02 3.10
AUXLVLx = 7 2.91 3.02 3.10

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0.7

0.6

0.5
ICC, monitor – µA

0.4

0.3

0.2

0.1

0
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDSYS Voltage – V

Figure 5-11. VDSYS Voltage vs ICC,Monitor

120

100

80
Imeas, monitor – nA

0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
AUXVCC1 Voltage – V

Figure 5-12. AUXVCC1 Voltage vs IMeas,Monitor

Table 5-21 lists the AUX switch ON resistance characteristics.

Table 5-21. Auxiliary Supplies, Switch ON-Resistance

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
ON-resistance of switch between DVCC
RON,DVCC ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω
and VDSYS
ON-resistance of switch between AUX1
RON,DAUX1 ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω
and VDSYS
ON-resistance of switch between AUX2
RON,DAUX2 ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA 5 Ω
and VDSYS
ON-resistance of switch between AVCC
RON,AVCC ILOAD = IModules = 10 mA 5 Ω
and VASYS
ON-resistance of switch between AUX1
RON,AAUX1 ILOAD = IModules = 5 mA 20 Ω
and VASYS
ON-resistance of switch between AUX2
RON,AAUX2 ILOAD = IModules = 5 mA 20 Ω
and VASYS

54 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-22 lists the switching times of the auxiliary supplies.

Table 5-22. Auxiliary Supplies, Switching Time

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
tSwitch Time from occurrence of trigger (SVM or software) to "new" supply connected to system supplies 100 ns
tRecover "Recovery time" after a switch over takes place; during this time, no further switching takes place 200 450 µs

Table 5-23 lists the leakage characteristics of the auxiliary supplies switch.

Table 5-23. Auxiliary Supplies, Switch Leakage

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current into DVCC, AVCC, AUX1 or AUX2 if not
ISW,Lkg Per supply (but not the highest supply) 50 100 nA
selected
IVmax Current drawn from highest supply 450 730 nA

Table 5-24 lists the characteristics of the auxiliary supplies to the ADC.

Table 5-24. Auxiliary Supplies, Auxiliary Supplies to ADC10_A

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.58 0.60 0.62
Supply voltage divider
V3 3.0 V 0.98 1.00 1.02 V
V3 = VSupply / 3
3.6 V 1.18 1.20 1.22
AUXADCRx = 0 18
RV3 Load resistance AUXADCRx = 1 1.5 kΩ
AUXADCRx = 2 0.6
AUXADCRx = 0 1000
AUXADC = 1, ADC10ON = 1,
Sampling time required if
tSample,V3 INCH = 0Ch, AUXADCRx = 1 1000 ns
V3 selected
Error of conversion result ≤ 1 LSB
AUXADCRx = 2 1000

Table 5-25 lists the characteristics of the charge-limiting resistor.

Table 5-25. Auxiliary Supplies, Charge-Limiting Resistor

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
CHCx = 1 3V 5
RCHARGE Charge limiting resistor CHCx = 2 3V 10 kΩ
CHCx = 3 3V 20

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5.8.7 Timer_A Module

Table 5-26 lists the characteristics of the Timer_A.

Table 5-26. Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fTA Timer_A input clock frequency External: TACLK 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
tTA,cap Timer_A capture timing 1.8 V, 3 V 20 ns
duration required for capture

5.8.8 eUSCI Module

Table 5-27 lists the supported clock frequencies of the eUSCI in UART mode.

Table 5-27. eUSCI (UART Mode) Clock Frequency

PARAMETER TEST CONDITIONS MIN MAX UNIT
Internal: SMCLK or ACLK,
feUSCI eUSCI input clock frequency External: UCLK, fSYSTEM MHz
Duty cycle = 50% ±10%
fBITCLK BITCLK clock frequency (equals baud rate in MBaud) 5 MHz

Table 5-28 lists the switching characteristics of the eUSCI in UART mode.

Table 5-28. eUSCI (UART Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
UCGLITx = 0 10 15 25
UCGLITx = 1 30 50 85
tt UART receive deglitch time (1) 2 V, 3 V ns
UCGLITx = 2 50 80 150
UCGLITx = 3 70 120 200
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.

56 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode.

Table 5-29. eUSCI (SPI Master Mode) Clock Frequency

PARAMETER TEST CONDITIONS MIN MAX UNIT
Internal: SMCLK or ACLK,
feUSCI eUSCI input clock frequency fSYSTEM MHz
Duty cycle = 50% ±10%

Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode.

Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 150
tSTE,LEAD STE lead time, STE active to clock ns
UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 150
STE lag time, Last clock to STE UCSTEM = 0, UCMODEx = 01 or 10 2 V, 3 V 200
tSTE,LAG ns
inactive UCSTEM = 1, UCMODEx = 01 or 10 2 V, 3 V 200
2V 50
UCSTEM = 0, UCMODEx = 01 or 10
STE access time, STE active to 3V 30
tSTE,ACC ns
SIMO data out 2V 50
UCSTEM = 1, UCMODEx = 01 or 10
3V 30
2V 40
UCSTEM = 0, UCMODEx = 01 or 10
STE disable time, STE inactive to 3V 25
tSTE,DIS ns
SIMO high impedance 2V 40
UCSTEM = 1, UCMODEx = 01 or 10
3V 25
2V 50
tSU,MI SOMI input data setup time ns
3V 30
2V 0
tHD,MI SOMI input data hold time ns
3V 0
2V 9
tVALID,MO SIMO output data valid time (2) UCLK edge to SIMO valid, CL = 20 pF ns
3V 5
2V 0
tHD,MO SIMO output data hold time (3) CL = 20 pF ns
3V 0
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
13 and Figure 5-14.

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UCMODEx = 01
STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0

UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI

SOMI

tSTE,ACC tVALID,MO tSTE,DIS

SIMO

Figure 5-13. BadDriveBacuSPI Master Mode, CKPH = 0

UCMODEx = 01

STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0

UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI

SOMI

tSTE,ACC tVALID,MO tSTE,DIS

SIMO

Figure 5-14. SPI Master Mode, CKPH = 1

58 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-31 lists the switching characteristics of the eUSCI in SPI slave mode.

Table 5-31. eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
2.0 V 4
tSTE,LEAD STE lead time, STE active to clock ns
3.0 V 3
2.0 V 0
tSTE,LAG STE lag time, Last clock to STE inactive ns
3.0 V 0
2.0 V 46
tSTE,ACC STE access time, STE active to SOMI data out ns
3.0 V 24
STE disable time, STE inactive to SOMI high 2.0 V 38
tSTE,DIS ns
impedance 3.0 V 25
2.0 V 2
tSU,SI SIMO input data setup time ns
3.0 V 1
2.0 V 2
tHD,SI SIMO input data hold time ns
3.0 V 2
UCLK edge to SOMI valid, 2.0 V 55
tVALID,SO SOMI output data valid time (2) ns
CL = 20 pF 3.0 V 32
2.0 V 24
tHD,SO SOMI output data hold time (3) CL = 20 pF ns
3.0 V 16
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-15 and Figure 5-16.

UCMODEx = 01
STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0
UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH tSU,SIMO

tHD,SIMO

SIMO

tACC tVALID,SOMI tDIS

SOMI

Figure 5-15. SPI Slave Mode, CKPH = 0

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UCMODEx = 01
STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0
UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH
tHD,SI
tSU,SI
SIMO

tACC tVALID,SO tDIS

SOMI

Figure 5-16. SPI Slave Mode, CKPH = 1

60 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-32 lists the characteristics of the eUSCI in I2C mode.

Table 5-32. eUSCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
feUSCI eUSCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL SCL clock frequency 2 V, 3 V 0 400 kHz
fSCL = 100 kHz 5.1
tHD,STA Hold time (repeated) START 2 V, 3 V µs
fSCL > 100 kHz 1.5
fSCL = 100 kHz 5.1
tSU,STA Setup time for a repeated START 2 V, 3 V µs
fSCL > 100 kHz 1.4
tHD,DAT Data hold time 2 V, 3 V 0.4 µs
fSCL = 100 kHz 2 V, 3 V 5.0
tSU,DAT Data setup time µs
fSCL > 100 kHz 2 V, 3 V 1.3
fSCL = 100 kHz 5.2
tSU,STO Setup time for STOP 2 V, 3 V µs
fSCL > 100 kHz 1.7
UCGLITx = 0 75 220
UCGLITx = 1 35 120
tSP Pulse duration of spikes suppressed by input filter 2 V, 3 V ns
UCGLITx = 2 30 60
UCGLITx = 3 20 35
UCCLTOx = 1 30
tTIMEOUT Clock low time-out UCCLTOx = 2 2 V, 3 V 33 ms
UCCLTOx = 3 37

tHD,STA tSU,STA tHD,STA tBUF

SDA

tLOW tHIGH tSP

SCL

tSU,DAT tSU,STO
tHD,DAT

Figure 5-17. I2C Mode Timing

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5.8.9 LCD Controller

Table 5-33 lists the operating conditions of the LCD.

Table 5-33. LCD_C Operating Conditions

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Supply voltage range, charge LCDCPEN = 1, 0000 < VLCDx ≤ 1111
VCC,LCD_C,CP en,3.6 2.2 3.6 V
pump enabled, VLCD ≤ 3.6 V (charge pump enabled, VLCD ≤ 3.6 V)
Supply voltage range, charge LCDCPEN = 1, 0000 < VLCDx ≤ 1100
VCC,LCD_C,CP en,3.3 2.0 3.6 V
pump enabled, VLCD ≤ 3.3 V (charge pump enabled, VLCD ≤ 3.3 V)
Supply voltage range, internal
VCC,LCD_C,int. bias LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
biasing, charge pump disabled
Supply voltage range, external
VCC,LCD_C,ext. bias LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
biasing, charge pump disabled
Supply voltage range, external
VCC,LCD_C,VLCDEXT LCD voltage, internal or external LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V
biasing, charge pump disabled
External LCD voltage at
VLCDCAP/R33 LCDCAP/R33, internal or external LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V
biasing, charge pump disabled
Capacitor on LCDCAP when LCDCPEN = 1, VLCDx > 0000
CLCDCAP 4.7 10 µF
charge pump enabled (charge pump enabled)
fFRAME = 1/(2 × mux) × fLCD
fLCD LCD frequency range 0 1024 Hz
with mux = 1 (static) to 8
fFRAME,4mux(MAX) = 1/(2 × 4) ×
fFRAME,4mux LCD frame frequency range 128 Hz
fLCD(MAX) = 1/(2 × 4) × 1024 Hz
fFRAME,8mux(MAX) = 1/(2 × 4) ×
fFRAME,8mux LCD frame frequency range 64 Hz
fLCD(MAX) = 1/(2 × 8) × 1024 Hz
fACLK,in ACLK input frequency range 30 32 40 kHz
CPanel Panel capacitance 100-Hz frame frequency 10000 pF
VCC +
VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 2.4 V
0.2
VR03 + 2/3 ×
LCDREXT = 1, LCDEXTBIAS = 1,
VR23,1/3bias Analog input voltage at R23 VR13 (VR33 – VR33 V
LCD2B = 0
VR03)
VR03 + 1/3 ×
Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,
VR13,1/3bias VR03 (VR33 – VR23 V
1/3 biasing LCD2B = 0
VR03)
VR03 + 1/2 ×
Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,
VR13,1/2bias VR03 (VR33 – VR33 V
1/2 biasing LCD2B = 1
VR03)
VR03 Analog input voltage at R03 R0EXT = 1 VSS V
Voltage difference between VLCD VCC +
VLCD-VR03 LCDCPEN = 0, R0EXT = 1 2.4 V
and R03 0.2
External LCD reference voltage
VLCDREF/R13 VLCDREFx = 01 0.8 1.2 1.5 V
applied at LCDREF/R13

62 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-34 lists the characteristics of the LCD.

Table 5-34. LCD_C Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VLCDx = 0000, VLCDEXT = 0 2.4 V to 3.6 V VCC
LCDCPEN = 1, VLCDx = 0001 2 V to 3.6 V 2.58
LCDCPEN = 1, VLCDx = 0010 2 V to 3.6 V 2.64
LCDCPEN = 1, VLCDx = 0011 2 V to 3.6 V 2.71
LCDCPEN = 1, VLCDx = 0100 2 V to 3.6 V 2.78
LCDCPEN = 1, VLCDx = 0101 2 V to 3.6 V 2.83
LCDCPEN = 1, VLCDx = 0110 2 V to 3.6 V 2.90
LCDCPEN = 1, VLCDx = 0111 2 V to 3.6 V 2.96
VLCD LCD voltage V
LCDCPEN = 1, VLCDx = 1000 2 V to 3.6 V 3.02
LCDCPEN = 1, VLCDx = 1001 2 V to 3.6 V 3.07
LCDCPEN = 1, VLCDx = 1010 2 V to 3.6 V 3.14
LCDCPEN = 1, VLCDx = 1011 2 V to 3.6 V 3.21
LCDCPEN = 1, VLCDx = 1100 2 V to 3.6 V 3.27
LCDCPEN = 1, VLCDx = 1101 2.2 V to 3.6 V 3.32
LCDCPEN = 1, VLCDx = 1110 2.2 V to 3.6 V 3.38
LCDCPEN = 1, VLCDx = 1111 2.2 V to 3.6 V 3.44 3.6
Peak supply currents due to 2.2 V
ICC,Peak,CP LCDCPEN = 1, VLCDx = 1111 400 µA
charge pump activities
Time to charge CLCD when CLCD = 4.7µF, LCDCPEN = 0→1, 2.2 V
tLCD,CP,on 150 500 ms
discharged VLCDx = 1111
Maximum charge pump load 2.2 V
ICP,Load LCDCPEN = 1, VLCDx = 1111 50 µA
current
LCD driver output impedance, LCDCPEN = 1, VLCDx = 1000, 2.2 V
RLCD,Seg 10 kΩ
segment lines ILOAD = ±10 µA
LCD driver output impedance, LCDCPEN = 1, VLCDx = 1000, 2.2 V
RLCD,COM 10 kΩ
common lines ILOAD = ±10 µA

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5.8.10 SD24_B Module

Table 5-35 lists the power supply and recommended operating conditions of the SD24_B.

Table 5-35. SD24_B Power Supply and Recommended Operating Conditions

MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC, AVSS = DVSS = 0 V 2.4 3.6 V
(1)
fSD Modulator clock frequency 0.03 2.3 MHz
VI Absolute input voltage range AVSS – 1 AVCC V
VIC Common-mode input voltage range AVSS – 1 AVCC V
VID,FS Differential full-scale input voltage VID = VI,A+ – VI,A– –VREF/GAIN +VREF/GAIN
SD24GAINx = 1 ±910 ±920
SD24GAINx = 2 ±455 ±460
SD24GAINx = 4 ±227 ±230
Differential input voltage for specified SD24GAINx = 8 ±113 ±115 mV
VID SD24REFS = 1
performance (2) SD24GAINx = 16 ±57 ±58
SD24GAINx = 32 ±28 ±29
SD24GAINx = 64 ±14 ±14.5
SD24GAINx = 128 ±7 ±7.2
CREF VREF load capacitance (3) SD24REFS = 1 100 nF
(1) Modulator clock frequency: MIN = 32.768 kHz – 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
(2) The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF / GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–; that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced
internally, the given VID ranges apply.
(3) There is no capacitance required on VREF. However, a capacitance of 100 nF is recommended to reduce any reference voltage noise.

Table 5-36 lists the analog input characteristics of the SD24_B.

(1)
Table 5-36. SD24_B Analog Input
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAINx = 1 5
SD24GAINx = 2 5
SD24GAINx = 4 5
CI Input capacitance pF
SD24GAINx = 8 5
SD24GAINx = 16 5
SD24GAINx = 32, 64, 128 5
SD24GAINx = 1 3V 200
Input impedance
ZI fSD24 = 1 MHz SD24GAINx = 8 3V 200 kΩ
(Pin A+ or A- to AVSS)
SD24GAINx = 32 3V 200
SD24GAINx = 1 3V 300 400
Differential input impedance
ZID fSD24 = 1 MHz SD24GAINx = 8 3V 400 kΩ
(Pin A+ to pin A-)
SD24GAINx = 32 3V 300 400
(1) All parameters pertain to each SD24_B converter.

64 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

1600

1400

1200
Input Leakage Current – nA

1000

800

600

400

200

-200
-1 -0.5 0 0.5 1 1.5 2 2.5 3
Input Voltage – V

Figure 5-18. Input Leakage Current vs Input Voltage

(Modulator OFF)

Table 5-37 lists the supply current of the SD24_B.

Table 5-37. SD24_B Supply Currents

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1 3V 600 675
SD24GAIN: 2 3V 600 675
SD24GAIN: 4 3V 600 675
Analog plus digital supply current per fSD24 = 1 MHz, SD24GAIN: 8 3V 700 750
ISD,256 µA
converter (reference not included) SD24OSR = 256 SD24GAIN: 16 3V 700 750
SD24GAIN: 32 3V 775 850
SD24GAIN: 64 3V 775 850
SD24GAIN: 128 3V 775 850
SD24GAIN: 1 3V 750 800
Analog plus digital supply current per fSD24 = 2 MHz,
ISD,512 SD24GAIN: 8 3V 825 900 µA
converter (reference not included) SD24OSR = 512
SD24GAIN: 32 3V 900 1000

Table 5-38 lists the performance characteristics of the SD24_B.

Table 5-38. SD24_B Performance

fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1 3V –0.01 0.01
Integral nonlinearity, end- % of
INL SD24GAIN: 8 3V –0.01 0.01
point fit FSR
SD24GAIN: 32 3V –0.01 0.01
SD24GAIN: 1 3V 1
SD24GAIN: 2 3V 2
SD24GAIN: 4 3V 4
SD24GAIN: 8 3V 8
Gnom Nominal gain
SD24GAIN: 16 3V 16
SD24GAIN: 32 3V 31.7
SD24GAIN: 64 3V 63.4
SD24GAIN: 128 3V 126.8

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Table 5-38. SD24_B Performance (continued)

fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1, with external reference (1.2 V) 3V –1% +1%
EG Gain error (1) SD24GAIN: 8, with external reference (1.2 V) 3V –2% +2%
SD24GAIN: 32, with external reference (1.2 V) 3V –2% +2%
Gain error temperature
ppm/
ΔEG/ΔT coefficient (2), internal SD24GAIN: 1, 8, or 32 (with internal reference) 3V 50
°C
reference
SD24GAIN: 1 0.15
(3)
ΔEG/ΔVCC Gain error vs VCC SD24GAIN: 8 0.15 %/V
SD24GAIN: 32 0.4
SD24GAIN: 1 (with Vdiff = 0 V) 3V 2.3
EOS[V] Offset error (4) SD24GAIN: 8 3V 0.73 mV
SD24GAIN: 32 3V 0.18
SD24GAIN: 1 (with Vdiff = 0 V) 3V –0.2 0.2
EOS[FS] Offset error (4) SD24GAIN: 8 3V –0.5 0.5 % FS
SD24GAIN: 32 3V –0.5 0.5
SD24GAIN: 1 3V 1
Offset error temperature
ΔEOS/ΔT SD24GAIN: 8 3V 0.15 µV/°C
coefficient (5)
SD24GAIN: 32 3V 0.1
SD24GAIN: 1 600
(6)
ΔEOS/ΔVCC Offset error vs VCC SD24GAIN: 8 100 µV/V
SD24GAIN: 32 50
SD24GAIN: 1 3V –110
Common-mode rejection at
CMRR,DC SD24GAIN: 8 3V –110 dB
DC (7)
SD24GAIN: 32 3V –110

(1) The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
(2) The gain error temperature coefficient ΔEG / ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) –
Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
(3) The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) –
Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) –
MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(4) The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF / G and –100% FS = –VREF / G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
(5) The offset error temperature coefficient ΔEOS / ΔT specifies the variation of the offset error EOS over temperature using the box method
(that is, MIN and MAX values):
ΔEOS / ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
(6) The offset error vs VCC ΔEOS / ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is,
MIN and MAX values):
ΔEOS / ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common-mode voltage (for example, calculating with 16-bit FSR = 65536, a maximum change by 1 LSB results in
–20log(1/65536) ≈ –96 dB) .
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and
the common-mode voltage is swept from –1 V to VCC.
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Table 5-38. SD24_B Performance (continued)

fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV 3V –110
Common-mode rejection at
CMRR,50Hz SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV 3V –110 dB
50 Hz (8)
SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV 3V –110
SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t), –61
fVcc = 50 Hz
SD24GAIN: 8,
AC power supply rejection
AC PSRR,ext VCC = 3 V + 50 mV × sin(2π × fVcc × t), –77 dB
ratio, external reference (9)
fVcc = 50 Hz
SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t), –79
fVcc = 50 Hz
SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t), –61
fVcc = 50 Hz
SD24GAIN: 8,
AC power supply rejection
AC PSRR,int VCC = 3 V + 50 mV × sin(2π × fVcc × t), –77 dB
ratio, internal reference (9)
fVcc = 50 Hz
SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t), –79
fVcc = 50 Hz
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
3V –120
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 1
Crosstalk source: SD24GAIN: 1,
Crosstalk between Sine wave with maximum possible Vpp,
XT 3V –115 dB
converters (10) fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 8
Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
3V –100
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 32
(8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple
applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the
analog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal (that is, no differential input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVcc × t) added to VCC.
The AC PSRR is measured with the inputs grounded (that is, no analog input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS
(10) The crosstalk (XT) is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.

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Table 5-39 lists the AC performance characteristics of the SD24_B.

Table 5-39. SD24_B AC Performance

fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1 3V 85 87
SD24GAIN: 2 3V 86
SD24GAIN: 4 3V 85
SD24GAIN: 8 3V 82 84
SINAD Signal-to-noise + distortion ratio fIN = 50 Hz (1) dB
SD24GAIN: 16 3V 80
SD24GAIN: 32 3V 73 74
SD24GAIN: 64 3V 68
SD24GAIN: 128 3V 62
SD24GAIN: 1 3V 100
THD Total harmonic distortion SD24GAIN: 8 fIN = 50 Hz (1) 3V 90 dB
SD24GAIN: 32 3V 80
(1) The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).

Table 5-40 lists the AC performance characteristics of the SD24_B.

Table 5-40. SD24_B AC Performance

fSD24 = 2 MHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1 3V 87
SD24GAIN: 2 3V 86
SD24GAIN: 4 3V 85
SD24GAIN: 8 3V 84
SINAD Signal-to-noise + distortion ratio fIN = 50 Hz (1) dB
SD24GAIN: 16 3V 81
SD24GAIN: 32 3V 76
SD24GAIN: 64 3V 71
SD24GAIN: 128 3V 65
(1) The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).

68 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

Table 5-41 lists the AC performance characteristics of the SD24_B.

Table 5-41. SD24_B AC Performance

fSD24 = 32 kHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAIN: 1 3V 89
SD24GAIN: 2 3V 85
SD24GAIN: 4 3V 84
SD24GAIN: 8 3V 86
SINAD Signal-to-noise + distortion ratio fIN = 12 Hz (1) dB
SD24GAIN: 16 3V 80
SD24GAIN: 32 3V 76
SD24GAIN: 64 3V 67
SD24GAIN: 128 3V 61
(1) The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).

80
SINAD – dB

55
32 64 128 256 512 1024
SD24OSRx

Figure 5-19. SINAD vs OSR

(fSD24 = 1 MHz, SD24REFS = 1, SD24GAIN = 1)

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80
SINAD – dB

60
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vpp/Vref/Gain

Figure 5-20. SINAD vs VPP

Table 5-42 lists the external reference input requirements of the SD24_B.

Table 5-42. SD24_B External Reference Input

ensure correct input voltage range according to VREF
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF(I) Input voltage SD24REFS = 0 3V 1.0 1.20 1.5 V
IREF(I) Input current SD24REFS = 0 3V 50 nA

70 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

5.8.11 ADC10_A Module

Table 5-43 lists the input requirements of the ADC.

Table 5-43. 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC and DVCC are connected together,
AVCC Analog supply voltage AVSS and DVSS are connected together, 1.8 3.6 V
V(AVSS) = V(DVSS) = 0 V
V(Ax) Analog input voltage range (1) All ADC10_A pins 0 AVCC V
Operating supply current into fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0, 2.2 V 70 105
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
and reference buffer off ADC10SREF = 00 3V 80 115
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, 3V 130 185
on, reference buffer on ADC10SREF = 01
IADC10_A µA
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, 3V 108 160
off, reference buffer on ADC10SREF = 10, VEREF = 2.5 V
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, 3V 74 105
off, reference buffer off ADC10SREF = 11, VEREF = 2.5 V
Only one terminal Ax can be selected at one time
CI Input capacitance from the pad to the ADC10_A capacitor array 2.2 V 3.5 pF
including wiring and pad.
AVCC > 2 V, 0 V ≤ VAx ≤ AVCC 36
RI Input MUX ON resistance kΩ
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC 96
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to
decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide.

Table 5-44 lists the timing parameters of the ADC.

Table 5-44. 10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
For specified performance of ADC10_A
fADC10CLK 2.2 V, 3 V 0.45 5 5.5 MHz
linearity parameters
Internal ADC10_A
fADC10OSC ADC10DIV = 0, fADC10CLK = fADC10OSC 2.2 V, 3 V 4.4 5.0 5.6 MHz
oscillator (1)
REFON = 0, Internal oscillator, 12
ADC10CLK cycles, 10-bit mode 2.2 V, 3 V 2.4 3.0
tCONVERT Conversion time fADC10OSC = 4 MHz to 5 MHz µs
External fADC10CLK from ACLK, MCLK or 12 ×
SMCLK, ADC10SSEL ≠ 0 1 / fADC10CLK
Turnon settling time of (2)
tADC10ON See 100 ns
the ADC
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (3) 1.8 V 3
tSample Sampling time µs
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (3) 3V 1
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(3) Approximately 8 Tau (t) are needed to get an error of less than ±0.5 LSB

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Table 5-45 lists the linearity parameters of the ADC.

Table 5-45. 10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Integral 1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF ±1.0
EI 2.2 V, 3 V LSB
linearity error 1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF ±1.0
Differential
ED 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF 2.2 V, 3 V ±1.0 LSB
linearity error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
EO Offset error 2.2 V, 3 V ±1.0 LSB
Internal impedance of source RS < 100 Ω
1.4 V ≤ (VeREF+ – VeREF–),
EG Gain error 2.2 V, 3 V ±1.0 LSB
CVeREF+ = 20 pF, ADC10SREFx = 11b
Total unadjusted 1.4 V ≤ (VeREF+ – VeREF–),
ET 2.2 V, 3 V ±1.0 ±2.0 LSB
error CVeREF+ = 20 pF, ADC10SREFx = 11b

Table 5-46 lists the characteristics of the external reference for the ADC.

Table 5-46. 10-Bit ADC, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Positive external reference (2)
VeREF+ VeREF+ > VeREF– 1.4 AVCC V
voltage input
Negative external (3)
VeREF– VeREF+ > VeREF– 0 1.2 V
reference voltage input
(VeREF+ – Differential external (4)
VeREF+ > VeREF– 1.4 AVCC V
VeREF–) reference voltage input
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, 2.2 V, 3 V ±8.5 ±26 µA
IVeREF+, Conversion rate 200 ksps
Static input current
IVeREF– 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTX = 0x1000, 2.2 V, 3 V ±1 µA
Conversion rate 20 ksps
Capacitance at VeREF+ (5)
CVeREF+/- See 10 µF
or VeREF- terminal
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide .

72 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

5.8.12 REF Module

Table 5-47 lists the characteristics of the built-in reference.

Table 5-47. REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
REFVSEL = {2} for 2.5 V, REFON = 1 3V 2.47 2.51 2.55
Positive built-in reference
VREF+ REFVSEL = {1} for 2.0 V, REFON = 1 3V 1.95 1.99 2.03 V
voltage
REFVSEL = {0} for 1.5 V, REFON = 1 2.2 V, 3 V 1.46 1.50 1.54
REFVSEL = {0} for 1.5 V 1.8
AVCC minimum voltage,
AVCC(min) Positive built-in reference REFVSEL = {1} for 2.0 V 2.2 V
active
REFVSEL = {2} for 2.5 V 2.7
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0, 23 30
REFVSEL = {2} for 2.5 V
fADC10CLK = 5 MHz,
Operating supply current
IREF+ REFON = 1, REFBURST = 0, 3V 21 27 µA
into AVCC terminal (1)
REFVSEL = {1} for 2.0 V
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0, 19 25
REFVSEL = {0} for 1.5 V
Temperature coefficient of ppm/
TCREF+ REFVSEL = {0, 1, 2}, REFON = 1 10 50
built-in reference (2) °C
Operating supply current REFON = 1, ADC10ON = 1, 2.2 V 145 220
ISENSOR µA
into AVCC terminal INCH = 0Ah, TA = 30°C 3V 170 245

(3) REFON = 1, ADC10ON = 1, 2.2 V 780

VSENSOR See mV
INCH = 0Ah, TA = 30°C 3V 780
ADC10ON = 1, INCH = 0Bh, 2.2 V 1.08 1.1 1.12
VMID AVCC divider at channel 11 V
VMID ≈ 0.5 × VAVCC 3V 1.48 1.5 1.52
Sample time required if REFON = 1, ADC10ON = 1, INCH = 0Ah,
tSENSOR(sample) 30 µs
channel 10 is selected (4) Error of conversion result ≤ 1 LSB
Sample time required if ADC10ON = 1, INCH = 0Bh,
tVMID(sample) 1 µs
channel 11 is selected (5) Error of conversion result ≤ 1 LSB
AVCC = AVCC(min) to AVCC(max),
Power supply rejection ratio
PSRR_DC TA = 25°C, 120 300 µV/V
(DC)
REFVSEL = {0, 1, 2}, REFON = 1
AVCC = AVCC(min) to AVCC(max),
Power supply rejection ratio
PSRR_AC TA = 25°C, f = 1 kHz, ΔVpp = 100 mV, 1 mV/V
(AC)
REFVSEL = {0, 1, 2}, REFON = 1
Settling time of reference AVCC = AVCC(min) to AVCC(max),
tSETTLE 75 µs
voltage (6) REFVSEL = {0, 1, 2}, REFON = 0 → 1
SD24_B internal reference
VSD24REF SD24REFS = 1 3V 1.137 1.151 1.165 V
voltage
SD24_B internal reference
tON SD24REFS = 0→1, CREF = 100 nF 3V 200 µs
turnon time (7)
(1) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(3) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(4) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
(6) The condition is that the error in a conversion started after tREFON is ≤ 1 LSB.
(7) The condition is that SD24_B conversion started after tON should ensure specified SINAD values for the selected Gain, OSR, and fSD24.

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5.8.13 Flash
Table 5-48 lists the characteristics of the flash memory.

Table 5-48. Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TJ MIN TYP MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program 3 5 mA
IERASE Average supply current from DVCC during erase 6 11 mA
IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 6 11 mA
(1)
tCPT Cumulative program time 16 ms
Program and erase endurance 104 105 cycles
tRetention Data retention duration 25°C 100 years
(2)
tWord Word or byte program time 64 85 µs
tBlock, 0 Block program time for first byte or word (2) 49 65 µs
Block program time for each additional byte or word, except for last byte
tBlock, 37 49 µs
1–(N–1) or word (2)
tBlock, N Block program time for last byte or word (2) 55 73 µs
Erase time for segment erase, mass erase, and bank erase when
tErase 23 32 ms
available (2)
MCLK frequency in marginal read mode
fMCLK,MGR 0 1 MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
modes: individual word or byte write and block write.
(2) These values are hardwired into the state machine of the flash controller.

5.8.14 Emulation and Debug

Table 5-49 lists the characteristics of the JTAG and Spy-Bi-Wire interface.

Table 5-49. JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW, En 2.2 V, 3 V 1 µs
edge) (1)
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
2.2 V 0 5
fTCK TCK input frequency for 4-wire JTAG (2) MHz
3V 0 10
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.

74 Specifications Copyright © 2015–2018, Texas Instruments Incorporated

6 Detailed Description
6.1 Overview
The MSP430F673xA and MSP430F673xA microcontrollers feature three high-performance 24-bit sigma-
delta ADCs, a 10-bit ADC, four enhanced universal serial communication interfaces (three eUSCI_A
modules and one eUSCI_B module), four 16-bit timers, a hardware multiplier, a DMA module, an RTC
module with alarm capabilities, a segment LCD driver with integrated contrast control, an auxiliary supply
system, and up to 72 I/O pins in the 100-pin devices and 52 I/O pins in the 80-pin devices.

6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.

Program Counter PC/R0

Stack Pointer SP/R1

Status Register SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register R4

General-Purpose Register R5

General-Purpose Register R6

General-Purpose Register R7

General-Purpose Register R8

General-Purpose Register R9

General-Purpose Register R10

General-Purpose Register R11

General-Purpose Register R12

General-Purpose Register R13

General-Purpose Register R14

General-Purpose Register R15

Figure 6-1. Integrated CPU Registers

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6.3 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address
modes.

Table 6-1. Instruction Word Formats

INSTRUCTION WORD FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC → (TOS), R8 → PC
Relative jump, conditional or unconditional JNE Jump-on-equal bit = 0

Table 6-2. Address Mode Descriptions

ADDRESS MODE S (1) D (1) SYNTAX EXAMPLE OPERATION
Register + + MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) + + MOV EDE,TONI M(EDE) → M(TONI)
Absolute + + MOV & MEM, & TCDAT M(MEM) → M(TCDAT)
Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
M(R10) → R11
Indirect autoincrement + MOV @Rn+,Rm MOV @R10+,R11
R10 + 2 → R10
Immediate + MOV #X,TONI MOV #45,TONI #45 → M(TONI)
(1) S = source, D = destination

76 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.4 Operating Modes

The MSP430F673xA and MSP430F673xA microcontrollers have one active mode and seven software-
selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-
power modes, service the request, and restore back to the low-power mode on return from the interrupt
program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– I/O pad state retention
– RTC clocked by low-frequency oscillator
– Wake-up input from RST/NMI, RTC_C events, Ports P1 and P2
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– RTC is disabled
– I/O pad state retention
– Wake-up input from RST/NMI, Ports P1 and P2

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6.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.

Table 6-3. Interrupt Sources, Flags, and Vectors

SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset 0FFFEh 63, highest
Watchdog Time-out, Key Violation
Flash Memory Key Violation
System NMI
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access
JMBOUTIFG (SYSSNIV) (1) (3)
JTAG Mailbox
User NMI
NMI
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG
Oscillator Fault (Non)maskable 0FFFAh 61
(SYSUNIV) (1) (3)
Flash Memory Access Violation
Supply Switch
Watchdog Timer_A Interval Timer
WDTIFG Maskable 0FFF8h 60
Mode
eUSCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4)
Maskable 0FFF6h 59
(1) (4)
eUSCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV) Maskable 0FFF4h 58
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10_A ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG Maskable 0FFF2h 57
(ADC10IV) (1) (4)
SD24_B SD24_B Interrupt Flags (SD24IV) (1) (4)
Maskable 0FFF0h 56
(4)
Timer TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
Timer TA0 Maskable 0FFECh 54
TA0IFG (TA0IV) (1) (4)
(1) (4)
eUSCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) Maskable 0FFEAh 53
eUSCI_A2 Receive or Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (4)
Maskable 0FFE8h 52
(1) (4)
Auxiliary Supplies Auxiliary Supplies Interrupt Flags (AUXIV) Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (4)
Maskable 0FFE4h 50
Timer TA1 TA1CCR0 CCIFG0 (4) Maskable 0FFE2h 49
TA1CCR1 CCIFG1,
Timer TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV) (1) (4)
(1) (4)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV) Maskable 0FFDEh 47
Timer TA2 TA2CCR0 CCIFG0 (4) Maskable 0FFDCh 46
TA2CCR1 CCIFG1,
Timer TA2 Maskable 0FFDAh 45
TA2IFG (TA2IV) (1) (4)
(1) (4)
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV) Maskable 0FFD8h 44
(4)
Timer TA3 TA3CCR0 CCIFG0 Maskable 0FFD6h 43
TA3CCR1 CCIFG1,
Timer TA3 Maskable 0FFD4h 42
TA3IFG (TA3IV) (1) (4)
LCD_C LCD_C Interrupt Flags (LCDCIV) (1) (4)
Maskable 0FFD2h 41
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTC_C Maskable 0FFD0h 40
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (4)

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Interrupt flags are located in the module.
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Table 6-3. Interrupt Sources, Flags, and Vectors (continued)

SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
0FFCEh 39
Reserved Reserved (5) ⋮ ⋮
0FF80h 0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.

6.6 Bootloader (BSL)

The BSL lets users program the flash memory or RAM using various serial interfaces. Access to the
device memory through the BSL is protected by an user-defined password. BSL entry requires a specific
entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the
features of the BSL and its implementation, see the MSP430™ Flash Device Bootloader (BSL) User's
Guide. Table 6-4 lists the BSL pin requirements.

Table 6-4. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P3.0 Data transmit
P3.1 Data receive
DVCC Power supply
DVSS Ground supply

6.7 JTAG Operation

6.7.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide and MSP430 Programming With the JTAG Interface.

Table 6-5. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/ACLK/TCK IN JTAG clock input
PJ.2/ADC10CLK/TMS IN JTAG state control
PJ.1/MCLK/TDI/TCLK IN JTAG data input/TCLK input
PJ.0/SMCLK/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
DVCC Power supply
DVSS Ground supply

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6.7.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
Table 6-6 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide and MSP430
Programming With the JTAG Interface.

Table 6-6. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
DVCC Power supply
DVSS Ground supply

6.8 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.

6.9 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
• RAM has n sectors of 2 kbytes each.
• Each sector 0 to n can be completely disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.

6.10 Backup RAM

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This
backup RAM is part of the Backup subsystem that operates on dedicated power supply AUXVCC3. 8
bytes of backup RAM are available in this device. The backup RAM can be word-wise accessed through
the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM registers cannot be
accessed by the CPU when the high-side SVS is disabled by software.

80 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide.

6.11.1 Oscillator and System Clock

The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed to
meet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator
(VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

6.11.2 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-
on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level
and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM are available on the primary supply and
the core supply.

6.11.3 Auxiliary Supply System

The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the
primary supply fails.There are two auxililary supplies (AUXVCC1 and AUXVCC2) are supported. This
module supports automatic and manual switching from primary supply to auxiliary suppllies while
maintaining full functionality. It allows threshold based monitoring of primary and auxiliary supplies. The
device can be started from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system
enables internal monitoring of voltage levels on primary and auxiliary supplies using ADC10_A. Also this
module implements simple charger for backup supplies.

6.11.4 Backup Subsystem

The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes low-
frequency oscillator (XT1), RTC module, and backup RAM. The functionality of the Backup subsystem is
retained during LPM3.5. The Backup subsystem module registers cannot be accessed by CPU when the
high-side SVS is disabled by the user. It is necessary to keep the high-side SVS enabled with SVSHMD =
1 and SVSMHACE = 0 to turn off the low-frequency oscillator (XT1) in LPM4.

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6.11.5 Digital I/O

Up to nine 8-bit I/O ports are implemented. For 100-pin options, Ports P1 to P8 are complete, and P9 is
reduced to 4-bit I/O. For 80-pin options, Ports P1 to P6 are complete, and P7 to P9 are completely
removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually
programmable.
• Any combination of input, output and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5, LPM4.5 wake-up input capability available for all bits of ports
P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).

6.11.6 Port Mapping Controller

The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and
P3 (see Table 6-7). Table 6-8 lists the default settings for all pins that support port mapping.

Table 6-7. Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_UCA0RXD eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
1
PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
2
PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
3 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
4 PM_UCA0STE eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1RXD eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
5
PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
6
PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
7 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
8 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA2RXD eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
9
PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
10
PM_ UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
11 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
12 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
13
PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
14
PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
15 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
16 PM_UCB0STE eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
17 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
18 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
19 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
20 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
21 PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1

82 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

Table 6-7. Port Mapping Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
22 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0
23 PM_TA2.1 TA2 CCR1 capture input CCI1A TA2 CCR1 compare output Out1
24 PM_TA3.0 TA3 CCR0 capture input CCI0A TA3 CCR0 compare output Out0
25 PM_TA3.1 TA3 CCR1 capture input CCI1A TA3 CCR1 compare output Out1
Timer_A clock input to
PM_TACLK None
26 TA0, TA1, TA2, TA3
PM_RTCCLK None RTC_C clock output
27 PM_SDCLK SD24_B bit stream clock input/output (direction controlled by SD24_B)
28 PM_SD0DIO SD24_B converter 0 bit stream data input/output (direction controlled by SD24_B)
29 PM_SD1DIO SD24_B converter 1 bit stream data input/output (direction controlled by SD24_B)
30 PM_SD2DIO SD24_B converter 2 bit stream data input/output (direction controlled by SD24_B)
(1) Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
31 (0FFh) PM_ANALOG
when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.

Table 6-8. Default Mapping

PIN NAME
PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
PZ PN
P1.0/PM_TA0.0/ P1.0/PM_TA0.0/
PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
VeREF-/A2 VeREF-/A2
P1.1/PM_TA0.1/ P1.1/PM_TA0.1/
PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
VeREF+/A1 VeREF+/A1
eUSCI_A0 UART RXD
P1.2/PM_UCA0RXD/ P1.2/PM_UCA0RXD/ PM_UCA0RXD, (direction controlled by eUSCI – input),
PM_UCA0SOMI/A0 PM_UCA0SOMI/A0 PM_UCA0SOMI eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
eUSCI_A0 UART TXD
P1.3/PM_UCA0TXD/ P1.3/PM_UCA0TXD/ PM_UCA0TXD, (direction controlled by eUSCI – output),
PM_UCA0SIMO/R03 PM_UCA0SIMO/R03 PM_UCA0SIMO eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
eUSCI_A1 UART RXD
P1.4/PM_UCA1RXD/ P1.4/PM_UCA1RXD/
PM_UCA1RXD, (direction controlled by eUSCI – input),
PM_UCA1SOMI/ PM_UCA1SOMI/
PM_UCA1SOMI eUSCI_A1 SPI slave out master in
LCDREF/R13 LCDREF/R13
(direction controlled by eUSCI)
eUSCI_A1 UART TXD
P1.5/PM_UCA1TXD/ P1.5/PM_UCA1TXD/ PM_UCA1TXD, (direction controlled by eUSCI – output),
PM_UCA1SIMO/R23 PM_UCA1SIMO/R23 PM_UCA1SIMO eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.6/PM_UCA0CLK/ P1.6/PM_UCA0CLK/
PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
COM4 COM4
P1.7/PM_UCB0CLK/ P1.7/PM_UCB0CLK/
PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
COM5 COM5
eUSCI_B0 SPI slave out master in
P2.0/PM_UCB0SOMI/ P2.0/PM_UCB0SOMI/ PM_UCB0SOMI, (direction controlled by eUSCI),
PM_UCB0SCL/COM6 PM_UCB0SCL/COM6/S39 PM_UCB0SCL eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out
P2.1/PM_UCB0SIMO/ P2.1/PM_UCB0SIMO/ PM_UCB0SIMO, (direction controlled by eUSCI),
PM_UCB0SDA/COM7 PM_UCB0SDA/COM7/S38 PM_UCB0SDA eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
eUSCI_A2 UART RXD
P2.2/PM_UCA2RXD/ P2.2/PM_UCA2RXD/ PM_UCA2RXD, (direction controlled by eUSCI – input),
PM_UCA2SOMI PM_UCA2SOMI/S37 PM_UCA2SOMI eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
eUSCI_A2 UART TXD
P2.3/PM_UCA2TXD/ P2.3/PM_UCA2TXD/ PM_UCA2TXD, (direction controlled by eUSCI – output),
PM_UCA2SIMO PM_UCA2SIMO/S36 PM_UCA2SIMO eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.4/PM_UCA1CLK P2.4/PM_UCA1CLK/S35 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)

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Table 6-8. Default Mapping (continued)

PIN NAME
PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
PZ PN
P2.5/PM_UCA2CLK P2.5/PM_UCA2CLK/S34 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
P2.6/PM_TA1.0 P2.6/PM_TA1.0/S33 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
P2.7/PM_TA1.1 P2.7/PM_TA1.1/S32 PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
P3.0/PM_TA2.0 P3.0/PM_TA2.0/S31 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0
P3.1/PM_TA2.1 P3.1/PM_TA2.1/S30 PM_TA2.1 TA2 CCR1 capture input CCI1A TA2 CCR1 compare output Out1
P3.2/PM_TACLK/ P3.2/PM_TACLK/ PM_TACLK, Timer_A clock input to
RTC_C clock output
PM_RTCCLK PM_RTCCLK/S29 PM_RTCCLK TA0, TA1, TA2, TA3
P3.3/PM_TA0.2 P3.3/PM_TA0.2/S28 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
SD24_B bit stream clock input/output
P3.4/PM_SDCLK/S39 P3.4/PM_SDCLK/S27 PM_SDCLK
(direction controlled by SD24_B)
SD24_B converter 0 bit stream data input/output
P3.5/PM_SD0DIO/S38 P3.5/PM_SD0DIO/S26 PM_SD0DIO
(direction controlled by SD24_B)
SD24_B converter 1 bit stream data input/output
P3.6/PM_SD1DIO/S37 P3.6/PM_SD1DIO/S25 PM_SD1DIO
(direction controlled by SD24_B)
SD24_B converter 2 bit stream data input/output
P3.7/PM_SD2DIO/S36 P3.7/PM_SD2DIO/S24 PM_SD2DIO
(direction controlled by SD24_B)

6.11.7 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see Table 6-9), bootloader entry mechanisms, and configuration management (device
descriptors). It also includes a data exchange mechanism through JTAG called a JTAG mailbox that can
be used in the application.

Table 6-9. System Module Interrupt Vector Registers

WORD
INTERRUPT VECTOR REGISTER INTERRUPT EVENT OFFSET PRIORITY
ADDRESS
No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (POR) 04h
DoBOR (BOR) 06h
Wakeup from LPMx.5 (BOR) 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SYSRSTIV, System Reset 019Eh
SVMH_OVP (POR) 12h
DoPOR (POR) 14h
WDT time-out (PUC) 16h
WDT key violation (PUC) 18h
KEYV flash key violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM key violation (PUC) 20h
Reserved 22h to 3Eh Lowest

84 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

Table 6-9. System Module Interrupt Vector Registers (continued)

WORD
INTERRUPT VECTOR REGISTER INTERRUPT EVENT OFFSET PRIORITY
ADDRESS
No interrupt pending 00h
SVMLIFG 02h Highest
SVMHIFG 04h
DLYLIFG 06h
DLYHIFG 08h
SYSSNIV, System NMI VMAIFG 019Ch 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
VLRLIFG 10h
VLRHIFG 12h
Reserved 14h to 1Eh Lowest
No interrupt pending 00h
NMIIFG 02h Highest
OFIFG 04h
SYSUNIV, User NMI 019Ah
ACCVIFG 06h
AUXSWNMIFG 08h
Reserved 0Ah to 1Eh Lowest

6.11.8 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.

6.11.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-10 lists the available DMA triggers.

Table 6-10. DMA Trigger Assignments (1)

CHANNEL
TRIGGER
0 1 2
0 DMAREQ
1 TA0CCR0 CCIFG
2 TA0CCR2 CCIFG
3 TA1CCR0 CCIFG
4 Reserved
5 TA2CCR0 CCIFG
6 Reserved
7 TA3CCR0 CCIFG
8 Reserved
9 Reserved
(1) Reserved DMA triggers may be used by other devices in the family.
Reserved DMA triggers do not cause any DMA trigger event when
selected.
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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
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MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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Table 6-10. DMA Trigger Assignments(1) (continued)

CHANNEL
TRIGGER
0 1 2
10 Reserved
11 Reserved
12 Reserved
13 SD24IFG
14 Reserved
15 Reserved
16 UCA0RXIFG
17 UCA0TXIFG
18 UCA1RXIFG
19 UCA1TXIFG
20 UCA2RXIFG
21 UCA2TXIFG
22 UCB0RXIFG0
23 UCB0TXIFG0
24 ADC10IFG0
25 Reserved
26 Reserved
27 Reserved
28 Reserved
29 MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 Reserved

6.11.10 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.11.11 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.

6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)

The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module supports for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module supports for SPI (3- or 4-pin) or I2C.
Three eUSCI_A and one eUSCI_B module are implemented.

6.11.13 ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion results buffer. A window
comparator with a lower and upper limit allows CPU independent result monitoring with three window
comparator interrupt flags.

86 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.11.14 SD24_B
The SD24_B module integrates up to three independent 24-bit sigma-delta analog-to-digital converters.
Each converter is designed with a fully differential analog input pair and programmable gain amplifier input
stage. The converters are based on second-order over-sampling sigma-delta modulators and digital
decimation filters. The decimation filters are comb-type filters with selectable oversampling ratios of up to
1024.

6.11.15 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.

Table 6-11. TA0 Signal Connections

MODULE OUTPUT DEVICE OUTPUT
DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK
SIGNAL SIGNAL
PM_TACLK TACLK
ACLK (internal) ACLK
Timer NA NA
SMCLK (internal) SMCLK
PM_TACLK INCLK
PM_TA0.0 CCI0A PM_TA0.0
DVSS CCI0B
CCR0 TA0
DVSS GND
DVCC VCC
PM_TA0.1 CCI1A PM_TA0.1
ADC10_A (internal)
ACLK (internal) CCI1B
ADC10SHSx = {1}
CCR1 TA1
SD24_B (internal)
DVSS GND
SD24SCSx = {1}
DVCC VCC
PM_TA0.2 CCI2A PM_TA0.2
DVSS CCI2B
CCR2 TA2
DVSS GND
DVCC VCC

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MSP430F6720A
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MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.11.16 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-12). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.

Table 6-12. TA1 Signal Connections

DEVICE OUTPUT
MODULE OUTPUT SIGNAL
DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK
SIGNAL
PZ
PM_TACLK TACLK
ACLK (internal) ACLK
Timer NA NA
SMCLK (internal) SMCLK
PM_TACLK INCLK
PM_TA1.0 CCI0A PM_TA1.0
DVSS CCI0B
CCR0 TA0
DVSS GND
DVCC VCC
PM_TA1.1 CCI1A PM_TA1.1
ACLK (internal) CCI1B
CCR1 TA1
DVSS GND
DVCC VCC

6.11.17 TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-13). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.

Table 6-13. TA2 Signal Connections

MODULE OUTPUT DEVICE OUTPUT
DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK
SIGNAL SIGNAL
PM_TACLK TACLK
ACLK (internal) ACLK
Timer NA NA
SMCLK (internal) SMCLK
PM_TACLK INCLK
PM_TA2.0 CCI0A PM_TA2.0
DVSS CCI0B
CCR0 TA0
DVSS GND
DVCC VCC
PM_TA2.1 CCI1A PM_TA2.1
SD24_B (internal)
ACLK (internal) CCI1B
CCR1 TA1 SD24SCSx = {2}
DVSS GND
DVCC VCC

88 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.11.18 TA3
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-14). TA3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.

Table 6-14. TA3 Signal Connections

MODULE OUTPUT DEVICE OUTPUT
DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK
SIGNAL SIGNAL
PM_TACLK TACLK
ACLK (internal) ACLK
Timer NA
SMCLK (internal) SMCLK
PM_TACLK INCLK
PM_TA3.0 CCI0A PM_TA3.0
ADC10_A (internal)
DVSS CCI0B
CCR0 TA0 ADC10SHSx = {2}
DVSS GND
DVCC VCC
PM_TA3.1 CCI1A PM_TA3.1
SD24_B (internal)
ACLK (internal) CCI1B
CCR1 TA1 SD24SCSx = {3}
DVSS GND
DVCC VCC

6.11.19 SD24_B Triggers

Table 6-15 lists the input trigger connections to SD24_B converters from Timer_A modules and the output
trigger pulse connection from SD24_B to ADC10_A.

Table 6-15. SD24_B Input/Output Trigger Connections

MODULE OUTPUT DEVICE OUTPUT
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK
SIGNAL SIGNAL
SD24_B ADC10_A (internal)
TA0.1 (internal) Trigger Pulse
SD24SCSx = {1} ADC10SHSx = {3}
SD24_B
TA2.1 (internal) SD24_B
SD24SCSx = {2}
SD24_B
TA3.1 (internal)
SD24SCSx = {3}

6.11.20 ADC10_A Triggers

Table 6-16 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B.

Table 6-16. ADC10_A Input Trigger Connections

DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK
ADC10_A
TA0.1 (internal)
ADC10SHSx = {1}
ADC10_A
ADC10_A
TA3.0 (internal)
ADC10SHSx = {2}

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.11.21 Real-Time Clock (RTC_C)

The RTC_C module can be configured for real-time clock or calendar mode that provides seconds, hours,
day of week, day of month, month, and year. The RTC_C control and configuration registers are
password-protected to ensure clock integrity against runaway code. Calendar mode integrates an internal
calendar that compensates for months with less than 31 days and includes leap year correction. The
RTC_C also supports flexible alarm functions, offset calibration, and temperature compensation. The
RTC_C on this device operates on dedicated AUXVCC3 supply and supports operation in LPM3.5.

6.11.22 Reference (REF) ModuleVoltage Reference

The REF is responsible for generation of all critical reference voltages that can be used by the various
analog peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.

6.11.23 LCD_C
The LCD_C driver generates the segment and common signals required to drive a segment liquid crystal
display (LCD). The LCD_C controller has dedicated data memories to hold segment drive information.
Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to
8-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage
with its integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by
software. The module also provides an automatic blinking capability for individual segments in static, 2-
mux, 3-mux, and 4-mux modes.

6.11.24 Embedded Emulation Module (EEM) (S Version)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level

90 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12 Input/Output Diagrams

6.12.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and
MSP430F67xxAIPN)
Figure 6-2 shows the port diagram. Table 6-17 summarizes the selection of the pin functions.

Pad Logic
to/from Reference

To ADC10_A

INCHx = y

P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS 0
DVCC 1 1
P1DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P1OUT.x 0
from Port Mapping 1
P1.0/PM_TA0.0/VeREF-/A2
P1DS.x
P1SEL.x P1.1/PM_TA0.1/VeREF+/A1
0: Low drive
1: High drive
P1IN.x

EN Bus
Keeper
to Port Mapping D

P1IE.x
EN
P1IRQ.x
Q
P1IFG.x Set

P1SEL.x Interrupt
Edge
P1IES.x Select

Figure 6-2. Port P1 (P1.0 and P1.1) Diagram (MSP430F67xxAIPZ and MSP430F67xxAIPN)

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-17. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x P1MAPx
P1.0 (I/O) I: 0; O: 1 0 X
P1.0/PM_TA0.0/ TA0.CCI0A 0 1 default
0
VeREF-/A2 TA0.TA0 1 1 default
VeREF-/A2 (2) X 1 = 31
P1.1 (I/O) I: 0; O: 1 0 X
P1.1/PM_TA0.1/ TA0.CCI1A 0 1 default
1
VeREF+/A1 TA0.TA1 1 1 default
VeREF+/A1 (2) X 1 = 31
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

92 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.2 Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and

MSP430F67xxAIPN)
Figure 6-3 shows the port diagram. Table 6-18 summarizes the selection of the pin functions.

Pad Logic
To ADC10_A

INCHx = y

P1REN.x
P1MAP.x = PMAP_ANALOG
DVSS 0
DVCC 1 1
P1DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P1OUT.x 0
from Port Mapping 1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1DS.x
P1SEL.x 0: Low drive
1: High drive
P1IN.x

EN Bus
Keeper
to Port Mapping D

P1IE.x
EN
P1IRQ.x
Q
P1IFG.x Set

P1SEL.x Interrupt
Edge
P1IES.x Select

Figure 6-3. Port P1 (P1.2) Diagram (MSP430F67xxAIPZ and MSP430F67xxAIPN)

Table 6-18. Port P1 (P1.2) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x P1MAPx
P1.2 (I/O) I: 0; O: 1 0 X
P1.2/PM_UCA0RXD/
2 UCA0RXD/UCA0SOMI X 1 default
PM_UCA0SOMI/A0
A0 (2) X 1 = 31
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

Copyright © 2015–2018, Texas Instruments Incorporated Detailed Description 93

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
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6.12.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and
MSP430F67xxAIPN)
Figure 6-4 shows the port diagram. Table 6-19 summarizes the selection of the pin functions.

to LCD_C

Pad Logic

P1REN.x

P1MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P1DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P1OUT.x 0

from Port Mapping 1

P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P1DS.x P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1SEL.x 0: Low drive P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
1: High drive
P1IN.x

EN Bus
Keeper
to Port Mapping D

P1IE.x
EN
P1IRQ.x
Q
P1IFG.x Set

P1SEL.x Interrupt
Edge
P1IES.x Select

Figure 6-4. Port P1 (P1.3 to P1.5) Diagram (MSP430F67xxAIPZ and MSP430F67xxAIPN)

Table 6-19. Port P1 (P1.3 to P1.5) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x P1MAPx
P1.3 (I/O) I: 0; O: 1 0 X
P1.3/PM_UCA0TXD/
3 UCA0TXD/UCA0SIMO X 1 default
PM_UCA0SIMO/R03
R03 (2) X 1 = 31
P1.4 (I/O) I: 0; O: 1 0 X
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/ 4 UCA1RXD/UCA1SOMI X 1 default
LCDREF/R13
LCDREF/R13 (2) X 1 = 31
P1.5 (I/O) I: 0; O: 1 0 X
P1.5/PM_UCA1TXD/
5 UCA1TXD/UCA1SIMO X 1 default
PM_UCA1SIMO/R23
R23 (2) X 1 = 31
(1) X = Don't care
(2) Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

94 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.4 Port P1 (P1.6 and P1.7) (MSP430F67xxAIPZ and MSP430F67xxAIPN) and

Port P2 (P2.0 and P2.1) (MSP430F67xxAIPZ Only) Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-20 and Table 6-21 summarize the selection of the pin
functions.

COM4 to COM7

from LCD_C

Pad Logic

PyREN.x

PyMAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
PyDIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

PyOUT.x 0

from Port Mapping 1

P1.6/PM_UCA0CLK/COM4
PyDS.x
PySEL.x P1.7/PM_UCB0CLK/COM5
0: Low drive
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
1: High drive
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
PyIN.x

EN Bus
Keeper
to Port Mapping D

PyIE.x
EN
PyIRQ.x
Q
PyIFG.x Set

PySEL.x Interrupt
Edge
PyIES.x Select

Figure 6-5. Port P1 (P1.6 and P1.7) (MSP430F67xxAIPZ and MSP430F67xxAIPN), Port P2 (P2.0 and P2.1)
(MSP430F67xxAIPZ Only) Diagram

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-20. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F67xxAIPZ and MSP430F67xxAIPN)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x) x FUNCTION COM4, COM5
P1DIR.x P1SEL.x P1MAPx
Enable Signal
P1.6 (I/O) I: 0; O: 1 0 X 0
UCA0CLK X 1 default 0
P1.6/PM_UCA0CLK/COM4 6 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
COM4 X X X 1
P1.7 (I/O) I: 0; O: 1 0 X 0
UCB0CLK X 1 default 0
P1.7/PM_UCB0CLK/COM5 7 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
COM5 X X X 1
(1) X = Don't care

Table 6-21. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxAIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x) x FUNCTION COM6, COM7
P2DIR.x P2SEL.x P2MAPx
Enable Signal
P2.0 (I/O) I: 0; O: 1 0 X 0
UCB0SOMI/UCB0SCL X 1 default 0
P2.0/PM_UCB0SOMI/
0 Output driver and input Schmitt
PM_UCB0SCL/COM6 X 1 = 31 0
trigger disabled
COM6 X X X 1
P2.1 (I/O) I: 0; O: 1 0 X 0
UCB0SIMO/UCB0SDA X 1 default 0
P2.1/PM_UCB0SIMO/
1 Output driver and input Schmitt
PM_UCB0SDA/COM7 X 1 = 31 0
trigger disabled
COM7 X X X 1
(1) X = Don't care

96 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.5 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
Figure 6-6 shows the port diagram. Table 6-22 summarizes the selection of the pin functions.

Pad Logic

P2REN.x

P2MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P2DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P2OUT.x 0

from Port Mapping 1

P2DS.x P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2SEL.x 0: Low drive P2.3/PM_UCA2TXD/PM_UCA2SIMO
1: High drive P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2IN.x P2.6/PM_TA1.0
P2.7/PM_TA1.1
EN Bus
Keeper
to Port Mapping D

P2IE.x
EN
P2IRQ.x
Q
P2IFG.x Set

P2SEL.x Interrupt
Edge
P2IES.x Select

Figure 6-6. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxAIPZ Only)

Copyright © 2015–2018, Texas Instruments Incorporated Detailed Description 97

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-22. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x) x FUNCTION
P2DIR.x P2SEL.x P2MAPx
P2.2 (I/O) I: 0; O: 1 0 X
P2.2/PM_UCA2RXD/
2 UCA2RXD/UCA2SOMI X 1 default
PM_UCA2SOMI
Output driver and input Schmitt trigger disabled X 1 = 31
P2.3 (I/O) I: 0; O: 1 0 X
P2.3/PM_UCA2TXD/
3 UCA2TXD/UCA2SIMO X 1 default
PM_UCA2SIMO
Output driver and input Schmitt trigger disabled X 1 = 31
P2.4 (I/O) I: 0; O: 1 0 X
P2.4/PM_UCA1CLK 4 UCA1CLK X 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
P2.5 (I/O) I: 0; O: 1 0 X
P2.5/PM_UCA2CLK 5 UCA2CLK X 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
P2.6 (I/O) I: 0; O: 1 0 X
TA1.CC10A 0 1 default
P2.6/PM_TA1.0 6
TA1.TA0 1 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
P2.7 (I/O) I: 0; O: 1 0 X
TA1.CCI1A 0 1 default
P2.7/PM_TA1.1 7
TA1.TA1 1 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
(1) X = Don't care

98 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.6 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
Figure 6-7 shows the port diagram. Table 6-23 summarizes the selection of the pin functions.

Pad Logic

P3REN.x

P3MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P3DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P3OUT.x 0

from Port Mapping 1

P3DS.x P3.0/PM_TA2.0
P3SEL.x 0: Low drive P3.1/PM_TA2.1
1: High drive P3.2/PM_TACLK/PM_RTCCLK
P3.3/PM_TA0.2
P3IN.x

EN Bus
Keeper
to Port Mapping D

Figure 6-7. Port P3 (P3.0 to P3.3) Diagram (MSP430F67xxAIPZ Only)

Table 6-23. Port P3 (P3.0 to P3.3) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x) x FUNCTION
P3DIR.x P3SEL.x P3MAPx
P3.0 (I/O) I: 0; O: 1 0 X
TA2.CC10A 0 1 default
P3.0/PM_TA2.0 0
TA2.TA0 1 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
P3.1 (I/O) I: 0; O: 1 0 X
TA2.CCI1A 0 1 default
P3.1/PM_TA2.1 1
TA2.TA1 1 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
P3.2 (I/O) I: 0; O: 1 0 X
P3.2/PM_TACLK/ TACLK 0 1 default
2
PM_RTCCLK RTCCLK 1 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
P3.3 (I/O) I: 0; O: 1 0 X
TA0.CCI2A 0 1 default
P3.3/PM_TA0.2 3
TA0.TA2 1 1 default
Output driver and input Schmitt trigger disabled X 1 = 31
(1) X = Don't care

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.12.7 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
Figure 6-8 shows the port diagram. Table 6-24 summarizes the selection of the pin functions.

S39 to S37

LCDS39 to LCDS37

Pad Logic

P3REN.x

P3MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P3DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P3OUT.x 0

from Port Mapping 1

P3.4/PM_SDCLK/S39
P3DS.x
P3SEL.x P3.5/PM_SD0DIO/S38
0: Low drive
P3.6/PM_SD1DIO/S37
1: High drive
P3.7/PM_SD2DIO/S36
P3IN.x

EN Bus
Keeper
to Port Mapping D

Figure 6-8. Port P3 (P3.4 to P3.7) Diagram (MSP430F67xxAIPZ Only)

100 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

Table 6-24. Port P3 (P3.4 to P3.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x) x FUNCTION LCDS39...
P3DIR.x P3SEL.x P3MAPx
LCDS36
P3.4 (I/O) I: 0; O: 1 0 X 0
SDCLK X 1 default 0
P3.4/PM_SDCLK/S39 4 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S39 X X X 1
P3.5 (I/O) I: 0; O: 1 0 X 0
SD0DIO X 1 default 0
P3.5/PM_SD0DIO/S38 5 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S38 X X X 1
P3.6 (I/O) I: 0; O: 1 0 X 0
SD1DIO X 1 default 0
P3.6/PM_SD1DIO/S37 6 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S37 X X X 1
P3.7 (I/O) I: 0; O: 1 0 X 0
SD2DIO X 1 default 0
P3.7/PM_SD2DIO/S36 7 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S36 X X X 1
(1) X = Don't care

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.12.8 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to
P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
Figure 6-9 shows the port diagram. Table 6-25 through Table 6-29 summarize the selection of the pin
functions.

LCDSz

Pad Logic

PyREN.x

DVSS 0

DVCC 1 1
PyDIR.x 0
Direction
1 0: Input
1: Output

PyOUT.x 0

DVSS 1
Py.x/Sz
PyDS.x
PySEL.x 0: Low drive
1: High drive
PyIN.x

EN Bus
Keeper
Not Used D

Figure 6-9. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port
P8 (P8.0 to P8.3) Diagram (MSP430F67xxAIPZ Only)

102 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

Table 6-25. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x) x FUNCTION LCDS35...
P4DIR.x P4SEL.x
LCDS28
P4.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.0/S35 0
DVSS 1 1 0
S35 X X 1
P4.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.1/S34 1
DVSS 1 1 0
S34 X X 1
P4.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.2/S33 2
DVSS 1 1 0
S33 X X 1
P4.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.3/S32 3
DVSS 1 1 0
S32 X X 1
P4.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.4/S31 4
DVSS 1 1 0
S31 X X 1
P4.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.5/S30 5
DVSS 1 1 0
S30 X X 1
P4.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.6/S29 6
DVSS 1 1 0
S29 X X 1
P4.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.7/S28 7
DVSS 1 1 0
S28 X X 1
(1) X = Don't care

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-26. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x) x FUNCTION LCDS27...
P5DIR.x P5SEL.x
LCDS20
P5.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.0/S27 0
DVSS 1 1 0
S27 X X 1
P5.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.1/S26 1
DVSS 1 1 0
S26 X X 1
P5.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.2/S25 2
DVSS 1 1 0
S25 X X 1
P5.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.3/S24 3
DVSS 1 1 0
S24 X X 1
P5.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.4/S23 4
DVSS 1 1 0
S23 X X 1
P5.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.5/S22 5
DVSS 1 1 0
S22 X X 1
P5.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.6/S21 6
DVSS 1 1 0
S21 X X 1
P5.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.7/S20 7
DVSS 1 1 0
S20 X X 1
(1) X = Don't care

104 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

Table 6-27. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x) x FUNCTION LCDS19...
P6DIR.x P6SEL.x
LCDS12
P6.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.0/S19 0
DVSS 1 1 0
S19 X X 1
P6.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.1/S18 1
DVSS 1 1 0
S18 X X 1
P6.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.2/S17 2
DVSS 1 1 0
S17 X X 1
P6.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.3/S16 3
DVSS 1 1 0
S16 X X 1
P6.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.4/S15 4
DVSS 1 1 0
S15 X X 1
P6.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.5/S14 5
DVSS 1 1 0
S14 X X 1
P6.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.6/S13 6
DVSS 1 1 0
S13 X X 1
P6.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.7/S12 7
DVSS 1 1 0
S12 X X 1
(1) X = Don't care

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-28. Port P7 (P7.0 to P7.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P7.x) x FUNCTION LCDS11...
P7DIR.x P7SEL.x
LCDS4
P7.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.0/S11 0
DVSS 1 1 0
S11 X X 1
P7.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.1/S10 1
DVSS 1 1 0
S10 X X 1
P7.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.2/S9 2
DVSS 1 1 0
S9 X X 1
P7.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.3/S8 3
DVSS 1 1 0
S8 X X 1
P7.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.4/S7 4
DVSS 1 1 0
S7 X X 1
P7.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.5/S6 5
DVSS 1 1 0
S6 X X 1
P7.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.6/S5 6
DVSS 1 1 0
S5 X X 1
P7.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P7.7/S4 7
DVSS 1 1 0
S4 X X 1
(1) X = Don't care

106 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

Table 6-29. Port P8 (P8.0 to P8.3) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P8.x) x FUNCTION LCDS3...
P8DIR.x P8SEL.x
LCDS0
P8.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P8.0/S3 0
DVSS 1 1 0
S3 X X 1
P8.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P8.1/S2 1
DVSS 1 1 0
S2 X X 1
P8.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P8.2/S1 2
DVSS 1 1 0
S1 X X 1
P8.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P8.3/S0 3
DVSS 1 1 0
S0 X X 1
(1) X = Don't care

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.12.9 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
Figure 6-10 shows the port diagram. Table 6-30 summarizes the selection of the pin functions.

Pad Logic
P8REN.x

DVSS 0

DVCC 1 1
P8DIR.x 0
Direction
1 0: Input
1: Output

P8OUT.x 0

Module X OUT 1
P8.4/TA1.0
P8DS.x P8.5/TA1.1
P8SEL.x 0: Low drive P8.6/TA2.0
1: High drive P8.7/TA2.1
P8IN.x

Module X IN D

Figure 6-10. Port P8 (P8.4 to P8.7) Diagram (MSP430F67xxAIPZ Only)

Table 6-30. Port P8 (P8.4 to P8.7) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS
PIN NAME (P8.x) x FUNCTION
P8DIR.x P8SEL.x
P8.4 (I/O) I: 0; O: 1 0
P8.4/TA1.0 4 TA1.CCI0A 0 1
TA1.TA0 1 1
P8.5 (I/O) I: 0; O: 1 0
P8.5/TA1.1 5 TA1.CCI1A 0 1
TA1.TA1 1 1
P8.6 (I/O) I: 0; O: 1 0
P8.6/TA2.0 6 TA2.CCI0A 0 1
TA2.TA0 1 1
P8.7 (I/O) I: 0; O: 1 0
P8.7/TA2.1 7 TA2.CCI1A 0 1
TA2.TA1 1 1

108 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)

Figure 6-11 shows the port diagram. Table 6-31 summarizes the selection of the pin functions.

Pad Logic
P9REN.x

DVSS 0

DVCC 1 1
P9DIR.x 0
Direction
1 0: Input
1: Output

P9OUT.x 0

Module X OUT 1
P9.0/TACLK/RTCCLK
P9DS.x
P9SEL.x 0: Low drive
1: High drive
P9IN.x

Module X IN D

Figure 6-11. Port P9 (P9.0) Diagram (MSP430F67xxAIPZ Only)

Table 6-31. Port P9 (P9.0) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS
PIN NAME (P9.x) x FUNCTION
P9DIR.x P9SEL.x
P9.0 (I/O) I: 0; O: 1 0
P9.0/TACLK/RTCCLK 0 TACLK 0 1
RTCCLK 1 1

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
Figure 6-12 shows the port diagram. Table 6-32 summarizes the selection of the pin functions.

Pad Logic
To ADC10

INCHx = y

P9REN.x

DVSS 0

DVCC 1 1

P9DIR.x

P9OUT.x

P9.1/A5
P9DS.x P9.2/A4
P9SEL.x 0: Low drive P9.3/A3
1: High drive

P9IN.x

Bus
Keeper

Figure 6-12. Port P9 (P9.1 to P9.3) Diagram (MSP430F67xxAIPZ Only)

Table 6-32. Port P9 (P9.1 to P9.3) Pin Functions (MSP430F67xxAIPZ Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P9.x) x FUNCTION
P9DIR.x P9SEL.x
P9.1 (I/O) I: 0; O: 1 0
P9.1/A5 1
A5 (2) X 1
P9.2 (I/O) I: 0; O: 1 0
P9.2/A4 2
A4 (2) X 1
P9.3 (I/O) I: 0; O: 1 0
P9.3/A3 3
A3 (2) X 1
(1) X = Don't care
(2) Setting P9SEL.x bit disables the output driver and the input Schmitt trigger.

110 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
Figure 6-13 shows the port diagram. Table 6-33 summarizes the selection of the pin functions.

S39, S38

LCDS39, LCDS38

COM6, COM7

from LCD_C

Pad Logic

P2REN.x

P2MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P2DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P2OUT.x 0

from Port Mapping 1

P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2DS.x
P2SEL.x P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
0: Low drive
1: High drive
P2IN.x

EN Bus
Keeper
to Port Mapping D

P2IE.x
EN
P2IRQ.x
Q
P2IFG.x Set

P2SEL.x Interrupt
Edge
P2IES.x Select

Figure 6-13. Port P2 (P2.0 and P2.1) Diagram (MSP430F67xxAIPN Only)

Copyright © 2015–2018, Texas Instruments Incorporated Detailed Description 111

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Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-33. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxAIPN Only)
CONTROL BITS OR SIGNALS (1)
COM6,
PIN NAME (P2.x) x FUNCTION LCDS39, COM7
P2DIR.x P2SEL.x P2MAPx
LCDS38 Enable
Signal
P2.0 (I/O) I: 0; O: 1 0 X 0 0
UCB0SOMI/UCB0SCL X 1 default 0 0
P2.0/PM_UCB0SOMI/
Output driver and input
PM_UCB0SCL/COM6/ 0 X 1 = 31 0 0
Schmitt trigger disabled
S39
COM6 X X X X 1
S39 X X X 1 0
P2.1 (I/O) I: 0; O: 1 0 X 0 0
UCB0SIMO/UCB0SDA X 1 default 0 0
P2.1/PM_UCB0SIMO/
Output driver and input
PM_UCB0SDA/COM7/ 1 X 1 = 31 0 0
Schmitt trigger disabled
S38
COM7 X X X X 1
S38 X X X 1 0
(1) X = Don't care

112 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
Figure 6-14 shows the port diagram. Table 6-34 summarizes the selection of the pin functions.

S37...S32

LCDS37...LCDS32

Pad Logic

P2REN.x

P2MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P2DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P2OUT.x 0

from Port Mapping 1

P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2DS.x
P2SEL.x P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
0: Low drive
P2.4/PM_UCA1CLK/S35
1: High drive
P2.5/PM_UCA2CLK/S34
P2IN.x P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
EN Bus
Keeper
to Port Mapping D

P2IE.x
EN
P2IRQ.x
Q
P2IFG.x Set

P2SEL.x Interrupt
Edge
P2IES.x Select

Figure 6-14. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxAIPN Only)

Copyright © 2015–2018, Texas Instruments Incorporated Detailed Description 113

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-34. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxAIPN Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x) x FUNCTION LCDS37...
P2DIR.x P2SEL.x P2MAPx
LCDS32
P2.2 (I/O) I: 0; O: 1 0 X 0
UCA2RXD/UCA2SOMI X 1 default 0
P2.2/PM_UCA2RXD/
2 Output driver and input Schmitt
PM_UCA2SOMI/S37 X 1 = 31 0
trigger disabled
S37 X X X 1
P2.3 (I/O) I: 0; O: 1 0 X 0
UCA2TXD/UCA2SIMO X 1 default 0
P2.3/PM_UCA2TXD/
3 Output driver and input Schmitt
PM_UCA2SIMO/S36 X 1 = 31 0
trigger disabled
S36 X X X 1
P2.4 (I/O) I: 0; O: 1 0 X 0
UCA1CLK X 1 default 0
P2.4/PM_UCA1CLK/S35 4 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S35 X X X 1
P2.5 (I/O) I: 0; O: 1 0 X 0
UCA2CLK X 1 default 0
P2.5/PM_UCA2CLK/S34 5 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S34 X X X 1
P2.6 (I/O) I: 0; O: 1 0 X 0
TA1.CCI0A 0 1 default 0
TA1.TA0 1 1 default 0
P2.6/PM_TA1.0/S33 6
Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S33 X X X 1
P2.7 (I/O) I: 0; O: 1 0 X 0
TA1.CCI1A 0 1 default 0
TA1.TA1 1 1 default 0
P2.7/PM_TA1.1/S32 7
Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S32 X X X 1
(1) X = Don't care

114 Detailed Description Copyright © 2015–2018, Texas Instruments Incorporated

6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
Figure 6-15 shows the port diagram. Table 6-35 summarizes the selection of the pin functions.

S31 to S24

LCDS31 to LCDS24

Pad Logic

P3REN.x

P3MAP.x = PMAP_ANALOG
DVSS 0

DVCC 1 1
P3DIR.x 0
Direction
from Port Mapping 1 0: Input
1: Output

P3OUT.x 0

from Port Mapping 1

P3.0/PM_TA2.0/S31
P3DS.x P3.1/PM_TA2.1/S30
P3SEL.x 0: Low drive P3.2/PM_TACLK/PM_RTCCLK/S29
1: High drive P3.3/PM_TA0.2/S28
P3IN.x P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
EN Bus
P3.7/PM_SD2DIO/S24
Keeper
to Port Mapping D

Figure 6-15. Port P3 (P3.0 to P3.7) Diagram (MSP430F67xxAIPN Only)

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-35. Port P3 (P3.0 to P3.7) Pin Functions (MSP430F67xxAIPN Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x) x FUNCTION LCDS31...
P3DIR.x P3SEL.x P3MAPx
LCDS24
P3.0 (I/O) I: 0; O: 1 0 X 0
TA2.CCI0A 0 1 default 0
TA2.TA0 1 1 default 0
P3.0/PM_TA2.0/S31 0
Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S31 X X X 1
P3.1 (I/O) I: 0; O: 1 0 X 0
TA2.CCI1A 0 1 default 0
TA2.TA1 1 1 default 0
P3.1/PM_TA2.1/S30 1
Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S30 X X X 1
P3.2 (I/O) I: 0; O: 1 0 X 0
TACLK 0 1 default 0
P3.2/PM_TACLK/ RTCCLK 1 1 default 0
2
PM_RTCCLK/S29
Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S29 X X X 1
P3.3 (I/O) I: 0; O: 1 0 X 0
TA0.CCI2A 0 1 default 0
TA0.TA2 1 1 default 0
P3.3/PM_TA0.2/S28 3
Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S28 X X X 1
P3.4 (I/O) I: 0; O: 1 0 X 0
SDCLK X 1 default 0
P3.4/PM_SDCLK/S27 4 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S27 X X X 1
P3.5 (I/O) I: 0; O: 1 0 X 0
SD0DIO X 1 default 0
P3.5/PM_SD0DIO/S26 5 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S26 X X X 1
P3.6 (I/O) I: 0; O: 1 0 X 0
SD1DIO X 1 default 0
P3.6/PM_SD1DIO/S25 6 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S25 X X X 1
P3.7 (I/O) I: 0; O: 1 0 X 0
SD2DIO X 1 default 0
P3.7/PM_SD2DIO/S24 7 Output driver and input Schmitt
X 1 = 31 0
trigger disabled
S24 X X X 1
(1) X = Don't care

6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output
With Schmitt Trigger (MSP430F67xxAIPN Only)
Figure 6-16 shows the port diagram. Table 6-36 through Table 6-38 summarize the selection of the pin
functions.

LCDSz

Pad Logic

PyREN.x

DVSS 0

DVCC 1 1
PyDIR.x 0
Direction
1 0: Input
1: Output

PyOUT.x 0

DVSS 1
Py.x/Sz
PyDS.x
PySEL.x 0: Low drive
1: High drive
PyIN.x

EN Bus
Keeper
Not Used D

Figure 6-16. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Diagram
(MSP430F67xxAIPN Only)

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-36. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxAIPN Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x) x FUNCTION LCDS23...
P4DIR.x P4SEL.x
LCDS16
P4.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.0/S23 0
DVSS 1 1 0
S23 X X 1
P4.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.1/S22 1
DVSS 1 1 0
S22 X X 1
P4.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.2/S21 2
DVSS 1 1 0
S21 X X 1
P4.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.3/S20 3
DVSS 1 1 0
S20 X X 1
P4.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.4/S19 4
DVSS 1 1 0
S19 X X 1
P4.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.5/S18 5
DVSS 1 1 0
S18 X X 1
P4.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.6/S17 6
DVSS 1 1 0
S17 X X 1
P4.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P4.7/S16 7
DVSS 1 1 0
S16 X X 1
(1) X = Don't care

Table 6-37. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxAIPN Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x) x FUNCTION LCDS15...
P5DIR.x P5SEL.x
LCDS8
P5.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.0/S15 0
DVSS 1 1 0
S15 X X 1
P5.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.1/S14 1
DVSS 1 1 0
S14 X X 1
P5.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.2/S13 2
DVSS 1 1 0
S13 X X 1
P5.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.3/S12 3
DVSS 1 1 0
S12 X X 1
P5.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.4/S11 4
DVSS 1 1 0
S11 X X 1
P5.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.5/S10 5
DVSS 1 1 0
S10 X X 1
P5.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.6/S9 6
DVSS 1 1 0
S9 X X 1
P5.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P5.7/S8 7
DVSS 1 1 0
S8 X X 1
(1) X = Don't care

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-38. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxAIPN Only)

CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x) x FUNCTION LCDS7...
P6DIR.x P6SEL.x
LCDS0
P6.0 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.0/S7 0
DVSS 1 1 0
S7 X X 1
P6.1 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.1/S6 1
DVSS 1 1 0
S6 X X 1
P6.2 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.2/S5 2
DVSS 1 1 0
S5 X X 1
P6.3 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.3/S4 3
DVSS 1 1 0
S4 X X 1
P6.4 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.4/S3 4
DVSS 1 1 0
S3 X X 1
P6.5 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.5/S2 5
DVSS 1 1 0
S2 X X 1
P6.6 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.6/S1 6
DVSS 1 1 0
S1 X X 1
P6.7 (I/O) I: 0; O: 1 0 0
N/A 0 1 0
P6.7/S0 7
DVSS 1 1 0
S0 X X 1
(1) X = Don't care

6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-17 shows the port diagram. Table 6-39 summarizes the selection of the pin functions.

Pad Logic
PJREN.x

DVSS 0

DVCC 1 1
PJDIR.x 0

DVCC 1

PJOUT.x 00

From JTAG 01
SMCLK 10 PJ.0/SMCLK/TDO
PJDS.0
11 0: Low drive
1: High drive
PJSEL.x
From JTAG

PJIN.x

EN Bus
Holder
D

Figure 6-17. Port PJ (PJ.0) Diagram

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-18 shows the port diagram. Table 6-39 summarizes the selection of the pin functions.

Pad Logic
PJREN.x

DVSS 0

DVCC 1 1
PJDIR.x 0

DVSS 1

PJOUT.x 00

From JTAG 01
PJ.1/MCLK/TDI/TCLK
MCLK/ADC10CLK/ACLK 10 PJDS.x
PJ.2/ADC10CLK/TMS
0: Low drive
11 PJ.3/ACLK/TCK
1: High drive
PJSEL.x
From JTAG

PJIN.x

EN Bus
Holder
To JTAG D

Figure 6-18. Port PJ (PJ.1 to PJ.3) Diagram

Table 6-39. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS OR SIGNALS (1)
PIN NAME (PJ.x) x FUNCTION JTAG
PJDIR.x PJSEL.x Mode
Signal
PJ.0 (I/O) (2) I: 0; O: 1 0 0
PJ.0/SMCLK/TDO 0 SMCLK 1 1 0
TDO (3) X X 1
(2)
PJ.1 (I/O) I: 0; O: 1 0 0
PJ.1/MCLK/TDI/TCLK 1 MCLK 1 1 0
(3) (4)
TDI/TCLK X X 1
(2)
PJ.2 (I/O) I: 0; O: 1 0 0
PJ.2/ADC10CLK/TMS 2 ADC10CLK 1 1 0
(3) (4)
TMS X X 1
(2)
PJ.3 (I/O) I: 0; O: 1 0 0
PJ.3/ACLK/TCK 3 ACLK 1 1 0
(3) (4)
TCK X X 1
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

6.13 Device Descriptors (TLV)

Table 6-40 and Table 6-41 list the complete contents of the device descriptor tag-length-value (TLV)
structure for each device type.

Table 6-40. MSP430F673xA Device Descriptors

SIZE VALUE
DESCRIPTION ADDRESS
(bytes) F6736A F6735A F6734A F6733A F6731A F6730A
Info length 01A00h 1 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Info Block Device ID 01A04h 1 86h 85h 84h 83h 81h 80h
Device ID 01A05h 1 82h 82h 82h 82h 82h 82h
Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Per unit Per unit
Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Per unit Per unit
Die record tag 01A08h 1 08h 08h 08h 08h 08h 08h
Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Per unit Per unit
Die Record
Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit
Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Test results 01A12h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC10 calibration tag 01A14h 1 13h 13h 13h 13h 13h 13h
ADC10 calibration length 01A15h 1 10h 10h 10h 10h 10h 10h
ADC gain factor 01A16h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC offset 01A18h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
01A1Ah 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 1.5-V reference
ADC10 01A1Ch 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 85°C
Calibration
ADC 2.0-V reference
01A1Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 2.0-V reference
01A20h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 85°C
ADC 2.5-V reference
01A22h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 2.5-V reference
01A24h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 85°C

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MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-41. MSP430F672xA Device Descriptors

SIZE VALUE
DESCRIPTION ADDRESS
(bytes) F6726A F6725A F6724A F6723A F6721A F6720A
Info length 01A00h 1 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Info Block Device ID 01A04h 1 7Ch 7Bh 7Ah 79h 77h 76h
Device ID 01A05h 1 82h 82h 82h 82h 82h 82h
Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Per unit Per unit
Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Per unit Per unit
Die record tag 01A08h 1 08h 08h 08h 08h 08h 08h
Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Per unit Per unit
Die Record
Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit
Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Test results 01A12h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC10 calibration tag 01A14h 1 13h 13h 13h 13h 13h 13h
ADC10 calibration length 01A15h 1 10h 10h 10h 10h 10h 10h
ADC gain factor 01A16h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC offset 01A18h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
01A1Ah 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 1.5-V reference
ADC10 01A1Ch 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 85°C
Calibration
ADC 2.0-V reference
01A1Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 2.0-V reference
01A20h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 85°C
ADC 2.5-V reference
01A22h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 30°C
ADC 2.5-V reference
01A24h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Temperature sensor 85°C

6.14 Memory

6.14.1 Memory Organization

Table 6-42 and Table 6-43 summarize the memory map for all device variants.

Table 6-42. Memory Organization

MSP430F6730A MSP430F6731A MSP430F6733A
MSP430F6720A MSP430F6721A MSP430F6723A
Main Memory
Total Size 16KB 32KB 64KB
(flash)
Main: Interrupt
00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
vector
Main: code
Bank 3 Not available Not available Not available
memory
Bank 2 Not available Not available Not available
16KB 32KB
Bank 1 Not available
00FFFFh–00C000h 013FFFh–00C000h
16KB 16KB 32KB
Bank 0
00FFFFh–00C000h 00BFFFh–008000h 00BFFFh–004000h
RAM Total Size 1KB 2KB 4KB
Sector 3 Not available Not available Not available
Sector 2 Not available Not available Not available
2KB
Sector 1 Not available Not available
002BFFh–002400h
1KB 2KB 2KB
Sector 0
001FFFh–001C00h 0023FFh–001C00h 0023FFh–001C00h
128 B 128 B 128 B
Info A
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
128 B 128 B 128 B
Info B
Information 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
memory (flash) 128 B 128 B 128 B
Info C
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
128 B 128 B 128 B
Info D
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
512 B 512 B 512 B
BSL 3
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
512 B 512 B 512 B
BSL 2
Bootloader (BSL) 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
memory (flash) 512 B 512 B 512 B
BSL 1
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
512 B 512 B 512 B
BSL 0
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
4 KB 4 KB 4 KB
Peripherals
000FFFh–0h 000FFFh–0h 000FFFh–0h

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-43. Memory Organization

MSP430F6734A MSP430F6735A MSP430F6736A
MSP430F6724A MSP430F6725A MSP430F6726A
Total
Main Memory (flash) 96KB 128KB 128KB
Size
Main: Interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
32KB 32KB
Main: code memory Bank 3 Not available
023FFFh–01C000h 023FFFh–01C000h
32KB 32KB 32KB
Bank 2
01BFFFh–014000h 01BFFFh–014000h 01BFFFh–014000h
32KB 32KB 32KB
Bank 1
013FFFh–00C000h 013FFFh–00C000h 013FFFh–00C000h
32KB 32KB 32KB
Bank 0
00BFFFh–004000h 00BFFFh–004000h 00BFFFh–004000h
Total
RAM 4KB 4KB 8KB
Size
2KB
Sector 3 Not available Not available
003BFFh–003400h
2KB
Sector 2 Not available Not available
0033FFh–002C00h
2KB 2KB 2KB
Sector 1
002BFFh–002400h 002BFFh–002400h 002BFFh–002400h
2KB 2KB 2KB
Sector 0
0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h
128 B 128 B 128 B
Info A
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
128 B 128 B 128 B
Info B
Information memory 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
(flash) 128 B 128 B 128 B
Info C
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
128 B 128 B 128 B
Info D
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
512 B 512 B 512 B
BSL 3
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
512 B 512 B 512 B
BSL 2
Bootloader (BSL) 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
memory (flash) 512 B 512 B 512 B
BSL 1
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
512 B 512 B 512 B
BSL 0
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
4 KB 4 KB 4 KB
Peripherals
000FFFh–0h 000FFFh–0h 000FFFh–0h

6.14.2 Peripheral File Map

Table 6-44 lists the available modules with the base address and the offset range for each. Table 6-45
through Table 6-82 list all of the available registers for each module.

Table 6-44. Peripheral File Map

OFFSET ADDRESS
MODULE NAME BASE ADDRESS
RANGE
Special Functions (see Table 6-45) 0100h 000h–01Fh
PMM (see Table 6-46) 0120h 000h–01Fh
Flash Control (see Table 6-47) 0140h 000h–00Fh
CRC16 (see Table 6-48) 0150h 000h–007h
RAM Control (see Table 6-49) 0158h 000h–001h
Watchdog (see Table 6-50) 015Ch 000h–001h
UCS (see Table 6-51) 0160h 000h–01Fh
SYS (see Table 6-52) 0180h 000h–01Fh
Shared Reference (see Table 6-53) 01B0h 000h–001h
Port Mapping Control (see Table 6-54) 01C0h 000h–007h
Port Mapping Port P1 (see Table 6-55) 01C8h 000h–007h
Port Mapping Port P2 (see Table 6-56) 01D0h 000h–007h
Port Mapping Port P3 (see Table 6-57) 01D8h 000h–007h
Port P1, P2 (see Table 6-58) 0200h 000h–01Fh
Port P3, P4 (see Table 6-59) 0220h 000h–00Bh
Port P5, P6 (see Table 6-60) 0240h 000h–00Bh
Port P7, P8 (see Table 6-61)
0260h 000h–00Bh
(Port P7, P8 not available in MSP430F67xxAIPN)
Port P9 (Port P9 not available in
MSP430F67xxAIPN) 0280h 000h–00Bh
(see Table 6-62)
Port PJ (refer toTable 6-63) 0320h 000h–01Fh
Timer TA0 (see Table 6-64) 0340h 000h–03Fh
Timer TA1 (see Table 6-65) 0380h 000h–03Fh
Timer TA2 (see Table 6-66) 0400h 000h–03Fh
Timer TA3 (see Table 6-67) 0440h 000h–03Fh
Backup Memory (see Table 6-68) 0480h 000h–00Fh
RTC_C (see Table 6-69) 04A0h 000h–01Fh
32-Bit Hardware Multiplier (see Table 6-70) 04C0h 000h–02Fh
DMA General Control (see Table 6-71) 0500h 000h–00Fh
DMA Channel 0 (see Table 6-72) 0500h 010h–01Fh
DMA Channel 1 (see Table 6-73) 0500h 020h–02Fh
DMA Channel 2 (see Table 6-74) 0500h 030h–03Fh
eUSCI_A0 (see Table 6-75) 05C0h 000h–01Fh
eUSCI_A1 (see Table 6-76) 05E0h 000h–01Fh
eUSCI_A2 (see Table 6-77) 0600h 000h–01Fh
eUSCI_B0 (see Table 6-78) 0640h 000h–02Fh
ADC10_A (see Table 6-79) 0740h 000h–01Fh
SD24_B (see Table 6-80) 0800h 000h–06Fh
Auxiliary Supply (see Table 6-74) 09E0h 000h–01Fh
LCD_C (see Table 6-82) 0A00h 000h–05Fh

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-45. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-46. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high-side control SVSMHCTL 04h
SVS low-side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control 0 PM5CTL0 10h

Table 6-47. Flash Control Registers (Base Address: 0140h)

Table 6-48. CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRC16DIRB 02h
CRC result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 6-49. RAM Control Registers (Base Address: 0158h)

Table 6-50. Watchdog Registers (Base Address: 015Ch)

Table 6-51. UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh

Table 6-51. UCS Registers (Base Address: 0160h) (continued)

Table 6-52. SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-53. Shared Reference Registers (Base Address: 01B0h)

Table 6-54. Port Mapping Controller (Base Address: 01C0h)

Table 6-55. Port Mapping for Port P1 (Base Address: 01C8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1.0 mapping P1MAP0 00h
Port P1.1 mapping P1MAP1 01h
Port P1.2 mapping P1MAP2 02h
Port P1.3 mapping P1MAP3 03h
Port P1.4 mapping P1MAP4 04h
Port P1.5 mapping P1MAP5 05h
Port P1.6 mapping P1MAP6 06h
Port P1.7 mapping P1MAP7 07h

Table 6-56. Port Mapping for Port P2 (Base Address: 01D0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P2.0 mapping P2MAP0 00h
Port P2.1 mapping P2MAP2 01h
Port P2.2 mapping P2MAP2 02h
Port P2.3 mapping P2MAP3 03h
Port P2.4 mapping P2MAP4 04h
Port P2.5 mapping P2MAP5 05h
Port P2.6 mapping P2MAP6 06h
Port P2.7 mapping P2MAP7 07h

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-57. Port Mapping for Port P3 (Base Address: 01D8h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3.0 mapping P3MAP0 00h
Port P3.1 mapping P3MAP3 01h
Port P3.2 mapping P3MAP2 02h
Port P3.3 mapping P3MAP3 03h
Port P3.4 mapping P3MAP4 04h
Port P3.5 mapping P3MAP5 05h
Port P3.6 mapping P3MAP6 06h
Port P3.7 mapping P3MAP7 07h

Table 6-58. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 resistor enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 resistor enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-59. Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 resistor enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 resistor enable P4REN 07h
Port P4 drive strength P4DS 09h
Port P4 selection P4SEL 0Bh

Table 6-60. Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 resistor enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 resistor enable P6REN 07h
Port P6 drive strength P6DS 09h
Port P6 selection P6SEL 0Bh

Table 6-61. Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 resistor enable P7REN 06h
Port P7 drive strength P7DS 08h
Port P7 selection P7SEL 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 resistor enable P8REN 07h
Port P8 drive strength P8DS 09h
Port P8 selection P8SEL 0Bh

Table 6-62. Port P9 Registers (Base Address: 0280h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P9 input P9IN 00h
Port P9 output P9OUT 02h
Port P9 direction P9DIR 04h
Port P9 resistor enable P9REN 06h
Port P9 drive strength P9DS 08h
Port P9 selection P9SEL 0Ah

Table 6-63. Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ resistor enable PJREN 06h
Port PJ drive strength PJDS 08h
Port PJ selection PJSEL 0Ah

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-64. TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
TA0 counter TA0R 10h
Capture/compare 0 TA0CCR0 12h
Capture/compare 1 TA0CCR1 14h
Capture/compare 2 TA0CCR2 16h
TA0 expansion 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-65. TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
TA1 counter TA1R 10h
Capture/compare 0 TA1CCR0 12h
Capture/compare 1 TA1CCR1 14h
TA1 expansion 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-66. TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION REGISTER OFFSET
TA2 control TA2CTL 00h
Capture/compare control 0 TA2CCTL0 02h
Capture/compare control 1 TA2CCTL1 04h
TA2 counter TA2R 10h
Capture/compare 0 TA2CCR0 12h
Capture/compare 1 TA2CCR1 14h
TA2 expansion 0 TA2EX0 20h
TA2 interrupt vector TA2IV 2Eh

Table 6-67. TA3 Registers (Base Address: 0440h)

REGISTER DESCRIPTION REGISTER OFFSET
TA3 control TA3CTL 00h
Capture/compare control 0 TA3CCTL0 02h
Capture/compare control 1 TA3CCTL1 04h
TA3 counter TA3R 10h
Capture/compare 0 TA3CCR0 12h
Capture/compare 1 TA3CCR1 14h
TA3 expansion 0 TA3EX0 20h
TA3 interrupt vector TA3IV 2Eh

Table 6-68. Backup Memory Registers (Base Address: 0480h)

REGISTER DESCRIPTION REGISTER OFFSET
Backup memory 0 BAKMEM0 00h
Backup memory 1 BAKMEM1 02h
Backup memory 2 BAKMEM2 04h
Backup memory 3 BAKMEM3 06h

Table 6-69. RTC_C Registers (Base Address: 04A0h)

REGISTER DESCRIPTION REGISTER OFFSET
RTC control 0 RTCCTL0 00h
RTC password RTCPWD 01h
RTC control 1 RTCCTL1 02h
RTC control 3 RTCCTL3 03h
RTC offset calibration RTCOCAL 04h
RTC temperature compensation RTCTCMP 06h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds RTCSEC 10h
RTC minutes RTCMIN 11h
RTC hours RTCHOUR 12h
RTC day of week RTCDOW 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year RTCYEAR 16h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
Binary-to-BCD conversion BIN2BCD 1Ch
BCD-to-binary conversion BCD2BIN 1Eh

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-70. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

Table 6-71. DMA General Control Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh

Table 6-72. DMA Channel 0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 10h
DMA channel 0 source address low DMA0SAL 12h
DMA channel 0 source address high DMA0SAH 14h
DMA channel 0 destination address low DMA0DAL 16h
DMA channel 0 destination address high DMA0DAH 18h
DMA channel 0 transfer size DMA0SZ 1Ah

Table 6-73. DMA Channel 1 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 1 control DMA1CTL 20h
DMA channel 1 source address low DMA1SAL 22h
DMA channel 1 source address high DMA1SAH 24h
DMA channel 1 destination address low DMA1DAL 26h
DMA channel 1 destination address high DMA1DAH 28h
DMA channel 1 transfer size DMA1SZ 2Ah

Table 6-74. DMA Channel 2 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 2 control DMA2CTL 30h
DMA channel 2 source address low DMA2SAL 32h
DMA channel 2 source address high DMA2SAH 34h
DMA channel 2 destination address low DMA2DAL 36h
DMA channel 2 destination address high DMA2DAH 38h
DMA channel 2 transfer size DMA2SZ 3Ah

Table 6-75. eUSCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA0CTLW0 00h
eUSCI _A control word 1 UCA0CTLW1 02h
eUSCI_A baud rate 0 UCA0BR0 06h
eUSCI_A baud rate 1 UCA0BR1 07h
eUSCI_A modulation control UCA0MCTLW 08h
eUSCI_A status UCA0STAT 0Ah
eUSCI_A receive buffer UCA0RXBUF 0Ch
eUSCI_A transmit buffer UCA0TXBUF 0Eh
eUSCI_A LIN control UCA0ABCTL 10h
eUSCI_A IrDA transmit control UCA0IRTCTL 12h
eUSCI_A IrDA receive control UCA0IRRCTL 13h
eUSCI_A interrupt enable UCA0IE 1Ah
eUSCI_A interrupt flags UCA0IFG 1Ch
eUSCI_A interrupt vector word UCA0IV 1Eh

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-76. eUSCI_A1 Registers (Base Address:05E0h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA1CTLW0 00h
eUSCI _A control word 1 UCA1CTLW1 02h
eUSCI_A baud rate 0 UCA1BR0 06h
eUSCI_A baud rate 1 UCA1BR1 07h
eUSCI_A modulation control UCA1MCTLW 08h
eUSCI_A status UCA1STAT 0Ah
eUSCI_A receive buffer UCA1RXBUF 0Ch
eUSCI_A transmit buffer UCA1TXBUF 0Eh
eUSCI_A LIN control UCA1ABCTL 10h
eUSCI_A IrDA transmit control UCA1IRTCTL 12h
eUSCI_A IrDA receive control UCA1IRRCTL 13h
eUSCI_A interrupt enable UCA1IE 1Ah
eUSCI_A interrupt flags UCA1IFG 1Ch
eUSCI_A interrupt vector word UCA1IV 1Eh

Table 6-77. eUSCI_A2 Registers (Base Address:0600h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA2CTLW0 00h
eUSCI _A control word 1 UCA2CTLW1 02h
eUSCI_A baud rate 0 UCA2BR0 06h
eUSCI_A baud rate 1 UCA2BR1 07h
eUSCI_A modulation control UCA2MCTLW 08h
eUSCI_A status UCA2STAT 0Ah
eUSCI_A receive buffer UCA2RXBUF 0Ch
eUSCI_A transmit buffer UCA2TXBUF 0Eh
eUSCI_A LIN control UCA2ABCTL 10h
eUSCI_A IrDA transmit control UCA2IRTCTL 12h
eUSCI_A IrDA receive control UCA2IRRCTL 13h
eUSCI_A interrupt enable UCA2IE 1Ah
eUSCI_A interrupt flags UCA2IFG 1Ch
eUSCI_A interrupt vector word UCA2IV 1Eh

Table 6-78. eUSCI_B0 Registers (Base Address: 0640h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B received address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI I2C slave address UCB0I2CSA 20h
eUSCI interrupt enable UCB0IE 2Ah
eUSCI interrupt flags UCB0IFG 2Ch
eUSCI interrupt vector word UCB0IV 2Eh

Table 6-79. ADC10_A Registers (Base Address: 0740h)

REGISTER DESCRIPTION REGISTER OFFSET
ADC10_A control 0 ADC10CTL0 00h
ADC10_A control 1 ADC10CTL1 02h
ADC10_A control 2 ADC10CTL2 04h
ADC10_A window comparator low threshold ADC10LO 06h
ADC10_A window comparator high threshold ADC10HI 08h
ADC10_A memory control 0 ADC10MCTL0 0Ah
ADC10_A conversion memory ADC10MCTL0 12h
ADC10_A interrupt enable ADC10IE 1Ah
ADC10_A interrupt flags ADC10IGH 1Ch
ADC10_A interrupt vector word ADC10IV 1Eh

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

Table 6-80. SD24_B Registers (Base Address: 0800h)

REGISTER DESCRIPTION REGISTER OFFSET
SD24_B control 0 SD24BCTL0 00h
SD24_B control 1 SD24BCTL1 02h
SD24_B interrupt flag SD24BIFG 0Ah
SD24_B interrupt enable SD24BIE 0Ch
SD24_B interrupt vector SD24BIV 0Eh
SD24_B converter 0 control SD24BCCTL0 10h
SD24_B converter 0 input control SD24BINCTL0 12h
SD24_B converter 0 OSR control SD24BOSR0 14h
SD24_B converter 0 preload SD24BPRE0 16h
SD24_B converter 1 control SD24BCCTL1 18h
SD24_B converter 1 input control SD24BINCTL1 1Ah
SD24_B converter 1 OSR control SD24BOSR1 1Ch
SD24_B converter 1 preload SD24BPRE1 1Eh
SD24_B converter 2 control SD24BCCTL2 20h
SD24_B converter 2 input control SD24BINCTL2 22h
SD24_B converter 2 OSR control SD24BOSR2 24h
SD24_B converter 2 preload SD24BPRE2 26h
SD24_B converter 0 conversion memory low word SD24BMEML0 50h
SD24_B converter 0 conversion memory high word SD24BMEMH0 52h
SD24_B converter 1 conversion memory low word SD24BMEML1 54h
SD24_B converter 1 conversion memory high word SD24BMEMH1 56h
SD24_B converter 2 conversion memory low word SD24BMEML2 58h
SD24_B converter 2 conversion memory high word SD24BMEMH2 5Ah

Table 6-81. Auxiliary Supplies Registers (Base Address: 09E0h)

REGISTER DESCRIPTION REGISTER OFFSET
Auxiliary supply control 0 AUXCTL0 00h
Auxiliary supply control 1 AUXCTL1 02h
Auxiliary supply control 2 AUXCTL2 04h
AUX2 charger control AUX2CHCTL 12h
AUX3 charger control AUX3CHCTL 14h
AUX ADC control AUXADCCTL 16h
AUX interrupt flag AUXIFG 1Ah
AUX interrupt enable AUXIE 1Ch
AUX interrupt vector word AUXIV 1Eh

Table 6-82. LCD_C Registers (Base Address: 0A00h)

REGISTER DESCRIPTION REGISTER OFFSET
LCD_C control 0 LCDCCTL0 000h
LCD_C control 1 LCDCCTL1 002h
LCD_C blinking control LCDCBLKCTL 004h
LCD_C memory control LCDCMEMCTL 006h
LCD_C voltage control LCDCVCTL 008h
LCD_C port control 0 LCDCPCTL0 00Ah
LCD_C port control 1 LCDCPCTL1 00Ch
LCD_C port control 2 LCDCPCTL2 00Eh
LCD_C charge pump control LCDCCPCTL 012h
LCD_C interrupt vector LCDCIV 01Eh
Static and 2 to 4 mux modes
LCD_C memory 1 LCDM1 020h
LCD_C memory 2 LCDM2 021h
⋮ ⋮ ⋮
LCD_C memory 20 LCDM20 033h
LCD_C blinking memory 1 LCDBM1 040h
LCD_C blinking memory 2 LCDBM2 041h
⋮ ⋮ ⋮
LCD_C blinking memory 20 LCDBM20 053h
5 to 8 mux modes
LCD_C memory 1 LCDM1 020h
LCD_C memory 2 LCDM2 021h
⋮ ⋮ ⋮
LCD_C memory 40 LCDM40 047h

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

6.15 Identification

6.15.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.13.

6.15.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.13.

6.15.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.

7 Applications, Implementation, and Layout

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

The following resources provide application guidelines and best practices when designing with the
MSP430F673xA and MSP430F672xA.
Implementation of a Single-Phase Electronic Watt-Hour Meter Using the MSP430F6736(A)
This application report describes the implementation of a single-phase electronic electricity meter using
the Texas Instruments MSP430F673x(A) metering processor. It also includes the necessary information
with regard to metrology software and hardware procedures for this single-chip implementation.
High-Accuracy Single-Phase Electricity Meter With Tamper Detection
This design, featuring the MSP430F6736(A) device, implements a highly-integrated single-chip electricity
metering (e-meter) solution. Hardware and software design files are provided to enable calculation of
various parameters for single phase energy measurement, such as RMS current and voltage, active and
reactive power and energies, power factor, and frequency.
Features
• Low-power single-phase e-metering implementation
• Calculate parameters such as RMS current and voltage, active and reactive power and energies,
power factor and frequency
• Based on the highly-integrated MSP430F67xx(A) family of metering-focused MCU SoCs
• Segment LCD is also implemented in this design
• RF modules can also be added to this design to enable unique connectivity solutions.

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

8 Device and Documentation Support

8.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.

8.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the
complete device name.

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

MSP 430 F 5 438 A I ZQW T -EP

Processor Family Optional: Additional Features

MCU Platform Optional: Tape and Reel

Device Type Packaging

Series Optional: Temperature Range

Feature Set Optional: A = Revision

Processor Family CC = Embedded RF Radio

MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform 430 = MSP430 low-power microcontroller platform
Device Type Memory Type Specialized Application
C = ROM AFE = Analog Front End
F = Flash BQ = Contactless Power
FR = FRAM CG = ROM Medical
G = Flash or FRAM (Value Line) FE = Flash Energy Meter
L = No Nonvolatile Memory FG = Flash Medical
FW = Flash Electronic Flow Meter
Series 1 = Up to 8 MHz 5 = Up to 25 MHz
2 = Up to 16 MHz 6 = Up to 25 MHz with LCD
3 = Legacy 0 = Low-Voltage Series
4 = Up to 16 MHz with LCD
Feature Set Various levels of integration within a series
Optional: A = Revision N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging http://www.ti.com/packaging
Optional: Tape and Reel T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified

Figure 8-1. Device Nomenclature

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

8.3 Tools and Software

All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs –
Tools & software.
Table 8-1 lists the debug features of the MSP430F673xA and MSP430F672xA MCUs. See the Code
Composer Studio for MSP430 User's Guide for details on the available features.

Table 8-1. Hardware Debug Features

BREAK- RANGE LPMx.5
MSP430 4-WIRE 2-WIRE CLOCK STATE TRACE
POINTS BREAK- DEBUGGING
ARCHITECTURE JTAG JTAG CONTROL SEQUENCER BUFFER
(N) POINTS SUPPORT
MSP430Xv2 Yes Yes 3 Yes Yes No No No

Design Kits and Evaluation Modules

MSP-TS430PZ100B - 100-Pin Target Development Board for MSP430F6x MCUs The MSP-
TS430PZ100B is a stand-alone 100-pin ZIF socket target board used to program and debug
the MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG)
protocol.
100-Pin Target Development Board and MSP-FET Programmer Bundle for MSP430F6x MCUs The
MSP-FET is a powerful flash emulation tool to quickly begin application development on the
MSP430 MCU. It includes USB debugging interface used to program and debug the
MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG)
protocol.
EVM430-F6736 - MSP430F6736 EVM for Metering This EVM430-F6736 is a single-phase electricity
meter evaluation module based on the MSP430F6736 device. The E-meter can be
connected to the main power lines and has inputs for voltage and current, as well as a third
connection to setup anti-tampering.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
Energy Measurement Design Center for MSP430 MCUs The Energy Measurement Design Center is a
rapid development tool that enables energy measurement using TI MSP430i20xx and
MSP430F67xx flash-based microcontrollers (MCUs). It includes a graphical user interface
(GUI), documentation, software library, and examples that can simplify development and
accelerate designs in a wide range of power monitoring and energy measurement
applications, including smart grid and building automation. Using the Design Center, you can
configure, calibrate, and view results without writing a single line of code.
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use – Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430s to help simplify the customer’s certification efforts of functional safety-
compliant consumer devices to IEC 60730-1:2010 Class B.
MSP430F673xA, MSP430F672xA Code Examples C Code examples are available for every MSP
device that configures each of the integrated peripherals for various application needs.

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

Capacitive Touch Software Library Free C libraries for enabling capacitive touch capabilities on
MSP430 MCUs. The MSP430 MCU version of the library features several capacitive touch
implementations including the RO and RC method.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energy-
based code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions that are up to 26 times faster
than the standard MSP430 math functions. Mathlib is easy to integrate into your designs.
This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. It includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler, and many other features.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP low-
power MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

8.4 Documentation Support

The following documents describe the MSP430F673xA and MSP430F672xA MCUs. Copies of these
documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (see Section 8.5 for links). In the upper right corner, click the "Alert me" button. This
registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430F6736A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6735A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6734A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6733A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6731A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6730A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6726A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6725A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6724A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6723A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6721A Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F6720A Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
MSP430x5xx and MSP430x6xx Family User's Guide Detailed information on the modules and
peripherals available in this device family.
MSP430™ Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) lets users
communicate with embedded memory in the MSP430 microcontroller during the prototyping
phase, final production, and in service. Both the programmable memory (flash memory) and
the data memory (RAM) can be modified as required. Do not confuse the bootloader with the
bootstrap loader programs found in some digital signal processors (DSPs) that automatically
load program code (and data) from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultra-
low-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.

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MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

Application Reports
Implementation of a Single-Phase Electronic Watt-Hour Meter Using MSP430F6736(A) This
application report describes the implementation of a single-phase electronic electricity meter
using the Texas Instruments MSP430F673x(A) metering processor. It also includes the
necessary information with regard to metrology software and hardware procedures for this
single-chip implementation.
Differences Between MSP430F67xx and MSP430F67xxA Devices This application report describes
the enhancements of the MSP430F67xxA devices from the non-A MSP430F67xx devices.
This application report describes the MSP430F67xx errata that are fixed in the
MSP430F67xxA and the additional features added to the MSP430F67xxA devices. In
addition, metrology results are compared to further show that the changes implemented in
the MSP430F67xxA devices do not affect the metrology performance.
MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper
board layout are important for a stable crystal oscillator. This application report summarizes
crystal oscillator function and explains the parameters to select the correct crystal for
MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to
ensure stable oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing cost-
effective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
Designing With MSP430 and Segment LCDs Segment liquid crystal displays (LCDs) are needed to
provide information to users in a wide variety of applications from smart meters to electronic
shelf labels (ESLs) to medical equipment. Several MSP430™ microcontroller families include
built-in low-power LCD driver circuitry that allows the MSP430 MCU to directly control the
segmented LCD glass. This application note helps explain how segmented LCDs work, the
different features of the various LCD modules across the MSP430 MCU family, LCD
hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and
an overview of the portfolio of MSP430 devices that include different LCD features to aid in
device selection.

Copyright © 2015–2018, Texas Instruments Incorporated Device and Documentation Support 147
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018 www.ti.com

8.5 Related Links

Table 8-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 8-2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
MSP430F6736A Click here Click here Click here Click here Click here
MSP430F6735A Click here Click here Click here Click here Click here
MSP430F6734A Click here Click here Click here Click here Click here
MSP430F6733A Click here Click here Click here Click here Click here
MSP430F6731A Click here Click here Click here Click here Click here
MSP430F6730A Click here Click here Click here Click here Click here
MSP430F6726A Click here Click here Click here Click here Click here
MSP430F6725A Click here Click here Click here Click here Click here
MSP430F6724A Click here Click here Click here Click here Click here
MSP430F6723A Click here Click here Click here Click here Click here
MSP430F6721A Click here Click here Click here Click here Click here
MSP430F6720A Click here Click here Click here Click here Click here

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.

8.7 Trademarks
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of
Texas Instruments.
All other trademarks are the property of their respective owners.

148 Device and Documentation Support Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
www.ti.com SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018

8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.

8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2015–2018, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information 149
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MSP430F6720AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6720A

MSP430F6720AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6720A

MSP430F6720AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6720A

MSP430F6720AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6720A

MSP430F6721AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6721A

MSP430F6721AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6721A

MSP430F6721AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6721A

MSP430F6721AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6721A

MSP430F6723AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6723A

MSP430F6723AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6723A

MSP430F6723AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6723A

MSP430F6723AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6723A

MSP430F6724AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6724A

MSP430F6724AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6724A

MSP430F6724AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6724A

MSP430F6724AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6724A

MSP430F6725AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6725A

MSP430F6725AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6725A

MSP430F6725AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6725A

MSP430F6725AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6725A

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MSP430F6726AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6726A

MSP430F6726AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6726A

MSP430F6726AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6726A

MSP430F6726AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6726A

MSP430F6730AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6730A

MSP430F6730AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6730A

MSP430F6730AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6730A

MSP430F6730AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6730A

MSP430F6731AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6731A

MSP430F6731AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6731A

MSP430F6731AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6731A

MSP430F6731AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6731A

MSP430F6733AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6733A

MSP430F6733AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6733A

MSP430F6733AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6733A

MSP430F6733AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6733A

MSP430F6734AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6734A

MSP430F6734AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6734A

MSP430F6734AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6734A

MSP430F6734AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6734A

MSP430F6735AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6735A

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MSP430F6735AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6735A

MSP430F6735AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6735A

MSP430F6735AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6735A

MSP430F6736AIPN ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6736A

MSP430F6736AIPNR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6736A

MSP430F6736AIPZ ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6736A

MSP430F6736AIPZR ACTIVE LQFP PZ 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 F6736A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 3
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F6720AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6720AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6721AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6721AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6723AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6723AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6724AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6724AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6725AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6725AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6726AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6726AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6730AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6730AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6731AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6731AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F6733AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6733AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6734AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6734AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6735AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6735AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F6736AIPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
MSP430F6736AIPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F6720AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6720AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6721AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6721AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6723AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6723AIPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F6724AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6724AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6725AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6725AIPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F6726AIPNR LQFP PN 80 1000 367.0 367.0 45.0
MSP430F6726AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6730AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6730AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6731AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6731AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6733AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6733AIPZR LQFP PZ 100 1000 350.0 350.0 43.0

Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F6734AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6734AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6735AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6735AIPZR LQFP PZ 100 1000 350.0 350.0 43.0
MSP430F6736AIPNR LQFP PN 80 1000 350.0 350.0 43.0
MSP430F6736AIPZR LQFP PZ 100 1000 350.0 350.0 43.0

Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
MSP430F6720AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6720AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6721AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6721AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6723AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6723AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6724AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6724AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6725AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6725AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6726AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6726AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6730AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6730AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6731AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6731AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6733AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95

Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW

Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
MSP430F6733AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6734AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6734AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6735AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6735AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45
MSP430F6736AIPN PN LQFP 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
MSP430F6736AIPZ PZ LQFP 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.45

Pack Materials-Page 6
PACKAGE OUTLINE
PN0080A SCALE 1.250
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

12.2
PIN 1 ID B
11.8
80 61
A

1 60

12.2 14.2
TYP
11.8 13.8

20
41

21 40

76X 0.5 0.27

80X
4X 9.5 0.17
0.08 C A B

1.6 MAX

C
(0.13) TYP
SEATING PLANE

0.08
SEE DETAIL A

0.25 (1.4)
GAGE PLANE

0.75 0.05 MIN

0 -7
0.45
DETAIL A
DETAIL A
SCALE: 14

TYPICAL
4215166/A 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.

www.ti.com
EXAMPLE BOARD LAYOUT
PN0080A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
80 61

80X (1.5)

1
60

80X (0.3)

76X (0.5) SYMM

(13.4)

(R0.05) TYP

20 41

21 40
(13.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS

4215166/A 08/2022
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com
EXAMPLE STENCIL DESIGN
PN0080A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
80 61

80X (1.5)

1
60

80X (0.3)

76X (0.5) SYMM

(13.4)
(R0.05) TYP

20 41

21 40
(13.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:6X

4215166/A 08/2022

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17
75 51

76 50

100 26 0,13 NOM

1 25
12,00 TYP Gage Plane
14,20
SQ
13,80
16,20 0,25
SQ 0,05 MIN 0°– 7°
15,80

1,45 0,75
1,35 0,45

Seating Plane

1,60 MAX 0,08

4040149 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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