BQ25731

SLUSE66A – JUNE 2020 – REVISED JANUARY 2021

BQ25731 I2C 1- to 5-Cell Buck-Boost Battery Charge Controller with USB-C PD 3.0
OTG Output
– Input, MOSFET, inductor overcurrent protection
1 Features • Package: 32-Pin 4.0 mm × 4.0 mm WQFN
• No battery MOSFET for saving cost and high
efficiency
2 Applications
• 400-kHz/800-kHz programmable switching • Cordless power tool
frequency for high efficiency/high power density • Battery pack: cordless power tool
• Buck-boost charger for USB-C Power Delivery • Appliances: battery charger, power bank
(PD) interface platform
3 Description
– 3.5-V to 26-V input range to charge 1- to 5-cell
battery The BQ25731 is a synchronous buck-boost battery
– Charge current up to 16.2 A/8.1 A with 128- charge controller to charge a 1- to 5-cell battery from
mA/64-mA resolution based on 5-mΩ/10-mΩ a wide range of input sources including USB adapter,
sensing resistor high voltage USB-C Power Delivery (PD) sources,
– Input current limit up to 10 A/6.35 A with 100- and traditional adapters. It offers a low component
mA/50-mA resolution based on 5-mΩ/10-mΩ count, high efficiency solution for space constrained,
sensing resistor 1- to 5-cell battery charging applications.
– Support USB 2.0, USB 3.0, USB 3.1 and USB During power up, the charger sets the converter to
Power Delivery (PD) a buck, boost, or buck-boost configuration based on
– Input Current Optimizer (ICO) to extract max the input source and battery conditions. The charger
input power without overloading the adapter seamlessly transits between the buck, boost, and
– Seamless transition between buck, buck-boost, buck-boost operation modes without host control.
and boost operations
– Input current and voltage regulation (IINDPM Device Information
and VINDPM) against source overload PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• TI patented switching frequency dithering pattern BQ25731 WQFN (32) 4.00 mm × 4.00 mm
for EMI noise reduction
• TI patented Pass Through Mode (PTM) for system (1) For all available packages, see the orderable addendum at
the end of the data sheet.
power efficiency improvement and battery fast
charging achieving 99% efficiency. Q2

• Input and battery current monitor through Q1 Q3 Q4

VBUS
3.5V-26V
dedicated pins HIDRV1 LODRV1 SW1 SW2 LODRV2 HIDRV2 BATT

• Integrated 8-bit ADC to monitor voltage, current

VBUS SYS (1S-5S)
ACN
BQ25731
and power ACP SRP
SRN

• Support independent comparator logic with

IIN/VIN, VBAT/ ICHG,IOTG/

CHRG_OK,IBAT, IADPT

dedicated pins
VOTG

• Power up USB port from battery (USB OTG)

– 3-V to 24-V OTG with 8-mV resolution
– Output current limit up to 12.7 A/6.35 A with
Host (I2C)

100-mA/50-mA resolution based on 5-mΩ/10- Application Diagram

mΩ sensing resistor
• I2C host control interface for flexible system
configuration
• High accuracy for the regulation and monitor
– ±0.5% Charge voltage regulation
– ±3% Charge current regulation
– ±2.5% Input current regulation
– ±2% Input/charge current monitor
• Safety
– Thermal shutdown
– Input, system, battery overvoltage protection

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 9.4 Device Functional Modes..........................................35
2 Applications..................................................................... 1 9.5 Programming............................................................ 35
3 Description.......................................................................1 9.6 Register Map.............................................................40
4 Revision History.............................................................. 2 10 Application and Implementation................................ 83
5 Description (continued).................................................. 3 10.1 Application Information........................................... 83
6 Device Comparison Table...............................................4 10.2 Typical Application.................................................. 83
7 Pin Configuration and Functions...................................5 11 Power Supply Recommendations..............................92
8 Specifications.................................................................. 8 12 Layout...........................................................................93
8.1 Absolute Maximum Ratings........................................ 8 12.1 Layout Guidelines................................................... 93
8.2 ESD Ratings............................................................... 8 12.2 Layout Example...................................................... 94
8.3 Recommended Operating Conditions.........................8 13 Device and Documentation Support..........................96
8.4 Thermal Information....................................................9 13.1 Device Support....................................................... 96
8.5 Electrical Characteristics(BQ25731)........................... 9 13.2 Documentation Support.......................................... 96
8.6 Timing Requirements................................................ 18 13.3 Support Resources................................................. 96
8.7 Typical Characteristics.............................................. 19 13.4 Trademarks............................................................. 96
9 Detailed Description......................................................22 13.5 Electrostatic Discharge Caution..............................96
9.1 Overview................................................................... 22 13.6 Glossary..................................................................96
9.2 Functional Block Diagram......................................... 23 14 Mechanical, Packaging, and Orderable
9.3 Feature Description...................................................24 Information.................................................................... 97

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (June 2020) to Revision A (January 2021) Page

• Changed from Advance Information to Production Data.................................................................................... 1

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5 Description (continued)
During power up, the charger sets the converter to a buck, boost, or buck-boost configuration based on the input
source and battery conditions. The charger seamlessly transitions between the buck, boost, and buck-boost
operation modes without host control.
In the absence of an input source, the BQ25731 supports the USB On-the-Go (OTG) function from a 1- to 5-cell
battery to generate an adjustable 3-V to 24-V output on VBUS with 8-mV resolution. The OTG output voltage
transition slew rate can be configured to comply with the USB-PD 3.0 PPS specification.
The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping
occurs in a timely fashion so that the device(s) connected to the dock can avoid experiencing momentary power
loss or glitching. This device integrates FRS in compliance with the PD specification.
TI patented switching frequency dithering pattern can significantly reduce EMI noise over the whole conductive
EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide flexibility for
different applications to simplify EMI noise filter design.
The charger can be operated in the TI patented Pass Through Mode (PTM) to improve efficiency over the full
load range. In PTM, input power is directly passed through the charger to the system. Switching losses of the
MOSFETs and inductor core loss can be saved for high efficiency operation.
The BQ25731 is available in a 32-pin 4 mm × 4 mm WQFN package.

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6 Device Comparison Table

BQ25710 BQ25713 BQ25792 BQ25731
Interface SMBus I2C I2C I2C
Device address 09h 6Bh 6Bh 6Bh
Integrated MOSFET/Controller Controller Controller Integrated MOSFET Controller
Maximum Charge Current 8.128 A 8.128 A 5A 16.256 A
Cell Count 1S~4S 1S~4S 1S~4S 1S~5S
Switching Frequency (Hz) 800 k/1.2 M 800 k/1.2 M 750 k/1.5 M 400 k/800 k
Input Current Sense Resistor 10 mΩ/20 mΩ 10 mΩ/20 mΩ Integrated 5 mΩ/10 mΩ
NA Latch/Non latch
Independent Comparator Latch Non Latch Non Latch
(default)
VSYS_UVP 2.4 V 2.4 V 2.2 V 1.6 V
OTG Voltage Range 3.0 V - 20.8 V 3.0 V - 20.8 V 2.8 V - 22 V 3.0 V - 24 V
Frequency Dithering No No No Yes
BATFET Power Path Yes Yes Yes No

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7 Pin Configuration and Functions

LODRV1

LODRV2
HIDRV1

BTST1

BTST2
REGN

PGND
SW1
32

31

30

29

28

27

26

25
VBUS 1 24 HIDRV2

ACN 2 23 SW2

ACP 3 22 VSYS

CHRG_OK 4 21 NC
Thermal
OTG/VAP/FRS 5 Pad 20 SRP

ILIM_HIZ 6 19 SRN

VDDA 7 18 CELL_BATPRESZ

IADPT 8 17 COMP2
10

12

13

14

15

16
11
9

PSYS

PROCHOT

SDA

SCL

CMPIN

CMPOUT

COMP1
IBAT

Figure 7-1. RSN Package 32-Pin WQFN Top View

Table 7-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NUMBER
Input current sense amplifier negative input. The leakage on ACP and ACN are matched. A
RC low-pass filter is required to be placed between the sense resistor and the ACN pin to
ACN 2 PWR
suppress the high frequency noise in the input current signal. Refer to Section 10.2.2.2 for
ACP/ACN filter design.
Input current sense amplifier positive input. The leakage on ACP and ACN are matched. A
RC low-pass filter is required to be placed between the sense resistor and the ACP pin to
ACP 3 PWR
suppress the high frequency noise in the input current signal. Refer to Section 10.2.2.2 for
ACP/ACN filter design.
NC 21 NA Not in use, this pin must be floating
Buck mode high-side power MOSFET driver power supply. Connect a 0.047-µF capacitor
BTST1 30 PWR
between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.
Boost mode high-side power MOSFET driver power supply. Connect a 0.047-μF capacitor
BTST2 25 PWR
between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.
Battery cell selection pin for 1- to 5- cell battery setting. CELL_BATPRESZ pin is biased from
VDDA through a resistor divider. CELL_BATPRESZ pin also sets SYSOVP thresholds to 5 V
for 1-cell, 12 V for 2-cell and 19.5 V for 3-cell/4-cell and 25V for 5s. CELL_BATPRESZ pin
CELL_BATPRESZ 18 I is pulled below VCELL_BATPRESZ_FALL to indicate battery removal. After battery is removed
the charge voltage register REG0x05/04h() goes back to default. No external cap is
allowed at CELL_BATPRESZ pin. The device exits LEARN mode and disables charge when
CELL_BATPRESZ pin is pulled low (upon battery removal).
Open drain active high indicator to inform the system good power source is connected to
the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5
V and falls below 25.8 V, CHRG_OK is HIGH after 50-ms deglitch time. When VBUS falls
CHRG_OK 4 O
below 3.2 V or rises above 26.8 V, CHRG_OK is LOW. When one of SYSOVP, SYSUVP,
ACOC, TSHUT, BATOVP, BATOC or force converter off faults occurs, CHRG_OK is asserted
LOW.

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Table 7-1. Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NUMBER
Input of independent comparator. The independent comparator compares the voltage
sensed on CMPIN pin with internal reference, and its output is on CMPOUT pin. Internal
reference, output polarity and deglitch time is selectable by the I2C host. With polarity HIGH
CMPIN 14 I
(CMP_POL = 1b), place a resistor between CMPIN and CMPOUT to program hysteresis.
With polarity LOW (CMP_POL = 0b), the internal hysteresis is 100 mV. If the independent
comparator is not in use, tie CMPIN to ground.
Open-drain output of independent comparator. Place a pullup resistor from CMPOUT to
CMPOUT 15 O pullup supply rail. Internal reference, output polarity and deglitch time are selectable by the
I2C host. If the independent comparator is not in use, float CMPOUT pin.
Buck boost converter compensation pin 2. Refer to Section 9.3.12 for COMP2 pin RC
COMP2 17 I
network.
Buck boost converter compensation pin 1. Refer to Section 9.3.12 for COMP1 pin RC
COMP1 16 I
network.
Active HIGH to enable OTG or FRS modes. 1) When OTG_VAP_MODE=1b and
OTG/VAP/FRS 5 I EN_OTG=1b, pulling high this pin can enable OTG mode. 2) When OTG_VAP_MODE=1b
and EN_FRS=1b, pulling high this pin can enable FRS mode in forward operation.
Buck mode high-side power MOSFET (Q1) driver. Connect to high-side n-channel MOSFET
HIDRV1 31 O
gate.
Boost mode high-side power MOSFET(Q4) driver. Connect to high-side n-channel MOSFET
HIDRV2 24 O
gate.
The adapter current monitoring output pin. VIADPT = 20 or 40 × (VACP – VACN) with ratio
selectable through IADPT_GAIN bit. This pin is also used to program the inductance used in
the application. Refer to Section 9.3.11 for selecting resistor from the IADPT pin to ground .
IADPT 8 O
For a 4.7-µH inductance, the resistor is 191-kΩ or 187-kΩ standard value. Place a 100-pF
or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is
clamped below 3.3 V.
The battery current monitoring output pin. VIBAT = 8 or 16 × (VSRP – VSRN) for charge
current, or VIBAT = 8 or 16 × (VSRN – VSRP) for discharge current, with ratio selectable
IBAT 9 O
through IBAT_GAIN bit. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin
to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.
Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider
from VDDA rail to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM ×
Rac, in which IDPM is the target input current limit.
When EN_EXTILIM = 1b the input current limit used by the charger is the lower setting of
ILIM_HIZ pin and IIN_HOST register. When EN_EXTILIM = 0b input current limit is only
ILIM_HIZ 6 I determined by IIN_HOST register.
When the pin voltage is below 0.4 V, the device enters high impedance (HIZ) mode with
low quiescent current. When the pin voltage is above 0.8 V, the device is out of HIZ mode.
The ILIM_HIZ pin voltage is continuous read and used for updating current limit setting (If
EN_EXTILIM=1b ), this allows dynamic change input current limit setting by adjusting this pin
voltage.
Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET
LODRV1 29 O
gate.
Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET
LODRV2 26 O
gate.
PGND 27 GND Device power ground.
Active low open drain output indicator. It monitors adapter input current, battery discharge
PROCHOT 11 O current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is
asserted. The minimum pulse width is adjustable through PROCHOT_WIDTH bits.
Current mode system power monitor. The output current is proportional to the total power
from the adapter and the battery. The gain is selectable through I2C. Place a resistor from
PSYS 10 O
PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output
voltage is clamped at 3.3 V. Place a capacitor in parallel with the resistor for filtering.
6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS
REGN 28 PWR above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power
ground. REGN pin output is for power stage gate drive.

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Table 7-1. Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NUMBER
I2C clock input. Connect to clock line from the host controller or smart battery. Connect a
SCL 13 I
10-kΩ pullup resistor according to specifications.
I2C open-drain data I/O. Connect to data line from the host controller or smart battery.
SDA 12 I/O
Connect a 10-kΩ pullup resistor according to I2C specifications.
Charge current sense amplifier negative input. SRN pin is for battery voltage sensing as
well. Connect a 0.1-μF filter cap cross battery charging sensing resistor and use 10-Ω
SRN 19 PWR
contact resistor between SRN pin and battery charging sensing resistor. The leakage current
on SRP and SRN are matched.
Charge current sense amplifier positive input. Connect a 0.1-μF filter cap cross battery
SRP 20 PWR charging sensing resistor and use 10-Ω contact resistor between SRP pin and battery
charging sensing resistor. The leakage current on SRP and SRN are matched.
Buck mode switching node. Connect to the source of the buck half bridge high side n-
SW1 32 PWR
channel MOSFET.
Boost mode switching node. Connect to the source of the boost half bridge high side
SW2 23 PWR
n-channel MOSFET.
Charger input voltage. An input low pass filter of 1 Ω and 0.47 µF (minimum) is
VBUS 1 PWR
recommended.
Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF
VDDA 7 PWR
ceramic capacitor from VDDA to power ground.
VSYS 22 PWR Charger system voltage sensing.
Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on
Thermal pad – – the thermal pad plane connecting to power ground planes. It serves as a thermal pad to
dissipate the heat.

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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
SRN, SRP, ACN, ACP, VBUS, VSYS –0.3 32
SW1, SW2 –2 32
BTST1, BTST2, HIDRV1, HIDRV2, –0.3 38
LODRV1, LODRV2 (25nS) –4 7
HIDRV1, HIDRV2 (25nS) –4 38
Voltage V
SW1, SW2 (25nS) –4 32
SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,
LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/ –0.3 7
FRS,
PROCHOT –0.3 5.5
IADPT, IBAT, COMP1 –0.3 3.6

Differential BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2 –0.3 7

V
Voltage SRP-SRN, ACP-ACN –0.5 0.5
Temperature Junction temperature range, TJ –40 150
°C
Temperature Storage temperature, Tstg –55 150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±500
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
ACN, ACP, VBUS 0 26
SRN, SRP, VSYS 0 23.15
SW1, SW2 –2 26
BTST1, BTST2, HIDRV1, HIDRV2, 0 32
Voltage V
SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,
0 6.5
LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/FRS
PROCHOT 0 5.3
IADPT, IBAT, COMP1 0 3.3
BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2 0 6.5
Differential
SRP-SRN, ACP-ACN –0.5 0.5 V
Voltage
BATDRV-VSYS 0 10.8

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8.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Junction temperature range, TJ –20 125
Temperature °C
Storage temperature, Tstg –20 85

8.4 Thermal Information

BQ25731
THERMAL METRIC(1) RSN (WQFN) UNIT
32 PINS
RθJA Junction-to-ambient thermal resistance (JEDEC(1)) 37.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26.1 °C/W
RθJB Junction-to-board thermal resistance 7.8 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 7.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

8.5 Electrical Characteristics(BQ25731)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage
VINPUT_OP 3.5 26 V
operating range
CHARGE VOLTAGE REGULATION
Battery voltage
VBAT_RNG 1.024 23.00 V
regulation
Battery voltage 21 V
VBAT_REG_ACC regulation accuracy REG0x05/04() = 0x5208H
(0°C to 85°C) –0.5% 0.5%

16.8 V
REG0x05/04() = 0x41A0H
–0.5% 0.5%
12.6 V
REG0x05/04() = 0x3138H
Battery voltage –0.5% 0.5%
VBAT_REG_ACC regulation accuracy
(0°C to 85°C) 8.4 V
REG0x05/04() = 0x20D0H
–0.6% 0.6%
4.2 V
REG0x05/04() = 0x1068H
–1.1% 1.45%
CHARGE CURRENT REGULATION IN FAST CHARGE
Charge current
VIREG_CHG_RNG regulation differential VIREG_CHG = VSRP – VSRN 0 81.28 mV
voltage range

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
8192 mA
REG0x03/02() = 0x1000H
–3.0% 3.0%
Charge current 4096 mA
regulation accuracy REG0x03/02() = 0x0800H
5-mΩ RSR sensing –5.0% 6.0%
ICHRG_REG_ACC
resistor, VBAT above 2048 mA
VSYS_MIN(0°C to REG0x03/02() = 0x0400H
85°C) –12% 13.5%
1024 mA
REG0x03/02() = 0x0200H
–18% 21.5%
CHARGE CURRENT REGULATION IN LOW BATTERY VOLTAGE
CELL(≥2 S),VSRN < VSYS_MIN 384 mA
current clamp under
ICLAMP CELL 1 S, VSRN < 3 V 384 mA
low battery voltage
CELL 1 S, 3 V < VSRN < 3.6V 2 A
SRP, SRN leakage
ILEAK_SRP_SRN current mismatch –13.5 10.0 µA
(0°C to 85°C)
INPUT CURRENT REGULATION
Input current
regulation differential
VIREG_DPM_RNG voltage range with VIREG_DPM = VACP – VACN 0.5 64 mV
10-mΩ RAC sensing
resistor
Input current REG0x0F/0E() = 0x4E00H 7600 7800 8000 mA
regulation accuracy REG0x0F/0E() = 0x3A00H 5600 5800 6000 mA
IIIN_DPM_REG_ACC (-40°C to 105°C) with
5-mΩ RAC sensing REG0x0F/0E() = 0x1C00H 2600 2800 3000 mA
resistor REG0x0F/0E() = 0x0800H 600 800 1000 mA
ACP, ACN leakage
ILEAK_ACP_ACN –16 10 µA
current mismatch
Voltage range
for input current
VIREG_DPM_RNG_ILIM 1.15 4 V
regulation (ILIM_HIZ
Pin)
Input Current VILIM_HIZ = 2.6 V 7600 8000 8400 mA
Regulation Accuracy
VILIM_HIZ = 2.2 V 5600 6000 6400 mA
on ILIM_HIZ pin
IIIN_DPM_REG_ACC_ILIM VILIM_HIZ = 1 V + 40 VILIM_HIZ = 1.6 V 2600 3000 3400 mA
× IDPM × RAC, with
5-mΩ RAC sensing VILIM_HIZ = 1.2 V 600 1000 1400 mA
resistor
ILIM_HIZ pin leakage
ILEAK_ILIM –1 1 µA
current
INPUT VOLTAGE REGULATION
Input voltage
VDPM_RNG Voltage on VBUS 3.2 19.52 V
regulation range
REG0x0B/0A()=0x3C80H 18688 mV
–3.5% 2%

Input voltage REG0x0B/0A()=0x1E00H 10880 mV

VDPM_REG_ACC
regulation accuracy –4.5% 3%
REG0x0B/0A()=0x0500H 4480 mV
–8% 5.5%
OTG CURRENT REGULATION

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OTG output current
VIOTG_REG_RNG regulation differential VIOTG_REG = VACP – VACN 0 81.28 mV
voltage range
OTG output current REG0x09/08() = 0x3C00H 5600 6000 6400 mA
regulation accuracy
REG0x09/08() = 0x1E00H 2600 3000 3400 mA
IOTG_ACC with 100-mA LSB
and 5-mΩ ACP/ACN
REG0x09/08() = 0x0A00H 600 1000 1400 mA
series resistor
OTG VOLTAGE REGULATION
OTG voltage
VOTG_REG_RNG regulation range(OOA Voltage on VBUS 3 24.00 V
disabled)
REG0x07/06()=0x2CECH 23.00 V
–2% 2%
OTG voltage
regulation REG0x07/06()=0x1770H 12.00 V
VOTG_REG_ACC
accuracy(OOA –2% 2%
disabled)
REG0x07/06()=0x09C4H 5.00 V
–4% 3.5%
REGN REGULATOR
REGN regulator
VREGN_REG voltage (0 mA – 60 VVBUS = 10 V 5.7 6 6.3 V
mA)
REGN voltage in drop
VDROPOUT VVBUS = 5 V, ILOAD = 20 mA 3.8 4.3 4.6 V
out mode
REGN current limit
IREGN_LIM when converter is VVBUS = 10 V, force VREGN =4 V 50 65 mA
enabled
QUIESCENT CURRENT
VBAT = 18 V, REG0x01[7] = 1,REG0x31[6] = 0b, in
22 45 µA
low-power mode, Disable PSYS
VBAT = 18 V, REG0x01[7] = 1, REG0x31[6] =
System powered by 1b, REG0x31[5:4] = 11b,REGN off, Disable PSYS, 35 60 µA
battery. . ISRN + ISRP + Enable low power PROCHOT
IBAT__ON ISW2 + IBTST2 + ISW1 +
IBTST1 + IACP + IACN + VBAT = 18 V, REG0x01[7]= 0,REG0x31[5:4]= 11b,
880 1170 µA
IVBUS + IVSYS REGN on, Disable PSYS, In performance mode
VBAT = 18 V, REG0x01[7] = 0, REG0x31[5:4]
= 00b, REGN on, Enable PSYS, In performance 980 1270 µA
mode
Input current during
PFM in buck mode,
no load, IVBUS + IACP VIN = 20 V, VBAT = 12.6 V, 3s, REG0x01[2] = 0;
IAC_SW_LIGHT_buck 2.2 mA
+ IACN + IVSYS + ISRP MOSFET Qg = 4 nC
+ ISRN + ISW1 + IBTST
+ ISW2 + IBTST2
Input current during
PFM in boost mode,
no load, IVBUS + IACP VIN = 5 V, VBAT = 8.4 V, 2s, REG0x01[2] = 0;
IAC_SW_LIGHT_boost 2.7 mA
+ IACN + IVSYS + ISRP MOSFET Qg = 4 nC
+ ISRN + ISW1 + IBTST2
+ ISW2 + IBTST2

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input current during
PFM in buck boost
mode, no load, IVBUS VIN = 12 V, VBAT = 12 V, REG0x01[2] = 0;
IAC_SW_LIGHT_buckboost 2.4 mA
+ IACP + IACN + IVSYS MOSFET Qg = 4 nC
+ ISRP + ISRN + ISW1 +
IBTST1 + ISW2 + IBTST2
Quiescent current VBAT = 8.4 V, VBUS = 5 V, 800 kHz switching
3 mA
during PFM in OTG frequency, MOSFET Qg = 4nC
mode, EN_OOA=0b,
VBAT = 8.4 V, VBUS = 12 V, 800 kHz switching
IOTG_STANDBY IVBUS + IACP + IACN + 4.2 mA
frequency, MOSFET Qg = 4nC
IVSYS + ISRP + ISRN +
ISW1 + IBTST2 + ISW2 + VBAT = 8.4 V, VBUS = 20 V, 800 kHz switching
6.2 mA
IBTST2 frequency, MOSFET Qg = 4nC
CURRENT SENSE AMPLIFIER
Input common mode
VACP_ACN_OP Voltage on ACP/ACN 3.8 26 V
range
IADPT output clamp
VIADPT_CLAMP 3.1 3.2 3.3 V
voltage
IIADPT IADPT output current 1 mA

Input current sensing V(IADPT) / V(ACP-ACN), REG0x00[4] = 0 20 V/V

AIADPT
gain V(IADPT) / V(ACP-ACN), REG0x00[4] = 1 40 V/V
V(ACP-ACN) = 40.96 mV –2% 2%

Input current monitor V(ACP-ACN) = 20.48 mV –3% 3%

VIADPT_ACC
accuracy V(ACP-ACN) =10.24 mV –6% 6%
V(ACP-ACN) = 5.12 mV –10% 10%
Maximum
CIADPT_MAX capacitance at IADPT 100 pF
Pin
Battery common
VSRP_SRN_OP Voltage on SRP/SRN 2.5 23.15 V
mode range
IBAT output clamp
VIBAT_CLAMP 3.05 3.2 3.3 V
voltage
IIBAT IBAT output current 1 mA
Charge and V(IBAT) / V(SRN-SRP), REG0x00[3] = 0, 8 V/V
discharge current
AIBAT
sensing gain on IBAT V(IBAT) / V(SRN-SRP), REG0x00[3] = 1, 16 V/V
pin
V(SRN-SRP) = 40.96 mV –2% 2%
Charge and
discharge current V(SRN-SRP) = 20.48 mV –4% 4%
IIBAT_CHG_ACC
monitor accuracy on V(SRN-SRP) =10.24 mV –7% 7%
IBAT pin
V(SRN-SRP) = 5.12 mV –15% 15%
Maximum
CIBAT_MAX capacitance at IBAT 100 pF
Pin
SYSTEM POWER SENSE AMPLIFIER
PSYS output voltage
VPSYS 0 3.3 V
range
IPSYS PSYS output current 0 160 µA
I(PSYS) / (P(IN) +P(BAT)), REG0x31[5:4] =
APSYS PSYS system gain 1 µA/W
00b;REG0x31[1] = 1b
APSYS PSYS system gain I(PSYS) / P(IN), REG0x31[5:4]= 01b;REG0x31[1] = 1b 1 µA/W

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Adapter only with system power = 19.5 V / 45 W, TA
PSYS gain accuracy –4% 4%
= 0 to 85°C
(REG0x30[13:12] =
00b) Battery only with system power = 11 V / 44 W, TA =
–3% 3%
VPSYS_ACC 0 to 85°C
PSYS gain accuracy
Adapter only with system power = 19.5 V / 45 W, TA
(REG0x30[13:12] = –4% 4%
= 0 to 85°C
01b)
VPSYS_CLAMP PSYS clamp voltage 3 3.3 V
VSYS UNDER VOLTAGE LOCKOUT COMPARATOR
VSYS undervoltage
VSYS_UVLOZ VSYS rising 1.5 1.7 1.85 V
rising threshold(≥1S)
VSYS undervoltage
VSYS_UVLO VSYS falling 1.4 1.6 1.75 V
falling threshold(≥1S)
VSYS undervoltage
VSYS_UVLO_HYST 100 mV
hysteresis(≥1S)
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
VBUS undervoltage
VVBUS_UVLOZ VBUS rising 2.35 2.55 2.80 V
rising threshold
VBUS undervoltage
VVBUS_UVLO VBUS falling 2.2 2.4 2.6 V
falling threshold
VBUS undervoltage
VVBUS_UVLO_HYST 150 mV
hysteresis
VBUS converter
VVBUS_CONVEN enable rising VBUS rising 3.2 3.5 3.9 V
threshold
VBUS converter
VVBUS_CONVENZ enable falling VBUS falling 2.9 3.2 3.5 V
threshold
VBUS converter
VVBUS_CONVEN_HYST 300 mV
enable hysteresis
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
VBAT undervoltage
VVBAT_UVLOZ VSRN rising 2.35 2.55 2.80 V
rising threshold
VBAT undervoltage
VVBAT_UVLO VSRN falling 2.2 2.4 2.6 V
falling threshold
VBAT undervoltage
VVBAT_UVLO_HYST 150 mV
hysteresis
VBAT OTG enable
VVBAT_OTGEN VSRN rising 3.25 3.55 3.85 V
rising threshold
VBAT OTG enable
VVBAT_OTGENZ VSRN falling 2.15 2.4 2.65 V
falling threshold
VBAT OTG enable
VVBAT_OTGEN_HYST 1150 mV
hysteresis
VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)
VBUS undervoltage
VVBUS_OTG_UV As percentage of REG0x07/06() 85%
falling threshold
VBUS time
tVBUS_OTG_UV 7 ms
undervoltage deglitch
VBUS OVER VOLTAGE COMPARATOR (OTG MODE)
VBUS overvoltage
VVBUS_OTG_OV As percentage of REG0x07/06() 110%
rising threshold

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBUS Time
tVBUS_OTG_OV 10 ms
Overvoltage Deglitch
BATTERY LOW VOLTAGE COMPARATOR (Charge current 384mA clamp corresponding battery voltage threshold for 1S)
BATLOWV falling
VBATLV_FALL 2.8 V
threshold
BATLOWV rising
VBATLV_RISE 3 V
threshold
VBATLV_RHYST BATLOWV hysteresis 200 mV
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VBUS overvoltage
VVBUSOV_RISE VBUS rising 26.0 26.8 27.7 V
rising threshold
VBUS overvoltage
VVBUSOV_FALL VBUS falling 25.0 25.8 26.7 V
falling threshold
VBUS overvoltage
VVBUSOV_HYST 1.0 V
hysteresis
VBUS deglitch
tVBUSOV_RISE_DEG VBUS converter rising to stop converter 100 us
overvoltage rising
VBUS deglitch
tVBUSOV_FALL_DEG VBUS converter falling to start converter 1 ms
overvoltage falling
INPUT OVER CURRENT COMPARATOR (ACOC)
ACP to ACN
Voltage across input sense resistor rising,
VACOC rising threshold, w.r.t. 180% 200% 220%
Reg0x32[2]= 1
ILIM2_VTH
Measure between
VACOC_FLOOR Set IIN_DPM to minimum 44 50 56 mV
ACP and ACN
Measure between
VACOC_CEILING Set IIN_DPM to maximum 172 180 188 mV
ACP and ACN
tACOC_DEG_RISE Rising deglitch time Deglitch time to trigger ACOC 250 us
tACOC_RELAX Relax time Relax time before converter starts again 250 ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
1s 5.8 6 6.1 V
2s 11.7 12 12.2 V
System overvoltage
VSYSOVP_RISE rising threshold to 3s 19 19.5 20 V
turnoff converter
4s 19 19.5 20 V
5s 24 25 26 V
1s 5.5 V
2s 11.7 V
System overvoltage
VSYSOVP_FALL 3s 19.3 V
falling threshold
4s 19.3 V
5s 24.5 V
Discharge current
when SYSOVP
ISYSOVP on VSYS pin 20 mA
stop switching was
triggered
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
Overvoltage rising 1s 102.3% 104% 106%
threshold as
VBATOVP_RISE percentage of
VBAT_REG in ≥2 s 102.3% 104% 105%
REG0x05/04h()

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overvoltage falling 1s 100% 102% 104%
threshold as
VBATOVP_FALL percentage of
VBAT_REG in ≥2 s 100% 102% 103%
REG0x05/04h()
Overvoltage 1s 2%
hysteresis as
VBATOVP_HYST percentage of
VBAT_REG in ≥2 s 2%
REG0x05/04h()
Discharge current
IBATOVP Discharge current through VSYS pin 20 mA
during BATOVP
CONVERTER OVER-CURRENT COMPARATOR (Q2)
Converter Over- Reg0x32[5]=1b 150 mV
Current Limit across
VOCP_lim_Q2
Q2 MOSFET drain to Reg0x32[5]=0b 210 mV
source voltage

System Short or SRN Reg0x32[5]=1b 45 mV

VOCP_lim_SYSSHRT_Q2
< 2.4 V Reg0x32[5]=0b 60 mV
CONVERTER OVER-CURRENT COMPARATOR (ACX)
Converter Over- Reg0x32[4]=1b; RSNS_RAC=0b 150 mV
Current Limit across Reg0x32[4]=1b; RSNS_RAC=1b 100 mV
VOCP_lim_ACX ACP-ACN input
current sensing Reg0x32[4]=0b;RSNS_RAC=0b 280 mV
resistor Reg0x32[4]=0b; RSNS_RAC=1b 200 mV
Reg0x32[4]=1b;RSNS_RAC=0b 90 mV

System Short or SRN Reg0x32[4]=1b;RSNS_RAC=1b 60 mV

VOCP_lim_SYSSHRT_ACX
< 2.4 V Reg0x32[4]=0b;RSNS_RAC=0b 150 mV
Reg0x32[4]=0b;RSNS_RAC=1b 120 mV
THERMAL SHUTDOWN COMPARATOR
Thermal shutdown
TSHUT_RISE Temperature increasing 155 °C
rising temperature
Thermal shutdown
TSHUTF_FALL Temperature reducing 135 °C
falling temperature
Thermal shutdown
TSHUT_HYS 20 °C
hysteresis
Thermal deglitch
tSHUT_RDEG 100 us
shutdown rising
Thermal deglitch
tSHUT_FHYS 12 ms
shutdown falling
ICRIT PROCHOT COMPARATOR
Input current rising
threshold for throttling
IICRIT_PRO Only when ILIM2 setting is higher than 2A 105% 110% 117%
as 10% above
ILIM2_VTH
INOM PROCHOT COMPARATOR
INOM rising threshold
IINOM_PRO as 10% above 105% 110% 116%
IIN_DPM
BATTERY DISCHARGE CURRENT LIMIT PROCHOT COMPARATOR(IDCHG)

IDCHG threshold1 for Reg0x39[7:2]=010000b, with 5mΩ SRP/SRN 16.384 A

IDCHG_TH1
throttling CPU current sensing resistor 96% 103%

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDCHG threshold1
IDCHG_DEG1 Reg0x39h[1:0]=01b 1.25 sec
deglitch time
IDCHG threshold2 for 24.567 A
Reg0x39[7:2]=010000b 3C[5:3]=001b,with 5mΩ
IDCHG_TH2 throttling for IDSCHG
SRP/SRN current sensing resistor 96% 103%
of 6 A
IDCHG threshold2
tDCHG_DEG2 Reg0x3C[7:6]=01b 1.6 ms
deglitch time
INDEPENDENT COMPARATOR

Independent Reg0x30h[7]= 1, CMPIN falling 1.17 1.2 1.23 V

VINDEP_CMP
comparator threshold Reg0x30h[7]= 0, CMPIN falling 2.27 2.3 2.33 V
Independent
VINDEP_CMP_HYS comparator CMPIN falling 100 mV
hysteresis
POWER MOSFET DRIVER
PWM OSCILLATOR AND RAMP

PWM switching Reg0x01[1] = 0 680 800 920 kHz

FSW
frequency Reg0x01[1] = 1 340 400 460 kHz
PWM HIGH SIDE DRIVER (HIDRV Q1)
The resistance of the
RDS_HI_ON_Q1 gate driver loop for VBTST1 - VSW1 = 5 V 6 Ω
turning on Q1
The resistance of the
RDS_HI_OFF_Q1 gate driver loop for VBTST1 - VSW1 = 5 V 1.3 2.2 Ω
turning off Q1
Bootstrap refresh
VBTST1 - VSW1 when low-side refresh pulse is
VBTST1_REFRESH comparator falling 3.2 3.7 4.6 V
requested
threshold voltage
PWM HIGH SIDE DRIVER (HIDRV Q4)
The resistance of the
RDS_HI_ON_Q4 gate driver loop for VBTST2 - VSW2 = 5 V 6 Ω
turning on Q4
The resistance of the
RDS_HI_OFF_Q4 gate driver loop for VBTST2 - VSW2 = 5 V 1.5 2.4 Ω
turning off Q4
Bootstrap refresh
VBTST2 - VSW2 when low-side refresh pulse is
VBTST2_REFRESH comparator falling 3.3 3.7 4.6 V
requested
threshold voltage
PWM LOW SIDE DRIVER (LODRV Q2)
The resistance of the
RDS_LO_ON_Q2 gate driver loop for VBTST1 - VSW1 = 5.5 V 6 Ω
turning on Q2
The resistance of the
RDS_LO_OFF_Q2 gate driver loop for VBTST1 - VSW1 = 5.5 V 1.7 2.6 Ω
turning off Q2
PWM LOW SIDE DRIVER (LODRV Q3)
The resistance of the
RDS_LO_ON_Q3 gate driver loop for VBTST2 - VSW2 = 5.5 V 6.8 Ω
turning on Q3
The resistance of the
RDS_LO_OFF_Q3 gate driver loop for VBTST2 - VSW2 = 5.5 V 2.2 4.6 Ω
turning off Q3
INTERNAL SOFT START During Charge Enable

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Charge current soft-
SSSTEP_SIZE 64 mA
start step size
Charge current soft-
SSSTEP_TIME start duration time for 8 us
each step
INTEGRATED BTST DIODE (D1)
VF_D1 Forward bias voltage IF = 20 mA at 25°C 0.8 V
Reverse breakdown
VR_D1 IR = 2 µA at 25°C 20 V
voltage
INTEGRATED BTST DIODE (D2)
VF_D2 Forward bias voltage IF = 20 mA at 25°C 0.8 V
Reverse breakdown
VR_D2 IR = 2 µA at 25°C 20 V
voltage
INTERFACE
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold I2C 0.4 V
VIN_ HI Input high threshold I2C 1.3 V
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
Output saturation
VOUT_ LO 5 mA drain current 0.4 V
voltage
VOUT_ LEAK Leakage current Voltage = 7 V –1 1 µA
LOGIC INPUT (OTG/VAP/FRS pin)
VIN_ LO_OTG Input low threshold 0.4 V
VIN_ HI_OTG Input high threshold 1.3 V
LOGIC OUTPUT OPEN DRAIN SDA
Output Saturation
VOUT_ LO_SDA 5 mA drain current 0.4 V
Voltage
VOUT_ LEAK_SDA Leakage Current Voltage = 7 V –1 1 µA
LOGIC OUTPUT OPEN DRAIN CHRG_OK
Output Saturation
VOUT_ LO_CHRG_OK 5 mA drain current 0.4 V
Voltage
VOUT_ LEAK _CHRG_OK Leakage Current Voltage = 7 V –1 1 µA
LOGIC OUTPUT OPEN DRAIN CMPOUT
Output Saturation
VOUT_ LO_CMPOUT 5 mA drain current 0.4 V
Voltage
VOUT_ LEAK _CMPOUT Leakage Current Voltage = 7 V –1 1 µA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
Output saturation
VOUT_ LO_PROCHOT 50 Ω pullup to 1.05 V / 5-mA 300 mV
voltage
VOUT_ LEAK_PROCHOT Leakage current Voltage = 5.5 V –1 1 µA
ANALOG INPUT (ILIM_HIZ)
Voltage to get out of
VHIZ_ LO ILIM_HIZ pin rising 0.8 V
HIZ mode
Voltage to enable HIZ
VHIZ_ HIGH ILIM_HIZ pin falling 0.4 V
mode
ANALOG INPUT (CELL_BATPRESZ)
CELL_BATPRESZ pin voltage as percentage of
VCELL_5S 5s 90% 100%
REGN = 6 V

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8.5 Electrical Characteristics(BQ25731) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CELL_BATPRESZ pin voltage as percentage of
VCELL_4S 4s setting 68.4% 75% 81.5%
REGN = 6 V
CELL_BATPRESZ pin voltage as percentage of
VCELL_3S 3s setting 51.7% 55% 65%
REGN = 6 V
CELL_BATPRESZ pin voltage as percentage of
VCELL_2S 2s setting 35% 40% 48.5%
REGN = 6 V
CELL_BATPRESZ pin voltage as percentage of
VCELL_1S 1s setting 18.4% 25% 31.6%
REGN = 6 V
VCELL_BATPRESZ_RISE Battery is present CELL_BATPRESZ rising 18%
VCELL_BATPRESZ_FALL Battery is removed CELL_BATPRESZ falling 15%
ANALOG INPUT (COMP1, COMP2)
ILEAK_COMP1 COMP1 Leakage –120 120 nA
ILEAK_COMP2 COMP2 Leakage –120 120 nA

8.6 Timing Requirements

MIN NOM MAX UNIT
I2C TIMING CHARACTERISTICS
tr SCL/SDA rise time 300 ns
tf SCL/SDA fall time 300 ns
tHIGH SCL pulse width high 0.6 50 µs
tLOW SCL pulse width low 1.3 µs
tSU:STA Setup time for START condition 0.6 µs
tHD:STA Start condition hold time after which first clock pulse is generated 0.6 µs
tSU:DAT Data setup time 100 ns
tHD:DAT Data hold time 300 ns
tSU:STO Set up time for STOP condition 0.6 µs
tBUF Bus free time between START and STOP conditions 1.3 µs
fSCL Clock frequency 10 400 kHz
HOST COMMUNICATION FAILURE
tTIMEOUT I2C bus release timeout(1) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
Watchdog timeout period, REG0x01[6:5]=01 4 5.5 7 s
tWDI Watchdog timeout period, REG0x01[6:5]=10 70 88 105 s
Watchdog timeout period, REG0x01[6:5]=11 140 175 210 s

(1) Devices participating in a transfer timeout when any clock low exceeds the 25-ms minimum timeout period. Devices that have detected
a timeout condition must reset the communication no later than the 35-ms maximum timeout period. Both a host and a target must
adhere to the maximum value specified because it incorporates the cumulative stretch limit for both a host (10 ms) and a target (25
ms).

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8.7 Typical Characteristics

100 100

98 98

96 96

94 94
Efficiency(%)

Efficiency(%)
92 92

90 90

88 88
VOUT=3.7V VOUT=3.7V
86 VOUT=7.4V 86 VOUT=7.4V
VOUT=11.1V VOUT=11.1V
84 VOUT=14.8V 84 VOUT=14.8V
VOUT=18.5V VOUT=18.5V
82 82
0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current(A) Output Current(A)
VIN = 5 V CCM VOUT=Battery Voltage VIN = 9 V CCM VOUT=Battery Voltage
Fs=400kHz Fs=400kHz
RAC=5mΩ RSR=5mΩ Inductance=4.7uH RAC=5mΩ RSR=5mΩ Inductance=4.7uH
Figure 8-1. Charge Efficiency Figure 8-2. Charge Efficiency
100 100

98 98

96 96

94 94
Efficiency(%)

Efficiency(%)

92 92

90 90

88 88
VOUT=3.7V VOUT=3.7V
86 VOUT=7.4V 86 VOUT=7.4V
VOUT=11.1V VOUT=11.1V
84 VOUT=14.8V 84 VOUT=14.8V
VOUT=18.5V VOUT=18.5V
82 82
0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12
Output Current(A) Output Current(A)
VIN = 15 V CCM VOUT=Battery Voltage VIN = 20 V CCM VOUT=Battery Voltage
Fs=400kHz Fs=400kHz
RAC=5mΩ RSR=5mΩ Inductance=4.7uH RAC=5mΩ RSR=5mΩ Inductance=4.7uH
Figure 8-3. Charge Efficiency Figure 8-4. Charge Efficiency

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8.7 Typical Characteristics (continued)

100 100

98 98

96 96

94 94
Efficiency(%)

Efficiency(%)
92 92

90 90

88 88
VOUT=3.7V
86 VOUT=7.4V 86 VOTG=5V
VOUT=11.1V VOTG=9V
84 VOUT=14.8V 84 VOTG=15V
VOUT=18.5V VOTG=20V
82 82
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Output Current(A) Output Current(A)
PTM Mode VOUT=Battery Voltage VBAT= 4 V CCM Fs=400kHz
RAC=5mΩ RSR=5mΩ Inductance=4.7uH RAC=5mΩ RSR=5mΩ Inductance=4.7uH
Figure 8-5. PTM Mode Charge Efficiency Figure 8-6. OTG Efficiency with 1S Battery
100 100

98 98

96 96

94 94
Efficiency(%)

Efficiency(%)

92 92

90 90

88 88

86 VOTG=5V 86 VOTG=5V
VOTG=9V VOTG=9V
84 VOTG=15V 84 VOTG=15V
VOTG=20V VOTG=20V
82 82
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Output Current(A) Output Current(A)
VBAT= 8 V CCM Fs=400kHz VBAT= 12 V CCM Fs=400kHz
RAC=5mΩ RSR=5mΩ Inductance=4.7uH RAC=5mΩ RSR=5mΩ Inductance=4.7uH
Figure 8-7. OTG Efficiency with 2S Battery Figure 8-8. OTG Efficiency with 3S Battery

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8.7 Typical Characteristics (continued)

100 100

98 98

96 96

94 94
Efficiency(%)

Efficiency(%)
92 92

90 90

88 88

86 VOTG=5V 86 VOTG=5V
VOTG=9V VOTG=9V
84 VOTG=15V 84 VOTG=15V
VOTG=20V VOTG=20V
82 82
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Output Current(A) Output Current(A)
VBAT= 16 V CCM Fs=400kHz VBAT= 20 V CCM Fs=400kHz
RAC=5mΩ RSR=5mΩ Inductance=4.7uH RAC=5mΩ RSR=5mΩ Inductance=4.7uH
Figure 8-9. OTG Efficiency with 4S Battery Figure 8-10. OTG Efficiency with 5S Battery

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9 Detailed Description
9.1 Overview
The BQ25731 is a buck-boost charger controller for cordless power tools, power banks, and other appliances
with rechargeable batteries. It provides seamless transition between different converter operation modes (buck,
boost, or buck-boost), fast transient response, and high light load efficiency.
The BQ25731 supports a wide range of power sources, including USB-C PD ports, legacy USB ports, traditional
AC-DC adapters, and so forth. It takes input voltage from 3.5 V to 26 V and charges a battery of 1 to 5 cells in
series. In the absence of an input source, the BQ25731 supports the USB On-the-Go (OTG) function from a 1- to
5-cell battery to generate an adjustable 3 V to 24 V at the USB port with 8-mV resolution.
The BQ25731 features Dynamic Power Management (DPM) to limit input power and avoid AC adapter
overloading. During battery charging, as system power increases, charging current is reduced to maintain total
input current below adapter rating.
The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping
occurs in a timely fashion so that the device(s) connected to the dock never experience momentary power loss
or glitching. The device integrates FRS with compliance to the USB-C PD specification.
The TI patented switching frequency dithering pattern can significantly reduce EMI noise over the entire
conductive EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide
flexibility for different applications to simplify EMI noise filter design.
The I2C host controls input current, charge current, and charge voltage registers with high resolution, high
accuracy regulation limits.

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9.2 Functional Block Diagram

CHRG_OK 4
CHRG_OK_DRV 50ms Rising
Deglitch
Block Diagram
** programmable in register
50ms Rising EN_REGN
Deglitch
3.5V

VBUS 1 VREF_CMP**
CMP_DEG**
ACOV
14 CMPIN
26.8V 15 CMPOUT

VREF_VINDPM or VREF_VOTG
COMP1
VDDA VSNS_VINDPM or VSYS_VOTG
16

EN_HIZ 17
COMP2
ILIM_HIZ
6 Decoder VREF_ILIM
VREF_IIN_DPM, or VREF_IOTG

ACP 2 VSNS_IIN_DPM, or VSNS_IOTG

20X/40X
ACN 3

20X/40X 30 BTST1
IADPT VSNS_IOTG 31 HIDRV1
8 VSNS_IIN Loop Selector
VSNS_ICHG and
IBAT 32 SW1
9 VSNS_IDCHG Error Amplier
PWM VDDA
7
16X/8X
VREF_ICHG
EN_REGN REGN REGN
28
LDO
EN_HIZ
SRP 20 VSNS_ICHG
16X/8X EN_LEARN
SRN 19 EN_LDO
EN_CHRG
VREF_VBAT PWM 29 LODRV1
EN_OTG
Driver
VSNS_VBAT Logic 27 PGND
VSYS 22 VREF_VSYS
25 BTST2
VSNS_VSYS
24 HIDRV2

23 SW2
VSNS_VSYS
ACN VSNS_VBAT
PSYS (ACP-ACN) VSNS_ICHG Over Current
10 SRN
VSNS_IDCHG Over Voltage
(SRN-SRP) VSNS_IIN_DPM Detect 26 LODRV2
VSNS_VINDPM

EN_HIZ
I2C
EN_LEARN
Interface BATPRESZ
SDA 12 EN_LDO
ChargeOp
on0() Decoder
EN_CHRG CELL_CONFIG 18 CELL_BATPRESZ
ChargeOp on1() EN_OTG
ChargeOpon2()
ChargeCurrent() VREF_VSYS
SCL 13
ChargeVoltage() VREF_VBAT
VREF_ICHG
InputCurrent() Loop
VREF_IIN_DPM IADPT
OTG/VAP/FRS 5 InputVoltage() Regulaon VREF_VINDPM IBAT Processor
MinSysVoltage() Reference Hot 11 PROCHOT
VREF_IOTG VSYS
OTGVoltage() VREF_VOTG CHRG_OK
OTGCurrent()

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9.3 Feature Description

9.3.1 Power-Up Sequence
The device powers up from the higher voltage of VBUS or VBAT through integrated power selector. The charger
starts POR (power on reset) when VBUS exceeds VVBUS_UVLOZ or VBAT exceeds VVBAT_UVLOZ. 5 ms after either
VBUS or VBAT becomes valid, the charger resets all the registers to the default state. Another 5 ms later, the
user registers become accessible to the host.
Power up sequence when the charger is powered up from VBUS:
• After VBUS above VVBUS_UVLOZ, enable 6-V LDO REGN pin and VDDA pin voltage increase accordingly.
CHRG_OK pin goes HIGH and the AC_STAT is configured to 1.
• After passing VBUS qualification, the REGN voltage is setup. VINDPM is detected in VBUS steady state
voltage and IIN_DPM is detected at ILIM_HIZ pin steady state voltage.
• Battery CELL configuration is read at CELL_BATPRESZ pin voltage and compared to VDDA to determine
cell configuration. Corresponding the default value of ChargeVoltage register (REG0x05/04()), ChargeCurrent
register (Reg0x03/02), VSYS_MIN and SYSOVP threshold are loaded.
• Converter powers up.
Power up sequence when the charger is powered up from VBAT:
• If only battery is present and the voltage is above VVBAT_UVLOZ , charger wakes up .
• By default, the charger is in low power mode (EN_LWPWR = 1b) with lowest quiescent current. The
REGN LDO stays off. The Quiescent current is minimized. PROCHOT is available through the independent
comparator by setting EN_PROCHOT_LPWR=1b.
• The adapter present comparator is activated, to monitor the VBUS voltage.
• SDA and SDL lines stand by waiting for host commands.
• Device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT
buffer through setting EN_IBAT=1b to monitor discharge current. The PSYS, PROCHOT or the independent
comparator also can be enabled by the host.
• In performance mode, the REGN LDO is always available to provide an accurate reference and gate drive
voltage for the converter.
9.3.2 Two-Level Battery Discharge Current Limit
To prevent the triggering of battery overcurrent protection and avoid battery wear-out, two battery current
limit levels (IDCHG_TH1 and IDCHG_TH2) PROCHOT profiles are recommended to be enabled. Define
IDCHG_TH1 through REG0x39h[7:2], IDCHG_TH2 is set through REG0x3Ch[5:3] for fixed percentage of
IDCHG_TH1. There are dedicated de-glitch time setting registers(IDCHG_DEG1 and IDCHG_DEG2) for both
IDCHG_TH1 and IDCHG_TH2.
• When battery discharge current is continuously higher than IDCHG_TH1 for more than IDCHG_DEG1 de-
glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH1,
then the time counter resets automatically. STAT_IDCHG1 bit will be set to 1 after PROCHOT is triggered.
Set PP_IDCHG1=1b to enable IDCHG_TH1 for triggering PROCHOT.
• When battery discharge current is continuously higher than IDCHG_TH2 for more than IDCHG_DEG2 de-
glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH2,
then the time counter resets automatically. STAT_IDCHG2 bit will be set to 1 after PROCHOT is triggered.
Set PP_IDCHG2=1b to enable IDCHG_TH2 for triggering PROCHOT.

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IDCHG_TH2

IDCHG_TH1

0A

/PROCHOT

IDCHG_DEG1 IDCHG_DEG1 IDCHG_DEG2 IDCHG_DEG2

Figure 9-1. Two-Level Battery Discharging Current Trigger PROCHOT Diagram

9.3.3 Fast Role Swap Feature

Fast Role Swap (FRS) means charger quickly swaps from power sink role to power source role to provide an
OTG output voltage to accessories when the original power source is disconnected. This feature is defined to
transfer the charger from forward mode to OTG mode quickly without dropping VBUS voltage per USB-C PD
specification requirement.Please contact factory for more detail information about FRS mode.

9.3.4 CHRG_OK Indicator

CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the
following conditions are valid:
• VBUS is above VVBUS_CONVEN
• VBUS is below VACOV_FALL
• No faults triggered such as: SYSOVP/SYSUVP/ACOC/TSHUT/BATOVP/BATOC/force converter off.
9.3.5 Input and Charge Current Sensing
The charger supports 10 mΩ and 5 mΩ for both input current sensing and charge current sensing. By default, 5
mΩ is enabled by POR setting RSNS_RAC=1b and RSNS_RSR=1b, if 10-mΩ sensing is used please configure
RSNS_RAC=0b and RSNS_RSR=0b. Lower current sensing resistor can help improve overall charge efficiency
especially under heavy load. At same time PSYS,IADPT,IBAT pin accuracy and IINDPM/ICHG/IOTG regulation
accuracy get worse due to effective signal reduction in comparison to error signal components.
When RSNS_RAC=RSNS_RSR=0b and 10 mΩ is used for both input and charge current sensing, the battery
low voltage current clamp is 384 mA (2 A for 1S if 3.6 V>VBAT>3 V ), the maximum IIN_HOST setting is
clamped at 6.35 A, and the maximum charge current is clamped at 8.128 A.
When RSNS_RAC=RSNS_RSR=1b and 5 mΩ is used for both input and charge current sensing, the charger
will internally compensate battery low voltage current clamp to be 384 mA (2 A for 1S if 3.6 V>VBAT>3 V )
under 5-mΩ current sensing which keeps consistent between 10 mΩ and 5 mΩ. Under 5-mΩ current sensing
application charge current range is doubled to 16.256 A. Based on EN_FAST_5MOHM register bit status and
IADPT pin resistor the maximum input current can be configured referring to Table 9-1:
For defined current sense resistors (10 mΩ/5 mΩ), PSYS function is still valid when unsymmetrical input current
sense and charge current sense resistors are used. But RSNS_RAC and RSNS_RSR bit status have to be
consistent with practical resistors used in the system.

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Table 9-1. Maximum Input Current Limit Configuration Table

INDUCTANCE (IADPT Pin MAXIMUM INPUT CURRENT LIMIT
EN_FAST_5MOHM RSR_RAC BIT
Resistance) (IINDPM)

Xb RSNS_RAC=0b 6.35 A
1.0 uH(90.9 kΩ)
1.5 uH(121 kΩ) 1b RSNS_RAC=1b 6.35 A
2.2 uH(137 kΩ)
0b RSNS_RAC=1b 10 A

Xb RSNS_RAC=0b 6.35 A
3.3 uH(169 kΩ)
Xb RSNS_RAC=1b 10 A

9.3.6 Input Voltage and Current Limit Setup

The actual input current limit being adopted by the device is the lower setting of IIN_DPM and ILIM_HIZ pin.
Register IIN_DPM input current limit setting will reset for below scenarios:
• When adapter is removed (CHRG_OK is not valid). Note when adapter is removed IIN_HOST will be reset
one time to 3.25 A, under battery only host is still able to overwrite IIN_HOST register with a new value. If the
adapter plug back in and CHRG_OK is pulled up, IIN_HOST will not be reset again.
• When input current optimization (ICO) is executed (EN_ICO_MODE=1b), the charger will automatically detect
the optimized input current limit based on adapter output characteristic. The final IIN_DPM register setting
could be different from IIN_HOST after ICO.
The voltage regulation loop of the charger regulates the input voltage to prevent the input adapter collapsing.
The VINDPM threshold should be configured based on no load input voltage level.Charger initiates a VBUS
voltage measurement without any load (VBUS at no load) right before the converter is enabled. The default
VINDPM threshold is VBUS at no load – 1.28 V. Host can adjust VINDPM threshold after device POR through
InputVoltage register(0x0B/0Ah[]), range from 3.2V to 19.52V with LSB 64mV.
After input current and voltage limits are set, the charger device is ready to power up. The host can always
program the input current and voltage limit after the charger being powered up based on the input source type.
9.3.7 Battery Cell Configuration
CELL_BATPRESZ pin is biased with a resistor divider from VDDA to GND. After REGN LDO is activated
(VDDA rise up), the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. No
external cap is allowed at CELL_BATPRESZ pin. When CELL_BATPRESZ pin is pulled down to GND (because
of battery removal) at the beginning of startup process, VSYS_MIN = 3.6 V and SYS_OVP = 25 V and
Maximum charge voltage (REG0x15) follow 1 cell default setting 4.2 V. VSYS and VBAT ADC offset is also
determined by CELL_BATPRESZ pin setting, under 1S-4S VSYS/VBAT ADC holds 2.88-V offset, however under
5S detection VSYS/VBAT ADC only holds 8.16-V offset to cover higher voltage range. Refer to Table 9-2 for
CELL_BATPRESZ pin configuration typical voltage for swept cell count.
Table 9-2. Battery Cell Configuration
PIN VOLTAGE w.r.t. CHARGEVOLTAGE VSYS/VBAT
CELL COUNT SYSOVP VSYS_MIN
VDDA (REG0x05/04h) ADC OFFSET
5S 100%(Directly connect to 21.000 V 25 V 15.4 V 8.16 V
VDDA)
4S 75% 16.800 V 19.5 V 12.3 V 2.88 V
3S 55% 12.600 V 19.5 V 9.2 V 2.88 V
2S 40% 8.400 V 12 V 6.6 V 2.88 V
1S 25% 4.200 V 6V 3.6 V 2.88 V
Battery removal 0% 4.200 V 25 V 3.6 V 2.88 V

9.3.8 Device HIZ State

When input source is present, the charger can enter HIZ mode (converter shuts off) when ILIM_HIZ pin voltage
is below 0.4 V or EN_HIZ is set to 1b. The charger is in the low quiescent current mode with REGN LDO

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enabled, ADC circuits are disactivated to reduce quiescent current. In order to exit HIZ mode, ILIM_HIZ pin
voltage has to be higher than 0.8 V and EN_HIZ bit has to be set to 0b.
9.3.9 USB On-The-Go (OTG)
The device supports USB OTG operation to deliver power from the battery to other portable devices through
USB port. The OTG mode output voltage is set in OTGVoltage register REG0x07/06() with 8-mV LSB range
from 3.0 V to 24 V. The OTG mode output current is set in OTGCurrent register REG0x09() with 100-mA LSB
range from 0 A to 12.7 A under 5-mΩ input current sensing. Both OTG voltage and OTG current are qualified for
USB-C™ programed power supply (PPS) specification in terms of resolution and accuracy. The OTG mode can
be enabled following below steps:
• Set target OTG current limit in OTGCurrent register, VBUS is below VVBUS_CONVENZ.
• Set OTG_VAP_MODE = 1b and EN_OTG = 1b.
• OTG/VAP/FRS pin is pulled high.
• 15 ms after the above conditions are valid, converter starts and VBUS ramps up to target voltage. CHRG_OK
pin goes HIGH if OTG_ON_CHRGOK= 1b.
OTG/VAP/FRS pin is used as multi-function to enable OTG and FRS mode.
9.3.10 Converter Operation
The charger operates in buck, buck-boost and boost mode under different VBUS and VBAT combination. The
buck-boost can operate seamlessly across the three operation modes. The 4 main switches operating status
under continuous conduction mode (CCM) are listed below for reference.
Table 9-3. MOSFET Operation
MODE BUCK BUCK-BOOST BOOST
Q1 Switching Switching ON
Q2 Switching Switching OFF
Q3 OFF Switching Switching
Q4 ON Switching Switching

9.3.11 Inductance Detection Through IADPT Pin

The charger reads both converter operation frequency and the inductance value through the resistance tied to
IADPT pin before the converter starts up. The resistances recommended for 2.2-μH (800 kHz), 3.3-μH (800 kHz)
and 4.7-μH (400 kHz) inductance refers to Table 9-4. A surface mount chip resistor with ±3% or better tolerance
must to be used for an accurate inductance detection.
Table 9-4. Inductor Detection through IADPT Resistance
INDUCTOR IN USE RESISTOR ON IADPT PIN
2.2 µH (recommended for 800 kHz) 137 kΩ or 140 kΩ
3.3 µH (recommended for 800 kHz) 169 kΩ
4.7 µH (recommended for 400 kHz) 191 kΩ or 187 kΩ

9.3.12 Converter Compensation

The charger employs two compensation pins COMP1 and COMP2 for converter compensation purpose,
appropriate RC network is needed to guarantee converter steady state and transient operation. Under different
operation frequency corresponding RC network value needs to be configured respectively as shown in below
table. The definition of these RC components can be referred to Figure 9-2. It is not recommended to change the
compensation network value due to the complexity of various operation modes.
Table 9-5. Compensation Configuration
COMPONENT
INDUCTOR COMP1 R1 COMP1 C11 COMP1 C12 COMP2 R2 COMP2 C21 COMP2 C22
VALUE
400 kHz 4.7 μH 40.2 kΩ 4.7 nF 33 pF 15 kΩ 680 pF 15 pF

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Table 9-5. Compensation Configuration (continued)

COMPONENT
INDUCTOR COMP1 R1 COMP1 C11 COMP1 C12 COMP2 R2 COMP2 C21 COMP2 C22
VALUE
800 kHz 3.3 μH 16.9 kΩ 3.3 nF 33 pF 15 kΩ 1200 pF 15 pF
800 kHz 2.2 μH 16.9 kΩ 3.3 nF 33 pF 10 kΩ 1200 pF 15 pF

COMP1 COMP2

R1 R2
C12 C22

C11 C21

Figure 9-2. Compensation RC Network

9.3.13 Continuous Conduction Mode (CCM)

With sufficient charge or system current, the inductor current does not cross 0 A, which is defined as CCM. The
controller starts a new cycle with ramp coming up from 200 mV. As long as the error amplifier output voltage
is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error
amplifier output voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle,
ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during
transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the
body-diode of the low-side power MOSFET conducts the inductor current.
During CCM, the inductor current always flows. Having the LSFET turn-on when the HSFET is off keeps the
power dissipation low and allows safe charging at high currents.
9.3.14 Pulse Frequency Modulation (PFM)
In order to improve converter light-load efficiency, BQ25731 switches to PFM operation at light load. The
effective switching frequency will decrease accordingly when system load decreases. The minimum frequency
can be limited to 25 kHz when the OOA feature is enabled (EN_OOA=1b) to avoid audible noise.
9.3.15 Switching Frequency and Dithering Feature
Normally, the IC switches in fixed frequency which can be adjusted through PWM_FREQ register bit. The
Charger also support frequency dithering function to improve EMI performance. This function is disabled by
default with setting EN_DITHER=00b. It can be enabled by setting EN_DITHER=01/10/11b, the switching
frequency is not fixed when dithering is enabled. It varies within determined range by EN_DITHER setting,
01/10/11b is corresponding to ±2%/4%/6% switching frequency. Please contact factory for more detail
information.
9.3.16 Current and Power Monitor
9.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
A high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, or
output current during OTG (IADPT) and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the
differential voltage across ACP and ACN. IBAT voltage is 8×/16× of the differential across SRP and SRN. After
input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current
monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be
achieved.

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• VIADPT = 20 or 40 × (VACP – VACN) during forward mode, or 20 or 40 × (VACN – VACP) during reverse OTG
mode.
• VIBAT = 8 or 16 × (VSRP – VSRN) during forward charging mode.
• VIBAT = 8 or 16 × (VSRN – VSRP) during forward supplement mode, reverse OTG mode and battery only
discharge scenario.
A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An
additional RC filter is optional. Note that RC filtering has additional response delay. The CSA output voltage is
clamped at 3.3 V.
9.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)
The charger monitors total system power. During forward mode, the input adapter powers the system. During
reverse OTG mode and battery only discharge scenario, the battery powers the system and VBUS output. The
ratio of PSYS pin output current and total system power, KPSYS, can be programmed in PSYS_RATIO register
bit with default 1 μA/W. The input and charge sense resistors (RAC and RSR) are selected in RSNS_RAC bit and
RSNS_RSR bit. By default, PSYS_CONFIG=00b and PSYS voltage can be calculated with Equation 1, where
IIN>0 when the charger is in forward charging and IIN<0 when charger is in OTG operation; where IBAT>0 when
the battery is in charging and IBAT<0 when battery is discharging.

VPSYS =RPSYS·KPSYS(VACP·IIN+VSYS·IBAT) (1)

RAC and RSR values are not limited to symmetrical both 5 mΩ or both 10 mΩ. For defined current sense resistors
(10 mΩ/5 mΩ), PSYS function is still valid when RAC=5 mΩ(RSNS_RAC=1b) and RSR=10 mΩ(RSNS_RAC=0b),
vice versa. As long as RSNS_RAC and RSNS_RSR bit status are consistent with practical resistors used in the
system.
Charger can block IBAT contribution to above equation by setting PSYS_CONFIG =01b in forward mode and
block IBUS contribution to above equation by setting PSYS_OTG_IDCHG=1b in OTG mode.
To minimize the quiescent current, the PSYS function is disabled by default PSYS_CONFIG = 11b.
Table 9-6. PSYS Configuration Table
OTG
PSYS_OTG_IDCHG FORWARD MODE PSYS
CASE # PSYS_CONFIG BITS MODE PSYS
BITS CONFIGURATION
CONFIGURATION
1 00b 0b PSYS = PBUS+PBAT PSYS = PBUS + PBAT
2 00b 1b PSYS = PBUS+PBAT PSYS =PBAT
3 01b Xb PSYS = PBUS PSYS = 0
4 11b Xb PSYS = 0 (Disabled) PSYS = 0 (Disabled)
5 (Reserved) 10b Xb PSYS = 0 (Reserved) PSYS = 0 (Reserved)

9.3.17 Input Source Dynamic Power Management

The charger supports Dynamic Power Management (DPM). Normally, the input power source provides power for
the system load and/or charging the battery. When the input current exceeds the input current setting (IIN_DPM),
or the input voltage falls below the input voltage setting (VINDPM), the charger decreases the charge current to
provide priority to the system load. As the system current rises, the available charge current drops accordingly
towards zero. If the system load keeps increasing after the charge current drops down to zero, the system
voltage starts to drop. As the system voltage drops below the battery voltage, the battery will discharge to
supplement the heavy system load.
9.3.18 Input Current Optimizer (ICO)
For a recognized input adapter, IINDPM can be configured precisely to prevent adapter collapasing. When a
third party unknown adapter is used, then input voltage regulation (VINDPM) feature can be leveraged to prevent
input crash. With the increasing of input current, voltage drops along the input cable also increases and voltage
measured it charger input port decreases accordingly. VINDPM feature can limit input power from adapter by
regulating VBUS at certain value configured at InputVoltage register(0x0Bh/0Ah[]). However, the adapter may

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still overheat when it is kept running at its voltage limit for a long period of time. Therefore, it is preferred to
operate the third party adapter slightly under its current rating. The Input Current Optimizer (ICO) feature can
automatically maximize the power of unknown input adapter without continuously working under VINDPM. Note
the ICO feature can only be employed when the adapter input current limit is at least 500 mA. Please contact
factory for more detail information about ICO feature.
9.3.19 Two-Level Adapter Current Limit (Peak Power Mode)
Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The
charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability. The
level 1 current limit, or ILIM1, is the same as adapter DC current, set in IIN_DPM register. The level 2 overloading
current, or ILIM2, is set in ILIM2_VTH, as a percentage of ILIM1.
When the charger detects input current surge and battery discharge due to load transient (both the adapter and
battery support the system together), the charger will first apply ILIM2 for TOVLD (PKPWR_TOVLD_DEG register
bits), and then ILIM1 for up to TMAX – TOVLD time. TMAX is programmed in PKPWR_TMAX register bits. After TMAX,
if the load is still high, another peak power cycle starts. Charging is disabled during TMAX and TOVLD already
expires; once TMAX, expires, a new cycle starts and resumes charging automatically.
To prepare entering peak power follow below steps:
• Set EN_IIN_DPM=1b to enable input current dynamic power management.
• Set EN_EXTILIM=0b to disable external current limit.
• Set register IIN_HOST based on adapter output current rating as the level 1 current limit(ILIM1)
• Set register bits ILIM2_VTH according to the adapter overload capability as the level 2 current limit(ILIM2) .
• Set register bits PKPWR_TOVLD_DEG as ILIM2 effective duration time for each peak power mode operation
cycle based on adapter capability.
• Set register bits PKPWR_TMAX as each peak power mode operation cycling time based on adapter
capability.
Host need to set EN_PKPWR_IIN_DPM=1b to enable peak power mode triggered by input current overshoot.
The overshoot threshold is IIN_DPM register which is same as the level 1 current limit (ILIM1). Typical application
waveform refer to Figure 10-18.
ICRIT_DEG

ICRIT
ILIM2

ILIM1

TOVLD
TOVLD
TMAX
IBUS

ISYS

IBAT 0A
Ba
ery Discharge
PROCHOT_WIDTH
PROCHOT

Figure 9-3. Two-Level Adapter Current Limit Timing Diagram

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9.3.20 Processor Hot Indication

The events monitored by the processor hot function includes:
• ICRIT: adapter peak current, as 110% of ILIM2
• INOM: adapter average current (110% of IIN_DPM)
• IDCHG1: battery discharge current level 1
• IDCHG2: battery discharge current level 2, note IDCHG2 threshold is always larger than IDCHG1 threshold
determined by IDCHG_TH2 register setting.
• VBUS_VAP: VBUS threshold to trigger PROCHOT in VAP mode 2 and 3.
• VSYS: system voltage on VSYS pin
• Adapter Removal: upon adapter removal (VBUS is lower than ACOK_TH=3.2 V same as VVBUS_CONVENZ
threshold)
• Battery Removal: upon battery removal (CELL_BATPRESZ pin goes LOW)
• CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)
• VINDPM: VBUS lower than 83%/91%/100% of VINDPM setting. The effective threshold PROCHOT_VINDPM
is determined by combination of register PROCHOT_VINDPM_80_90 bit and LOWER_PROCHOT_VINDPM
bit:
– PROCHOT_VINDPM=VINDPM register setting: LOWER_PROCHOT_VINDPM=0b;
– PROCHOT_VINDPM=83% VINDPM register setting:
LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=0b;
– PROCHOT_VINDPM=91% VINDPM register setting:
LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=1b;
• EXIT_VAP: Every time when the charger exits VAP mode.
The threshold of ICRIT, IDCHG1,IDCHG2,VSYS or VINDPM, and the deglitch time of ICRIT, INOM, IDCHG1,
IDCHG2, or CMPOUT are programmable through I2C register bits. Except the PROCHOT_EXIT_VAP is always
enabled, the other triggering events can be individually enabled in ProchotOption1[7:0], PP_IDCHG2 and
PP_VBUS_VAP. When any enabled event in PROCHOT profile is triggered, PROCHOT is asserted low for
a single pulse with minimal width programmable in PROCHOT_WIDTH register bits. At the end of the single
pulse, if the PROCHOT event is still active, the pulse gets extended until the event is removed.
If the PROCHOT pulse extension mode is enabled by setting EN_PROCHOT_EXT= 1b, the PROCHOT pin will
be kept low until host writes PROCHOT_CLEAR= 0b, even if the triggering event has been removed.
If the PROCHOT_VINDPM or PROCHOT_EXIT_VAP is triggered, PROCHOT pin will always stay low until
the host clears it, no matter the PROCHOT is in one pulse mode or in extended mode. In order to clear
PROCHOT_VINDPM, host needs to write 0 to STAT_VINDPM. In order to clear PROCHOT_EXIT_VAP, host
needs to write 0 to STAT_EXIT_VAP.

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PP_ICRIT
IADPT
+

ICRIT Adjustable
Low Pass Deglitch
Filter PP_INOM

+
EXIT_VAP
INOM (triggered by IN_VAP 1.05V
falling edge)
PP_IDCHG2
IDCHG2
+
IDCHG_VTH2

PP_IDCHG1
IDCHG1
+ PROCHOT

IDCHG_VTH1
10ms
Debounce
PP_VSYS

VSYS_VTH2 +
VSYS

10ms
Fixed
Deglitch
4us
PP_VINDPM

A*VINDPM +
VBUS
Fixed
Deglitch
4us
PP_VBUS_VAP PP_ACOK
VBUS_VAP_TH +
+

PP_BATPRES PP_CMP VVBUS_CONVENZ

CELL_BATPRESZ VBUS
(one shot on pin falling edge) CMPOUT (one shot on pin falling edge)

Figure 9-4. PROCHOT Profile

9.3.20.1 PROCHOT During Low Power Mode

During low power mode (EN_LWPWR = 1), the charger offers a low power PROCHOT function with very low
quiescent current consumption (~35 μA), which uses the independent comparator to monitor the system voltage,
and assert PROCHOT to CPU if the system power is too high and resulting system voltage is lower than specific
threshold.
Below lists the register setting to enable PROCHOT monitoring system voltage in low power mode.
• EN_LWPWR = 1b to enable charger low power mode.
• REG0x34[7:0] = 00h
• REG0x30[6:4] = 000b
• Independent comparator threshold is always 1.2 V

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• When EN_PROCHOT_LPWR = 1b, charger monitors system voltage. Connect CMPIN to voltage
proportional to system voltage. PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above
1.2 V.

1.2 V PROCHOT
Independent
Comparator
CMPIN
Voltage v VSYS

Figure 9-5. PROCHOT Low Power Mode Implementation

9.3.20.2 PROCHOT Status

report which event in the profile triggers PROCHOT if the corresponding bit is set to 1. The status bit can be
reset back to 0 after it is read by the host, when the current PROCHOT event is not active any more.
Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B
is also active. Both status bits will be HIGH. At the end of the 10-ms PROCHOT pulse, if any of the PROCHOT
event is still active (either A or B), the PROCHOT pulse is extended.
9.3.21 Device Protection
9.3.21.1 Watchdog Timer
The charger includes a watchdog timer to terminate charging if the charger does not receive a
write ChargeVoltage() or write ChargeCurrent() command within 175s (default value and adjustable via
WDTMR_ADJ). When watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent()
resets to 256 mA . Write ChargeVoltage() or write ChargeCurrent() commands must be resent to reset watchdog
timer. Writing WDTMR_ADJ = 00b to disable watchdog timer or update new watchdog timer values can also
reset watchdog timer.
9.3.21.2 Input Overvoltage Protection (ACOV)
The charger has fixed ACOV voltage threshold with hysteresis. When VBUS pin voltage is higher than
VACOV_RISE for more than 100 μs, it is considered as adapter overvoltage. CHRG_OK pin will be pulled low
by the charger, and the converter will be disabled. When VBUS pin voltage falls below VACOV_FALL for more
than 1 ms, it is considered as adapter voltage returns back to normal voltage. CHRG_OK pin is pulled high by
external pull-up resistor. The converter resumes if enable conditions are valid.
9.3.21.3 Input Overcurrent Protection (ACOC)
If the input current exceeds the 1.33× or 2× of ILIM2_VTH set point ACOC_TH (adjustable through ACOC_VTH),
after 250-μs rising edge de-glitch time converter stops switching because of input overcurrent protection
(ACOC). ACOC is a non-latch fault, if input current falls below set point, after 250-ms falling edge de-glitch
time converter starts switching again. ACOC is disabled by default and need to be enabled by configuring
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EN_ACOC=1b. When ACOC is triggered, its corresponding status bit Fault ACOC will be set and it can be
cleared by host read.
9.3.21.4 System Overvoltage Protection (SYSOVP)
When the converter starts up, the BQ25731 reads CELL_BATPRESZ pin configuration and sets ChargeVoltage()
and SYSOVP threshold (1s – 6 V, 2s – 12 V, 3s/4s – 19.5 V and 5s – 25 V ). Before ChargeVoltage() is written
by the host, the battery configuration will change with CELL pin voltage. When SYSOVP happens, the device
latches off the converter. Fault SYSOVP status bit is set to 1. The user can clear latch-off by either writing 0
to the Fault SYSOVP status bit or removing and plugging in the adapter again. After latch-off is cleared, the
converter starts again.
9.3.21.5 Battery Overvoltage Protection (BATOVP)
Battery overvoltage may happen when user plugs in a wrong battery or a wrong regulation voltage is written
into ChargeVoltage() register. The BATOVP rising threshold is 104% of regulation voltage set in ChargeVoltage()
register, and falling threshold is 102% of regulation voltage set in ChargeVoltage() register. When BATOVP rising
condition is triggered: if charge is enabled (charge current is not 0A) converter should shut down with both
HS MOSFET and LS MOSFET turned off; if charge is disabled the converter should keep operating without
disturbance until battery rise up system voltage to be high enough trigger SYSOVP. There is no user status bit
to monitor. Note VBAT voltage used for BATOVP detection is based on SRN pin measurement. When BATOVP
is triggered with charge enabled, 40-mA discharge current is added on VSYS pin will help discharge battery
voltage.
9.3.21.6 Battery Discharge Overcurrent Protection (BATOC)
The charger monitors the battery discharge current to provide the battery overcurrent protection (BATOC)
through voltage across SRN and SRP. BATOC can be enabled by configuring EN_BATOC=1b. BATOC threshold
is selected either 133% of IDCHG_TH2 or 200% IDCHG_TH2 through BATOC_VTH bit. The threshold is also
clamped between 100 mV and 360 mV SRN-SRP cross voltage.
When discharge current is higher than the threshold after 250-μs deglitch time, BATOC fault is triggered, status
bit Fault BATOC is set accordingly. Converter shuts down when BATOC is asserted to disable OTG operation
and reduce discharge current.
BATOC is not a latch fault, therefore after BATOC fault is removed, with 250-ms relax time, converter resume
switching automatically. But status bit Fault BATOC is only cleared by host read.
9.3.21.7 Battery Short Protection (BATSP)
For multicell operation, if BAT voltage falls below VSYS_MIN during charging, the maximum charger current
is limited to 384 mA. For single-cell operation, if BAT voltage falls below 3.0 V during charging, the maximum
charge current is limited to 384 mA; if BAT voltage is between 3.0 V and 3.6V then maximum charge current is
limited to 2 A. Note VBAT voltage used for battery short detection is based on SRN pin measurement.
9.3.21.8 System Undervoltage Lockout (VSYS_UVP)
During converter steady state operation VSYS pin is monitoring the system voltage, when VSYS is lower than
1.6 V, there is 2-ms deglitch time, the IIN_DPM is set to 0.5 A by the charger itself. After 2-ms deglitch time, the
charger should shut down and latched off. Fault VSYS_UVP bit will be set to 1 to report a system short fault. The
charger only can be enabled again once the host writes Fault VSYS_UVP bit to 0b.
During converter startup after VBUS rise above VVBUS_CONVEN: when VSYS is lower than 1.6 V, the IIN_DPM is
set to 0.5 A by the charger itself. After VSYS rise up higher than 1.6-V threshold IIN_DPM will be released to
default charger IIN_DPM setting. If after converter startup for 3 min (BQ25731), VSYS is still lower than 1.6-V
threshold, then the charger should shut down and latched off. Fault VSYS_UVP bit will be set to 1 to report a
system short fault. The charger only can be enabled again once the host writes Fault VSYS_UVP bit to 0b.
The charger VSYS_UVP is enabled by POR and can be disabled by writing VSYS_UVP_ENZ=1b.

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9.3.21.9 Thermal Shutdown (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to
the ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for
self-protection whenever the junction temperature reaches the 155°C. The charger stays off until the junction
temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16 mA and
stays on. When the temperature falls below 135°C, charge can be resumed with soft start.
When thermal shut down is triggered, TSHUT status bit will be triggered. This status bit keep triggered until host
read to clear it. If TSHUT is still present during host read, then this bit will try to be cleared when host read but
finally keep triggered because TSHUT still exists.
9.4 Device Functional Modes
9.4.1 Forward Mode
When input source is connected to VBUS, BQ25731 is in forward mode to charge 1- to 5-cell battery in constant
current (CC), and constant voltage (CV) mode. Based on CELL_BATPREZ pin setting, the charger sets default
battery voltage 4.2V/cell to ChargeVoltage(). According to battery capacity, the host programs appropriate
charge current to ChargeCurrent() register. When battery is full or battery is not in good condition to charge,
host terminates charge by setting CHRG_INHIBIT bit to 1b, or setting ChargeCurrent() to zero(WDTMR_ADJ=00
should be configured to disable watch dog timer, otherwise charge current will reset to 256 mA after watch dog
timer expires).
9.4.2 USB On-The-Go
The BQ25731 supports USB OTG functionality to deliver power from the battery to other portable devices
through USB port (reverse mode). The OTG output voltage is compliant with USB-C PD specification, including
5 V, 9 V, 15 V, and 20 V. The output current regulation is compliant with USB-C PD specification, including 500
mA, 1.5 A, 3 A and 5 A, and so forth.
Similar to forward operation, the device switches from PWM operation to PFM operation at light load to improve
efficiency.
9.4.3 Pass Through Mode (PTM)-Patented Technology
The charger can be operated in the pass through mode (PTM) to improve efficiency. In PTM, the Buck and Boost
high-side FETs (Q1 and Q4) are both turned on, while the Buck and Boost low-side FETs are both turned off.
The input power is directly passed through the charger to the system. The switching losses of MOSFETs and
the inductor core loss are saved. The charger quiescent current under PTM mode is also minimized to further
increase light load efficiency. Charger will be transition from normal Buck-Boost operation to PTM operation by
setting EN_PTM = 1b; and will transition out of PTM mode with host control by setting EN_PTM =0b. Please
contact factory for more detail information about PTM mode.
9.5 Programming
The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Section 9.5.1.7. The I2C address is 6Bh(0b1101011) consist of 7 bits. Adding read(1b) and
write(0b) to the end of address 7bits, the total 8bits data format address should be D6h (1101011_0 for write)/
D7h(1101011_1 for read). The ManufacturerID and DeviceID registers are assigned to identify the charger
device. The ManufacturerID register command always returns 40h.
9.5.1 I2C Serial Interface
The BQ25731 uses I2C compatible interface for flexible charging parameter programming and instantaneous
device status reporting. I2C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as host or target when performing data
transfers. A host is the device which initiates a data transfer on the bus and generates the clock signals to permit
that transfer. At that time, any device addressed is considered a target device.
The device operates as a target device with address D6h, receiving control inputs from the host device like micro
controller or a digital signal processor through REG00-REG3F. The I2C interface supports both standard mode

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(up to 100 kHz), and fast mode (up to 400 kHz). connecting to the positive supply voltage via a current source or
pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
9.5.1.1 Timing Diagrams

SCL

SDA

A = Start condition H = LSB of data clocked into target

B = MSB of address clocked into target I = Target pulls SDA line low

C = LSB of address clocked into target J = Acknowledge clocked into host

D = R/W bit clocked into target K = Acknowledge clock pulse

E = Target pulls SDA line low L = Stop condition, data executed by target

F = ACKNOWLEDGE bit clocked into host M = New start condition

G = MSB of data clocked into target

Figure 9-6. I2C Write Timing

SCL

SDA

A = Start condition G = MSB of data clocked into host

B = MSB of address clocked into target H = LSB of data clocked into host

C = LSB of address clocked into target I = Acknowledge clock pulse

D = R/W bit clocked into target J = Stop condition

E = Target pulls SDA line low K = New start condition

F = ACKNOWLEDGE bit clocked into host

Figure 9-7. I2C Read Timing

9.5.1.2 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.

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SDA

SCL
Data line stable; Change
Data valid of data
allowed
Figure 9-8. Bit Transfer on the I2C Bus

9.5.1.3 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the host. The bus is considered busy after the START
condition, and free after the STOP condition.

SDA SDA

SCL SCL

START (S) STOP (P)

Figure 9-9. START and STOP Conditions

9.5.1.4 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the host into a wait state (clock stretching). Data
transfer then continues when the target is ready for another byte of data and release the clock line SCL.
Acknowledgement Acknowledgement
signal from slave signal from receiver

MSB
SDA

SCL S or Sr 1 2 7 8 9 1 2 8 9 P or Sr
START or ACK ACK
STOP or
Repeated Repeated
START START

Figure 9-10. Data Transfer on the I2C Bus

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9.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the host.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The host can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
9.5.1.6 Target Address and Data Direction Bit
After the START, a target address is sent. This address is 7 bits long followed by the eighth bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

SCL S 1-7 8 9 1-7 8 9 1-7 8 9 P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

Figure 9-11. Complete Data Transfer

9.5.1.7 Single Read and Write

Figure 9-12. Single Write

Figure 9-13. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.
9.5.1.8 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write.

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Figure 9-14. Multi Write

Figure 9-15. Multi Read

9.5.1.9 Write 2-Byte I2C Commands

A few I2C commands combine two 8-bit registers together to form a complete value. These commands include:
• ChargeCurrent()
• ChargeVoltage()
• IIN_DPM()
• OTGVoltage()
• InputVoltage()
Host has to write LSB bit first and then move on to MSB bit. No other command can be inserted in between
these two writes. The charger waits for the complete write to the two registers to decide whether to accept or
ignore the new value.
After the completion of LSB and MSB bytes, the two bytes will be updated at the same time. If host writes MSB
byte first, the command will be ignored. If the time between write of LSB and MSB bytes exceeds watchdog
timer, both the LSB and MSB commands will be ignored.

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9.6 Register Map

Table 9-7. Charger Command Summary
I2C ADDR
REGISTER NAME TYPE DESCRIPTION LINKS
(MSB/LSB)
01/00h ChargeOption0() R/W Charge Option 0 Go
03/02h ChargeCurrent() R/W 7-bit charge current setting Go
LSB 128 mA, Range 0 mA – 16256 mA
(RSR=5mΩ)
05/04h ChargeVoltage() R/W 12-bit charge voltage setting Go
LSB 8 mV, Default: 1S-4200mV, 2S-8400mV,
3S-12600mV, 4S-16800mV, 5S-21000mV
07/06h OTGVoltage() R/W 12-bit OTG voltage setting Go
LSB 8 mV, Range: 3000 mV – 24000 mV
09/08h OTGCurrent() R/W 7-bit OTG output current setting Go
LSB 100 mA, Range: 0 A – 12700 mA
(RAC=5mΩ)
0B/0Ah InputVoltage() R/W 8-bit input voltage setting Go
LSB 64 mV, Range: 3200 mV – 19520 mV
0F/0Eh IIN_HOST() R/W 6-bit Input current limit set by host Go
LSB: 100-mA, Range: 100 mA - 10000 mA with
100 mA offset (RAC=5mΩ)
21/20h ChargerStatus() R with R/W Charger Status Go
bits
23/22h ProchotStatus() R and R/W Prochot Status Go
bits
25/24h IIN_DPM() R 7-bit input current limit in use Go
LSB: 50 mA, Range: 100 mA - 10000 mA
(RAC=5mΩ)
27/26h ADCVBUS/PSYS() R 8-bit digital output of input voltage, Go
8-bit digital output of system power
PSYS: Full range: 3.06 V, LSB: 12 mV
VBUS: Full range: 0 V - 24.48 V, LSB 96 mV
29/28h ADCIBAT() R 7-bit digital output of battery charge current, Go
7-bit digital output of battery discharge current
ICHG: Full range 16.256 A, LSB 128 mA
IDCHG: Full range: 65.024 A, LSB: 512 mA
(RSR=5mΩ)
2B/2Ah ADCIINCMPIN() R 8-bit digital output of input current, Go
8-bit digital output of CMPIN voltage
POR State - IIN: Full range: 25.5 A, LSB 100 mA
(RAC=5mΩ)
CMPIN: Full range 3.06 V, LSB: 12 mV
2D/2Ch ADCVSYSVBAT() R 8-bit digital output of system voltage, Go
8-bit digital output of battery voltage
VSYS: Full range: 2.88 V - 19.2 V, LSB: 64 mV
(1S-4S)
VSYS: Full range: 8.16 V - 24.48 V, LSB: 64 mV
(5S)
VBAT: Full range : 2.88 V - 19.2 V, LSB 64 mV
(1S-4S)
VBAT: Full range : 8.16 V - 24.48 V, LSB 64 mV
(5S)
2Eh ManufacturerID() R Manufacturer ID - 0x0040H Go
2Fh DeviceID() R Device ID Go
31/30h ChargeOption1() R/W Charge Option 1 Go
33/32h ChargeOption2() R/W Charge Option 2 Go
35/34h ChargeOption3() R/W Charge Option 3 Go
37/36h ProchotOption0() R/W PROCHOT Option 0 Go

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Table 9-7. Charger Command Summary (continued)

I2C ADDR
REGISTER NAME TYPE DESCRIPTION LINKS
(MSB/LSB)
39/38h ProchotOption1() R/W PROCHOT Option 1 Go
3B/3Ah ADCOption() R/W ADC Option Go
3D/3Ch ChargeOption4() R/W Charge Option 4 Go
3F/3Eh Vmin Active Protection() R/W Vmin Active Protection Go

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9.6.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]

Figure 9-14. ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
7 6 5 4 3 2 1 0
EN_LWPWR WDTMR_ADJ IIN_DPM_AUT OTG_ON_CH EN_OOA PWM_FREQ LOW_PTM_RIP
O_DISABLE RGOK PLE
R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
EN_CMP_LAT VSYS_UVP_E EN_LEARN IADPT_GAIN IBAT_GAIN Reserved EN_IIN_DPM CHRG_INHIBIT
CH NZ
R/W R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-8. ChargeOption0 Register (I2C address = 01h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 EN_LWPWR R/W 1b Low Power Mode Enable, under low power mode lowest quiescent current is
achieved when only battery exist. It is not recommended to enable low power
mode when adapter present.
0b: Disable Low Power Mode. Device in performance mode with battery only.
The PROCHOT, current/power monitor buffer and comparator follow register
setting.
1b: Enable Low Power Mode. Device in low power mode with battery only
for lowest quiescent current. The REGN is off. The PROCHOT, discharge
current monitor buffer, power monitor buffer and independent comparator are
disabled. ADC is not available in Low Power Mode. Independent comparator
and its low power mode PROCHOT profile can be enabled by setting
EN_PROCHOT_LPWR bit to 1b. <default at POR>
6-5 WDTMR_ADJ R/W 11b WATCHDOG Timer Adjust
Set maximum delay between consecutive Host write of charge voltage or
charge current command.
If device does not receive a write on the REG0x15() or the REG0x14()
within the watchdog time period, the charger will be suspended by setting
the REG0x14() to 0 mA 256 mA (BQ25731).
After expiration, the timer will resume upon the write of REG0x14(),
REG0x15() or REG0x12[14:13].
00b: Disable Watchdog Timer
01b: Enabled, 5 sec
10b: Enabled, 88 sec
11b: Enable Watchdog Timer, 175 sec <default at POR>
4 IIN_DPM_AUTO_DISAB R/W 0b IIN_DPM Auto Disable
LE When CELL_BATPRESZ pin is LOW, the charger automatically disables the
IIN_DPM function by setting EN_IIN_DPM (REG0x12[1]) to 0. The host can
enable IIN_DPM function later by writing EN_IIN_DPM bit (REG0x12[1]) to 1.
0b: Disable this function. IIN_DPM is not disabled when CELL_BATPRESZ
goes LOW. <default at POR>
1b: Enable this function. IIN_DPM is disabled when CELL_BATPRESZ goes
LOW.
3 OTG_ON_CHRGOK R/W 0b Add OTG to CHRG_OK
Drive CHRG_OK to HIGH when the device is in OTG mode.
0b: Disable <default at POR>
1b: Enable

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Table 9-8. ChargeOption0 Register (I2C address = 01h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
2 EN_OOA R/W 1b Out-of-Audio Enable
In both forward mode and OTG mode, switching frequency reduces with
diminishing load, under extreme light load condition the switching frequency
could be lower than 25 kHz which is already in audible frequency range. By
configuring EN_OOA=1b, the minimum PFM burst frequency is clamped at
around 25 kHz to avoid any audible noise.
0b: No limit of PFM burst frequency
1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise
<default at POR>
1 PWM_FREQ R/W 1b Switching Frequency Selection: Recommend 800 kHz with 2.2 µH, and 400
kHz with 4.7 µH.
0b: 800kHz
1b: 400 kHz<default at POR>
0 LOW_PTM_RIPPLE R/W 1b PTM mode input voltage and current ripple reduction
0b: Disable
1b: Enable <default at POR>

Table 9-9. ChargeOption0 Register (I2C address = 00h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 EN_CMP_LATCH R/W 0b The EN_CMP_LATCH bit, will latch the independent comparator output after
it is triggered at low state. If enabled in PROCHOT profile REG34H[6]=1 ,
STAT_COMP bit REG0x21[6] keep 1b after triggered until read by host and
clear
0b: Independent comparator output will not latch when it is low<default at
POR>
1b: Independent comparator output will latch when it is low, host can clear
CMPOUT pin by toggling this REG0x12[7] bit.
6 VSYS_UVP_ENZ R/W 0b To disable system under voltage protection.
0b: VSYS under voltage protection is enabled <default at POR>
1b: VSYS under voltage protection is disabled
5 EN_LEARN R/W 0b LEARN mode allows the battery to discharge and converter to shut off while
the adapter is present . It calibrates the battery gas gauge over a complete
discharge/charge cycle. When the host determines the battery voltage is
below battery depletion threshold, the host switch the system back to adapter
input by writing this bit back to 0b.
0b: Disable LEARN Mode <default at POR>
1b: Enable LEARN Mode
4 IADPT_GAIN R/W 0b IADPT Amplifier Ratio
The ratio of voltage on IADPT and voltage across ACP and ACN.
0b: 20× <default at POR>
1b: 40×
3 IBAT_GAIN R/W 1b IBAT Amplifier Ratio
The ratio of voltage on IBAT and voltage across SRP and SRN
0b: 8×
1b: 16× <default at POR>
2 Reserved R/W 1b Reserved

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Table 9-9. ChargeOption0 Register (I2C address = 00h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
1 EN_IIN_DPM R/W 1b IIN_DPM Enable
Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM
is disabled by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes
LOW.
0b: IIN_DPM disabled
1b: IIN_DPM enabled <default at POR>
0 CHRG_INHIBIT R/W 0b Charge Inhibit
When this bit is 0, battery charging will start with valid values in the
ChargeVoltage() register and the ChargeCurrent register.
0b: Enable Charge <default at POR>
1b: Inhibit Charge

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9.6.2 ChargeCurrent Register (I2C address = 03/02h) [reset = 0080h]

To set the charge current, write 16-bit ChargeCurrent() command (REG0x03/02h()) using the data format listed
Figure 9-15.
With 5-mΩ sense resistor, the charger provides charge current range of 0 A to 16.256 A, with a 128-mA step
resolution. With 10-mΩ sense resistor, the charger provides charge current range of 0 A to 8.128 A, with a
64-mA step resolution.
Upon POR, ChargeCurrent() is 0 A. Below scenarios will also reset Charge current to zero:
• CELL_BATPRESZ going LOW (battery removal).
• STAT_AC is not valid(Adapter removal).
• RESET_REG is asserted and reset all registers.
• Charge voltage is written to be 0 V.
• Watch dog event is triggered.
Charge current is not reset in force converter latch off fault (REG0x20[2]), and ACOC/TSHUT/SYSOVP/ACOV/
VSYS_UVP/BATOVP/BATOC faults.
Figure 9-15. ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
7 6 5 4 3 2 1 0
Reserved Charge Current, Charge Current, Charge Current, Charge Current, Charge Current,
bit 6 bit 5 bit 4 bit 3 bit 2
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Charge Current, Charge Current, Reserved Reserved
bit 1 bit 0
R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-10. Charge Current Register with 5-mΩ Sense Resistor (I2C address = 03h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-5 Reserved R/W 000b Not used. 1 = invalid write.
4 Charge Current, bit 6 R/W 0b 0 = Adds 0 mA of charger current.
1 = Adds 8192 mA of charger current.
3 Charge Current, bit 5 R/W 0b 0 = Adds 0 mA of charger current.
1 = Adds 4096 mA of charger current.
2 Charge Current, bit 4 R/W 0b 0 = Adds 0 mA of charger current.
1 = Adds 2048 mA of charger current.
1 Charge Current, bit 3 R/W 0b 0 = Adds 0 mA of charger current.
1 = Adds 1024 mA of charger current.
0 Charge Current, bit 2 R/W 0b 0 = Adds 0 mA of charger current.
1 = Adds 512 mA of charger current.

Table 9-11. Charge Current Register with 5-mΩ Sense Resistor (I2C address = 02h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 Charge Current, bit 1 R/W 1b 0 = Adds 0 mA of charger current.
1 = Adds 256 mA of charger current.
6 Charge Current, bit 0 R/W 0b 0 = Adds 0 mA of charger current.
1 = Adds 128 mA of charger current.
5-0 Reserved R/W 000000b Not used. Value Ignored.

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9.6.2.1 Battery Low Voltage Current Clamp

During battery voltage is low, there is current clamp implemented by converter. For 2-4 cell battery, if the battery
voltage is below battery low voltage threshold(VSYS_MIN) then the charge current is clamped at 384 mA. For
1 cell battery, the battery low voltage threshold is 3 V, and the charge current is clamped at 384 mA if battery
voltage is below 3V. However, during battery voltage from 3 V to 3.6 V(VSYS_MIN for 1 cell), the charge current
is clamped at 2 A. Until battery voltage is above VSYS_MIN, charge current is not clamped anymore.

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9.6.3 ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
To set the output charge voltage, write a 16-bit ChargeVoltage register command (REG0x05/04h()) using the
data format listed in Figure 9-16, Table 9-12, and Table 9-13. The charger provides charge voltage range from
1.024 V to 23.000 V, with 8-mV step resolution. Any write below 1.024 V or above 23.000 V is ignored.
Upon POR, ChargeVoltage() is by default set as 4200 mV for 1 s, 8400 mV for 2 s, 12600 mV for 3 s or 16800
mV for 4 s, 21000 mV for 5s. After CHRG_OK goes high, the charge will start when the host writes the charging
current to ChargeCurrent() register, the default charging voltage is used if ChargeVoltage() is not programmed. If
the battery is different from 4.2 V/cell, the host has to write to ChargeVoltage() before ChargeCurrent() register
for correct battery voltage setting. Writing ChargeVoltage() to 0 should keep ChargeVoltage() value unchanged,
and force ChargeCurrent() register to zero to disable charge.
The SRN pin senses the battery voltage for voltage regulation and should be connected as close to the battery
as possible.
Figure 9-16. ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin
setting]
7 6 5 4 3 2 1 0
Reserved Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage,
bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Reserved
bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-12. ChargeVoltage Register (I2C address = 05h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R/W 0b Not used. 1 = invalid write.
6 Charge Voltage, bit 11 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 16384 mV of charger voltage.
5 Charge Voltage, bit 10 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 8192 mV of charger voltage
4 Charge Voltage, bit 9 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 4096 mV of charger voltage.
3 Charge Voltage, bit 8 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 2048 mV of charger voltage.
2 Charge Voltage, bit 7 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 1024 mV of charger voltage.
1 Charge Voltage, bit 6 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 512 mV of charger voltage.
0 Charge Voltage, bit 5 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 256 mV of charger voltage.

Table 9-13. ChargeVoltage Register (I2C address = 04h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Charge Voltage, bit 4 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 128 mV of charger voltage.
6 Charge Voltage, bit 3 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 64 mV of charger voltage.

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Table 9-13. ChargeVoltage Register (I2C address = 04h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
5 Charge Voltage, bit 2 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 32 mV of charger voltage.
4 Charge Voltage, bit 1 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 16 mV of charger voltage.
3 Charge Voltage, bit 0 R/W 0b 0 = Adds 0 mV of charger voltage.
1 = Adds 8 mV of charger voltage.
2-0 Reserved R/W 000b Not used. Value Ignored.

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9.6.4 ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]

Figure 9-17. ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
7 6 5 4 3 2 1 0
STAT_AC ICO_DONE IN_VAP IN_VINDPM IN_IIN_DPM IN_FCHRG Reserved IN_OTG
R R R R R R R R
7 6 5 4 3 2 1 0
Fault ACOV Fault BATOC Fault ACOC FAULT Fault VSYS Fault Fault_OTG Fault_OTG
SYSOVP _UVP Force_Converte _OVP _UVP
r_Off
R R R R/W R/W R R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-14. ChargerStatus Register (I2C address = 21h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 STAT_AC R 0b Input source status. STAT_AC is valid as long as VBUS go within
3.5-V to 26-V range. It is different from CHRG_OK bit, When
CHRG_OK is valid, STAT_AC must be valid, but if STAT_AC is valid,
it is not necessary CHRG_OK is valid. There are Force converter
off, ACOC, TSHUT , SYSOVP, VSYS_UVP, BATOVP can pull low
CHRG_OK.
0b: Input not present
1b: Input is present
6 ICO_DONE R 0b After the ICO routine is successfully executed, the bit goes 1.
0b: ICO is not complete
1b: ICO is complete
5 IN_VAP R 0b 0b: Charger is not operated in VAP mode
1b: Charger is operated in VAP mode
Digital status bit indicates VAP has enabled(1) or disabled(0). The
enable of VAP mode only follows the host command, which is not
blocked by any status of /PROCHOT. The exit of VAP mode also
follows the host command, except that any faults will exit VAP mode
automatically. STAT_EXIT_VAP (REG0x21[8]) becomes 1 which will
pull low /PROCHOT until host clear.
The host can enable VAP by setting OTG/VAP/FRS pin high and
0x32[5]=0, disable VAP by setting either OTG/VAP/FRS pin low
or 0x32[5]=1. Any faults in VAP When IN_VAP bit goes 0->1,
charger should disable VINDPM, IIN_DPM, ICRIT, ILIM pin, disable
PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When
IN_VAP bit goes 1->0, charger should enable VINDPM, IIN_DPM,
ICRIT, ILIM pin function.
4 IN_VINDPM R 0b 0b: Charger is not in VINDPM during forward mode, or voltage
regulation during OTG mode
1b: Charger is in VINDPM during forward mode, or voltage
regulation during OTG mode
3 IN_IIN_DPM R 0b 0b: Charger is not in IIN_DPM during forward mode.
1b: Charger is not in IIN_DPM during forward mode.
2 IN_FCHRG R 0b 0b: Charger is not in fast charge
1b: Charger is in fast charger
1 Reserved R 0b Reserved

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Table 9-14. ChargerStatus Register (I2C address = 21h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
0 IN_OTG R 0b 0b: Charger is not in OTG
1b: Charge is in OTG

Table 9-15. ChargerStatus Register (I2C address = 20h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Fault ACOV R 0b The status are latched if triggered until a read from host.
0b: No fault
1b: ACOV
6 Fault BATOC R 0b The status is latched if triggered until a read from host. Fault
indicator for BATOC only during normal operation. However, in PTM
mode when EN_BATOC=1b, this status bit is fault indicator for both
BATOVP and BATOC; when EN_BATOC=0b, this status bit is not
effective.
0b: No fault
1b: BATOC is triggered
5 Fault ACOC R 0b The status is latched if triggered until a read from host.
0b: No fault
1b: ACOC
4 Fault SYSOVP R/W 0b SYSOVP Status and Clear. SYSOVP fault is latched until a clear
from host by writing this bit to 0.
When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the
converter is disabled.
After the SYSOVP is removed, the user must write a 0 to this bit
or unplug the adapter to clear the SYSOVP condition to enable the
converter again.
0b: Not in SYSOVP <default at POR>
1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the
SYSOVP latch.
3 Fault VSYS_UVP R/W 0b VSYS_UVP fault status and clear. VSYS_UVP fault is latched until a
clear from host by writing this bit to 0.
0b: No fault <default at POR>
1b: When system voltage is lower than VSYS_UVP, then 7 times
restart tries are failed.
2 Fault Force_Converter_Off R 0b The status is latched if triggered until a read from host.
0b: No fault
1b: Force converter off triggered (when FORCE_CONV_OFF
(REG0x30[3])=1b)
1 Fault_OTG_OVP R 0b The status is latched if triggered until a read from host.
0b: No fault
1b: OTG OVP fault is triggered
0 Fault_OTG_UVP R 0b The status is latched if triggered until a read from host.
0b: No fault
1b: OTG UVP fault is triggered

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9.6.5 ProchotStatus Register (I2C address = 23/22h) [reset = B800h]

All the status bits in REG0x23[7,2],REG0x23[6:0] will be cleared after host read.
Figure 9-18. ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
7 6 5 4 3 2 1 0
Reserved EN_PROCHOT PROCHOT_WIDTH PROCHOT_CL Reserved STAT_VAP_FAI STAT_EXIT_VA
_EXT EAR L P
R R/W R/W R/W R R/W R/W
7 6 5 4 3 2 1 0
STAT_VINDPM STAT_COMP STAT_ICRIT STAT_INOM STAT_IDCHG1 STAT_VSYS STAT_BAT_Re STAT_ADPT_R
moval emoval
R/W R R R R R R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-16. ProchotStatus Register (I2C address = 23h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R 1b Reserved
6 EN_PROCHOT _EXT R/W 0b PROCHOT Pulse Extension Enable. When pulse extension is
enabled, keep the PROCHOT pin voltage LOW until host writes
PROCHOT _CLEAR = 0b.
0b: Disable pulse extension <default at POR>
1b: Enable pulse extension
5-4 PROCHOT _WIDTH R/W 11b PROCHOT Pulse Width Minimum PROCHOT pulse width when
EN_PROCHOT _EXT = 0b
00b: 100 us
01b: 1 ms
10b: 5 ms
11b: 10 ms <default at POR>
3 PROCHOT _CLEAR R/W 1b PROCHOT Pulse Clear.
Clear PROCHOT pulse when EN_PROCHOT _EXT = 1b.
0b: Clear PROCHOT pulse and drive PROCHOT pin HIGH
1b: Idle <default at POR>
2 TSHUT R 0b TSHUT trigger:
0b: TSHUT is not triggered
1b: TSHUT is triggered
1 STAT_VAP_FAIL R/W 0b This status bit reports a failure to load VBUS 7 consecutive times
in VAP mode, which indicates the battery voltage might be not
high enough to enter VAP mode, or the VAP loading current
settings are too high.
0b: Not is VAP failure <default at POR>
1b: In VAP failure, the charger exits VAP mode, and latches off
until the host writes this bit to 0.
0 STAT_EXIT_VAP R/W 0b When the charger is operated in VAP mode, it can exit VAP
by either being disabled through host, or there are ACOV/ACOC/
SYSOVP/BATOVP/VSYS_UVP faults.
0b: PROCHOT_EXIT_VAP is not active <default at POR>
1b: PROCHOT_EXIT_VAP is active, PROCHOT pin is low until
host writes this status bit to 0.

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Table 9-17. ProchotStatus Register (I2C address = 22h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 STAT_VINDPM R/W 0b PROCHOT Profile VINDPM status bit
0b: Not triggered
1b: Triggered, PROCHOT pin is low until host writes this status bit
to 0 when PP_VINDPM = 1b
6 STAT_COMP R 0b PROCHOT Profile CMPOUT status bit. The status is latched until
a read from host.
0b: Not triggered
1b: Triggered
5 STAT_ICRIT R 0b PROCHOT Profile ICRIT status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
4 STAT_INOM R 0b PROCHOT Profile INOM status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
3 STAT_IDCHG1 R 0b PROCHOT Profile IDCHG1 status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
2 STAT_VSYS R 0b PROCHOT Profile VSYS status bit. The status is latched until a
read from host.
0b: Not triggered
1b: Triggered
1 STAT_Battery_Removal R 0b PROCHOT Profile Battery Removal status bit. The status is
latched until a read from host.
0b: Not triggered
1b: Triggered
0 STAT_Adapter_Removal R 0b PROCHOT Profile Adapter Removal status bit. The status is
latched until a read from host.
0b: Not triggered
1b: Triggered

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9.6.6 IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]

IIN_DPM register reflects the actual input current limit programmed in the register, either from IIN_HOST register
or from ICO.
After ICO, the current limit used by DPM regulation may differ from the IIN_HOST register settings. The actual
DPM limit is reported in IIN_DPM register.
To read the nominal or typical input current limit
• When using a 10-mΩ sense resistor (RSNS_RAC=0b). There is 50-mA offset at code 0. Note this offset is
only applied to code 0, not applied to other codes.
• When using a 5-mΩ sense resistor (RSNS_RAC=1b). There is 100-mA offset at code 0. Note this offset is
only applied to code 0, not applied to other codes.
To read the maximum input current limit, need to add 100 mA/200 mA offset based on above nominal input
current limit reading approach.
• When using a 10-mΩ sense resistor (RSNS_RAC=0b). There is 150-mA offset at code 0 and this 150 mA
offset is only applied to code 0, 100-mA offset should be added for all other non-zero codes.
• When using a 5-mΩ sense resistor (RSNS_RAC=1b). There is 300-mA offset at code 0 and this 300 mA
offset is only applied to code 0, 200-mA offset should be added for all other non-zero codes
Figure 9-19. IIN_DPM Register with 10-mΩ Sense Resistor (I2C address = 25/24h) [reset = 4100h]
7 6 5 4 3 2 1 0
Reserved Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in
DPM, bit 6 DPM, bit 5 DPM, bit 4 DPM, bit 3 DPM, bit 2 DPM, bit 1 DPM, bit 0
R R R R R R R R
7 6 5 4 3 2 1 0
Reserved
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-18. IIN_DPM Register with 5-mΩ Sense Resistor (I2C address = 25h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R 0b Not used. 1 = invalid write.
6 Input Current in DPM, bit 6 R 0b 0 = Adds 0 mA of input current.
1 = Adds 6400 mA of input current.
5 Input Current in DPM, bit 5 R 0b 0 = Adds 0 mA of input current.
1 = Adds 3200 mA of input current.
4 Input Current in DPM, bit 4 R 0b 0 = Adds 0 mA of input current.
1 = Adds 1600 mA of input current.
3 Input Current in DPM, bit 3 R 0b 0 = Adds 0 mA of input current.
1 = Adds 800mA of input current
2 Input Current in DPM, bit 2 R 0b 0 = Adds 0 mA of input current.
1 = Adds 400 mA of input current.
1 Input Current in DPM, bit 1 R 0b 0 = Adds 0 mA of input current.
1 = Adds 200 mA of input current.
0 Input Current in DPM, bit 0 R 0b 0 = Adds 0 mA of input current.
1 = Adds 100 mA of input current.

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Table 9-19. IIN_DPM Register with 5-mΩ Sense Resistor (I2C address = 24h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-0 Reserved R 00000000b Not used. Value Ignored.

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9.6.7 ADCVBUS/PSYS Register (I2C address = 27/26h)

• PSYS: Full range: 3.06 V, LSB: 12 mV (ADC_FULLSCALE=1b)
• PSYS: Full range: 2.04 V, LSB: 8 mV (ADC_FULLSCALE=0b)
• VBUS: Full range: 0 mV to 24480 mV, LSB: 96 mV
Figure 9-20. ADCVBUS/PSYS Register (I2C address = 27/26h)
7 6 5 4 3 2 1 0

R R R R R R R R

7 6 5 4 3 2 1 0

R R R R R R R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-20. ADCVBUS Register (I2C address = 27h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 R 8-bit Digital Output of Input Voltage

Table 9-21. ADCPSYS Register (I2C address = 26h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 R 8-bit Digital Output of System Power

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9.6.8 ADCIBAT Register (I2C address = 29/28h)

• ICHG: Full range when using a 10-mΩ sense resistor (RSNS_RSR=0b):8.128 A, LSB: 64 mA.
• ICHG: Full range when using a 5-mΩ sense resistor (RSNS_RSR=1b):16.256A,LSB: 128 mA.
• IDCHG: Full range when using a 10-mΩ sense resistor (RSNS_RSR=0b):32.512 A, LSB: 256 mA. Note when
discharge current is higher than 32.512 A, the ADC will report 32.512 A
• IDCHG: Full range when using a 5-mΩ sense resistor (RSNS_RSR=1b):65.024A,LSB: 512 mA. Note when
discharge current is higher than 65.024 A, the ADC will report 65.024 A
Figure 9-21. ADCIBAT Register (I2C address = 29/28h)
7 6 5 4 3 2 1 0

Reserved R R R R R R R

7 6 5 4 3 2 1 0

Reserved R R R R R R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-22. ADCICHG Register (I2C address = 29h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R Not used. Value ignored.
6-0 R 7-bit Digital Output of Battery Charge Current

Table 9-23. ADCIDCHG Register (I2C address = 28h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R Not used. Value ignored.
6-0 R 7-bit Digital Output of Battery Discharge Current

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9.6.9 ADCIIN/CMPIN Register (I2C address = 2B/2Ah)

• IIN Full range: When using a 10-mΩ sense resistor (RSNS_RAC=0b): 12.75 A, LSB: 50 mA.
• IIN Full range: When using a 5-mΩ sense resistor (RSNS_RAC=1b): 25.5A, LSB:100 mA.
• CMPIN Full range: 3.06 V, LSB: 12 mV (ADC_FULLSCALE=1b)
• CMPIN Full range: 2.04 V, LSB: 8 mV (ADC_FULLSCALE=0b)
Figure 9-22. ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
7 6 5 4 3 2 1 0

R R R R R R R R

7 6 5 4 3 2 1 0

R R R R R R R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-24. ADCIIN Register (I2C address = 2Bh) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 R 8-bit Digital Output of Input Current

Table 9-25. ADCCMPIN Register (I2C address = 2Ah) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 R 8-bit Digital Output of CMPIN voltage

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9.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)

• VSYS: Full range: 2.88 V to 19.2 V, LSB: 64 mV (1S-4S)
• VSYS: Full range: 8.16 V to 24.48 V, LSB: 64 mV (5S)
• VBAT: Full range: 2.88 V to 19.2 V, LSB: 64 mV (1S-4S)
• VBAT: Full range: 8.16 V to 24.48 V, LSB: 64 mV (5S)
Figure 9-23. ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
7 6 5 4 3 2 1 0

R R R R R R R R

7 6 5 4 3 2 1 0

R R R R R R R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-26. ADCVSYS Register (I2C address = 2Dh) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 R 8-bit Digital Output of System Voltage

Table 9-27. ADCVSYSVBAT Register (I2C address = 2Ch) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 R 8-bit Digital Output of Battery Voltage

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9.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]

Figure 9-24. ChargeOption1 Register (I2C address = 31/30h) [reset = 3300h]
7 6 5 4 3 2 1 0
EN_IBAT EN_PROCHOT PSYS_CONFIG RSNS_RAC RSNS_RSR PSYS_RATIO EN_FAST_5MO
_LPWR HM
R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
CMP_REF CMP_POL CMP_DEG FORCE_CON EN_PTM EN_SHIP_DCH AUTO_WAKEU
V_OFF G P_EN
R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-28. ChargeOption1 Register (I2C address = 31h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 EN_IBAT R/W 0b IBAT Enable
Enable the IBAT output buffer. In low power mode (EN_LWPWR=1b), IBAT
buffer is always disabled regardless of this bit value.
0b Turn off IBAT buffer to minimize Iq <default at POR>
1b: Turn on IBAT buffer
6 EN_PROCHOT_LPWR R/W 0b Enable PROCHOT during battery only low power mode
With battery only, enable VSYS in PROCHOT with low power consumption. Do
not enable this function with adapter present. Refer to Section 9.3.20.1 for more
details.
0b: Disable Independent Comparator low power PROCHOT <default at POR>
1b: Enable Independent Comparator low power PROCHOT
5-4 PSYS_CONFIG R/W 11b PSYS Enable and Definition Register
Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low
power mode (EN_LWPWR=1b), PSYS sensing and buffer are always disabled
regardless of this bit value.
00b: PSYS=PBUS+PBAT
01b: PSYS=PBUS
10b: Reserved
11b: Turn off PSYS buffer to minimize Iq<default at POR>
3 RSNS_RAC R/W 1b Input sense resistor RAC
0b: 10 mΩ
1b: 5 mΩ <default at POR>
2 RSNS_RSR R/W 1b Charge sense resistor RSR
0b: 10 mΩ
1b: 5 mΩ <default at POR>
1 PSYS_RATIO R/W 1b PSYS Gain
Ratio of PSYS output current vs total system power
0b: 0.25 µA/W
1b: 1 µA/W <default at POR>

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Table 9-28. ChargeOption1 Register (I2C address = 31h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
0 EN_FAST_5MOHM R/W 1b Enable fast compensation to increase bandwidth under 5 mΩ RAC
(RSNS_RAC=1b) for input current up to 6.4-A application (the fast
compensation will only work when IADPT pin is configured less than 160 kΩ)
0b: Turn off bandwidth promotion under RSNS_RAC=1b
(Note when this bit configured as 0b, IIN_HOST DAC can be extended up to
10 A, writing IIN_HOST value higher than 10 A will be neglected, the ICHG
regulation loop will be slower to guarantee stability under 6.4-A to 10-A input
current range)
1b: Turn on bandwidth promotion under RSNS_RAC=1b <default at POR>
(Note when this bit configured as 1b, IIN_HOST DAC is clamped at 6.4 A,
writing IIN_HOST value higher than 6.4 A will be neglected, the ICHG regulation
loop will be faster within 6.4-A input current range)

Table 9-29. ChargeOption1 Register (I2C address = 30h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 CMP_REF R/W 0b Independent Comparator internal Reference
0b: 2.3 V <default at POR>
1b: 1.2 V
6 CMP_POL R/W 0b Independent Comparator output Polarity
0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal
hysteresis) <default at POR>
1b: When CMPIN is below internal threshold, CMPOUT is LOW (external
hysteresis)
5-4 CMP_DEG R/W 00b Independent comparator deglitch time, only applied to the falling edge of
CMPOUT (HIGH → LOW).
00b: Independent comparator is enabled with output deglitch time 5 µs <default
at POR>
01b: Independent comparator is enabled with output deglitch time of 2 ms
10b: Independent comparator is enabled with output deglitch time of 20 ms
11b: Independent comparator is enabled with output deglitch time of 5 sec
3 FORCE_CONV_OFF R/W 0b Force Converter Off function
When independent comparator triggers, (CMPOUT pin pulled down) converter
latches off, at the same time, CHRG_OK signal goes LOW to notify the system.
Charge current is also set to zero internally, but charge current register setting
keeps the same. To get out of converter latches off, firstly the CMPOUT should
be released to high and secondly FORCE_CONV_OFF bit should be cleared
(=0b).
0b: Disable this function <default at POR>
1b: Enable this function
2 EN_PTM R/W 0b PTM enable register bit, it will automatically reset to zero
0b: disable PTM. <default at POR>
1b: enable PTM.

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Table 9-29. ChargeOption1 Register (I2C address = 30h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
1 EN_SHIP_DCHG R/W 0b Discharge SRN for Shipping Mode. Used to discharge VBAT pin capacitor
voltage which is necessary for battery gauge device shipping mode.
When this bit is 1, discharge SRN pin down in 140 ms 20 mA. When 140 ms is
over, this bit is reset to 0b automatically. If this bit is written to 0b by host before
140 ms expires, VSYS should stop discharging immediately. Note if after 140-ms
SRN voltage is still not low enough for battery gauge device entering ship mode,
the host may need to start a new 140-ms discharge cycle.
0b: Disable shipping mode <default at POR>
1b: Enable shipping mode
0 AUTO_WAKEUP_EN R/W 0b Auto Wakeup Enable
When this bit is HIGH, if the battery is below VSYS_MIN , the device should
automatically enable 128-mA charging current for 30 mins. When the battery is
charged up above minimum system voltage, charge will terminate and the bit is
reset to LOW. The charger will also exit auto wake up if host write a new charge
current value to charge current register Reg0x14().
0b: Disable <default at POR>
1b: Enable

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9.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]

Figure 9-25. ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
7 6 5 4 3 2 1 0
PKPWR_TOVLD_DEG EN_PKPWR_II EN_PKPWR_V PKPWR_OVLD PKPWR_RELA PKPWR_TMAX[1:0]
N_DPM SYS _STAT X_STAT
R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
EN_EXTILIM EN_ICHG_IDC Q2_OCP ACX_OCP EN_ACOC ACOC_VTH EN_BATOC BATOC_VTH
HG
R/W R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-30. ChargeOption2 Register (I2C address = 33h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 PKPWR_TOVLD_DEG R/W 00b Input Overload time in Peak Power Mode
00b: 1 ms <default at POR>
01b: 2 ms
10b: 5 ms
11b: 10 ms
5 EN_PKPWR_IIN_DPM R/W 0b Enable Peak Power Mode triggered by input current overshoot
If REG0x33[5:4] are 00b, peak power mode is disabled. Upon adapter
removal, the bits are reset to 00b.
0b: Disable peak power mode triggered by input current overshoot
<default at POR>
1b: Enable peak power mode triggered by input current overshoot.
4 EN_PKPWR_VSYS R/W 0b Enable Peak Power Mode triggered by system voltage under-shoot
If REG0x33[5:4] are 00b, peak power mode is disabled. Upon adapter
removal, the bits are reset to 00b.
0b: Disable peak power mode triggered by system voltage under-shoot
<default at POR>
1b: Enable peak power mode triggered by system voltage under-shoot.
3 STAT_PKPWR_OVLD R/W 0b Indicator that the device is in overloading cycle. Write 0 to get out of
overloading cycle.
0b: Not in peak power mode. <default at POR>
1b: In peak power mode.
2 STAT_PKPWR_RELAX R/W 0b Indicator that the device is in relaxation cycle. Write 0 to get out of
relaxation cycle.
0b: Not in relaxation cycle. <default at POR>
1b: In relaxation mode.
1-0 PKPWR_TMAX[1:0] R/W 00b Peak power mode overload and relax cycle time.
00b: 20 ms <default at POR>
01b: 40 ms
10b: 80 ms
11b: 1 sec

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Table 9-31. ChargeOption2 Register (I2C address = 32h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 EN_EXTILIM R/W 1b Enable ILIM_HIZ pin to set input current limit
0b: Input current limit is set by IIN_DPM register..
1b: Input current limit is set by the lower value of ILIM_HIZ pin and
IIN_DPM register.. <default at POR>
6 EN_ICHG_IDCHG R/W 0b 0b: IBAT pin as discharge current. <default at POR>
1b: IBAT pin as charge current.
5 Q2_OCP R/W 1b Q2 OCP threshold by sensing Q2 VDS
0b: 210 mV
1b: 150 mV <default at POR>
4 ACX_OCP R/W 1b Fixed Input current OCP threshold by sensing ACP-ACN, converter
is disabled immediately when triggered non latch protection resume
switching automatically after ACX comparator release.
0b: 280 mV(RSNS_RAC=0b)/200 mV(RSNS_RAC=1b)
1b: 150 mV(RSNS_RAC=0b)/100 mV(RSNS_RAC=1b) <default at
POR>
3 EN_ACOC R/W 0b ACOC Enable
Configurable Input overcurrent (ACOC) protection by sensing the
voltage across ACP and ACN. Upon ACOC (after 250-μs blank-out
time), converter is disabled. Non latch fault, after 250-ms falling edge
de-glitch time converter starts switching automatically.
0b: Disable ACOC <default at POR>
1b: ACOC threshold 133% or 200% ILIM2
2 ACOC_VTH R/W 1b ACOC Limit
Set MOSFET OCP threshold as percentage of IIN_DPM with current
sensed from RAC.
0b: 133% of ILIM2
1b: 200% of ILIM2 <default at POR>
1 EN_BATOC R/W 1b BATOC
Battery discharge overcurrent (BATOC) protection by sensing the
voltage across SRN and SRP. Upon BATOC, converter is disabled.
0b: Disable BATOC
1b: Enable BATOC threshold 133% or 200% PROCHOT IDCHG_TH2
<default at POR>
0 BATOC_VTH R/W 1b Set battery discharge overcurrent threshold as percentage of
PROCHOT battery discharge current limit. Note when SRN and SRP
common voltage is low for 1S application, the BATOC threshold could
be derating.
0b: 133% of PROCHOT IDCHG_TH2
1b: 200% of PROCHOT IDCHG _TH2<default at POR>

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9.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]

Figure 9-26. ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
7 6 5 4 3 2 1 0
EN_HIZ RESET_REG RESET_VINDP EN_OTG EN_ICO_MOD Reserved Reserved EN_OTG_BIGC
M E AP
R/W R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
Reserved EN_VBUS_VAP OTG_VAP_MO IL_AVG CMP_EN Reserved PSYS_OTG_ID
DE CHG
R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-32. ChargeOption3 Register (I2C address = 35h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 EN_HIZ R/W 0b Device HIZ Mode Enable
When the charger is in HIZ mode, the device draws minimal quiescent
current. With VBUS above UVLO. REGN LDO stays on, and system
powers from battery.
0b: Device not in HIZ mode <default at POR>
1b: Device in HIZ mode
6 RESET_REG R/W 0b Reset Registers
All the registers are reset to POR default setting except the VINDPM
register.
0b: Idle <default at POR>
1b: Reset all the registers to default values. After reset, this bit goes back
to 0.
5 RESET_VINDPM R/W 0b Reset VINDPM Threshold
0b: Idle
1b: Converter is disabled to measure VINDPM threshold. After VINDPM
measurement is done, this bit goes back to 0 and converter starts.
4 EN_OTG R/W 0b OTG Mode Enable
Enable device in OTG mode when OTG/VAP/FRS pin is HIGH.
0b: Disable OTG <default at POR>
1b: Enable OTG mode to supply VBUS from battery.
3 EN_ICO_MODE R/W 0b Enable ICO Algorithm
0b: Disable ICO algorithm. <default at POR>
1b: Enable ICO algorithm.
2 Reserved R/W 1b Reserved
1 Reserved R/W 0b Reserved
0 EN_OTG_BIGCAP R/W 0b Enable OTG compensation for VBUS effective capacitance larger than 33
μF
0b: Disable OTG large VBUS capacitance compensation (Recommended
for VBUS effective capacitance smaller than 33 μF) <default at POR>
1b: Enable OTG large VBUS capacitance compensation (Recommended
for VBUS effective capacitance larger than 33 μF)

Table 9-33. ChargeOption3 Register (I2C address = 34h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R/W 0b Reserved

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Table 9-33. ChargeOption3 Register (I2C address = 34h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
6 EN_VBUS_VAP R/W 0b Enable the VBUS VAP for VAP operation mode 2&3
0b: Disabled <default at POR>
1b: Enabled
5 OTG_VAP_MODE R/W 1b The selection of the external OTG/VAP/FRS pin control. Don't
recommend to change pin control after OTG/VAP/FRS pin is pulled high.
0b: the external OTG/VAP/FRS pin controls the EN/DIS VAP mode
1b: the external OTG/VAP/FRS pin controls the EN/DIS OTG mode
<default at POR>
4-3 IL_AVG R/W 10b Converter inductor average current clamp. It is recommended to choose
the smallest option which is higher than maximum possible converter
average inductor current.
00b: 6A
01b: 10A
10b: 15A <default at POR>
11b: Disabled
2 CMP_EN R/W 1b Enable Independent Comparator with effective low.
0b: Disabled
1b: Enabled <default at POR>
1 Reserved R/W 0b Reserved
0 PSYS_OTG_IDCHG R/W 0b PSYS function during OTG mode.
0b: PSYS as battery discharge power minus OTG output power <default
at POR>
1b: PSYS as battery discharge power only

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9.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]

To set VSYS_TH1 threshold to trigger discharging VBUS in VAP mode, write a 6-bit Vmin Active Protection
register command (REG0x37<7:2>()) using the data format listed in Figure 9-27, Table 9-34, and Table 9-35.
The charger Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is below the
thresholds. The threshold range from 3.2 V (000000b) to 9.5 V (111111b) for 2s~5s and 3.2 V (000000b) to 3.9
V (000111b) for 1S, with 100-mV step resolution. There is a fixed DC offset which is 3.2 V. Under 1S application
writing beyond 3.9 V will be ignored. For example 000111b and xxx111b result in same VSYS_TH1 setting 3.9
V. Upon POR, the VSYS_TH1 threshold to trigger VBUS discharge in VAP mode is 3.4 V (000010b) for 1S and
6.400 V (100000b) for 2s~5s.
Figure 9-27. ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
7 6 5 4 3 2 1 0
ILIM2_VTH ICRIT_DEG PROCHOT_VI
NDPM_80_90
R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
VSYS_TH1 INOM_DEG LOWER_PRO
CHOT_VINDP
M
R/W R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-34. ProchotOption0 Register (I2C address = 37h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-3 ILIM2_VTH R/W 01001b ILIM2 Threshold
5 bits, percentage of IIN_DPM in 0x22H. Measure current between ACP and
ACN.
Trigger when the current is above this threshold:
00001b - 11001b: 110% - 230%, step 5%
11010b - 11110b: 250% - 450%, step 50%
11111b: Out of Range (Ignored)
Default 150%, or 01001
2-1 ICRIT_DEG R/W 01b ICRIT Deglitch time
ICRIT threshold is set to be 110% of ILIM2.
Typical ICRIT deglitch time to trigger PROCHOT.
00b: 15 µs
01b: 100 µs <default at POR>
10b: 400 µs (max 500 μs)
11b: 800 µs (max 1 ms)
0 PROCHOT_VINDPM_ R/W 0b Lower threshold of the PROCHOT_VINDPM comparator
80_90 When REG0x33[0]=1, the threshold of the PROCHOT_VINDPM comparator is
determined by this bit setting.
0b: 83% of VinDPM threshold <default at POR>.
1b: 91% of VinDPM threshold

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Table 9-35. ProchotOption0 Register (I2C address = 36h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-2 VSYS_TH1 R/W 100000b( VSYS Threshold to trigger discharging VBUS in VAP mode.
2S~5s) Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is
000010b( below the thresholds. There is a fixed DC offset which is 3.2 V.
1S) 2S - 5s battery (Default: 6.4 V)
000000b- 111111b: 3.2 V - 9.5 V with 100-mV step size.
1S battery (Default: 3.4 V)
XXX000b - XXX111b: 3.2 V - 3.9 V with 100-mV step size.
1 INOM_DEG R/W 0b INOM Deglitch Time
INOM is always 10% above IIN_DPM register setting. Measure current between
ACP and ACN.
Trigger when the current is above this threshold.
0b: 1 ms(max) <default at POR>
1b: 60 ms(max)
0 LOWER_PROCHOT_ R/W 1b Enable the lower threshold of the PROCHOT_VINDPM comparator
VINDPM 0b: the threshold of the PROCHOT_VINDPM comparator follows the same
VINDPM REG0x3D() setting.
1b: the threshold of the PROCHOT_VINDPM comparator is lower and determined
by PROCHOT_VINDPM_80_90 bit setting. <default at POR>

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9.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]

Figure 9-28. ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
7 6 5 4 3 2 1 0
IDCHG_TH1 IDCHG_DEG1
R/W R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
PP_VINDPM PP_COMP PP_ICRIT PP_INOM PP_IDCHG1 PP_VSYS PP_BATPRES PP_ACOK
R/W R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

When the REG0x38h[7:0] are set to be disabled, the PROCHOT event associated with that bit will not be
reported in the PROCHOT status register REG0x22h[7:0] any more, and the PROCHOT pin will not be pulled
low any more if the event happens.
Table 9-36. ProchotOption1 Register (I2C address = 39h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-2 IDCHG_TH1 R/W 010000b IDCHG level 1 Threshold
6 bit, range, range 0 A to 64512 mA, step 1024 mA.
Measure current between SRN and SRP.
Trigger when the discharge current is above the threshold.
If the value is programmed to 000000b PROCHOT is always triggered.
Default: 16256 mA or 010000b
1-0 IDCHG_DEG1 R/W 00b IDCHG level 1 Deglitch Time
00b: 78 ms
01b: 1.25s <default at POR>
10b: 5s
11b: 20s

Table 9-37. ProchotOption1 Register (I2C address = 38h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 PP_VINDPM R/W 1b VINDPM PROCHOT Profile
When all the REG0x38[7:0] , REG0x3D[1], REG0x3C[2]bits are 0, PROCHOT
function is disabled.
0b: disable
1b: enable<default at POR>
6 PP_COMP R/W 0b Independent comparator PROCHOT Profile
When not in low power mode(Battery only), use this bit to control independent
comparator PROCHOT profiles.
When in low power mode(Battery only), this bit will lose controllability
to independent comparator PROCHOT profiles. Need to use
EN_PROCHOT_LPWR to enable independent comparator and its PROCHOT
profile.
0b: disable <default at POR>
1b: enable
5 PP_ICRIT R/W 1b ICRIT PROCHOT Profile
0b: disable
1b: enable <default at POR>
4 PP_INOM R/W 0b INOM PROCHOT Profile
0b: disable <default at POR>
1b: enable

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Table 9-37. ProchotOption1 Register (I2C address = 38h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
3 PP_IDCHG1 R/W 0b IDCHG1 PROCHOT Profile
0b: disable <default at POR>
1b: enable
2 PP_VSYS R/W 0b VSYS PROCHOT Profile
0b: disable <default at POR>
1b: enable
1 PP_BATPRES R/W 0b Battery removal PROCHOT Profile
0b: disable <default at POR>
1b: enable (one-shot falling edge triggered)
If BATPRES is enabled in PROCHOT after the battery is removed, it will
immediately send out one-shot PROCHOT pulse.
0 PP_ACOK R/W 0b Adapter removal PROCHOT Profile
0b: disable <default at POR>
1b: enable
EN_LWPWR= 0b to assert PROCHOT pulse after adapter removal.
If PP_ACOK is enabled in PROCHOT after the adapter is removed, it will be
pulled low.

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9.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]

Figure 9-29. ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
7 6 5 4 3 2 1 0
ADC_CONV ADC_START ADC_FULLSCA Reserved
LE
R/W R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
EN_ADC_CMPI EN_ADC_VBU EN_ADC_PSY EN_ADC_IIN EN_ADC_IDCH EN_ADC_ICHG EN_ADC_VSY EN_ADC_VBAT
N S S G S
R/W R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC
is disabled in low power mode. Before enabling ADC, low power mode should be disabled first.
Table 9-38. ADCOption Register (I2C address = 3Bh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 ADC_CONV R/W 0b Typical each ADC channel conversion time is 25 ms maximum. Total ADC
conversion time is the product of 25 ms and enabled channel counts.
0b: One-shot update. Do one set of conversion updates to registers
REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C() after
ADC_START = 1.
1b: Continuous update. Do a set of conversion updates to registers
REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C()every 1
sec.
6 ADC_START R/W 0b 0b: No ADC conversion
1b: Start ADC conversion. After the one-shot update is complete, this bit
automatically resets to zero
5 ADC_FULLSCALE R/W 1b ADC input voltage range adjustment for PSYS and CMPIN ADC Channels.
2.04-V full scale holds 8 mV/LSB resolution and 3.06-V full scale holds 12
mV/LSB resolution
0b: 2.04 V
1b: 3.06 V <default at POR>(Not accurate for REGN<6-V application (VBUS
& VSYS< 6V))
4-0 Reserved R/W 00000b Reserved

Table 9-39. ADCOption Register (I2C address = 3Ah) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 EN_ADC_CMPIN R/W 0b 0b: Disable <default at POR>
1b: Enable
6 EN_ADC_VBUS R/W 0b 0b: Disable <default at POR>
1b: Enable
5 EN_ADC_PSYS R/W 0b 0b: Disable <default at POR>
1b: Enable
4 EN_ADC_IIN R/W 0b 0b: Disable <default at POR>
1b: Enable
3 EN_ADC_IDCHG R/W 0b 0b: Disable <default at POR>
1b: Enable
2 EN_ADC_ICHG R/W 0b 0b: Disable <default at POR>
1b: Enable

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Table 9-39. ADCOption Register (I2C address = 3Ah) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
1 EN_ADC_VSYS R/W 0b 0b: Disable <default at POR>
1b: Enable
0 EN_ADC_VBAT R/W 0b 0b: Disable <default at POR>
1b: Enable

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9.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]

Figure 9-30. ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
7 6 5 4 3 2 1 0
Reserved EN_Dither Reserved PP_VBUS_VAP STAT_VBUS_V
AP
R/W R/W R/W R/W R

7 6 5 4 3 2 1 0
IDCHG_DEG2 IDCHG_TH2 PP_IDCHG2 STAT_IDCHG2 STAT_PTM
R/W R/W R/W R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-40. ChargeOption4 Register (I2C address = 3Dh) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-5 Reserved R/W 000b Reserved
4-3 EN_DITHER R/W 00b Frequency Dither configuration
00b: Disable Dithering<default at POR>
01b: Dither 1X (±2% Fs dithering range)
10b: Dither 2X (±4% Fs dithering range)
11b: Dither 3X (±6% Fs dithering range)
2 Reserved R/W 0b Reserved
1 PP_VBUS_VAP R/W 0b VBUS_VAP PROCHOT Profile
0b: disable <default at POR>
0b: enable
0 STAT_VBUS_VAP R 0b PROCHOT profile VBUS_VAP status bit. The status is latched until a read
from host.
0b: Not triggered <default at POR>
1b: Triggered

Table 9-41. ChargeOption4 Register (I2C address = 3Ch) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 IDCHG_DEG2 R/W 01b Battery discharge current limit 2 deglitch time(minimum value)
00b: 100 μs
01b: 1.6 ms <default at POR>
10b: 6 ms
11b: 12 ms
5-3 IDCHG_TH2 R/W 001b Battery discharge current limit2 based on percentage of IDCHG_TH1.
Note IDCHG_TH2 setting higher than 32256 mA should lose accuracy
de-rating between target value and 32256 mA. (Recommend not to set
higher than 20 A for 1S OTG boost operation)
000b: 125% IDCHG_TH1
001b: 150% IDCHG_TH1 <default at POR>
010b: 175% IDCHG_TH1
011b: 200% IDCHG_TH1
100b: 250% IDCHG_TH1
101b: 300% IDCHG_TH1
110b: 350% IDCHG_TH1
111b: 400% IDCHG_TH1
2 PP_IDCHG2 R/W 0b IDCHG2 PROCHOT Profile
0b: disable <default at POR>
1b: enable

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Table 9-41. ChargeOption4 Register (I2C address = 3Ch) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
1 STAT_IDCHG2 R 0b The status is latched until a read from host.
0b: Not triggered <default at POR>
1b: Triggered
0 STAT_PTM R 0b PTM operation status bit monitor
0b: Not in PTM Operation <default at POR>
1b: In PTM Operation

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9.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
To set the VAP VBUS PROCHOT trigger threshold, write a 7-bit Vmin Active Protection register command
(REG0x3F[7:1]) using the data format listed in Figure 9-31 and Table 9-42. The charger provides VAP mode
VBUS PROCHOT trigger threshold range from 3.2 V (0000000b) to 15.9 V (1111111b), with 100-mV step
resolution. There is a fixed offset of 3.2 V. Upon POR, the VBUS PROCHOT trigger threshold is 3.2 V
(0000000b).
To set VSYS_TH2 Threshold to assert STAT_VSYS, write a 6-bit Vmin Active Protection register command
(REG0x3E[7:2]) using the data format listed in Figure 9-31 and Table 9-43. The charger Measure on VSYS with
fixed 5-µs deglitch time. Trigger when SYS pin voltage is below the thresholds. The threshold range from 3.2
V (000000b) to 9.5 V (111111b) for 2s~5s and 3.2 V (000000b) to 3.9 V (000111b) for 1S, with 100-mV step
resolution. There is a fixed DC offset which is 3.2 V. Under 1S application writing beyond 3.9 V will be ignored.
For example, xxx111b and 000111b result in same VSYS_TH2 setting 3.9 V. Upon POR, the VSYS PROCHOT
trigger threshold is 3.2 V (000000b) for 1S and 5.9 V (011011b) for 2s~5s .
Figure 9-31. Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 0070h/0004h]
7 6 5 4 3 2 1 0
VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_T VBUS_VAP_TH VBUS_VAP_TH Reserved
Bit6 Bit5 Bit4 Bit3 H Bit2 Bit1 Bit0
R/W R/W

7 6 5 4 3 2 1 0
VSYS_TH2 Bit6 VSYS_TH2 Bit5 VSYS_TH2 Bit4 VSYS_TH2 Bit3 VSYS_TH2 VSYS_TH2 Bit1 EN_TH2_FOLL EN_FRS
Bit2 OW_TH1
R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-42. Vmin Active Protection Register (I2C address = 3Fh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 VBUS_VAP_TH, Bit6 R/W 0b 0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 6400 mV of VAP Mode VBUS PROCHOT trigger voltage
threshold
6 VBUS_VAP_TH, Bit5 R/W 0b 0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 3200 mV of VAP Mode VBUS PROCHOT trigger voltage
threshold
5 VBUS_VAP_TH, Bit4 R/W 0b 0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 1600 mV of VAP Mode VBUS PROCHOT trigger voltage
threshold
4 VBUS_VAP_TH, Bit3 R/W 0b 0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
1 = Adds 800 mV of VAP mode VBUS PROCHOT trigger voltage threshold
3 VBUS_VAP_TH, Bit2 R/W 0b 0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 = Adds 400 mV of VAP mode VBUS PROCHOT trigger voltage threshold
2 VBUS_VAP_TH, Bit1 R/W 0b 0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 = Adds 200 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 VBUS_VAP_TH, Bit0 R/W 0b 0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 = Adds 100 mV of VAP mode VBUS PROCHOT trigger voltage threshold
0 Reserve R/W 0b Reserve

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Table 9-43. Vmin Active Protection Register (I2C address = 3Eh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 VSYS_TH2, Bit5 R/W 0b 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 3200 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
6 VSYS_TH2, Bit4 R/W 1b(2S~5s 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
) 1 = Adds 1600 mV of VAP mode VSYS PROCHOT trigger voltage
0b(1S) threshold
5 VSYS_TH2, Bit3 R/W 1b(2S~5s 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
) 1 = Adds 800 mV of VAP mode VSYS PROCHOT trigger voltage
0b(1S) threshold
4 VSYS_TH2, Bit2 R/W 0b 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 400 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
3 VSYS_TH2, Bit1 R/W 0b(1S) 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1b(2S~5s 1 = Adds 200 mV of VAP mode VSYS PROCHOT trigger voltage
) threshold
2 VSYS_TH2, Bit0 R/W 1b 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 = Adds 100 mV of VAP mode VSYS PROCHOT trigger voltage
threshold
1 EN_VSYSTH2_FOLLOW_VS R/W 0b Enable internal VSYS_TH2 follow VSYS_TH1 setting neglecting register
YSTH1 REG37[7:2] setting
0b: disable <default at POR>
1b: enable
0 EN_FRS R/W 0b Fast Role Swap feature enable (note not recommend to change EN_FRS
during OTG operation, the FRS bit from 0 to 1 change will disable power
stage for about 200 μs (Fs = 400 kHz). HIZ mode holds higher priority, If
EN_HIZ=1b, this EN_FRS bit should be forced to 0b.
0b: disable <default at POR>
1b: enable

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9.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]

To set the OTG output voltage limit, write to REG0x07/06h() using the data format listed in Figure 9-32, Table
9-44, and Table 9-45.
The DAC is clamped in digital core at minimal 3 V and maximum 24.0 V during normal OTG operation. Any
register writing lower than the minimal or higher than the maximum will be ignored.
Figure 9-32. OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
7 6 5 4 3 2 1 0
Reserved OTG Voltage, OTG Voltage, OTG Voltage, OTG Voltage, OTG Voltage, OTG Voltage,
bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
OTG Voltage, OTG Voltage, OTG Voltage, OTG Voltage, OTG Voltage, OTG Voltage, Reserved
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-44. OTGVoltage Register (I2C address = 07h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15-14 Reserved R/W 00b Not used. 1 = invalid write.
13 OTG Voltage, bit 11 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 16384 mV of OTG voltage.
12 OTG Voltage, bit 10 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 8192 mV of OTG voltage.
11 OTG Voltage, bit 9 R/W 1b 0 = Adds 0 mV of OTG voltage.
1 = Adds 4096 mV of OTG voltage.
10 OTG Voltage, bit 8 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 2048 mV of OTG voltage.
9 OTG Voltage, bit 7 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 1024 mV of OTG voltage.
8 OTG Voltage, bit 6 R/W 1b 0 = Adds 0 mV of OTG voltage.
1 = Adds 512 mV of OTG voltage.

Table 9-45. OTGVoltage Register (I2C address = 06h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 OTG Voltage, bit 5 R/W 1b 0 = Adds 0 mV of OTG voltage.
1 = Adds 256 mV of OTG voltage.
6 OTG Voltage, bit 4 R/W 1b 0 = Adds 0 mV of OTG voltage.
1 = Adds 128 mV of OTG voltage.
5 OTG Voltage, bit 3 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 64 mV of OTG voltage.
4 OTG Voltage, bit 2 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 32 mV of OTG voltage.
3 OTG Voltage, bit 1 R/W 0b 0 = Adds 0 mV of OTG voltage.
1 = Adds 16 mV of OTG voltage.
2 OTG Voltage, bit 0 R/W 1b 0 = Adds 0 mV of OTG voltage.
1 = Adds 8 mV of OTG voltage.

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Table 9-45. OTGVoltage Register (I2C address = 06h) Field Descriptions (continued)
BIT FIELD TYPE RESET DESCRIPTION
1-0 Reserved R/W 00b Not used. Value Ignored.

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9.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]

To set the OTG output current limit, write to REG0x09() using the data format listed in Figure 9-33 and Table
9-46.
Figure 9-33. OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
7 6 5 4 3 2 1 0
Reserved OTG Current OTG Current OTG Current OTG Current OTG Current OTG Current OTG Current
set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit
6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-46. OTGCurrent Register (I2C address = 09h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R/W 0b Not used. 1 = invalid write.
6 OTG Current set by host, bit 6 R/W 0b 0 = Adds 0 mA of OTG current.
1 = Adds 3200 mA of OTG current.
5 OTG Current set by host, bit 5 R/W 1b 0 = Adds 0 mA of OTG current.
1 = Adds 1600 mA of OTG current.
4 OTG Current set by host, bit 4 R/W 1b 0 = Adds 0 mA of OTG current.
1 = Adds 800 mA of OTG current.
3 OTG Current set by host, bit 3 R/W 1b 0 = Adds 0 mA of OTG current.
1 = Adds 400 mA of OTG current.
2 OTG Current set by host, bit 2 R/W 1b 0 = Adds 0 mA of OTG current.
1 = Adds 200 mA of OTG current.
1 OTG Current set by host, bit 1 R/W 0b 0 = Adds 0 mA of OTG current.
1 = Adds 100 mA of OTG current.
0 OTG Current set by host, bit 0 R/W 0b 0 = Adds 0 mA of OTG current.
1 = Adds 50 mA of OTG current.

Table 9-47. OTGCurrent Register (I2C address = 08h) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 Reserved R/W 00000000b Not used. Value Ignored.

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9.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]

To set the input voltage limit, write a 16-bit InputVoltage register command (REG0x0B/0A()) using the data
format listed in Figure 9-34, Table 9-48, and Table 9-49.
If the input voltage drops more than the InputVoltage register allows, the device enters VINDPM and reduces the
charge current. The default setting is 1.28 V below the no-load VBUS voltage. There is a fixed DC offset 3.2 V
for all codes.
Figure 9-34. InputVoltage Register (I2C address = 0B/0Ah) [reset = VBUS-1.28V]
7 6 5 4 3 2 1 0
Reserved Input Voltage, Input Voltage, Input Voltage, Input Voltage, Input Voltage, Input Voltage,
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 0
Input Voltage, Input Voltage, Reserved
bit 1 bit 0
R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-48. InputVoltage Register (I2C address = 0Bh) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-6 Reserved R/W 00b Not used. 1 = invalid write.
5 Input Voltage, bit 7 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 8192 mV of input voltage.
4 Input Voltage, bit 6 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 4096 mV of input voltage.
3 Input Voltage, bit 5 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 2048 mV of input voltage.
2 Input Voltage, bit 4 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 1024 mV of input voltage.
1 Input Voltage, bit 3 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 512 mV of input voltage.
0 Input Voltage, bit 2 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 256 mV of input voltage.

Table 9-49. InputVoltage Register (I2C address = 0Ah) Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Input Voltage, bit 1 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 128 mV of input voltage.
6 Input Voltage, bit 0 R/W 0b 0 = Adds 0 mV of input voltage.
1 = Adds 64 mV of input voltage
5-0 Reserved R/W 000000b Not used. Value Ignored.

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9.6.22 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]

To set the nominal or typical input current limit based on the adapter rated current. Write a 7-bit IIN_HOST
register command using the data format listed below.
When using a 10-mΩ sense resistor (RSNS_RAC=0b), the charger provides a nominal input-current limit range
of 50 mA to 6350 mA, with 50-mA resolution. The upper boundary is implemented through DAC clamp, writing
value higher than limitation will be neglected. The lower boundary is implemented through 50-mA offset at code
0. Note this offset is only applied to code 0, not applied to other codes. The default nominal input current limit is
3.25 A. Upon adapter removal, the input current limit is reset to the default value of 3.25 A.
When using a 5-mΩ sense resistor (RSNS_RAC=1b) referring to Section 9.3.5, the input-current limit range can
be found under certain IADPT pin, EN_FAST_5MOHM bit status. The lower boundary is implemented through
100-mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default current
limit is 3.2 A. Due to the USB current setting requirement, the register setting specifies the maximum current
instead of the typical current. Upon adapter removal, the nominal input current limit is reset to the default value
of 3.2 A.
To set the maximum input current limit based on adapter rated current. Additional 100-mA (10-mΩ sense
resistor)/200-mA (5-mΩ sense resistor) offset should be added based on above nominal input current limit to
obtain the maximum input current limit.
The ACP and ACN pins are used to sense RAC with the default value of 5 mΩ. For a 10-mΩ sense resistor, a
larger sense voltage is given and a better regulation accuracy, but at the cost of higher conduction loss.
Instead of using the internal IIN_DPM loop, the user can build up an external input current regulation loop and
have the feedback signal on the ILIM_HIZ pin.
In order to disable ILIM_HIZ pin, the host can write EN_EXTILIM=0b to disable ILIM_HIZ pin, or pull ILIM_HIZ
pin above 4.0 V.
Figure 9-35. IIN_HOST Register (I2C address = 0F/0Eh) [reset = 4100h]
7 6 5 4 3 2 1 0
Reserved Input Current Input Current Input Current Input Current Input Current Input Current Input Current
set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit
6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-50. IIN_HOST Register With 5-mΩ Sense Resistor (I2C address = 0Fh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R/W 0b Not used. 1 = invalid write.
6 Input Current set by host, bit 6 R/W 0b 0 = Adds 0 mA of input current.
1 = Adds 6400 mA of input current.
5 Input Current set by host, bit 5 R/W 1b 0 = Adds 0 mA of input current.
1 = Adds 3200 mA of input current.
4 Input Current set by host, bit 4 R/W 0b 0 = Adds 0 mA of input current.
1 = Adds 1600 mA of input current.
3 Input Current set by host, bit 3 R/W 0b 0 = Adds 0 mA of input current.
1 = Adds 800 mA of input current.
2 Input Current set by host, bit 2 R/W 0b 0 = Adds 0 mA of input current.
1 = Adds 400 mA of input current.

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Table 9-50. IIN_HOST Register With 5-mΩ Sense Resistor (I2C address = 0Fh) Field Descriptions
(continued)
BIT FIELD TYPE RESET DESCRIPTION
1 Input Current set by host, bit 1 R/W 0b 0 = Adds 0 mA of input current.
1 = Adds 200 mA of input current.
0 Input Current set by host, bit 0 R/W 0b 0 = Adds 0 mA of input current.
1 = Adds 100 mA of input current.

Table 9-51. IIN_HOST Register With 5-mΩ Sense Resistor (I2C address = 0Eh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-0 Reserved R 00000000 Not used. Value Ignored.
b

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9.6.23 ID Registers
9.6.23.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
Figure 9-36. ManufactureID Register (I2C address = 2Eh) [reset = 40h]
7-0
Manufacturer ID
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-52. ManufactureID Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION (READ ONLY)
7-0 MANUFACTURE_ID R 40h 40h

9.6.23.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D6h]

Figure 9-37. Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D6h]
7-0
DEVICE_ID
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-53. Device ID (DeviceAddress) Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-0 DEVICE_ID R BQ25731: 11 01 0110b (D6h) BQ25731: 11 01 0110b (D6h)

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

The BQ2573xEVM evaluation module (EVM) is a complete charger module for evaluating the BQ25731. The
application curves were taken using the BQ2573xEVM.
As shown in Figure 10-1, at the charger VSYS terminal, a minimum 7-μF effective MLCC capacitance (7 × 10-μF
0603 package MLCC) is suggested for a 45-W to 65-W adapter, and two more 10-μF MLCC capacitors are
needed when power reaches 90 W. Overall 50-μF effective capacitance on VSYS net is necessary (POSCAP
is preferred). These capacitors do not have to be placed at the charger VSYS output terminal; all capacitors
connected to VSYS net can be counted including the input capacitor of the next stage converters.
10.2 Typical Application
4.7uH
RAC=5m
/10m RSR=5m/10m
VBUS
 Q2 BATT
Q1 Q3 Q4
10nF 1nF (1-5s)
1uF 6x10uF 47nF 47nF 7x10uF 2x33uF 2x10uF
0.1uF
1.0uF
1x33uF
(Optional)   33nF HIDRV1 HIDRV2
SW2
SW1

10 10
LODRV2
BTST1

BTST2
LODRV1

SYS
10nF
33nF ACN
ACP SRP
10
VDDA SRN
380k
REGN REGN
ILIM_HIZ
1uF 2.2–3.3uF
220k VDDA

VBUS
BQ25731 PGND
350k
CELL_BATPRES
4.7nF 40.2k  250k 
COMP1
33pF
COMP2 IADPT
15pF IBAT
CHRG_OK

OTG/VAP

 
CMPOUT

680pF 15k PSYS 30k 100pF 100pF 191k

CMPIN


SDA

SCL

10k
3.3V or 1.8V PROCHOT

To Host 10k
10k
10k
3.3V or 1.8V 10k

Host
(I2C)

Figure 10-1. Application Diagram of BQ25731 with Non Power Path

10.2.1 Design Requirements

DESIGN PARAMETER EXAMPLE VALUE
Input Voltage(2) 3.5 V < Adapter Voltage < 26V
Input Current Limit (2) 3.2 A for 65-W adapter
Battery Charge Voltage(1) 8400 mV for 2s battery

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DESIGN PARAMETER EXAMPLE VALUE

Battery Charge Current(1) 3072 mA for 2s battery
Minimum System Voltage(1) 6600 mV for 2s battery

(1) Refer to battery specification for settings.

(2) Refer to adapter specification for settings for Input Voltage and Input Current Limit.

10.2.2 Detailed Design Procedure

The parameters are configurable using the evaluation software. The simplified application circuit (see Figure
10-1, as the application diagram) shows the minimum component requirements. Inductor, capacitor, and
MOSFET selection are explained in the rest of this section. Refer to the EVM user's guide for the complete
application schematic.
10.2.2.1 Input Snubber and Filter for Voltage Spike Damping
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VBUS pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent overvoltage event on VBUS pin.
There are several methods to damp or limit the overvoltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the overvoltage level to an IC safe level.
However these two solutions may not save cost or have small size.
A cost effective and small size solution is shown in Figure 10-2. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used
for reverse voltage protection for VBUS pin. C2 is VBUS pin decoupling capacitor and it should be placed as
close as possible to VBUS pin. C2 value should be less than C1 value so R1 can dominate the equivalent ESR
value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when
adapter hot plug-in. R2 and C2 should have 10-µs time constant to limit the dv/dt on VBUS pin to reduce inrush
current when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle
inrush current power loss according to resistor manufacturer’s data sheet. The filter components' value always
need to be verified with real application and minor adjustments may need to fit in the real application circuit.
D1

R1(2010) R2(0805)
Adapter 2W 1W
connector VBUS pin
C1 C2
2.2mF 0.47-1mF

Figure 10-2. Input Filter

10.2.2.2 ACP-ACN Input Filter

The BQ25731 has average current mode control. The input current sensing through ACP/ACN is critical to
recover inductor current ripple. Parasitic inductance on board will generate high frequency ringing on ACP-
ACN which overwhelms converter sensed inductor current information. It is also difficult to manage parasitic
inductance created based on different PCB layout. Larger parasitic inductance will generate larger sense current
ringing which could cause the average current control loop to go into oscillation. Therefore ACP-ACN sensing
information need to be conditioned.
For real system board condition, we suggest using below circuit design to get best result and filter noise induced
from different PCB parasitic factor. With time constant of filter from 47 ns to 200 ns, the filter is effective and the
delay of on the sensed signal is small, therefore there is no concern for average current mode control. If 400-kHz
switching frequency is employed, 10 nF is recommended for CDIFF; if 800-kHz switching frequency is chosen,
then CDIFF can be left open.

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RAC
Q1

6x10uF
RACP RACN
4.99ohm 4.99ohm
10nF(0402) 1nF(0402)
CDIFF
10nF for 400kHz
CACP CACN
Open for 800kHz
33nF 33nF

ACP ACN
HIDRV1

Figure 10-3. ACN-ACP Input Filter

10.2.2.3 Inductor Selection

The BQ25731 has two selectable fixed switching frequency. Higher switching frequency allows the use of
smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current
(ICHG) plus half the ripple current (IRIPPLE):

ISAT ³ ICHG + (1/2) IRIPPLE (2)

The inductor ripple current in buck operation depends on input voltage (VIN), duty cycle (DBUCK = VOUT/VIN),
switching frequency (fS) and inductance (L):

IRIPPLE_BUCK = VIN × DBUCK× (1-DBUCK) / (fS × L) (3)

During boost operation, the duty cycle is:

DBOOST = 1 – (VIN/VBAT)
and the ripple current is:
IRIPPLE_BOOST = (VIN × DBOOST) / (fS × L)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to
16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20 – 40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
10.2.2.4 Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current (plus system current there is any system load) when duty cycle
is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS
current occurs where the duty cycle is closest to 50% and can be estimated by Equation 4:

ICIN = ICHG ´ D × (1 - D) (4)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed in front of RAC current sensing and as close as possible to the power stage half bridge MOSFETs.

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Capacitance after RAC before power stage half bridge should be limited to 10 nF + 1 nF referring to Figure 10-3
diagram. Because too large capacitance after RAC could filter out RAC current sensing ripple information. Voltage
rating of the capacitor must be higher than normal input voltage level, 25-V rating or higher capacitor is preferred
for 19-V to 20-V input voltage.
Ceramic capacitors (MLCC) show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias
voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead
to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the
manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary
to choose a higher voltage rating or nominal capacitance value in order to get the required effective capacitance
value at the operating point.
10.2.2.5 Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. To
get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed
between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum
7 pcs of 10-μF 0603 package capacitor is suggested to be placed as close as possible to Q3&Q4 half bridge
(between Q4 drain and Q3 source terminal). Total minimum output effective capacitance along VSYS distribution
line is 50 μF refers to Table 10-1. Recommend to place minimum 20-μF MLCC capacitors after the charge
current sense resistor for best stability.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias
voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead
to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the
manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary
to choose a higher voltage rating or nominal capacitance value in order to get the required capacitance value at
the operating point. Considering the 25-V 0603 package MLCC capacitance derating under 21-V to 23-V output
voltage, the recommended practical capacitors configuration at VSYS output terminal can also be found in
Table 10-1. Tantalum capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which are
recommend to be used along VSYS output distribution line to meet total minimum effective output capacitance
requirement.
Table 10-1. Minimum Output Capacitance Requirement
OUTPUT CAPACITORS vs TOTAL INPUT
65 W 90 W 130 W
POWER
Minimum Effective Output Capacitance 50 μF 50 μF 50 μF
Minimum output capacitors at charger VSYS 7*10 μF (0603 25 V MLCC) 9*10 μF (0603 25 V MLCC) 9*10 μF (0603 25 V MLCC)
output terminal
Additional output capacitors along VSYS 2*22 μF (25 V~35 V 2*22 μF (25 V~35 V 2*22 μF (25 V~35 V
distribution line POSCAP) POSCAP) POSCAP)

10.2.2.6 Power MOSFETs Selection

Four external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
integrated into the IC with 6 V of gate drive voltage. 30 V or higher voltage rating MOSFETs are preferred for
19-V to 20-V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.

FOMtop = RDS(on) · QGD; FOMbottom = RDS(on) · QG (5)

The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.

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The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as
an example the power loss is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-
resistance (RDS(ON)_top), input voltage (VIN), switching frequency (fS), turn-on time (ton) and turn-off time (toff):

Ptop =Pcon_top+Psw_top (6)

Pcon_top =D · IL_RMS 2 · RDS(on)_top; (7)

IL_RMS 2=IL_DC 2+Iripple 2/12 (8)

• IL_DC is the average inductor DC current under buck mode;

• Iripple is the inductor current ripple peak-to-peak value;

Psw_top =PIV_top+PQoss_top+PGate_top; (9)

The first item Pcon_top represents the conduction loss which is straight forward. The second term Psw_top
represents the multiple switching loss items in top MOSFET including voltage and current overlap losses
(PIV_top), MOSFET parasitic output capacitance loss (PQoss_top) and gate drive loss (PGate_top). To calculate
voltage and current overlap losses (PIV_top):

PIV_top =0.5x VIN · Ivalley · ton· fS+0.5x VIN · Ipeak · toff · fS (10)

Ivalley =IL_DC- 0.5 · Iripple (inductor current valley value); (11)

Ipeak =IL_DC+ 0.5 · Iripple (inductor current peak value); (12)

• ton is the MOSFET turn-on time that VDS falling time from VIN to almost zero (MOSFET turn on conduction
voltage);
• toff is the MOSFET turn-off time that IDS falling time from Ipeak to zero;
The MOSFET turn-on and turn-off times are given by:

QSW Q
t on = , t off = SW
Ion Ioff (13)

where Qsw is the switching charge, Ion is the turn-on gate driving current, and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):

Qsw =QGD+QGS (14)

Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:

VREGN - Vplt Vplt

Ion = , Ioff =
Ron Roff (15)

To calculate top MOSFET parasitic output capacitance loss (PQoss_top):

PQoss_top =0.5 · VIN· Qoss · fS (16)

• Qoss is the MOSFET parasitic output charge which can be found in MOSFET datasheet;
To calculate top MOSFET gate drive loss (PGate_top):

PGate_top =VIN· QGate_top · fS (17)

• QGate_top is the top MOSFET gate charge which can be found in MOSFET datasheet;

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• Note here VIN is used instead of real gate drive voltage 6 V because, the gate drive 6 V is generated based
on LDO from VIN under buck mode, the total gate drive related loss are all considered when VIN is used for
gate drive loss calculation .
The bottom-side MOSFET loss also includes conduction loss and switching loss:

Pbottom =Pcon_bottom+Psw_bottom (18)

Pcon_bottom =(1 - D) · IL_RMS 2 · RDS(on)_bottom; (19)

Psw_bottom =PRR_bottom+PDead_bottom+PGate_bottom; (20)

The first item Pcon_bottom represents the conduction loss which is straight forward. The second term Psw_bottom
represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (PRR_bottom),
Dead time body diode conduction loss (PDead_bottom) and gate drive loss (PGate_bottom). The detail calculation can
be found below:

PRR_bottom=VIN · Qrr · fS (21)

• Qrr is the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;

PDead_bottom=VF · Ivalley · fS · tdead_rise+VF · Ipeak · fS · tdead_fall (22)

• VF is the body diode forward conduction voltage drop;

• tdead_rise is the SW rising edge deadtime between top and bottom MOSFETs which is around 40 ns;
• tdead_fall is the SW falling edge deadtime between top and bottom MOSFETs which is around 30 ns;
PGate_bottom can follow the same method as top MOSFET gate drive loss calculation approach refer to Equation
17.

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10.2.3 Application Curves

CH1: VBUS CH1: VBUS

CH2: VDDA CH2: VDDA

CH3: CHRG_OK CH3: CHRG_OK

CH4: VSYS CH4: VSYS

2-cell without battery 2-cell without battery

Figure 10-4. Power Up From 20 V Figure 10-5. Power Up From 5 V

CH1: VBUS

CH1: VBUS

CH2: SW1
CH2: SW1
CH3: SW2

CH3: SW2

CH4: VSYS with 9Vos

CH4: IL

3-cell VBAT = 10 V VBUS 5 V to 20 V

Figure 10-6. Power Off From 12 V Figure 10-7. Line Regulation

CH2: SW1
CH1: HIDRV1

CH2: SW1

CH3: LODRV1
CH3: SW2

CH1: IL
CH4: IL

VBUS = 20 V, VSYS = 10 V, ISYS = 200 mA VBUS = 20 V, VSYS = 10 V, ISYS = 2 A

Figure 10-8. PFM Operation Figure 10-9. PWM Operation

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CH2: SW2

CH2: SW1

CH1: HIDRV2 CH3: SW2

CH3: LODRV2

CH4: IL CH4: IL

VBUS = 5 V, VBAT = 10 V VBUS = 12 V, VBAT = 12 V

Figure 10-10. Switching During Boost Mode Figure 10-11. Switching During Buck Boost Mode

CH2:IIN
CH2: IIN

CH3: ISYS CH3:ISYS

CH4:IBAT

CH4: IBAT

VBUS = 20 V/3.25 A, VBAT = 7.5 V VBUS = 5 V/3.25 A, VBAT = 7.5 V

Figure 10-12. Input Current Regulation in Buck Figure 10-13. Input Current in Boost Mode
Mode

CH1: EN_OTG
CH1: SCL

CH2: VBUS
CH2: VBUS

CH3: SW2

VBUS = 5 V VBAT = 10 V, VBUS 5 V to 20 V, IOTG = 500 mA

Figure 10-14. OTG Power Up from 8-V Battery Figure 10-15. OTG Voltage Ramp Up

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CH2: VBUS
CH1: SCL

CH2: VBUS

CH3: SW2 CH3: IVBUS

Figure 10-16. OTG Power Off VBAT = 10 V, VBUS = 20 V

Figure 10-17. OTG Load Transient

VBUS = 20 V IIN_DPM = 2 A ILIM2_VTH = 200%

TMAX = 20 ms TOVLD = 10 ms VBAT = 12.8 V
ISYS = 1 to 6 A ICHG = 0 A

Figure 10-18. Peak Power Mode IBUS Trigger

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11 Power Supply Recommendations

The valid adapter range is from 3.5 V (VVBUS_CONVEN) to 26 V with at least 500-mA current rating. When
CHRG_OK goes HIGH, the system is powered from adapter through the charger. When adapter is removed, the
system is connected to battery.

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12 Layout
12.1 Layout Guidelines
Proper layout of the components to minimize high frequency current path loop (see Section 12.2) is important
to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout
priority list for proper layout.
Table 12-1. PCB Layout Guidelines
RULES COMPONENTS FUNCTION IMPACT GUIDELINES

1 PCB layer stack up Thermal, efficiency, Multi- layer PCB is suggested. Allocate at least one ground layer.
signal integrity The BQ257XXEVM uses a 4-layer PCB (top layer, ground layer,
signal layer and bottom layer).

2 CBUS, RAC, Q1, Input loop High frequency VBUS capacitors, RAC, Q1 and Q2 form a small loop 1. It is best
Q2 noise, ripple to put them on the same side. Connect them with large copper to
reduce the parasitic resistance. Move part of CBUS to the other
side of PCB for high density design. After RAC before Q1 and
Q2 power stage recommend to put 10 nF + 1 nF (0402 package)
decoupling capacitors as close as possible to IC to decoupling
switching loop high frequency noise.

3 RAC, Q1, L1, Q4 Current path Efficiency The current path from VBUS to VSYS, through RAC, Q1, L1, Q4,
has low impedance. Pay attention to via resistance if they are not
on the same side. The number of vias can be estimated as 1 to
2A/via for a 10-mil via with 1 oz. copper thickness.

4 CSYS, Q3, Q4 Output loop High frequency VSYS capacitors, Q3 and Q4 form a small loop 2. It is best to
noise, ripple put them on the same side. Connect them with large copper to
reduce the parasitic resistance. Move part of CSYS to the other
side of PCB for high density design.

5 RSR Current path Efficiency, battery Place RSR near the battery terminal. The current path from VBAT
voltage detection to VSYS, through RSR, has low impedance. Pay attention to via
resistance if they are not on the same side. The device detects
the battery voltage through SRN near battery terminal.

6 Q1, Q2, L1, Q3, Power stage Thermal, efficiency Place Q1, Q2, L1, Q3 and Q4 next to each other. Allow
Q4 enough copper area for thermal dissipation. The copper area
is suggested to be 2x to 4x of the pad size. Multiple thermal
vias can be used to connect more copper layers together and
dissipate more heat.

7 RAC, RSR Current sense Regulation accuracy Use Kelvin-sensing technique for RAC and RSR current sense
resistors. Connect the current sense traces to the center of the
pads, and run current sense traces as differential pairs.

8 Small capacitors IC bypass caps Noise, jittering, Place VBUS cap, VCC cap, REGN caps near IC.
ripple

9 BST capacitors HS gate drive High frequency Place HS MOSFET boost strap circuit capacitor close to IC and
noise, ripple on the same side of PCB board. Capacitors SW1/2 nodes are
recommended to use wide copper polygon to connect to power
stage and capacitors BST1/2 node are recommended to use at
least 8mil trace to connected to IC BST1/2 pins.

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Table 12-1. PCB Layout Guidelines (continued)

RULES COMPONENTS FUNCTION IMPACT GUIDELINES

10 Ground partition Measurement Separate analog ground(AGND) and power grounds(PGND) is

accuracy, regulation preferred. PGND should be used for all power stage related
accuracy, jitters, ground net. AGND should be used for all sensing, compensation
ripple and control network ground for example ACP/ACN/COMP1/
COMP2/CMPIN/CMPOUT/IADPT/IBAT/PSYS. Connect all
analog grounds to a dedicated low-impedance copper plane,
which is tied to the power ground underneath the IC exposed
pad. If possible, use dedicated COMP1, COMP2 AGND traces.
Connect analog ground and power ground together using power
pad as the single ground connection point.

12.2 Layout Example

12.2.1 Layout Example Reference Top View
Based on the above layout guidelines, the buck-boost charger layout example top view is shown below including
all the key power components.

Figure 12-1. Buck-Boost Charger Layout Reference Example Top View

12.2.2 Inner Layer Layout and Routing Example

For both input sensing resistor and charging current sensing resistor, differential sensing and routing method are
suggested and highlighted in below figure. Use wide trace for gate drive traces, minimum 15 mil trace width.
Connect all analog grounds to a dedicated low-impedance copper plane, which is tied to the power ground
underneath the IC exposed pad. Suggest using dedicated COMP1, COMP2 analog ground traces shown in
below figure.

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www.ti.com SLUSE66A – JUNE 2020 – REVISED JANUARY 2021

Figure 12-2. Buck-Boost Charger Gate Drive/Current Sensing/AGND Signal Layer Routing Example

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Product Folder Links: BQ25731
BQ25731
SLUSE66A – JUNE 2020 – REVISED JANUARY 2021 www.ti.com

13 Device and Documentation Support

13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Semiconductor and IC Package Thermal Metrics Application Report
• BQ2571x Evaluation Module User's Guide
• QFN/SON PCB Attachment Application Report
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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 BQ25731
www.ti.com SLUSE66A – JUNE 2020 – REVISED JANUARY 2021

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 7-Apr-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ25731RSNR ACTIVE QFN RSN 32 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BQ25731 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25731RSNR QFN RSN 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ25731RSNR QFN RSN 32 3000 367.0 367.0 35.0

Pack Materials-Page 2
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