EECS1010 Logic Design
Memory Basics and
Programmable Logic
Hsi-Pin Ma ⾺席彬
https://eeclass.nthu.edu.tw/course/21649
Department of Electrical Engineerin
National Tsing Hua University
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Outline
•Random-Access Memor
•Memory Decodin
•Read-Only Memor
•Programmable Logic Arra
•Programmable Array Logi
•Sequential Programmable Devices
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The Memory Hierarchy
[https://www.semianalysis.com/p/on-device-ai-double-edged-sword]
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Category of Memory Arrays
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory
(CAM)
Read/Write Memory Read Only Memory Shift registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)
1. Static RAM (SRAM) 1. Serial In Parallel Out (SIPO) 1. First In First Out (FIFO)
2. Dynamic RAM (DRAM) 2. Parallel In Serial Out (PISO) 2. Last In Fast Out (LIFO)
1. Mask ROM
2. Programmable ROM (PROM) (fuses)
3. Erasable Programmable ROM (EPROM)
4. Electrically Erasable Programmable ROM (EEPROM)
5. Flash ROM
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Memory Unit
• A collection of storage cells together with associated
circuits needed to transfer information in and out of
storage
• RAM: Random-Access Memor
– Volatile (memory units that lose stored information when power is
turned off
– To accept new information for storage to be available later for us
– read/write operatio
• ROM: Read-Only Memor
– Nonvolatil
– The information inside can not be altered by writin
– Programmable devices are speci ed by some hardware procedure
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Random-Access Memory
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Random-Access Memory
• Characteristic
– The time it takes to transfer data to or from any desired location is
always the same
– A memory unit stored binary information in groups of bits (words
– The size of the RAM is 2k x n bits. It has k address lines, n input data
lines and n output data lines
– For a commodity RAM, 16<=k<=30, n=1, 4, 8, 16, 32 or 64
• The communication between a memory and its
environment is achieved throug
– Data input lines
– Data output lines
– Address selection line
– Control lines (read and write)
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Memory Content Array
•A memory with k-bit
address has 2k data
(depth
– (depth)x(width) memor
•eg. 1K x 16 memory
(1024x16 memory)
2k-2
2k-1
k-bit address n bits
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Memory Cell
• A memory cell virtual model (binary storage cell)
1: read, 0: write
. Storage Components 7-15
Row select
Input D Q Output
C
MC
Write enable
Hsi-Pin Ma 9
Static RAM vs. Dynamic RAM
• A memory cell (MC) can be considered as a clocked
D latch with an AND gate and an output drive
– For a static RAM (SRAM), MC is constructed by 6 transistors,
using cross-coupled inverters to serve as a latch, and
implementing the input AND gate and the output driver with
one transistor each
– For a dynamic RAM (DRAM), MC is constructed by only 1
transisto
•The latch is implemented by a capacitor.
•It needs to be refreshed periodically (read and write back).
•It has high density (therefore low cost)
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Write and Read Operation
•Write operatio
– Apply the binary address to the address line
– Apply the data bits to the data input line
– Activate the write input (0
T 8-1
•Read operatio
– Apply the binary address to the address line
TABLE 8-1 – Activate the read input (1)
Control Inputs to a Memory Chip
Chip select Read/ Write
CS R/W Memory operation
0 X None
1 0 Write to selected word
1 1 Read from selected word
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© 2008 Pearson Education, Inc.
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Timing Waveforms (1/3)
•The operation of the memory unit is controlled
by an external device such as a CP
•The access time is the time required to select a
word and read i
•The write cycle time is the time required to
complete a write operatio
•Read and write operations must be controlled
by CPU and be synchronized with an external
clock.
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Timing Waveforms (2/3)
•A write cycl Suppose the access time and cycle time do not exceed 50 ns
– T1: providing the address and input data to the memory, and
the write/read control signa
– Address bus and read/write control must stay active for 50n
– The address and data signal must remain stable for a short
time after control signal is deactivated.
activated after
address stable
CPU clock frequency 50MHz
(20ns period)
>= 50ns
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Timing Waveforms (3/3)
•A read cycle of access time < 50 ns
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Memory Decoding
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Memory Unit and Internal Construction
•A memory unit has two part
– The storage components (memory cell
– The decoding circuits to select the memory wor
•A RAM of m (2k) words and n bits per wor
– m*n binary storage cell
– Decoding circuits to select individual word
•k-to-2k decoder: address input to word lin
•Read/Write contro memory cell (BC)
•Input data/Output data
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4x4 RAM
check the decoder
with enable input
in Chapter 4
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Coincident Decoding (1/2)
•A two-dimensional selection schem
– To reduce the complexity of the decoding circuit
– To arrange the memory cells in an array that is close as
possible to square
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Coincident Decoding (2/2)
•Example: 1k-word memor
– A 10-to-1024 decode
•1024 AND gates with 10 inputs per gat
– Two 5-to-32 decoder
•2*(32 AND gates with 5 inputs per gate
•Each word in the memory is selected by the coincidence
between 1 of 32 rows and 1 of 32 columns for a total 1024
word
•Two dimensional decoding structure reduces the circuit
complexity and the cycle time of the memory
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Error Detection and Correction
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Error Detection and Correction
•Error detection and correction improve the
reliability of a memory unit
•Error detection (Parity check
– A single bit error can be detected but cannot be correcte
•Error correction (Hamming code
– Generate multiple parity check bits stored with the data
word in memor
– Read out and check a unique pattern, a syndrome
– The speci ed bit in error can be identi ed and corrected
implementing erroneous bit
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Hamming Code
•k parity bits are added to an n-bit data wor
– 2k –1 ≥ n +
– Number the bits starting from 1: bit 1, 2, 3, 4, 5 , etc
– All bit positions that are power of two are parity bit
– All other bit positions are data bits
– In general each parity bit covers all bits where the
binary AND of the parity position and the bit position
is non-zero.
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k
Hamming Code: Encoding
• Example: 8-bit data word 1100010
– Include 4 parity bits and the 8-bit word ⇒ 12 bit
2k –1 ≥ n + k, n = 8 ⇒ k =
Bit position: 10 11 1
P1 P2 P4 P8 1 0
– Calculate the parity bits: even parity ⎯ assumptio
P1 = XOR of bits (3, 5, 7, 9, 11) = 1 ⊕ 1 ⊕ 0 ⊕ 0 ⊕ 0 =
P2 = XOR of bits (3, 6, 7, 10, 11) = 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 0 =
P4 = XOR of bits (5, 6, 7, 12) = 1 ⊕ 0 ⊕ 0 ⊕ 0 =
P8 = XOR of bits (9, 10, 11, 12) = 0 ⊕ 1 ⊕ 0 ⊕ 0 =
– Store the 12-bit composite word in memory
Bit position: 10 11 1
0 1 1 1 0
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1
1
0
2
2
3
1
3
1
4
4
5
1
5
1
4
6
0
6
0
7
0
7
0
8
8
9
0
0
9
0
0
Hamming Code: Decoding
•When the 12 bits are read from the memor
– Check bits are calculated using XOR operation for even-
parit
C1 = XOR of bits (1, 3, 5, 7, 9, 11
C2 = XOR of bits (2, 3, 6, 7, 10, 11
C4 = XOR of bits (4, 5, 6, 7, 12
C8 = XOR of bits (8, 9, 10, 11, 12)
– If no error has occurre
Bit position: 1 1 1
⇒ C = C8C4C2C1 = 0000
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1
0
2
0
3
1
4
1
d
5
1
6
0
7
0
8
1
)
9
0
)
1
0
0
1
0
Hamming Code: Decoding
• One-bit erro
– error in bit
• C1 = XOR of bits (1, 3, 5, 7, 9, 11) =
• C2 = XOR of bits (2, 3, 6, 7, 10, 11) =
• C4 = XOR of bits (4, 5, 6, 7, 12) =
• C8 = XOR of bits (8, 9, 10, 11, 12) =
• C8C4C2C1 = 000
– error in bit
• C8C4C2C1 = 010
• Two-bit error can not be identi ed
– errors in bits 1 and 5
– errors in bit 4
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Example
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Single Error Correction
Double Error Detection
•Hamming cod
– It can detect and correct only a single erro
– Multiple errors may not be detected
•Hamming code + a parity bi
– It can detect double errors and correct a single error
– The additional parity bit is the XOR of all the other
bits
•E.g.: the previous 12-bit coded wor
0 0 1 1 1 0 0 1 0 1 0 0 P13 ⇒ 0 0 1 1 1 0 0 1 0 1 0 0 1 (even
parity).
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Single Error Correction
Double Error Detection
–When the word is read from memor
•If P = 0, the parity is correct; P = 1, incorrec
•Four case
1.If C = 0, P = 0, no erro
2.If C ≠ 0, P = 1, a single error that can be correcte
3.If C ≠ 0, P = 0, a double error that is detected but
cannot be correcte
4.If C = 0, P = 1, an error occurred in the P13 bit
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Read-Only Memory
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Read-Only Memory (ROM)
•ROM stores permanent binary informatio
•Once the pattern is established in the ROM, it
stays within the unit, no matter power is on or
of
•2k x n RO
– k address input line
– enable input(s
– three-state outputs
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Example
•32 x 8 ROM (25 x 8
– 5-to-32 decoder (k=5
– 32(25) outputs of the decoder are connected to each of the
eight OR gates, which have 32(25) input
– 32 x 8 internal programmable connections
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ROM Programming (1/2)
• Programmable interconnection
• close [1]: connected to high voltag
• open [0]: ground lef
• A fuse that can be blown by applying a high voltage pulse
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ROM Programming (2/2)
•ROM programming according to ROM table
using fusing
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Combinational Circuit Implementation
•The internal operation of ROM can be
interpreted in two way
– A memory contains a xed pattern of stored word
– A unit that implements a combinational circuit as sum of
minterms
•ROM: a decoder + OR gate
– a Boolean function = sum of minterm
– Ex. A7 (I4 , I3 , I2 , I1 , I0 ) = (0, 2, 3, ..., 29)
– For an n-input, m-output combinational circui
•2n x m ROM
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Design Procedure
•Determine the size of ROM
•Obtain the programming truth table of RO
•The truth table = the fuse pattern
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Example: ROM Implementation (1/2)
•A combinational circuit has 3 inputs, 6 outputs
and the truth table, construct the circuit
B0=A0, B1=0, leave only 8x4 ROM
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Example: ROM Implementation (2/2)
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Types of ROM
• Mask programmable RO
– Data is programmed by IC manufacturer
– Economical if a large quantity of the same RO
• PROM: Programmable RO
– Fuses in the ROM are blown by high-voltage puls
– Universal programmer can program PROM on tim
• EPROM: erasable PRO
– Floating gat
– The data in the ROM can be erased by UV ligh
• EEPROM: electrically erasable PRO
– Longer time is needed to write
– Flash RO
– Limited times of write operations
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Combinational PLDs
•PLD: Programmable logic devic
•Programmable two-level logi
– sum of product
– an AND array and an OR array
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Sequential Programmable Devices
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Sequential Programmable Devices
•Sequential programmable devices include both
programmable gates and ip- o
•Three major types os sequential programmable
device
– SPLD: Sequential (or simple) PL
– CPLD: Complex PL
– FPGA: Field Programmable Gate Array
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fl
D
fl
p
SPLD
•A PAL or PLA is modi ed by including a
number of ip- ops
SPLD macrocell
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fl
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CPLD
•Complex PL
– Put a lot of PLDs on a chi
– Adds wires between PLDs whose connections can be
programme
– Use fuse/EEPROM technology
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FPGA
•What is in the array? All sorts of stuff
– I/O Cells
– Logic Cells
– Memories
– Microprocessors
– Clock Management
– High Speed I/O Transceivers
– Programmable routing.
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Simple FPGA Logic Cell (1/2)
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Simple FPGA Logic Cell (2/2)
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Simple FPGA Routing Cell (1/2)
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Simple FPGA Routing Cell (2/2)
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Routed FPGA
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