BECE 102L

DIGITAL SYSTEM DESIGN

Module-II
Verilog HDL
Module-II (Verilog HDL)
Lexical Conventions, Ports and Modules, Operators, Dataflow Modelling, Gate
Level Modelling, Behavioural Modeling, Test Bench

(5 hours)
 • Introduction
• Hardware Description Languages
• Introduction to Verilog HDL
• Lexical Conventions
• Data types
• Ports and Modules
Content
• Operators
• Abstraction Levels.
• Gate Level Modelling,
• Data Flow Modelling,
• Behavioural level Modelling
• Test Bench.
Introduction
Digital IC’s are classified as
• Small Scale Integration Circuit (SSI).
• Medium Scale Integration.
• Large Scale Integration.
• Very Large Scale Integration (more than 1, 00, 000 transistors).
• Ultra Large Scale Integration.
• Smaller circuits can be verified using simple Breadboard connections.
• Highly impossible with LSI and higher integrated circuits.
• As the design becomes more and more difficult Computer Aided Design (CAD)
are evolved for the design and testing of Digital circuits.
• So CAD tools are more popular.
Introduction
• For a long time, programming languages such as FORTRAN, Pascal, and C were
being used to describe computer programs that were sequential in nature.
• Similarly, in the digital design field, designers felt the need for a standard
language to describe digital circuits. Thus, Hardware Description Languages
(HDLs) came into existence.
• Hardware description languages such as Verilog HDL and VHDL became
popular.
• Verilog HDL originated in 1983 at Gateway Design Automation. Later, VHDL
was developed under contract from DARPA.
• Both Verilog and VHDL simulators to simulate large digital circuits quickly
gained acceptance from designers.
Why HDL ???
 Fast design and better verification are possible, using HDL.
 Complex digital systems need more time for simulation, verification, synthesis, and debugging., these tasks are done
simultaneously using HDL, which will save time. The sequential execution of statements is possible in HDL.
 The different parameters, such as power, delay, and area, can be extracted using HDL.
 Using HDL, the designer can make the necessary engineering trade-offs and can develop the design in a better and
efficient way.
 The testing of large circuits was not possible because the large circuits contain lots of gates, and the response of every
gate could not be checked. HDL has evolved the testing process easy and feasible.
 The designer can develop HDL codes on hardware using PLDs, which saves time as well as cost.
 The Top-down design and hierarchical design method allow the design time, design cost, and design errors to be
reduced.
 HDL provides the timing information and allows the design to be described in the gate level and register transfer level.
 HDL allows reusability of resources. Design reuse is the process of migrating high-quality intellectual property (IP)
from one ASIC design to another. Designs can be reused for variable-width implementations using unconstrained
arrays.
 Using HDL, the designers can create tools that manipulate the design for synthesis, verification, and optimization, etc.
Introduction to Verilog HDL
• VERILOG HDL – VERIfiable LOGic HDL: Programming language used to
describe digital circuits and systems.
• HDL is a language used to describe digital system.
• The goal of an HDL is to describe and model digital systems faithfully and
accurately.
• Different HDLs are available different purpose such as Analog system design,
digital system design, and PCB design.
• The two main HDLs are Verilog and VHDL for digital system design.
• There are other, limited capability, languages such as ABEL, CUPL, and
PALASM that are tailored specifically for PALs and CPLDs.
Introduction to Verilog HDL
• Verilog Simulators:
• Commercial Simulators:
• Xilinx ISE
• Active HDL • Open Source Simulators:
• Model Sim • Verilator
• Quartus-II • Icarus Verilog
• MP Sim • GPL cver
• VeriWell
• Online Simulators:
• iverilog.com
• EDAPlayground.com
• easyeda.com
Verilog Program-Format
• All components except module, module name, and endmodule are optional and
can be mixed and matched as per design needs.
• Verilog allows multiple modules to be defined in a single file.
• The modules can be defined in any order in the file.
Module Name,
Port List, Port Declarations (if ports present)
Parameters (optional)

Declarations of wires, Data flow statements

regs and other variables (assign)

always and initial blocks.

Instantiation of lower All behavioral statements
level variables go in these blocks

Tasks and functions

endmodule statement
Module-Introduction
• Verilog uses the concept called Module.
• A module is the basic building block in Verilog.
• A module can be an element or a collection of lower-level design blocks.
• Typically, elements are grouped into modules to provide common functionality
that is used at many places in the design.
• A module provides the necessary functionality to the higher-level block
through its port interface (inputs and outputs), but hides the internal
implementation.
• This allows the designer to modify module internals without affecting the rest of
the design.
• Each module must have a name.
• Modules are designated with a key word “Module”.
Module-Introduction
• A module in Verilog consists of distinct parts.
• A module definition always begins with the keyword module and must
completed with the keyword endmodule.
• The module name, port list, port declarations, and optional parameters must come
first in a module definition.
• Port list and port declarations are present only if the module has any ports to
interact with the external environment.
• The five components within a module are - variable declarations, dataflow
statements, instantiation of lower modules, behavioral blocks, and tasks or
functions.
• These components can be in any order and at any place in the module definition.
Module Instances
• A module provides a template from which you can create actual objects.
• When a module is invoked, Verilog creates a unique object from the template.
• Each object has its own name, variables, parameters and I/ O interface.
• The process of creating objects from a module template is called
instantiation, and the objects are called instances.
Module-Format
• Example:

module <module-name> (<module-terminal-list>) ;

…
<module internals>
…
…
endmodule

• Internals of each modules are defined in 4 different ways. (Abstractions)

• The internals of the modules are hidden from environment.
• Verilog is both structural and Behavioral language.
A sample Verilog HDL Program
• Structure of Verilog Program:

// A simple example  comment line

module and2 (a, b ,c);  module name and port list
input a, b;  port declarations
output c;  port declarations
assign c = a & b;  body
endmodule  end of the module
Lexical Conventions
• Very similar to C
• Verilog is case-sensitive
• All keywords are in lowercase.
• List element separator: ,
• Statement terminator: ;
• A Verilog program is a string of tokens and keywords are classified as
• Identifiers
• Escape Identifiers
• Keywords
• Comments
• Value Set
• Numbers
• Whitespace
• Strings
Lexical Conventions-Identifier
• Identifiers are name given to objects so that they can be referenced in the
design.
• Identifiers are case sensitive
• Mymodule ≠ mymodule
• Formed from {[A-Z], [a-z], [0-9], _, $}, but .. .. can’t begin with $ or [0-9].
• Examples:
• myidentifier valid
• m_y_identifier valid
• 3my_identifier invalid
• $my_identifier invalid
• _myidentifier$ valid
Lexical Conventions-ESCAPE IDENTIFIERS
• It provides the way of including any of the printable ASCII
characteristics in an identifiers.
• It begin with back slash (\) and end with white space.
• An escaped keyword is not treated as same as the keyword.
• The identifier (\ ) begin is distinct from the identifier begin.
• myname ≠ \myname
• Some examples of escape identifiers are
• \a*b*c
• \**print value**
• \4000
Lexical Conventions-Keywords
• Keywords are predefined, special identifiers that define the language
constructs.
• All key words defined in lower case.
• Some of them are
• input, output, inout
• reg, wire, task, tri, time,
• pmos, nmos, and, or, not, wor, xnor,
• begin, parameter, buf, edge, join, medium, wait, use
• if, else, case, while, always, initial, posedge, negedge, assign
• end, endtask, endcase, endfunction, default, endtable, endmodule.
Lexical Conventions-Comments
• Two types of comments possible.
• Single Line Comment (\\).
• Example:
• A= x^y; // this is single line comment
• Multiple Line Comment (/*……*/).
• Example:
• /* this is example of multiline comment
A= x^y;
C=a+b; */
• Nesting of Comments not possible.
Lexical Conventions-Numbers
• Number Specification allowed are
• Sized numbers
• Unsized numbers
• Unknown and high-impedance values
• Negative numbers
• Underscore character and question marks used to improve readability.
• Not allowed as the first character.
• Examples:
• 12’b1111_0000_1010
• ‘?’ is the same as ‘z’ (only regarding numbers)
• 4’b10?? // the same as 4’b10zz
Lexical Conventions - Sized Numbers
• Size of Number is specified along with the number.
• General syntax: <size>’<base><number>
<size> number of bits in number (in decimal).
<number> is the number in radix.
’<base> type of number
• ’d or D for decimal (radix 10)
• ’b or B for binary (radix 2)
• ’o or O for octal (radix 8)
• ’h or H for hexadecimal (radix 16) Examples:
Examples: n’b[integer]: 1’b1 = 1
8’b1 = 000000001
4’b1111, 12’habc, 8’d255 4’b0101= 0101
n’h[integer]: 8’hA9 = 10101001
16’hf1= 0000000011110001
Lexical Conventions - Unsized Numbers
• Size of Number is not specified. Default size is at least 32 (depends on
Verilog compiler).
• Default base is decimal.
• Examples:
• 23232
• ’habc
• ’o234
Lexical Conventions – Negative Numbers
• Negative numbers can be used with negative sign (-) before size.
• Examples:
• -6’d35
• 4’d-12 // illegal
Lexical Conventions - Unknown or High Impedance Values
X or Z values:
• Unknown value: lowercase x or Uppercase X
• 4 bits in hex, 3 bits in octal, 1 bit in binary.
• High-impedance value: lowercase z or Uppercase Z
• 4 bits in hex, 3 bits in octal, 1 bit in binary.
• Examples:
• 12’h13x
• 4’hX
• 32’bz
Lexical Conventions- White spaces and Strings
Whitespace:
• Blank space (\b)
• Tab (\t)
• Newline (\n)
Strings:
• As like C, use double-quotes
• Examples:
• “Hello world!”
• “a / b”
• “text \t column1 \b column2 \n”
Data Types
• The Data types used in Verilog are
• Value Set
• Nets
• Registers
• Vectors
• Integer, Real, and Time Registers
• Arrays
• Memories
• Parameters
• Strings
Data Types
• Value Set:
• Verilog Supports 4 values and 8 strengths.

S. No. Value Level Condition in Hardware Circuits

1 0 Logic zero, false condition
2 1 Logic one, true condition
3 X Unknown value
4 Z High impedance, floating state
Data Types
• Value Set:
• Strength levels are often used to resolve conflicts between drivers of different
strengths in digital circuits.
• Value levels 0 and 1 can have the strength levels.
S. No. Strength level Type Degree
1 Supply Driving Strongest
2 Strong Driving
3 Pull Driving
4 Large Storage
5 Weak Driving
6 Medium Storage
7 Small Storage
8 Highz High Impedance Weakest
Data Types
• If two signals of unequal strengths are driven on a wire, the stronger signal
prevails.
• For example, if two signals of strength strong1 and weak 0 contend, the result is
resolved as a strong 1.
• If two signals of equal strengths are driven on a wire, the result is unknown.
• If two signals of strength strong 1 and strong 0 conflict, the result is an x.
• Strength levels are particularly useful for accurate modelling of signal contention,
MOS devices, dynamic MOS, and other low-level devices.
• Only trireg nets can have storage strengths large, medium, and small.
Data Types-Nets

• Nets represent connections between hardware elements.

• Just as in real circuits, nets have values continuously driven on them by the
outputs of devices that they are connected to.
• Nets are declared primarily with the keyword wire.
• Nets are one-bit values by default unless they are declared explicitly as vectors.
• The terms wire and net are often used interchangeably.
• The default value of a net is z (except the trireg net, which defaults to x ).
• Nets get the output value of their drivers.
• If a net has no driver, it gets the value z.
Data Types-Nets

• net is not a keyword but represents a class of data types such as wire, wand, wor,
tri, triand, trior, trireg, etc.
• The wire declaration is used most frequently.

wire a; / / Declare net a for the circuit

wire b, c; / / Declare two wires b, c for the circuit
wire d = 1’b0; / / Net d is fixed to logic value 0 at declaration.
Data Types-Registers
• Registers represent data storage elements.
• Registers retain value until another value is placed onto them.
• In Verilog, the term register merely means a variable that can hold a value.
• Unlike a net, a register does not need a driver.
• Verilog registers do not need a clock as hardware registers do.
• Values of registers can be changed anytime in a simulation by assigning a new
value to the register.
• Register data types are commonly declared by the keyword reg.
• The default value for a reg data type is x.
Data Types-Registers
• Registers represent data storage elements.
• Registers retain value until another value is placed onto them.

reg reset; / / declare a variable reset that can hold its value
initial / / this construct will be discussed later
begin
reset = 1’b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1’b0; // after 100 time units reset is deasserted.
end
Data Types-Vectors
• Nets or reg data types can be declared as vectors (multiple bit widths).
• If bit width is not specified, the default is scalar (l-bit).
• Vectors can be declared at [high#:low#] or [low# :high#], but the left number in
the squared brackets is always the most significant bit of the vector.

wire a; / / scalar net variable, default.

wire [7:0] bus; / / 8-bit bus.
wire [31:0] busA, busB, busC; / / 3 buses of 32-bit width.
reg clock; / / scalar register, default.
reg [0:40] virtual-addr; //vector register, virtual address 41 bits wide.
Data Types-Vectors
• Examples: wire b; //scalar net variable
wire[7:0] databus; //8-bit data bus
• Represent buses
• wire[3:0] busA;
• reg [1:4] busB;
• reg [1:0] busC;
• Left number is always MSB.
• Vector assignment by position also possible.
• busB[1] = busA[3];
• busB[2] = busA[2];
• busB[3] = busA[1];
• busB[4] = busA[0];
Data Types-Integer
• An integer is a general purpose register data type used for manipulating
quantities.
• Integers are declared by the keyword integer.
• Although it is possible to use reg as a general-purpose variable, it is more
convenient to declare an integer variable for purposes such as counting.
• The default width for an integer is the host-machine word size, which is
implementation specific but is at least 32 bits.
• Registers declared as data type reg store values as unsigned quantities, whereas
integers store values as signed quantities.

integer counter; / / general purpose variable used as a counter.

initial
counter = -1; / / A negative one is stored in the counter
Data Types-Real
• Real number constants and real register data types are declared with the keyword
real.
• They can be specified in decimal notation (e.g., 3.14) or in scientific notation
(e.g., 3e6, which is 3 × 106).
• Real numbers cannot have a range declaration, and their default value is 0.
• When a real value is assigned to an integer, the real number is rounded off to the
nearest integer.
Data Types-Real
• Real number constants and real register data types are declared with the keyword
real.

real delta; / / Define a real variable called delta

initial
begin
delta = 4e10; / / delta is assigned in scientific notation
delta = 2.13; / / delta is assigned a value 2.13
end
integer i; / / Define an integer i
initial
i = delta; / / i gets the value 2 (rounded value of 2.13)
Data Types-Time
• Time register is used to store and manipulate time values.
• They are used to store simulation time and it is declared with the keyword time.
• Syntax:
Time time_id1, time_id2,………………..time_idn
Examples:
time currtime;
initial
begin
currtime=$time;
end
Data Types-Arrays
• Arrays are allowed in Verilog for reg, integer, time, and vector register data types.
• Arrays are not allowed for real variables.
• Arrays are accessed by <array-name> [<subscript>].
• Multidimensional arrays are not permitted in Verilog.
• It is important not to confuse arrays with net or register vectors.
• A vector is a single element that is n-bits wide.
• On the other hand, arrays are multiple elements that are l-bit or n-bits wide.
Data Types-Arrays
• Arrays are allowed in Verilog for reg, integer, time, and vector register data types.

integer count[0:7]; // An array of 8 count variables

reg booll[31:01; //Array of 32 one-bit Boolean register variables
time chk_point[1:100]; //Array of 100 time checkpoint variables
reg [ 4:0] port_id[0 :7] ; //Array of 8 port_ids; each port_id is 5 bits wide
integer matrix[4:0][4:0]; // Illegal declaration. Multidimensional array
count[5] // 5th element of array of count variables
chk_point[100] //100th time check point value
Port_id[3] //3rd element of port-id array. This is a 5-bit value.
Data Types-Memories
• In digital simulation, one often needs to model register files, RAMS, and
ROMs.
• Memories are modelled in Verilog simply as an array of registers.
• Each element of the array is known as a word.
• Each word can be one or more bits. It is important to differentiate between n 1-
bit registers and one n-bit register.
• A particular word in memory is obtained by using the address as a memory array
subscript.

reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words

reg [ 7:0] membyte [0:1023]; // Memory membyte with 1K 8-bit words (bytes)
membyte[511] // Fetches 1 byte word whose address is 511.
Data Types-parameters
• Verilog allows constants to be defined in a module by the keyword parameter.
• Parameters cannot be used as variables.
• Parameter values for each module instance can be overridden individually at
compile time.

parameter port_id = 5; // Defines a constant port-id

parameter cache_line_width=256; //Constant defines width of cache line.
parameter bussize = 8;
Parameter bit=1, byte=8;
reg [bussize-1 : 0] databus;
Data Types-Strings
• Strings can be stored in reg.
• The width of the register variables must be large enough to hold the string.
• Each character in the string takes up 8 bits (1 byte).
• If the width of the register is greater than the size of the string, Verilog fills bits
to the left of the string with zeros.
• If the register width is smaller than the string width, Verilog truncates the
leftmost bits of the string.
• It is always safe to declare a string that is slightly wider than necessary.

reg [8*18:1] string-value; //Declare a variable that is l8 bytes wide

initial
string-value = "Hello Verilog World"; // String can be stored in variable
Data Types-Strings
• Some special characters are used along with the strings for the purpose of
display.
S. No. Escaped Characters Character Displayed
1 \n New line
2 \t Tab
3 %% %
4 \\ \
5 \” “
6 \000 Character written in 1-3 octal digits
Data Types-Usage restrictions
Data Flow and Structural Modeling
• Can use only wire data type.
• Cannot use reg data type.
Behavioral Modeling
• Can use only reg data type (within initial and always constructs).
• Cannot use wire data type.
Operators
Many types of operators are supported by Verilog HDL. They are
• Arithmetic Operators.
• Logical Operators.
• Relational Operators.
• Equality Operators.
• Bitwise Operators.
• Reduction Operators.
• Shift Operators.
• Concatenation Operators.
• Conditional Operators.
Arithmetic Operators
• Used to perform arithmetic operations like addition, subtraction,
multiplication and division.
• The Arithmetic Operators are +, -, *, /, %,**.
• If any operand is x the result is x.
• Negative registers:
• -regs can be assigned negative but are treated as unsigned.
Example:
reg [15:0] regA;
regA = -4’d12; // stored as 216-12 = 65524
regA/3 // evaluates to 21861
Logical Operators
The Logical Operators are
&& logical AND
|| logical OR
! logical NOT
• Operands evaluated to ONE bit value: 0, 1 or x.
• Result is ONE bit value: 0, 1 or x.
• Example:
A = 1; B = 0; C = x;
A && B //  1 && 0 0
A || !B //  1 || 1  1
C || B // x || 0 x
Relational Operators
The Relational Operators are
> greater than
< less than
>= greater or equal than
<= less or equal than
• Result is one bit value: 0, 1 or x.
Example:
1>0 // 1
’b1x1 <= 0 // x
10 < z // x
Equality Operators
The Equality Operators are
==  logical equality
Returns 0, 1, or X.
!= logical inequality
===  case equality
Returns 0, or 1.
!== case inequality
Bitwise Operators
The Bitwise Operators operates over operand bit by bit.
& bitwise AND
| bitwise OR
~ bitwise NOT
^ bitwise XOR
~^ or ^~  bitwise XNOR
Reduction Operators
The reduction operators operates over single operand and results in a single
bit of result.
&  AND
|  OR
^  XOR
~& NAND
~| NOR
~^ or ^~ XNOR
• One multi-bit operand One single-bit result.
Example:
a = 4’b1001;
c = |a; // c = 1|0|0|1 = 1
Shift Operators
Used to left shift/ right shift the data. (circular).
>> shift right
<< shift left
>>> arithmetic shift right
<<< arithmetic shift left
Example:
• Result is same size as first operand, always zero filled
a = 4’b1010; d = a >> 2; // d = 0010
c = a << 1; // c = 0100
• Vacant position filled by either LSB (>>>) or MSB (<<<) value
a = 4’b0101; d = a >>>1; // d = 1010
c = a <<<1; // c = 1010
Concatenation Operators
Used to combine two or more numbers/ variables.
{op1, op2, ..} concatenates op1, op2, .. to single number
• Operands must be sized !!
Example:
Replication ..
reg a;
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
reg [2:0] b, c;
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
Conditional Operators
The conditional operators operates as
cond_expr ? true_expr : false_expr.
Example:
• A 2X1 MUX can be expressed as
Operators Precedence
System Tasks
• Verilog provides standard system tasks to do certain routine operations.
• All system tasks appear in the form $<keyword>.
• Operations such as displaying on the screen, monitoring values of nets, stopping,
and finishing are done by system tasks.
• Displaying information:
• $display is the main system task for displaying values of variables or strings or
expressions.
//Display the string in quotes //Display value of current simulation time 230
$display("HelloVerilog World"); $display($time);

-- Hello Verilog World -- 230

System Tasks
• Some other systems tasks are $stop, $finish, $time etc.
• Verilog provides a mechanism to monitor a signal when its value changes. This
facility is provided by the $monitor task.
• The task $stop is provided to stop during a simulation.
• The $finish task terminates the simulation.
 Testbench

Circuit Description Testfixture

A program that is used to verify the Verilog Simulator

correctness of an HDL representation
for a circuit

Applies a set of input combinations to

the circuit that thoroughly tests the
HDL representation
Simulation Result
Testbench
• Once a design block is completed, it must be tested.
• The functionality of the design block can be tested by applying stimulus and
checking results.
• We call such a block the stimulus block also called as test bench. It is good
practice to keep the stimulus and design blocks separate.
• The stimulus block can be written in Verilog. A separate language is not required
to describe stimulus.
• Different test benches can be used to thoroughly test the design block.
• Two styles of stimulus application are possible.
• Stimulus Block Instantiates Design Block
• Stimulus and Design Blocks instantiated in a Dummy Top-Level Module
Testbench
1. Stimulus Block Instantiates Design Block:
• In this simulation method, the stimulus block instantiates the design block
and directly drives the signals in the design block.
• Here, the stimulus block becomes the top-level block.
• It manipulates input signals, and it checks and displays the output signal.
Testbench
2. Stimulus and Design Blocks instantiated in a Dummy Top-Level Module:
• In the second style of applying stimulus, both the stimulus and design blocks
are instantiated in to a top-level dummy module.
• The function of top-level block is simply to instantiate the design and
stimulus blocks.
• The stimulus block interacts with the design block only through the interface.
Abstraction levels
The Verilog HDL supports four types of modelling a Hardware circuit.
1. Behavioural or Algorithmic Model
2. Dataflow Model
3. Structural or Gate level Model
4. Switch level Model
Abstraction levels
1. Behavioural or algorithmic level:
• This is the highest level of abstraction provided by Verilog HDL.
• A module can be implemented in terms of the desired design algorithm
without concern for the hardware implementation details.
• Designing at this level is very similar to C programming.

2. Dataflow level:
• At this level the module is designed by specifying the data flow.
• The designer is aware of how data flows between hardware registers and
how the data is processed in the design.
Abstraction levels
3. Gate level:
• The module is implemented in terms of logic gates and interconnections
between these gates.
• Design at this level is similar to describing a design in terms of a gate-
level logic diagram.
3. Switch level:
• This is the lowest level of abstraction provided by Verilog.
• A module can be implemented in terms of switches, storage nodes, and the
interconnections between them.
• Design at this level requires knowledge of switch-level implementation
details.
Switch Level Modeling
• Switch level modeling is the lowest level of abstraction provided by Verilog. It consists of
PMOS and NMOS switches.
• A module can be implemented in terms of transistors, switches, storage nodes, and the
interconnections between them.
• In Verilog, HDL transistors are known as Switches that can either conduct or open.
• Design at this level requires knowledge of switch-level implementation details.
• Format for PMOS, NMOS and CMOS are:
nmos (out, data, ncontrol);
pmos (out, data, pcontrol);
cmos (out, data, ncontrol, pcontrol);
 module my_nor(Y,A,B);
output Y;
input A,B;
wire C;
supply1 pwr;
supply0 gnd ;
pmos (C, pwr, A);
pmos (Y,C,B);
nmos (Y, gnd, A);
nmos (Y, gnd, B);
NOR gate using CMOS Logic
endmodule
Structural Modelling
• At gate level, the circuit is described in terms of gates. (e.g., and,
nand…)
• Hardware design at this level is intuitive for a user with a basic knowledge
of digital logic design.
• It is possible to see a one-to-one correspondence between the logic circuit
diagram and the Verilog description.
• Actually, the lowest level of abstraction is switch- (transistor-) level
modeling.
• However, with designs getting very complex, very few hardware designers
work at switch level.
• So most of the digital design is now done at gate level or higher levels of
abstraction.
Structural Modelling
• All logic circuits can be designed by using basic gates.
• Verilog supports basic logic gates as predefined primitives.

• There are three classes of basic gates.

1. Multiple-input gates: and, or, nand, nor, xor, xnor
2. Multiple-output gates: buffer, not
3. Tristate gates: bufif0, bufif1, notif0, notif1

• These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition.
• Logic gates can be used in design using gate instantiation.
Structural Modelling
• The Syntax is
Gate_type [instance_name] (term1, term2,……………..termn);

• Example

// Module Name: Andgate

module Andgate(a, b, c);
input a;
input b;
output c;
and (c, a, b);
endmodule
Structural Modelling
Structural Modelling
Structural Modelling
Structural Modelling
• Full Adder using Half Adder (Module Instantiation)
Structural Modelling
 Structural Modeling of Digital Circuit
Structural Modelling
module IC7283 (A0, B0, C0, C1, S0);
input A0, B0, C0;
output C1, S0;
//Seven internal wires needed
wire N1, N2, N3, N4, N5, N6, N7;
// Ports on primitive gates - output port
// is listed first
not G1 (N3,C0), G2 (N5,N2), G3 (N6,N3);
nand G4 (N1,A0,B0);
nor G5 (N2,A0,B0), G6 (C1,N2,N4);
and G7 (N4,N1,N3), G8 (N7,N1,N5);
xor G9 (S0,N6,N7);
endmodule
Dataflow Modelling
• Data flow level description is higher level modelling and it makes the
circuit description more compact as compared to structural modelling.
• Design implement using data flow modeling uses a continuous assignment
statement and Verilog provides different operators to perform a function.
• The assignment statement start with the keyword assign and results are
assigned to nets.
• Continuous assignment – most basic statement used to drive value onto net
Dataflow Modelling
• Implicit continuous assignment – it is the shortcut method of assigning the
expression on the net.

• Implicit net declaration – if a signal name of the left hand side of the
continuous assignment statement is not declared the Verilog simulator
assign an implicit net declaration for the net
Dataflow Modelling
• Regular assignment delay – the assignment takes effect with the time delay
of 2 time steps. If the values of ‘a’ and ‘b’ changes then ‘c’ wait for two
time steps to compute the result.

• Implicit continuous assignment delay – it is a shortcut method of assigning

the delay and the expression on the net.

• Net declaration delay – a delay can be specified on a net when it is declared

without putting a continuous assignment on the net.
Dataflow Modelling
EXPRESSIONS
• An expression is formed using operands & operators.
• Expression can be used whenever a value is expected.
• Example: a & b, x1[7:0] + x2[7:0].
OPERANDS
• Operands are the data types used in the expression.
• An operands can be constant, net, parameter, register, memory, bit
select.
• Example: c = a + b // a, b, c are real operands.
Dataflow Modelling
OPERATORS:
• Operators act on operands to produce desired result.
• Various types: arithmetic, logical, relational, equality, bitwise, shift, etc.,
• Example:
c = a % b // % is operator to perform modules operation on a, b.
Dataflow Modelling-Examples
Dataflow Modelling - Examples
Dataflow Modelling - Examples
Behavioural Modelling
• Behavioral model enables you to describe the system at a higher level of
abstraction (i.e.) it specify the circuit in terms of behavior.
• All we need to do is to describe the behavior (Algorithm) of our design.
• Action  How the model of our circuit should behave?
• Timing control At what time do what thing & At what condition do what
thing.
• Verilog supports the following construct to model circuit behavior.
• Procedural block
• Procedural assignment
• Timing controls
• Block statement
• Conditional statement
Behavioural Modelling
• Procedural Block:
• In Verilog procedural block are the basic of behavior modeling.
• We can describe one logic in one procedural block.
• Procedural block types:
(i) initial
(ii) always.
• All initial & always statement execute concurrently starting at time t=0.
• A module may contain any number of initial & always statement.
Behavioural Modelling
• Procedural Block:
• Structure of procedural block
Behavioural Modelling
• Procedural Block:
• Initial statement causes procedural statement to executes only once and it begin
its execution at start of simulation time 0.
• Sequential block (begin-end) is the most commonly used procedural statement,
that is it wait for a certain time until an event occurs.
Behavioural Modelling
• Procedural Block-Always Statement
• For circuit synthesis we use the always block and such a block must contain all
sequential constructs.
• Note that the statements in an always block between begin/end are executed
sequentially just as they are written.
• Variables assigned a value inside an always block must be of type reg or integer.
• The if, case, for loop, and while loop must appear inside an always block.
• A module can have multiple blocks, but blocks cannot be nested.
• For modules that have multiple always blocks all of the always blocks are
executed in parallel.
 Behavioural Modelling
• Procedural Block-Always Statement
• Always blocks are repeated executed until simulation is stopped. Similar to
initial block it begin its execution at start of simulation time 0.
• This statement is used to model a block of activity that is repeated continuously
in a digital circuit.
 Behavioural Modelling
• Procedural Statement
• The assignment statement within an initial statement or always statement is
called procedural statement.
• It is used to assign to only a register data type.
• Procedural statement executes sequentially respect to other statements that
appear around it.
• Sequential block always start execution when an event occurs.
• Two types of procedural assignments are:
(i) blocking assignment
(ii) non-blocking assignment
Behavioural Modelling
• BLOCKING PROCEDURAL ASSIGNMENT
• A procedural statement in which the assignment
operator is an “=” in a blocking procedural
assignment.

• Blocking procedural assignment is executed

before any of the statement that follow it are
executed.
Behavioural Modelling
• NON-BLOCKING PROCEDURAL ASSIGNMENT
• The main characteristics of non-blocking assignment
statement is execution is performed concurrently.
• In non-blocking assignment, the assignment symbol
"<=" is used.
Behavioural Modelling
Behavioural Modelling
• BLOCKING STATEMENT - SEQUENTIAL BLOCK
• Block statements are used to group multiple statements to act together as one.
There are two types of blocks:
• Sequential blocks and
• Parallel blocks
• The keywords begin and end are used to group statements into sequential blocks.
• Sequential blocks have the following characteristics:
• The statements in a sequential block are processed in the order they are specified.
• A statement is executed only after its preceding statement completes execution.
• If delay or event control is specified, it is relative to the simulation time when the previous
statement in the block completed execution.
Behavioural Modelling
• BLOCKING STATEMENT - SEQUENTIAL BLOCK
Behavioural Modelling
• BLOCKING STATEMENT - PARALLEL BLOCK
• Parallel blocks, specified by keywords fork and join, provide interesting
simulation features
• Parallel blocks have the following characteristics:
• Statements in a parallel block are executed concurrently.
• Ordering of statements is controlled by the delay or event control assigned to
each statement.
• If delay or event control is specified, it is relative to the time the block was
entered.
Behavioural Modelling
• BLOCKING STATEMENT - PARALLEL BLOCK
• All statements in a parallel block start at the time when the block was entered.
• Thus, the order in which the statements are written in the block is not important.
• The result of simulation remains the same except that all statements start in
parallel at time 0.
• Hence, the block finishes at time 20 instead of time 35.
Behavioural Modelling
• CONDITIONAL STATEMENT – IF
• Conditional statements are used for making
decisions based upon certain conditions.
• These conditions are used to decide whether or not
a statement should execute.
• If the condition evaluates to a non zero known
value, then procedural_statement1 is executed.
• If condition_ 1 evaluates 0.x,z, then
procedural_statement2 is not executed and an else
branch, if it exist, is executed.
Behavioural Modelling
• CONDITIONAL STATEMENT – CASE
• The keywords case, endcase, and default are
used in the case statement.
• The expression is compared to the alternatives
in the order they are written.
• For the first alternative that matches, the
corresponding statement or block is executed.
• If none of the alternatives match, the
default_statement is executed.
• The default_statement is optional.
Behavioural Modelling
• CONDITIONAL STATEMENT – CASE
• Case treats each value 0, 1, x, and z literally.
• 4ʼb01xz only matches 4ʼb01xz
• Example: 4ʼb0110 does not match 4ʼb01xx in a case
• Casez treats 0, 1, and x literally.
• Casez treats z as a donʼt care.
• Example: 4ʼb0110 matches 4ʼb01zz, but not 4ʼb01xz
• Casex treats 0 and 1 literally
• Casex treats both x and z as donʼt cares
• Example: 4ʼb0110 matches 4ʼb01xx and also 4ʼb01xz
Behavioural Modelling
• CONDITIONAL STATEMENT – FOR Loop
• When a circuit exhibits regularity, a for loop can be used inside an always
statement to simplify the design description (for loop is a procedural statement
used only inside an always block).
• C style syntax: for (k = 0; k < 4; k = k+1)
• Loop index must be type integer (not reg!)
• Can`t use the convenience of k++
• Use begin …end for multiple statements in the loop
• Each iteration of the loop specifies a different piece of the circuit
• Has nothing to do with the changes over “time”
Behavioural Modelling
• CONDITIONAL STATEMENT – FOREVER
Loop
• The keyword forever is used to express this loop.
A forever loop can be exited by use of the disable
statement.
• The loop does not contain any expression and
executes forever until the $finish task is
encountered.
• The loop is equivalent to a while loop with an
expression that always true, e.g., while (1).
• A forever loop is typically used in conjunction
with timing control constructs.
Behavioural Modelling-Examples
• Half Adder
Behavioural Modelling-Examples
• Full Adder
Behavioural Modelling-Examples
 Half Adder - Design

x1
Structural Dataflow Behavioral
Modeling Modeling Modeling
a1
module ha(S,C,A,B); module ha(S,C,A,B); module ha(S,C,A,B);
output S,C; output S,C; output S,C;
input A,B; input A,B; input A,B;
xor x1(S,A,B); assign S=A^B; reg S,C;
and a1(C,A,B); assign C=A&B; always @(A,B)
endmodule endmodule begin
S=A^B;
C=A&B;
end
Endmodule
 Testbench

Circuit Description Testfixture

A program that is used to verify the

correctness of an HDL representation Verilog Simulator
for a circuit

Applies a set of input combinations to

the circuit that thoroughly tests the
HDL representation

Simulation Result
Test Bench
• We need to apply appropriate stimulus to the design to test it.
• Stimulus is nothing but the application of various permutations and
combinations of inputs at various points of time and, looking for correct results
produced by the design.
• This can be done by writing another Verilog code called Test Bench.
• Test bench used to simulate your design without physical hardware.
• This is written as a separate file, different from the design file(s).
• The biggest benefit of this is that you can actually inspect every signal that is in
your design.
Test Bench - Structure
module test_module_name;
//declare local reg and wire identifiers.
//instantiate the design module under test
//generate stimulus (inputs to design module) using initial and always.
// display output response.(display on screen or print)
endmodule
Test Bench - Example
Test Bench-Example
module HalfTB(); //the test bench doesn’t have any port
reg p,q;
wire sum,carry;
Half H1(.a(p),.b(q),.s(sum),.c(carry)); //Module instantiation
initial
begin
p=1’b0; q=1’b0;
#2 p=1’b0; q=1’b1;
#2 p=1’b1; q=1’b0;
#2 p=1’b1; q=1’b1;
#2 $stop;
end
endmodule
Verilog Program for Full Adder using Half Adder
// Test bench module:
// Main Module module FullTB();
module Full(A,B,Cin,Sum,Carry); reg a,b,cin;
input A,B,Cin; wire s, cout;
output Sum, Carry; Full f1(.A(a),.B(b),.Cin(cin),.Sum(s),.Carry(cout));
wire s0,c0,c1; initial
Half H1(A,B,s0,c0); begin
Half H2(s0,Cin,s,c1); a=1’b0; b=1’b0;cin=1’b0;
or o1(cout,c0,c1); #2 a=1’b0; b=1’b1; cin=1’b0;
endmodule #2 a=1’b1; b=1’b0; cin=1’b0;
#2 a=1’b1; b=1’b1; cin=1’b1;
#2 $stop;
end
endmodule
Behavioral Code of Half Subtractor
Test bench module:
module HalfSubTB(); //the test bench doesn’t have any port
Main module:
reg p,q;
module HalfSub(a,b,d,bo);
wire diff,borrow;
input a,b;
HalfSub H1(p,q, diff,borrow); //Module instantiation; here H1 is the instance name
output reg d,bo;
initial
always @(*)
begin
begin
p=1’b0; q=1’b0;
d=a ^ b;
#2 p=1’b0; q=1’b1;
bo=(~a) & b;
#2 p=1’b1; q=1’b0;
end
#2 p=1’b1; q=1’b1;
endmodule
#2 $stop;
end
endmodule
Verilog Program for MUX
// Main Module (STRUCTURAL)
// Main Module (DATAFLOW) // Main Module (DATAFLOW) module mux21(Y,A,B,S);
module mux21(Y,A,B,S); module mux21(Y,A,B,S); output Y;
input A, B, S;
output Y; output Y;
wire SA, SB,N;
input A, B, S; input A, B, S; and g1(SB, S, B);
assign Y = (S & ~B) | (~S & A); assign Y = (S == 1'b0) ? A : not g2(N, S);
endmodule (S == 1'b1) ? B : 1'bx ; and g3(SA, A, N);
endmodule or g4(Y,SA, SB);
endmodule

B SB
g1
S

g2 N g4

A
g3
SA
// Main Module (BEHAVIOURAL)
module mux21(Y,A,B,S); // Main Module (BEHAVIOURAL)
output Y; module mux21(Y,A,B,S);
input A, B, S; output Y;
always @(*) input A, B, S;
begin always @(*)
if (S == 0) begin
begin Y = A; if (S == 0)
end begin Y = A;
else end
begin Y = B; else
B
end begin Y = B;
end end
endmodule end
endmodule
A
Verilog Program for MUX // Testbench Module
module mux21TB();
// Main Module reg sel, a, b;
module mux21(Y,A,B,S); wire y;
output Y; mux21 m1 (.S(sel), .A(a), .B(b), .Y(y));
input A, B, S; initial
assign Y = (S & ~B) | (~S & A);
begin
endmodule
$monitor("S=%b, A=%b, B=%b, Y=%b", S, A, B, Y);
B
// Test case 1: S=0, A=1, B=0
S = 0; A = 1; B = 0; #10;
// Test case 2: S=1, A=0, B=1
S = 1; A = 0; B = 1; #10;
A
// Test case 3: S=0, A=0, B=1
S = 0; A = 0; B = 1; #10;
// Test case 4: S=1, A=1, B=0
S = 1; A = 1; B = 0; #10;
$finish;
end
endmodule