CCS 1202

COMPUTER ORGANIZATION AND ARCHITECTURE

VonNeuman Architecture

1
General System Architecture
• The General System Architecture is divided into two major
classification units.
• Stored Program Control Concept
• Flynn's Classification of Computers
Flynn's Classification of Computers
Stored Program Control Concept
• The term Stored Program Control Concept refers to the storage of
instructions in computer memory to enable it to perform a variety of tasks
in sequence.

• The idea was introduced in the late 1940s by John von Neumann who
proposed that a program be electronically stored in the binary-number
format in a memory device so that instructions could be modified by the
computer as determined by intermediate computational results.

• ENIAC (Electronic Numerical Integrator and Computer) was the first

computing system designed in the early 1940s. It was based on Stored
Program Concept in which machines used memory for processing data.
 The Stored Program Concept
Learning how instructions are represented leads to discovering the secret of
computing: “the stored-program concept”
Today’s computers are build on two key principles : Memory
Instructions are represented as numbers Accounting program
Programs can be stored in memory to be read or written (machine code)

just like numbers Editor program

(machine code)
The power of the concept: C compiler
(machine code)
Memory can contain: Processor

the source code for an editor Payroll data

the compiled machine code for the editor Book text

the text that the compiled program is using Source code in C

for editor program
the compiler that generated the code
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Flynn's Classification of Computers
• M.J. Flynn proposed a classification for the organization of a computer
system by the number of instructions and data items that are manipulated
simultaneously.

• The sequence of instructions read from memory constitutes an instruction

stream.

• The operations performed on the data in the processor constitute a data

stream.

• Parallel processing may occur in the instruction stream, in the data stream,
or both.
Flynn's Classification of Computers
 The Von Neumann Architecture
The architecture is named after the mathematician,
John Von Neumann, who supposedly proposed storing
instructions in the memory of a computer and using a
control unit to handle the fetch-decode-execute cycle.

A similar architecture was proposed in 1830 by

Charles Babbage for his Analytic Engine:
ALU mill Portion of the mill of the Analytical Engine
with printing mechanism, under
construction at the time of Babbage’s
memory store death. © Science Museum/Science & Society Picture Library

control unit operator (process cards storing instructions)

I/O units output (typewriter)
 The Von Neumann Architecture
• Model for designing and building computers, based on the
following three characteristics:

1) The computer consists of four main sub-systems:

• Memory
• ALU (Arithmetic/Logic Unit)
• Control Unit
• Input/Output System (I/O)
2) Program is stored in memory during execution.
3) Program instructions are executed sequentially.
 Von Neumann Architecture
1) Memory: The unit that stores and retrieves instructions and data.

2) Processor: The unit that houses two separate components:

The control unit: Repeats the following 3 tasks repeatedly
Fetches an instruction from memory
Decodes the instruction
Executes the instruction
The arithmetic/logic unit (ALU): Performs mathematical and
logical operations.
3) Input/Output (I/O) Units: Handles communication with the
outside world.
Flow of Information
• The parts are connected to one another by a collection of wires called
a bus

Processor

Data flow through a von Neumann architecture

 von Neumann
Architecture

(c) Yngvi Bjornsson

 Memory Subsystem
• Memory, also called RAM (Random Access Memory),
• Consists of many memory cells (storage units) of a fixed size.
Each cell has an address associated with it: 0, 1, …
• All accesses to memory are to a specified address.
A cell is the minimum unit of access (fetch/store a complete cell).
• The time it takes to fetch/store a cell is the same for all cells.

• When the computer is running, both

• Program
• Data (variables)
are stored in the memory.
 RAM
• Need to distinguish between N
• the address of a memory cell and the 0000000000000001
content of a memory cell 1 bit
• Memory width (W): 0
• How many bits is each memory cell, 1
typically one byte (=8 bits) 2
• Address width (N): 2N
• How many bits used to represent each
address, determines the maximum ...
memory size = address space
• If address width is N-bits, then address
space is 2N (0,1,...,2N-1) 2N-1

W
 Memory Size / Speed
• Typical memory in a personal computer (PC):
• 64MB – 16 GB or more
• Memory sizes:
• Kilobyte (KB) = 210 = 1,024 bytes ~ 1 thousand
• Megabyte(MB) = 220 = 1,048,576 bytes ~ 1 million
• Gigabyte (GB) = 230 = 1,073,741,824 bytes ~ 1 billion
• Memory Access Time (read from/ write to memory)
• DRAM - 50 to 150 nanoseconds (billionths of a second)
• SRAM - 10 nanoseconds (1 nsec. = 0.000000001 sec.)
• RAM is
• volatile (can only store when power is on)
• relatively expensive
 Operations on Memory
• Fetch (address):
• Fetch a copy of the content of memory cell with the specified address.
• Non-destructive, copies value in memory cell.
• Store (address, value):
• Store the specified value into the memory cell specified by address.
• Destructive, overwrites the previous value of the memory cell.
• The memory system is interfaced via:
• Memory Address Register (MAR)
• Memory Data Register (MDR)
• Fetch/Store signal
Structure of the Memory Subsystem
• Fetch(address)
• Load address into MAR.
MAR MDR
• Decode the address in MAR.
F/S
Memory
• Copy the content of memory cell with
Fetch/Store specified address into MDR.
decoder
controller
circuit • Store(address, value)
• Load the address into MAR.
• Load the value into MDR.
• Decode the address in MAR
... • Copy the content of MDR into memory
cell with the specified address.
Input/Output Subsystem
• Handles devices that allow the computer system to:
• Communicate and interact with the outside world
• Screen, keyboard, printer, ...
• Store information (mass-storage)
• Hard-drives, floppies, CD, tapes, …

• Mass-Storage Device Access Methods:

• Direct Access Storage Devices (DASDs)
• Hard-drives, floppy-disks, CD-ROMs, ...
• Sequential Access Storage Devices (SASDs)
• Tapes (for example, used as backup devices)
 I/O Controllers
• Speed of I/O devices is slow compared to RAM
• RAM ~ 50 nsec.
• Hard-Drive ~ 10msec. = (10,000,000 nsec)
• Solution:
• I/O Controller, a special purpose processor:
• Has a small memory buffer, and a control logic to control I/O device (e.g.
move disk arm).
• Sends an interrupt signal to CPU when done read/write.
• Data transferred between RAM and memory buffer.
• Processor free to do something else while I/O controller reads/writes
data from/to device into I/O buffer.
 The ALU Subsystem
• The ALU (Arithmetic/Logic Unit) performs
• mathematical operations (+, -, x, /, …)
• logic operations (=, <, >, and, or, not, ...)

• Consists of:
• Circuits to do the arithmetic/logic operations.
• Registers (fast storage units) to store intermediate computational
results.
• Bus that connects the two.
 Structure of the ALU
• Registers:
• Very fast local memory cells, that R0
store operands of operations and R1
intermediate results.
R2
• CCR (condition code register), a
special purpose register that stores
the result of <, = , > operations
• ALU circuitry: Rn
• Contains an array of circuits to do
mathematical/logic operations.
• Bus: ALU circuitry
• Data path interconnecting the
registers to the ALU circuitry.
GT EQ LT
The Control Unit
• Program is stored in memory
• as machine language instructions, in binary

• The task of the control unit is to execute programs by repeatedly:

• Fetch from memory the next instruction to be executed.
• Decode it, that is, determine what is to be done.
• Execute it by issuing the appropriate signals to the ALU, memory, and I/O
subsystems.
• Continues until the HALT instruction
 Machine Language Instructions
• A machine language instruction consists of:
• Operation code, telling which operation to perform
• Address field(s), telling the memory addresses of the values on which the
operation works.
• Example: ADD X, Y (
• Add content of memory locations X and Y, and store back in memory location Y).
• Assume: opcode for ADD is 9, and addresses X=99, Y=100

Opcode (8 bits) Address 1 (16 bits) Address 2 (16 bits)

00001001 0000000001100011 0000000001100100

 Typical Machine Instructions
• Notation:
• We use X, Y, Z to denote RAM cells
• Assume only one register R (for simplicity)
• Use English-like descriptions (should be binary)

• Data Transfer Instructions

• LOAD X Load content of memory location X to R
• STORE X Load content of R to memory location X
• MOVE X, Y Copy content of memory location X to loc. Y
(not absolutely necessary)
 Machine Instructions (cont.)
• Arithmetic
• ADD X, Y, Z CON(Z) = CON(X) + CON(Y)
• ADD X, Y CON(Y) = CON(X) + CON(Y)
• ADD X R = CON(X) + R
• similar instructions for other operators, e.g. SUBTR,OR, ...

• Compare
• COMPARE X, Y
Compare the content of memory cell X to the content of memory cell Y
and set the condition codes (CCR) accordingly.
• E.g. If CON(X) = R then set EQ=1, GT=0, LT=0
 Example
• Pseudo-code: Set A to B + C
• Assuming variable:
• A stored in memory cell 100, B stored in memory cell 150, C stored in
memory cell 151
• Machine language (really in binary)
• LOAD 150
• ADD 151
• STORE 100
• or
• (ADD 150, 151, 100)
 Structure of the Control Unit
• PC (Program Counter):
• stores the address of next instruction to fetch
• IR (Instruction Register):
• stores the instruction fetched from memory
• Instruction Decoder:
• Decodes instruction and activates necessary circuitry

PC IR

+1
Instruction
Decoder
How does this all work together?
• Program Execution:

• PC is set to the address where the first program instruction is stored in

memory.

• Repeat until HALT instruction or fatal error

Fetch instruction
Decode instruction
Execute instruction
End of loop
Program Execution (cont.)
• Fetch phase
• PC --> MAR (put address in PC into MAR)
• Fetch signal (signal memory to fetch value into MDR)
• MDR --> IR (move value to Instruction Register)
• PC + 1 --> PC (Increase address in program counter)

• Decode Phase
• IR -> Instruction decoder (decode instruction in IR)
• Instruction decoder will then generate the signals to activate the
circuitry to carry out the instruction
Program Execution (cont.)
• Execute Phase
• Differs from one instruction to the next.

• Example:
• LOAD X (load value in addr. X into register)
• IR_address -> MAR
• Fetch signal
• MDR --> R
Instruction Set for Our Von Neumann Machine
Opcode Operation Meaning
0000 LOAD X CON(X) --> R
0001 STORE X R --> CON(X)
0010 CLEAR X 0 --> CON(X)
0011 ADD X R + CON(X) --> R
0100 INCREMENT X CON(X) + 1 --> CON(X)
0101 SUBTRACT X R - CON(X) --> R
0101 DECREMENT X CON(X) - 1 --> CON(X)
COMPARE X If CON(X) > R then GT = 1 else 0
0111 If CON(X) = R then EQ = 1 else 0
If CON(X) < R then LT = 1 else 0
1000 JUMP X Get next instruction from memory location X
1001 JUMPGT X Get next instruction from memory loc. X if GT=1
... JUMPxx X xx = LT / EQ / NEQ
1101 IN X Input an integer value and store in X
1110 OUT X Output, in decimal notation, content of mem. loc. X
1111 HALT Stop(c)program execution
Yngvi Bjornsson
 Data Bus
• Data lines that provide a path for moving data among system
modules
• May consist of 32, 64, 128, or more separate lines
• The number of lines is referred to as the width of the data bus
• The number of lines determines how many bits can be transferred at
a time
• The width of the data bus is a key factor in determining overall
system performance
 Address Bus Control Bus
• Used to designate the source • Used to control the access and the
or destination of the data on use of the data and address lines
the data bus
• Because the data and address lines
• If the processor wishes to read a
word of data from memory it are shared by all components there
puts the address of the desired must be a means of controlling their
word on the address lines use
• Width determines the • Control signals transmit both
maximum possible memory command and timing information
capacity of the system among system modules
• Also used to address I/O ports • Timing signals indicate the validity of
• The higher order bits are used to data and address information
select a particular module on the
bus and the lower order bits • Command signals specify operations
select a memory location or I/O to be performed
port within the module
 Computer Systems architectures
• The bottleneck in von-Neumann is the fetch-decode-execute cycle.
• It is difficult to speed up operations due to use of one processor.

Other architectures with improved speeds:

• Synchronous processing: multiple processors apply the same program
to multiple data sets.
• Pipelining: Arranges processors in tandem, where each processor
contributes one part to an overall computation. Pipelined computers
are often used for high speed arithmetic calculations.
• Shared-memory: Different processors do different things to different
data. A shared-memory area is used for communication.
 Synchronous processing
• One approach to parallelism is to have multiple processors apply the same
program to multiple data sets

Processors in a synchronous computing environment

 Pipelining
• Arranges processors in tandem, where each processor contributes
one part to an overall computation

Processors in a pipeline
 Shared-Memory

Shared Memory

Processor Processor Processor Processor

Local Local Local

Local
Memory2 Memory3 Memory4
Memory1

Different processors do different things to different data.

A shared-memory area is used for communication.
Comparing Various Types of Architecture
• Synchronous computers have fairly simple processors so there can
be many of them – in the thousands.

• Pipelined computers are often used for high speed arithmetic

calculations as these pipeline easily.

• Shared-memory computers basically configure independent

computers to work on one task. Typically, there are something like
8, 16, or at most 64 such computers configured together.