COA REVIEWER
COA REVIEWER
1642: Blaise Pascal, 19, invented a gear-based 1952: IAS completed at Princeton: the stored
machine for addition and subtraction program computer.
1672: Leibnitz added multiplication and division The architecture for almost all moderm
to machine machines follows the IAS Design
Registers:
CPU: The central processing unit (CPU) ○ It might tell the ALU what
is the brain of a computer. It performs operation to perform (add,
most of the data processing tasks. subtract, etc.).
Here's a breakdown of its parts and 4. The PU performs the operation
functions: and stores the result.
5. The CU might store the result in
CPU Parts: memory or a register.
● Processor Unit (PU): This unit Types of instructions:
does the actual calculations
(addition, subtraction, etc.) and ● Instructions come in different
data manipulation (moving, formats, specifying how many
comparing, etc.) It has two main memory locations (addresses)
parts: they need to reference their data.
○ Arithmetic Logic Unit ○ Three-address
(ALU): Performs instructions: Specify two
arithmetic and logical operands (data to be
operations on data. used) and a result location
○ Registers: Small, (where to store the
temporary storage answer). (Less common)
locations within the CPU ○ Two-address
that hold data for the ALU instructions: Most
to work on. common type. Specify one
● Control Unit (CU): Fetches operand and a result
instructions from memory, location (the other operand
decodes them, and tells the other is usually in a register).
parts of the CPU what to do. It's ○ One-address instruction:
like the conductor of an Use an implied register
orchestra, directing the flow of (accumulator) for one
data and instructions. operand and a memory
location for the other.
How it Works: (Used in older machines)
○ Zero-address
1. The CU fetches an instruction
instructions: Don't use
from memory.
any address fields in the
2. The CU decodes the instruction
instruction itself. (For
to understand what needs to be
specific operations like
done.
push/pop to a stack)
3. The CU sends signals to the PU:
○ It might tell the registers to
provide data to the ALU.
CHAPTER 3 CONTROL UNIT 2. Addressing Sequencing:
3. Conditional Branching:
1. Control Memory:
● Branch Logic: Provides
● Definition: Control Memory is a decision-making capabilities
storage unit within the control based on status conditions.
unit responsible for storing ● Unconditional/Branch
microprograms. Instructions: Alter control flow
● Hardwired Control Unit: based on specified conditions.
Generates control signals using ● Mapping of Instructions: Convert
conventional logic design operation code bits to
techniques. microinstruction addresses.
● Microprogramming: Offers an
elegant and systematic method 4. Symbolic Microinstructions:
for controlling microoperation
sequences. ● Usage: Allows specifying
● Bus-Organized Systems: Control microinstructions in symbolic
signals are groups of bits form similar to assembly
selecting paths in multiplexers, language.
decoders, and arithmetic logic ● Translation: Symbols are
units. translated into binary equivalents
● Microprogrammed Control Unit: using a microprogram assembler.
Control variables stored in
5. Microinstruction Format:
memory, known as a
microprogram.
● Structure: Divided into functional
● Control Memory Types: ROM or
parts specifying microoperations,
Writable Control Memory
conditions, and branching.
(dynamic microprogramming).
6. Control Unit Operation:
● Microoperations: Atomic
operations of CPU execution,
essential for each instruction
cycle.
● Functions: Sequencing and
execution of microoperations
using control signals.
● Hardwired Implementation:
Combinational circuit generating
control signals based on inputs.
● Micro-programmed
Implementation: Sequences of
instructions controlling
microoperations stored in control
memory.
8. Microprogram Sequencer: