Chapter 3

System Architecture

Dr. Norhaslinda Kamaruddin

Faculty of Computer and Mathematical Sciences
MARA University of Technology
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From hardware to software
 Hardwired systems are inflexible
 Changing function requires changing the wiring
 But general purpose hardware can do different tasks,
given correct control signals
 Instead of rewiring, supply a new set of control signals
as needed
 under the control of a “program”

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From hardware to software

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What is a program?
 A sequence of steps
 For each step, an arithmetic, logical, control or data
movement operation is done
 For each operation, a different set of control signals is
needed

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Execution of the program
 For each operation a unique code is provided
 e.g. ADD, MOVE
 A hardware circuit interprets the code and issues the
control signals
 We have a computer!

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 One of the foremost mathematicians of the 20th
century
John von Neumann
(1903-1957)

First Draft of a Report on the

Edvac (1945)

Edvac:
Electronic Discrete Variables
Automatic Computer
(1952)
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The von Neumann computer
Arithmetic and Logic Unit

Input
Output Main
Equipment Memory

Program Control Unit

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von Neumann/Turing architecture
 Binary representation for data and program
 Main memory storing DATA and PROGRAMS
 Control unit interpreting instructions from memory
and executing
 Normal control flow is sequential
 Specialized device (ALU) to operate on data
 Memory accessed by means of address
 Input and output equipment operated by control unit

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Architecture & Organization
 Architecture expresses those attributes visible to the
programmer (i.e.: functions, commands) --> features
 Instruction set, number of bits used for data
representation, I/O mechanisms, addressing techniques.
 e.g. Is there a multiply instruction?
 Organization is how features are implemented
 Control signals, interfaces, memory technology.
 e.g. Is there a hardware multiply unit or is it done by
repeated addition?
 Architecture = Specification
 Organization = Implementation
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Architecture & Organization
 All Intel x86 family share the same basic architecture
 The IBM System/370 family share the same basic
architecture

 This gives code compatibility

 At least backwards
 Organization differs between different versions

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Structure & Function
 Structure is the way in which components relate to each
other
 Function is the operation of individual components as
part of the structure

 Structure = static relations among components

 Function = dynamic behaviour of each component

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Function
 All computer functions are:
 Data processing
 Data storage
 Data movement
 Control

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 Structure - Top Level
Peripherals (input/output device) Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines

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Main Structural Component

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Computer Components: Top Level
View
 Central Processing Unit (CPU)
 Memory
 I/O
 System Interconnections (usually a “bus")

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Components
 Central Processing Unit (CPU):
 Control Unit
 Arithmetic and Logic Unit
 Internal Registers
 Input/output
 Data and instructions need to get into the system and
results out
 Main memory
 Temporary storage of code and results is needed

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Main Structural Component
 Central processing unit (CPU): Controls the operation of the
computer and performs its data processing functions; often simply
referred to as processor.
 Main memory: Stores data. Temporary storage of code and results
 I/O: Moves data between the computer and its external environment.
 System interconnection: Some mechanism that provides for
communication among CPU, main memory, and I/O. A common
example of system interconnection is by means of a system bus,
consisting of a number of conducting wires to which all the other
components attach

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 Structure - The CPU
CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit

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CPU: Central Processing Unit
 Contained on a single integrated circuit called a processor
(micro) that is located on the motherboard.
 Brain of the computer
 Functions :
 execute programs stored in the main memory by fetching their
instruction
 decoding : translate the program instruction into the
commands that computer can process
 execute them one after another and store back into main
memory
 Contains 3 major components :
1. Control unit (CU)
2. Arithmetic Logic Unit (ALU)
3. Registers

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 Microprocessor Architecture

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CPU structural components
 Control unit: Controls the operation of the CPU and hence the
computer.
 Moves data to and from CPU registers and other hardware
components (no change in data)
 Accesses program instructions and issues commands to the ALU
 Arithmetic and logic unit (ALU): Performs the computer’s
data processing functions.
 Calculations
 Comparisons (Data changes)

 Registers: Provides storage internal to the CPU.

 CPU interconnection: Some mechanism that provides for
communication among the control unit, ALU, and registers.

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CPU Components: Top Level View
Registry

Address Lines

Control Lines
Data Lines
PC
IR

ALU CPU Internal Bus

AC
MBR
MAR

Control Unit

Control Signals

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Register
 is a single, permanent storage location within CPU used for
particular, defined purpose
 holds binary value temporarily for storage, manipulation and/or
for simple calculation
 manipulated directly by CU during execution of instruction
 various types of registers :
 data registers
 address registers
 status registers
 general-purpose register (Accumulators) are considered to be of
the ALU
 hold data that are used for arithmetic operation and the result
 also used to transfer data between different memory and
between I/O and memory

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24
 Register (cont.)
Concept of Registers :
 Small, permanent storage locations within the CPU used for a
particular purpose
 Manipulated directly by the Control Unit
 Wired for specific function
 Size in bits or bytes (not MB like memory)
 Can hold data, an address or an instruction

 Use of Registers :
 Scratchpad for currently executing program
Holds data needed quickly or frequently
 Stores information about status of CPU and currently executing
program
 Address of next program instruction
 Signals from external devices

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 Registers types (1)
 Processor contains a number of registers used for temporary
storage of data other than ALU and Control circuitry Refer side No 28
 Instruction Register (IR) – holds the instruction that is
currently being executed – its output is available to the control
circuits which generate the timing signals that control the
various processing elements involved in executing the
instruction.
 Program Counter (PC) – It contains the address of the
instruction currently being executed. During the execution of
an instruction, the contents of the program counter are
updated to hold the address of the next instruction to be
executed. i.e. PC points to the next instruction that is to be
fetched from the memory.

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 Registers types (2)
 General Purpose Registers (R0 to Rn-1) – Facilitates
communication with the main memory. Access to data in these
registers is much faster than to data stored in memory locations
because the registers are inside the processor. Most modern
computers have 8 to 32 general purpose registers.
 Memory Address Register (MAR) – holds the address of the
location to or from which data are to be transferred
 Memory Data Register (MDR) – contains the data to be
written into or read out of the address location.

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CPU: Function of registers
 Program Counter (PC)
 Address of the next instruction Registers

Address Lines
Data Lines
 Instruction Register (IR) PC
IR
 Code of instruction to execute
 Accumulator (ACC)
AC
 Temporary storage for ALU operations MBR
MAR
 Memory Address Register (MAR)
 Memory address where to R/W
 Memory Buffer Register (MBR)
 Data read/written from/to memory

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 Structure - The Control Unit
Control Unit

CPU
Sequencing
ALU Login
Control
Internal
Unit
Bus
Control Unit
Registers Registers and Control
Decoders Memory

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Control Unit
 Interprets and controls the execution of instruction
 performs fetch/execute cycle
 Issues the signals necessary to control operations of the
microprocessor
 Responsible of sequencing the actions, where it controls what
registers and devices are to be enabled, and when they are to
function
 the control is achieved through a structure called control bus
(carry control signal)
 Bus :
 parallel electrical line or paths connecting a source to a
destination  common path used for specific exchange of data
between various block functions
 can be on printed circuit board or parallel-connected wires in a ribbon
cable or conductive paths etched on the microprocessor chip

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Control Unit (CU) (cont.)
 Subparts:
 Memory management unit: supervises fetching instructions and
data
 I/O Interface: sometimes combined with memory management
unit as Bus Interface Unit
 Instruction decoder
Arithmetic Logic Unit
 Performs calculations and comparisons (data changed) /
arithmetic logic operations
 In short ALU performs :
 arithmetic operations such as addition and subtraction,
division and multiplication
 all logic operations such as AND, OR, XOR etc
 Components :
 Comparator : compares the magnitude of two numbers
placed in the buffer register. Works in conjunction with
status registers to display result of the comparison
 Logic registers : perform the logic operations
 Shifter : move the content of the register one or more
positions to the left or right, perform rotate operation
 Operation of ALU is controlled by the control signal to
facilitate the sequencing and operation of each individual
block.
 Processor Machine Cycle
 Four operations of the CPU comprise a machine cycle

Step 1. Fetch
Obtain program
instruction or data
item from memory

Memory
Step 2.
Step 4. Store Decode
Write result to memory Translate
instruction
Processor into
ALU Control Unit commands
Step 3. Execute
Carry out
command

Chapter 7 CPU and Memory 7-34

Instruction Cycle
 Two phases:
 Fetch
 Execute

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Fetch Phase
 Program Counter (PC) holds address of next
instruction to fetch
 Processor fetches instruction from memory location
pointed to by PC
 Increment PC
 Unless told otherwise
 Instruction loaded into Instruction Register (IR)
 Processor interprets instruction and performs required
actions

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Execute Phase
 Processor decodes instruction and set-up circuits to
perform required actions
 Actual execution of operation:
 Processor-memory
 data transfer between CPU and main memory
 Processor-I/O
 Data transfer between CPU and I/O module
 Data processing
 Some arithmetic or logical operation on data
 Control
 Alteration of sequence of operations
 e.g. jump
 Combination of above
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A very simple processor
 word size: 16 bits
 for instructions and data

 INSTRUCTION: OP_CODE + ADDRESS

 Opcode: 4 bits
 Address: 12 bits

Eg: 1940
 OP_CODES: 1 9 4 0
 1 (address) -> Accumulator Opcode + address
1 refer to Write address
 2Accumulator -> address
to accumulator
 5 (address)+Accumulator -> Accumulator

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Example of Program Execution

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Instruction Cycle -State Diagram

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Interrupts
 Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
 Program
 e.g. overflow, division by zero
 Timer
 Generated by internal processor timer
 Used in pre-emptive multi-tasking
 I/O
 from I/O controller
 Hardware failure
 e.g. memory parity error

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Interrupt Cycle
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler routine
 Process interrupt
 Restore context and continue interrupted program

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Transfer of Control via Interrupts

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Instruction Cycle with Interrupts

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Instruction Cycle (with Interrupts) -
State Diagram

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Multiple Interrupts
 Disable interrupts
 Processor will ignore further interrupts whilst processing one
interrupt
 Interrupts remain pending and are checked after first
interrupt has been processed
 Interrupts handled in sequence as they occur

 Define priorities
 Low priority interrupts can be interrupted by higher priority
interrupts
 When higher priority interrupt has been processed,
processor returns to previous interrupt

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 Multiple Interrupts - Sequential

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Multiple Interrupts – Nested

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Time Sequence of Multiple Interrupts

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Connecting
 All the units must be connected
 Different type of connection for different type of unit
 Memory
 Input/Output
 CPU

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Computer Modules: Overview

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Memory Connection
 Receives and sends data
 Receives addresses (of locations)
 Receives control signals
 Read
 Write
 Timing

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Input/Output Connection(1)
 Similar to memory from computer’s viewpoint
 Data (during output operations)
 Receive data from computer
 Send data to peripheral
 Data (during input operations)
 Receive data from peripheral
 Send data to computer

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Input/Output Connection(2)
 Receive addresses from computer
 e.g. port number to identify peripheral
 Receive control signals from computer
 Send control signals to peripherals
 e.g. spin disk
 Send interrupt signals (control)

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CPU Connection
 Reads instruction and data
 Writes out data (after processing)
 Sends control signals to other units
 Receives (& acts on) interrupts

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Buses
 There are a number of possible interconnection
systems
 Single and multiple BUS structures are most common
 e.g. Control/Address/Data bus (PC)
 e.g. Unibus (DEC-PDP)

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What is a Bus?
 A communication pathway connecting two or more
devices
 more devices share the same bus
 Usually broadcast
 Often grouped
 A number of channels in one bus
 e.g. 32 bit data bus is 32 separate single bit channels

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Data Bus
 Carries data
 Remember that there is no difference between “data”
and “instruction” at this level
 Width is a key determinant of performance
 8, 16, 32, 64 bit

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Address bus
 Identify the source or destination of data
 e.g. CPU needs to read an instruction (data) from a
given location in memory
 Bus width determines maximum memory capacity of
system
 e.g. 8080 has 16 bit address bus giving 64k address space

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Control Bus
 Control and timing information
 Memory read/write signal
 Interrupt request
 Clock signals

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Bus Interconnection Scheme

 Every device is attached to the bus:

 its use needs to be coordinated

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What do buses look like?
Big and Yellow?
 Parallel lines on circuit boards
 Ribbon cables
 Strip connectors on mother boards
 e.g. PCI
 Sets of wires

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Single Bus Problems
 Lots of devices on one bus leads to:
 Propagation delays
 Long data paths mean that co-ordination of bus use can
adversely affect performance
 If aggregate data transfer approaches bus capacity
 Most systems use multiple buses to overcome these
problems

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Traditional (with cache)

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High Performance Bus

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Bus Types
 Dedicated
 Separate data & address lines
 Multiplexed
 Shared lines
 Address valid or data valid control line
 Advantage - fewer lines
 Disadvantages
 More complex control
 Ultimate performance

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Bus arbitration
 Process of ensuring only 1 devices places information
onto the bus at a time
 Master - slave mechanism
 Master is given control of the bus and can place information
onto it
 Slave receives the information from the master
 Two methods
 Centralized
 Central bus controller mediates all device requests for the bus

 May be part of CPU or a hardware of its own (arbiter)

 Decentralized
 No centralized controller

 All devices contain logic to control access to the bus

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Bus timing
 Synchronous
 Occurrence of events on the bus is determined by the clock
 All events start at the beginning of a clock cycle
 Example: PCI bus (Peripheral Component Interface bus)

 Asynchronous
 The occurrence of one event follows and depends on the
occurrence of a previous event
 More flexible than synchronous bus but more complicated as
well
 Accommodates wider range of device speeds
 Example: Futurebus+

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