ARM Cortex-M Series:

Hardware
 Textbook
• ARM Assembly Language Fundamentals and Techniques, 2nd edition, W.
Hohl, and C. Hinds, CRC Press, 2014, ISBN-10: 1482229854 – 90%
• Computers as Components – Principles of Embedded Computing System
Design, 4th Edition, Marilyn Wolf, October 2016, 978-0128053874 – 10%
 What is ARM Architecture
• ARM architecture is a family of RISC-based processor architectures
• Well-known for its power efficiency
• Hence widely used in mobile devices, such as smart phones and tablets
• Designed and licensed to a wide eco-system by ARM
 ARM Processor Families

ARM Processor ARM

Families
Processor Families
• Cortex-A series (Application) • Cortex-A series (Application) Cortex-A57
• High performance processors capable of full Operating System (OS) Cortex-A53

support; – High performance processors Cortex-A15

Cortex-A9 Cortex-A
• Applications include smart-phones, digital
capable TV of
, smart
full books, home
Operating Sys- Cortex-A8
gateways etc. Cortex-A7
Cortex-A5

• Cortex-R series (Real-time) tem (OS) support; Cortex-R7

• High performance for real time applications;

Cortex-R5 Cortex-R
– Applications include smart- Cortex-R4

• High reliability Cortex-M4 New!: Cortex-M7, Cortex-M33

phones,
• Applications include automotive braking digital
system, power- TV, smart
trains etc.
Cortex-M3
Cortex-M1 Cortex-M
• Cortex-M series (Microcontroller) books, home gateways etc.
Cortex-M0+
Cortex-M0 New!: Cortex-M23 (no DSP)

• Cost-sensitive solutions for deterministic

• Cortex-R microcontroller applications;
series (Real-time)
SC000
SC100 SecurCore
• Applications include microcontrollers, mixed signal devices, smart SC300

sensors, automotive body electronics and airbags;

– High more recently
performance IoT
for real- ARM11
ARM9 Classic
• Secure Core series time applications;
ARM7

• High security applications.

– High reliability
• Previous classic processors: Include ARM7, ARM9, ARM11
As
Asof
ofJan
Dec2017
2013

families – Applications include automotive braking system, power-

• Still in market
trains etc.
 Design an ARM-based SoC
Design an ARM-based SoC - Example
• Select a set of IP cores from ARM and/or other third-party IP
vendors
• Select a set of IP (Intellectual Property) cores from ARM and/or other third-
party IP vendors
• Integrate
• Integrate IP into
IP cores cores into achip
a single single chip design
design
• Give
• Give designdesign to semiconductor
to semiconductor foundriesfoundries for chip fabrication
for chip fabrication
IP libraries SoC
Cortex-A9 Cortex-R5 Cortex-M4 ARM
ROM RAM
processor
ARM7 ARM9 ARM11
System bus ARM-based
DRAM ctrl FLASH ctrl SRAM ctrl SoC
Peripherals
AXI bus AHB bus APB bus

GPIO I/O blocks Timer

External Interface

Licensable IPs SoC Design

1. https://www.arm.com/products/processors/cortex-m
 ARM Cortex-M Series
• Cortex-M series: Cortex-M0, M0+, M1, M3, M4, M7, M33.
• Energy-efficiency
• Lower energy cost, longer battery life
• Smaller code
• Lower silicon costs
• Ease of use
• Faster software development and reuse
• Embedded applications
• Smart metering, human interface devices, automotive and industrial control systems, white
goods, consumer products and medical instrumentation, IoT
• Companies Making ARM Chips
• Apple, AppliedMicro, Microchip (Atmel), Broadcom, Cypress Semiconductor, Nvidia, NXP,
Samsung Electronics, ST Microelectronics, and Texas Instruments (http://en.wiki-
pedia.org/wiki/ARM_architecture)
• More — Xilinx (Zynq), ...
 Cortex-M Series

oT,
.
rals

Harvard Architecture
 CORTEX-M: Core + Peripherals
• Chip • Peripherals
• Memory • ADC (Analog to Digital Converter)
• FLASH: Non-Volatile / Instruction memory • LCD Controller
• SRAM/DRAM: Volatile / data memory • SPI (Serial Peripheral Interface, eg.
• Processor Core Sensor)
• I2C (Inter-Integrated Circuit, eg. I/O,
• ALU
A/D, D/A, EEPROM)
• Processor Control Unit (CPU) • Etc.
• Registers
• Special Purpose Registers (SP, FP)
• General Purpose Registers (R0-R13)
• Buses
• Data Bus
• Instruction Bus
• Bus bridge to connect diff. buses
• Advanced High-performance Bus (AHB)
• Advanced Peripheral Bus (APB)
• GPIO (General Purpose Input/Output)
 ARM-v7 Cortex-M4 Processor - Introduction
• Cortex-M4 Processor
• Introduced in 2010
• Designed with large variety of highly efficient signal processing features
• Features extended single-cycle multiply accumulate instructions, optimized SIMD
arithmetic, saturating arithmetic and an optional Floating Point Unit.
• High Performance Efficiency
• 1.25 MIPS (Million Instructions Per Second) at the order of μWatts
• Low Power Consumption
• Longer battery life – especially critical in mobile products
• Enhanced Determinism
• The critical tasks and interrupt routines can be served quickly in a known number of
cycles (trying to perform as Cortex-R)
Cortex-M4 Processor Block Diagram With Peripheral Connectivity

Cortex-M4 Block Diagram

ARM Cortex-M4 Microprocessor

Optional FPU
Nested Vector Optional
Optional Interrupt
WIC Embedded
Controller Processor core Trace Macrocell
(NVIC)

Optional
Optional Memory Optional Serial
Debug
protection unit Wire Viewer
Access Port

Optional Optional
Flash Data
patch watchpoints

Cortex-M4 Block D
Bus matrix
SRAM and
Code interface
peripheral interface
 Cont..
• Processor core
• Contains internal registers, the ALU, data path, and some control logic
• Registers include sixteen 32-bit registers for both general and special usage
• Nested Vectored Interrupt Controller (NVIC)
• Up to 240 interrupt request signals
• Automatically handles nested interrupts, such as comparing priorities between interrupt
requests and the current priority level
• Wakeup Interrupt Controller (WIC)
• For low-power applications, the microcontroller can enter sleep mode by shutting down
most of the components.
• When an interrupt request is detected, the WIC can inform the power management unit
to power up the system.
• Memory Protection Unit (MPU) - optional
• Used to protect memory content, e.g. make some memory regions read-only or
preventing user applications from accessing privileged application data
 Cont..
• Bus interconnect
• Allows data transfer to take place on different buses simultaneously
• Provides data transfer management, e.g. a write buffer, bit- oriented operations (bit-
band)
• May include bus bridges (e.g. AHB-to-APB bus bridge) to connect different buses into a
network using a single global memory space
• Includes the internal bus system, the data path in the processor core, and the AHB LITE
interface unit
• Debug subsystem
• Handles debug control, program breakpoints, and data watchpoints
• When a debug event occurs, it can put the processor core in a halted state, where
developers can investigate the status of the processor at that point, such as register
values and flags
 TM4C123GH6PM MC Block Diagram
• JTAG (Joint Test Action Group)– Design
testing and Verification
• SWD (Serial Wire Debug)
• ETM (Embedded Trace Macrocell)- low-
power debug tool for instruction trace
• NVIC (Nested Vector Interrupt)- Use for
prioritizing interrupts
• MPU (Memory Protection Unit)- Memory
management
Tiva C Series
TM4C123G LaunchPad
 Cortex-M4 Pipeline
• Processor pipeline stages
• Three-stage pipeline: fetch, decode, and execution
• Some instructions may take multiple cycles to execute, in which case the pipeline will be
Three-state pipeline: Fetch, Decode, Execution
stalled
• The pipeline will be flushed
• Pipelining allows if a branch
hardware instruction
resources to be fullyis executed
utilized
• One 32-bitcan
• Up to two instructions instruction or two 16-bit
be fetched in oneinstructions
transfer can(16-
be fetched.
bit instructions)

1. Fetch
instruction at
PC address

3. Execute 2. Decode
the the
instruction instruction

Pipeline of 32-bit instructions

 Pipeline Cont..
3-Stage Pipeline (1/2)

Multi-cycle Instruction
Fetch
– The instruction is fetched from memory and placed in the instruction pipeline
Decode
– The instruction is decoded and the datapath control signals prepared for the
next cycle
Execute
– The register bank is read, an operand shifted, the ALU result generated and
written back into destination register
SOC Consortium Course Material

Memory access (fetch, data transfer) in every cycle

Datapath used in every cycle (execute, address calculation,
 Cortex-M4 Registers
• Processor registers
• The internal registers are used to store and process temporary data within the processor
core
• All registers are inside the processor core, hence they can be accessed quickly
• Load-store architecture
• To process memory data, they have to be first loaded from memory to registers,
processed inside the processor core using register data only, and then written back to
memory if needed
• Cortex-M4 registers
• Register bank
• Sixteen 32-bit registers (thirteen are used for general-purpose)
• Special registers
Register
Register bank R0
R1

Bank (V7-M) R2
R3
Low
R4 Registers

R5
General purpose
R6
register
R7
R8
R9
R10 High
Registers
R11
R12 MSP
Stack Pointer (SP) R13(banked) Main Stack Pointer

Link Register (LR) R14 PSP

Program Counter (PC) R15 Process Stack Pointer

Special registers Program Status Registers (PSR) x PSR APSR EPSR IPSR
PRIMASK Application Execution Interrupt
PSR PSR PSR
Interrupt mask register FAULTMASK
BASEPRI
Stack definition CONTROL
 Register Bank User/System Supervisor Abort
Mode
Undefined Interrupt Fast interrupt

(ARM7TDMI) R0
R1
R0
R1
R0
R1
R0
R1
R0
R1
R0
R1

• ARM7TDMI processor
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3

has a total of 37 R4
R5
R4
R5
R4
R5
R4
R5
R4
R5
R4
R5
registers R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
• 30 general-purpose R8 R8 R8 R8 R8 R8_FIQ

registers, i.e., registers R9

R10
R9
R10
R9
R10
R9
R10
R9
R10
R9_FIQ
R10_FIQ
which can hold any R11 R11 R11 R11 R11 R11_FIQ

value R12
R13
R12
R13_SVC
R12 R12
R13_ABORT R13_UNDEF
R12
R13_IRQ
R12_FIQ
R13_FIQ
• 6 status registers R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ
PC PC PC PC PC PC
• A Program Counter
register CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF
CPSR
SPSR_IRQ
CPSR
SPSR_FIQ

= banked register
 General Purpose Registers
• R0 – R12: general purpose registers
• Low registers (R0–R7): can be accessed by any instruction
• High registers (R8 – R12): sometimes cannot be accessed e.g. by some Thumb (16-bit)
instructions
 Stack Pointer (SP) and Link Register (LR)
• R13: Stack Pointer (SP)
Cortex-M4 Registers (cont.)
• Records the current address of the stack
• Used for saving the context of a program while switching between tasks
• R14:
• Cortex-M4 hasLink Register (LR)
two SPs:
• Main–SPThe
– usedLRin applications
is used tothat require
store theprivileged access e.g.of
return address OSakernel, and exception handlers,
subroutine
• Process SP - used in base-level application code (when not running an exception handler)
or a function call
• R14: Link Register (LR)
• The LR is–used
Thetoprogram
store the counter (PC) of
return address will load the orvalue
a subroutine fromcall
a function LR
• The program counter
after (PC) will
a function is load the value from LR after a function is finished
finished
Current PC Current LR
PC LR
1. Save current Main Main
PC to LR Program C Program
o C
code d Load PC with the code o
LR e d
re address in LR to e
g re
io return to the main g
2. Load PC with n program io
the starting n
address of the
subroutine subroutine
subroutine Current PC
PC

Call a subroutine Return from a subroutine to the main program

 bit instruction code), except branching op
– A branching operation, such as function c
Program Counter (PC) the PC to a specific address, meanwhile it
PC to the Link Register (LR)
• Program Counter (PC) Data Data

• Records the address of the current instruction code PUSH POP

• Automatically incremented by 4 at each operation Low

(for 32- bit instruction code), except branching
operations Stack Address

• A branching operation, such as function calls, will SP

change the PC to a specific address, meanwhile it PC

High

saves the current PC to the Link Register (LR) Heap

Code
 • xPSR, combined Program Status Register

Special Purpose
– Provides Registers
information (SPR)
about program execution and ALU
flags
• xPSR, combined Program Status Register
– Application PSR (APSR)
• Provides information about program execution and ALU flags
• – Interrupt
Application PSR–(IPSR)
PSR (APSR) ALU status
• Interrupt PSR (IPSR)
• – Execution
Execution PSR (EPSR)
PSR (EPSR)

APSR NZC VQ Reserved

IPSR Reserved ISR number

EPSR ICI/IT T Reserved ICI/IT

xPSR NZC VQ ICI/IT T Reserved ICI/IT ISR number

bit31 bit24 bit16 bit8 bit0

 Program Status Register (xPSR)
• APSR
• N: negative flag – set to one if the result from ALU is negative
• Z: zero flag – set to one if the result from ALU is zero
• C: carry flag – set to one if an unsigned overflow occurs
• V: overflow flag – set to one if a signed overflow occurs
• Q: sticky saturation flag – set to one if saturation has occurred in saturating arithmetic
instructions, or overflow has occurred in certain multiply instructions
• IPSR
• ISR number – current executing interrupt service routine number
• EPSR
• T: Thumb state – always one since Cortex-M4 only sup- ports the Thumb state (more on
processor states in the next module)
• IC/IT: Interrupt-Continuable Instruction (ICI) bit, IF- THEN instruction status bit
 Interrupt mask registers
• 1-bit PRIMASK
• Set to one will block all the interrupts apart from non-maskable
interrupt (NMI) and the hard fault exception
• 1-bit FAULTMASK
• Set to one will block all the interrupts apart from NMI
• 8-bit BASEPRI
• Set to one will block all interrupts of the same or lower level (only
allow for interrupts with higher priorities)
 • CONTROL: special register
CONTROL: special register
– 1-bit stack definition
• 1-bit stack definition
– Set to one: use the process stack pointer (PSP)
• Set to one: use the process stack pointer (PSP)
– Clear
• Clear to zero:
to zero: useuse
thethe main
main stack
stack pointer
pointer (MSP)
(MSP)
PRIMASK Reserved

FAULTMASK Reserved

BASEPRI Reserved

CONTROL Reserved

bit31 bit24 bit16 bit8

Stack definition
 address of the
subroutine subroutine
subroutine Current PC
PC

Nested Vector Table (V7-M)

Call a subroutine Return from a subroutine to the main program

• xPSR, combined Program Status Register The Programmer’s Model

• Table in memory
– Provides informationthat
aboutthe processor
program branches
execution and ALU to when an exception
occurs,
flags based on the cause of the exception TABLE 2.3
Cortex-M4 Exception Vectors
Start fromPSR
– •Application address 0x0000 0000
(APSR) Exception Type Exception No. Vector Address
• Access through ISR (Interrupt Service Routine)
– Interrupt PSR (IPSR)
(Top of Stack) — 0x00000000
Reset 1 0x00000004
NMI 2 0x00000008
– Execution PSR (EPSR) Hard fault 3 0x0000000C
Memory management fault 4 0x00000010
Bus fault 5 0x00000014
APSR NZC VQ Reserved
Usage fault 6 0x00000018
IPSR Reserved ISR number SVcall 11 0x0000002C
Debug monitor 12 0x00000030
EPSR ICI/IT T Reserved ICI/IT PendSV 14 0x00000038
SysTick 15 0x0000003C
Interrupts 16 and above 0x00000040 and above
xPSR NZC VQ ICI/IT T Reserved ICI/IT ISR number

bit31 bit24 bit16 bit8 bit0

over the next few chapters, we’ll discover that the Cortex-M4 only executes Th
instructions, rather than ARM instructions as the ARM7TDMI does, and the
col requires it. This vector table is relocatable after the processor comes out o
ECE 5655/4655 Real-Time DSP however,
2–19 our focus for now is to write short blocks of code without any excep
errors, covering procedural details first and worrying about all of the variation
be ignored.

Vector Table (ARM7TDMI)

The format of the Current Program Status Register and the Saved Program Status
Register is shown in Figure 2.4. You can see that it contains four bits at the top,
ARM Assembly
The Programmer’s Language
Model 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M M M MM
N Z C V Do not modify/Read as zero TABLE 2.2I F T
4 3 2 1 0
ARM7TDMI Exception Vectors
TABLE 2.1
Exception Type Mode Vector Address
FIGURE 2.4 Format of the program status registers.
The Mode Bits Reset SVC 0x00000000
Undefined instruction UNDEF 0x00000004
xPSR[4:0] Mode Software Interrupt (SVC) SVC 0x00000008
Prefetch abort (instruction fetch memory abort) ABORT 0x0000000C
10000 User mode Data abort (data access memory abort) ABORT 0x00000010
10001 FIQ mode IRQ (interrupt) IRQ 0x00000018
FIQ (fast interrupt) FIQ 0x0000001C
10010 IRQ mode
10011 Supervisor mode
are actual ARM instructions, so the next instruction that the machine will likel
10111 Abort mode fetch is a branch (B) instruction, assuming the programmer put such an instructio
11011 Undefined modeat address 0x18. Once this branch instruction is executed, the processor will begi
fetching instructions for the interrupt handler that resides at the target address, als
11111 System mode specified with the branch instruction, somewhere in memory. It is worth noting her
that many processors, including the Cortex-M4, have addresses at these vector loca
 Concept of Memory – 32 bit Architecture Data
Memory Address
8 bits 32 bits

• Memory is arranged as
• a series isofarranged
Memory “locations”
as a series of “locations” 0xFFFFFFFF
• Each location has a unique• Each location has a unique “address”
“address”
• Each location holds a byte (byte-addressable)
• Each location holds a byte• (byte-addressable)
e.g. the memory location at address 0x080001B0
• e.g. the memory location atcontains
address the0x080001B0 contains
byte value 0x70, i.e., 112the byte
value 0x70, i.e., 112 • The number of locations in memory is limited
• The number of locations ••ine.g. 4 GB of RAM
memory is limited
1 Gigabyte (GB) = 230 bytes
70
BC
0x080001B0
0x080001AF
• e.g.4GB of RAM • 232 locations è 4,294,967,296 locations! 18 0x080001AE
01 0x080001AD
• 1 Gigabyte (GB) = 230 bytes
• Values stored at each location can represent A0 0x080001AC
either program
• 232 locations à 4,294,967,296 locationsdata or program instructions
• e.g. the value 0x70 might be the code used to tell
• Values stored at each location can represent
the processor either
to add two values program
together
data or program instructions
• e.g. the value 0x70 might be the code used to tell the processor to
add two values together 0x00000000
13 Memory
 Cortex-M4 Memory Map
• The Cortex-M4 processor has 4 GB of memory address space
• Support for bit-band operation (detailed later)
• The 4GB memory space is architecturally defined as a number of regions
• Each region is given for recommended usage
• Easy for software programmer to port between different devices
• Nevertheless, despite of the default memory map, the actual usage of the
memory map can also be flexibly defined by the user, except some fixed
memory addresses, such as internal private peripheral bus
 Cortex M4 Memory Map
Reserved for other purposes Vendor specific 0xFFFFFFFF
ROM table
Memory 0xE0100000
512MB
Private peripherals Private Peripheral Bus 0xE00FFFFF External PPB
e.g. NVIC, SCS (PPB) 0xE0000000
External PPB
0xDFFFFFFF
Embedded trace macrocell
Mainly used for external peripherals Trace port interface unit
e.g. SD card External device 1GB
Reserved
0xA0000000
0x9FFFFFFF System Control Space, including
Mainly used for external memories Nested Vectored Interrupt
e.g. external DDR, FLASH, LCD External RAM 1GB Controller (NVIC) Internal PPB
0x60000000 Reserved
Mainly used for on-chip peripherals 0x5FFFFFFF
Fetch patch and breakpoint unit
e.g. AHB, APB peripherals Peripherals 512MB
0x40000000 Data watchpoint and trace unit
0x3FFFFFFF
Mainly used for data memory
e.g. on-chip SRAM, SDRAM SRAM 512MB Instrumentation trace macrocell
0x20000000
0x1FFFFFFF
Mainly used for program code
Code 512MB
e.g. on-chip FLASH 0x00000000
 M4 Memory Map
• Code Region
• Used to store program code
• On-chip memory, such as on-chip FLASH
• SRAM Region
• Used to store data, such as heaps and stacks
• On-chip memory; despite its name “SRAM”, the actual device could be SRAM, SDRAM
or other types
• Peripheral Region
• Used for peripherals, such as Advanced High performance Bus (AHB) or Advanced
Peripheral Bus (APB) peripherals
 M4 Memory Map
• External RAM Region
• Primarily used to store large data blocks, or memory caches
• Off-chip memory, slower than on-chip SRAM region
• External Device Region
• Primarily used to map to external devices
• Off-chip devices, such as SD card
• Internal Private Peripheral Bus (PPB)
• Used inside the processor core for internal control
• Within PPB, a special range of memory is defined as System Control Space (SCS)
• The Nested Vectored Interrupt Controller (NVIC) is part of SCS
Loading Code and Data into Memory
Loading Code and Data into Memory

SRAM
 • However, Endianness only exists in the hardware level
• Endian refers to the order of bytes stored in memory
Endianness
– Little endian: lowest byte of a word-sizeAddress
data is stored in
[31:24] [23:16] [15:8] [7:0]

bit 0 to bit
• Endian 7
refers to the order of bytes stored in memory
0x00000008 Byte3 Byte2 Byte1 Byte0
Word 3
• Little
– Big endian:
endian: lowestlowest byte
byte of of a word-size
a word-size data isdata is stored
stored in bit in bit 0 to bit 7
0x00000004 Byte3 Byte2 Byte1 Byte0
Big endian: lowest byte of a word-size data is stored in bit 24 to Word
24• to bit 31 bit 231
Cortex-M4
• •Cortex-M4 supports
supports both
both little littleand
endian endian and big endian
big endian
0x00000000 Byte3 Byte2
Word 1
Byte1 Byte0

• Instruction
• However, REV only
Endianness reverses
existsthe
in byte order oflevel
the hardware a register, and RBIT reverses the bit order of
a register. Little endian 32-bit memory

Address [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]

0x00000008 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3

Word 3 Word 3

0x00000004 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3

Word 2 Word 2

0x00000000 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3

Word 1 Word 1

Little endian 32-bit memory Big endian 32-bit memory

[31:24] [23:16] [15:8] [7:0]

 Suppose a register that contained the 32-bit value
Example 0x0A0B0C0D, and this value needed to be stored to memory
addressesthat
• Suppose a register 0x400 to 0x403.
contained the 32-bit value 0x0A0B0C0D, and this
value needed to be stored
Cortex-M4: to memory
instruction REVaddresses
reverses the0x400 to 0x403.
byte order of a
register, and RBIT reverses the bit order of a register.

2 TCES430, Autumn 2019 10/3/2019

 ARM7TDMI. If you have a Cortex-M4 that includes a floating-point unit, the

Processor Operating Modes actually more. Excluding peripherals, the Cortex-M4 with floating-point har
contains the following registers as part of the programmer’s model:

• Operating modes that allow

• 17different levels
general purpose of access
registers, to resources
i.e., registers than can hold any value
• A status register than can be viewed in its entirety or in three specialized vi
• Handler mode – Background (as Interrupt Service Routine)
• Thread mode - Foreground
Privileged User
• Resource access levels
• Privileged Use: Exception
• User Handler handling
mode
Stack: Main

Use: Applications Use: Applications

Thread
mode Stack: Main or Stack: Main or
Process Process
 Bit-band Operations
• Bit-band operation allows a single load/store operation to access a single bit in the
memory, for example, to change a single bit of one 32-bit data:
• Normal operation without bit-band (read-modify-write)
• Read the value of 32-bit data
• Modify a single bit of the 32-bit value (keep other bits unchanged)
• Write the value back to the address
• Bit-band operation
• Directly write a single bit (0 or 1) to the “bit-band alias address” of the data
• Bit-band alias address
• Each bit-band alias address is mapped to a real data address
• When writing to the bit-band alias address, only a single bit of the data will be changed
• Only works in the specific memory region
• For 1-bit bit-band support requires 32-bits of alias memory
• Onchip Data: 0X2000.0000 – 0X2000.7FFF address requires alias address of 0X2200.0000 –
0X220F.FFFF
• Peripheral Data: 0X4000.0000 – 0X400F.FFFF address requires alias address of 0X4200.0000 –
0X423F.FFFF
 Bit-band
Bit-band Operations
Operation ExampleExample
• For example,
• For in order
example, to to
in order setset(‘1’) in bit[3=4
bit[3] in wordth]data
in word data in address
in address
0x20000000:
0x20000000:
;Read-Modify-Write Operation ;Bit-band Operation

LDR R1, =0x20000000 ;Setup address LDR R1, =0x2200000C ;Setup address
LDR R0, [R1] ;Read MOV R0, #1 ;Load data
ORR.W R0, #0x8 ;Modify bit STR R0, [R1] ;Write
STR R0, [R1] ;Write back

• Read-Modify-Write operation
• Read-Modify-Write operation
• Read the real data address (0x20000000)
• – Readthe
Modify thedesired
real data
bitaddress (0x20000000)
(retain other bits unchanged)
• Write the modified
– Modify databit
the desired back
(retain other bits unchanged)
• Bit-band operation
– Write the modified data back
• Directly set the bit by writing ‘1’ to address 0x2200000C, which is the alias address of
• the fourthoperation
Bit-band bit of the 32-bit data at 0x20000000
• In effect, this single instruction is mapped to 2 bus transfers: read data from
– Directly set
0x20000000 the buffer,
to the bit by writing
and then‘1’ to address
write 0x2200000C,
to 0x20000000 from the buffer with bit [3] set
which is the alias address of the fourth bit of the 32-bit
 Bit-band Region Mapping in Bit-band Alias
Region
• bit_word_offset =
(byte_offset x 32) +
(bit_number × 4)
• bit_word_addr =
bit_band_base +
bit_word_offset
• Where:
Bit_word_offset is the
position of the target bit in
the bit-band memory region.
Bit_word_addr is the address
of the word in the alias
memory region that maps to
the targeted bit.
Bit_band_base is the starting
address of the alias region.
Byte_offset is the number of
the byte in the bit-band
region that contains the
targeted bit.
Bit_number is the bit position
(0-7) of the targeted bit.
 used as the bit-band alias region for 1MB data
(0x20000000 – 0x200FFFFF)
Example
• Peripherals region
• We want to modify
– 32MB the 13th
memory bit(0x42000000
space of the memory–word stored at address
0x43FFFFFF) is
0x20000FF0usedusing
as bit
thebanding. What
bit-band memory
alias address,
region for from
1MB the bit band
data
alias region, should be used to modify this bit?
(0x40000000 – 0x400FFFFF)
0x43FFFFFF

32MB Bit-band alias

0x42000000
0x41FFFFFF
31MB non-bit-band region
0x40100000
External RAM
0x40000000 1MB Bit-band region
0x60000000
0x5FFFFFFF
0x23FFFFFF Peripherals 512MB
0x40000000
32MB Bit-band alias 0x3FFFFFFF
0x22000000 SRAM 512MB
0x21FFFFFF 0x20000000
31MB non-bit-band region 0x1FFFFFFF
0x20100000
Code 512MB
0x20000000 1MB Bit-band region 0x00000000
 ARM Bus Architecture
• ARM has created a separate bus specification for single-chip systems.
• The AMBA (Adv. Microcontroller Bus Archi.) bus supports CPUs, memories,
and peripherals integrated in a system-on-silicon.
• The AMBA high-performance bus (AHB) optimized for high-speed transfers and is
directly connected to the CPU.
• It supports several high-performance features: pipelining, burst transfers, split transactions, and
166busCHAPTER
multiple 4 Bus-Based Computer Systems
masters.
• A bridge can be used to connect the AHB to an AMBA peripherals bus (APB)
AMBA
high-performance bus (AHB)

SRAM ARM Low-speed

CPU I/O device
External

Bridge
DRAM
controller
High-speed
I/O Low-speed
device I/O device
AMBA
On-chip peripherals bus (APB)
 Note: Within the memory map, attempts to read or write addresses in reserved spaces result in
a bus fault. In addition, attempts to write addresses in the flash range also result in a bus

Memory Map for Tiva TM4C123GH6PM MC

fault.

Table 2-4. Memory Map

Start End Description For details,
see page ...
Memory
0x0000.0000 0x0003.FFFF On-chip Flash 540
0x0004.0000 0x1FFF.FFFF Reserved -
0x2000.0000 0x2000.7FFF Bit-banded on-chip SRAM 525
0x2000.8000 0x21FF.FFFF Reserved -
0x2200.0000 0x220F.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 525
0x2000.0000
0x2210.0000 0x3FFF.FFFF Reserved -
Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 0 776
0x4000.1000 0x4000.1FFF Watchdog timer 1 776
0x4000.2000 0x4000.3FFF Reserved -
0x4000.4000 0x4000.4FFF GPIO Port A 658
0x4000.5000 0x4000.5FFF GPIO Port B 658

• Page 92
 Tiva TM4C123GH6PM Microcontroller

Memory Map for Tiva TM4C123GH6PM MC

Table 2-4. Memory Map (continued)
Start End Description For details,
see page ...
0x4000.6000 0x4000.6FFF GPIO Port C 658
0x4000.7000 0x4000.7FFF GPIO Port D 658
0x4000.8000 0x4000.8FFF SSI0 967
0x4000.9000 0x4000.9FFF SSI1 967
0x4000.A000 0x4000.AFFF SSI2 967
0x4000.B000 0x4000.BFFF SSI3 967
0x4000.C000 0x4000.CFFF UART0 903
0x4000.D000 0x4000.DFFF UART1 903
0x4000.E000 0x4000.EFFF UART2 903
0x4000.F000 0x4000.FFFF UART3 903
0x4001.0000 0x4001.0FFF UART4 903
0x4001.1000 0x4001.1FFF UART5 903
0x4001.2000 0x4001.2FFF UART6 903
0x4001.3000 0x4001.3FFF UART7 903
0x4001.4000 0x4001.FFFF Reserved -
Peripherals
 0x4001.0000 0x4001.0FFF UART4 903
0x4001.1000 0x4001.1FFF UART5 903

Memory Map for Tiva TM4C123GH6PM MC

0x4001.2000 0x4001.2FFF UART6 903
0x4001.3000 0x4001.3FFF UART7 903
0x4001.4000 0x4001.FFFF Reserved -
Peripherals
0x4002.0000 0x4002.0FFF I2C 0 1017
0x4002.1000 0x4002.1FFF I2C 1 1017

• Page 93 0x4002.2000
0x4002.3000
0x4002.2FFF
0x4002.3FFF
I2C 2
2
I C3
1017
1017
0x4002.4000 0x4002.4FFF GPIO Port E 658
0x4002.5000 0x4002.5FFF GPIO Port F 658
0x4002.6000 0x4002.7FFF Reserved -
0x4002.8000 0x4002.8FFF PWM 0 1240
0x4002.9000 0x4002.9FFF PWM 1 1240
0x4002.A000 0x4002.BFFF Reserved -
0x4002.C000 0x4002.CFFF QEI0 1310
0x4002.D000 0x4002.DFFF QEI1 1310
0x4002.E000 0x4002.FFFF Reserved -
0x4003.0000 0x4003.0FFF 16/32-bit Timer 0 725
0x4003.1000 0x4003.1FFF 16/32-bit Timer 1 725
0x4003.2000 0x4003.2FFF 16/32-bit Timer 2 725
0x4003.3000 0x4003.3FFF 16/32-bit Timer 3 725
0x4003.4000 0x4003.4FFF 16/32-bit Timer 4 725
0x4003.5000 0x4003.5FFF 16/32-bit Timer 5 725
0x4003.6000 0x4003.6FFF 32/64-bit Timer 0 725
0x4003.7000 0x4003.7FFF 32/64-bit Timer 1 725
0x4003.8000 0x4003.8FFF ADC0 818
0x4003.9000 0x4003.9FFF ADC1 818
0x4003.A000 0x4003.BFFF Reserved -
0x4003.C000 0x4003.CFFF Analog Comparators 1220
 The Cortex-M4F Processor

Memory Map for Tiva TM4C123GH6PM MC

Table 2-4. Memory Map (continued)
Start End Description For details,
see page ...
0x4003.D000 0x4003.FFFF Reserved -

• Page 94 0x4004.0000
0x4004.1000
0x4004.0FFF
0x4004.1FFF
CAN0 Controller
CAN1 Controller
1067
1067
0x4004.2000 0x4004.BFFF Reserved -
0x4004.C000 0x4004.CFFF 32/64-bit Timer 2 725
0x4004.D000 0x4004.DFFF 32/64-bit Timer 3 725
0x4004.E000 0x4004.EFFF 32/64-bit Timer 4 725
0x4004.F000 0x4004.FFFF 32/64-bit Timer 5 725
0x4005.0000 0x4005.0FFF USB 1114
0x4005.1000 0x4005.7FFF Reserved -
0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) 658
0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) 658
0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) 658
0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) 658
0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) 658
0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture) 658
0x4005.E000 0x400A.EFFF Reserved -
0x400A.F000 0x400A.FFFF EEPROM and Key Locker 540
0x400B.0000 0x400F.8FFF Reserved -
0x400F.9000 0x400F.9FFF System Exception Module 485
0x400F.A000 0x400F.BFFF Reserved -
0x400A.F000 0x400A.FFFF EEPROM and Key Locker 540
0x400B.0000 0x400F.8FFF Reserved -

Memory Map for Tiva TM4C123GH6PM MC

0x400F.9000
0x400F.A000
0x400F.9FFF
0x400F.BFFF
System Exception Module
Reserved
485
-
0x400F.C000 0x400F.CFFF Hibernation Module 505
0x400F.D000 0x400F.DFFF Flash memory control 540
0x400F.E000 0x400F.EFFF System control 231
0x400F.F000 0x400F.FFFF µDMA 606
0x4010.0000 0x41FF.FFFF Reserved -
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
0x4400.0000 0xDFFF.FFFF Reserved -
Private Peripheral Bus
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 71
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 71
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 71
0xE000.3000 0xE000.DFFF Reserved -
0xE000.E000 0xE000.EFFF Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB) 134
0xE000.F000 0xE003.FFFF Reserved -
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 72
0xE004.1000 0xE004.1FFF Embedded Trace Macrocell (ETM) 71
0xE004.2000 0xFFFF.FFFF Reserved -