CMOS Digital Integrated Circuits
Chapter 8
Sequential MOS Logic
Circuits
S.M. Kang, Y. Leblebici, and
C. Kim
1 Copyright © 2014 McGraw-Hill Education. Permission required for reproduction or display.
Introduction (1)
Sequential Circuit Classification of logic
circuits
Combinational block Based on behavior
+memory block
2 © CMOS Digital Integrated Circuits – 4th Edition
Bistable Elements : Cross Coupled Inverter
Static behavior of the two inverter basic bistable
elements
vo1 vi 2
vo 2 vi1 VTC of the two inverters & qualitative
view of the potential energy levels
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Bistable Elements : Circuit
Circuit diagram Time domain behavior
Stable operating point : Two energy minima
Unstable operating point: One energy maximum
All four transistors are in saturation
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Bistable Elements : Small Signal (1)
Small signal input and output currents of the inverters
ig1 id 2 g m vg 2 ,ig 2 id 1 g m vg1(8.1)
q1 q
vg 1 , vg 2 2
Cg Cg
dvg1 dvg 2
ig 1 C g , ig 2 C g
dt dt
(8.1)=>(8.3) dvg1 dvg 2 (8.2) gm dq g dq
g m vg 2 C g , g m v g1 C g q2 1 , m q1 2
dt dt Cg dt Cg dt
2 τ0
gm Cg d q1 2
d q1 g m2 d 2 q1 1 Cg
q1 2 q1 q1 with 0
Cg g m dt 2
dt Cg dt 2 0 2 gm
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Bistable Elements : Small Signal (2)
The time domain solution
t t
q1 (0) 0 q '1 (0) 0 q1 (0) 0 q '1 (0) 0
q1 (t ) e e , q1 (0) C g vg1 (0)
2 2
q
t t
1 1
vo 2 (t ) (vo 2 (0) 0 v 'o 2 (0))e (vo 2 (0) 0 v 'o 2 (0))e 0
0
2
t
2
t
vg1 vo 2 , vg 2 vo1
1 1
vo1 (t ) (vo1 (0) 0 v 'o1 (0))e (vo1 (0) 0v 'o1 (0))e 0
0
2 2
The time domain expressions (t is a large value)
t
1
vo1 (t ) (vo1 (0) 0 v 'o1 (0))e 0
2
t
1
vo 2 (t ) (vo 2 (0) 0 v 'o 2 (0))e 0
2
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Phase Plane Representation
The bistable circuit behavior
vo1 Vth , vo 2 Vth Unstable
vo1 : Vth VOH or VOL
vo 2 : Vth VOL or VOH
Stable
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Propagation of a Transient Signal
t
vo1 (t )
The time domain behavior : e 0
vo1 (0)
T
The loop gain: An e 0
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SR Latch Circuit
SR latch circuit based on Gate level schematic
NOR2 gates and block diagram
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Truth Table and Operation Mode
Truth table of the NOR based SR latch circuit
Operation mode of the NOR based SR latch circuit
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Circuit Diagram of the SR Latch
Total lumped capacitance at each output node
CQ C gb,2 C gb ,5 Cdb ,3 Cdb ,4 Cdb,7 Csb,7 Cdb,8
CQ C gb ,3 C gb ,7 Cdb ,1 Cdb ,4 Cdb,5 Csb ,5 Cdb ,6
Rise time : rise,Q ( SR latch) rise,Q ( NOR 2) fall ,Q ( NOR 2)
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CMOS SR Latch : Another Type
Pseudo nMOS SR latch SR latch based on
circuit based on NOR2 gates NAND2 gates
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NAND Based SR Latch
Gate level schematic Pseudo-nMOS NAND-
& Block diagram based SR latch circuit
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Clocked SR Latch
Gate level schematic Input and output waveform
Level sensitive circuit
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Clocked NOR Based SR Latch : AOI
AOI-based implementation of the clocked NOR-based
SR-latch Circuit
very small transistor count
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Clocked NAND-Based SR Latch Circuit
Schematic w/ active low i/p (CK=S=0 for set or CK=R=0 for reset)
Schematic w/ active high i/p (CK=S=1 for set or CK=R=1 for reset)
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Clocked JK Latch
Gate level schematic
SR-latch : indeterminate when both inputs S and R
are activated
JK latch : adding two feedback lines from the outputs
to the inputs
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Clocked JK Latch : All NAND Implementation
All-NAND implementation of the clocked JK latch circuit
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Clocked JK Latch : Another Type
Clocked NOR-based JK latch CMOS AOI JK latch
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Clocked JK Latch : Truth Table
Clocked JK Latch : Toggle Switch
Toggle Switch
If both inputs are equal to logic 1, output will oscillate.
(The clock pulse width < input to output propagation delay)
JK latch is operated exclusively in this mode
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Master-Slave Flip-Flop
Master-Slave Flip-Flop
Two cascaded stages are activated with opposite clock phases.
Master Slave
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Master-Slave Flip-Flop : Operation
Clock pulse 0
Master latch inactive
(slave becomes active)
Clock pulse 1
Slave latch inactive
(master becomes active)
No uncontrolled
oscillation : J=K=1
Ones catching problem
Unwanted o/p transition
due to glitch at i/p
Sol. : edge-triggered
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NOR Based Master-Slave Flip-Flop
Circuit toggling when J=K=1
one stage must be active at any given time A NOR-Based
master-slave flip-flop
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Timing Diagram for (+)ve-edge Triggered FF
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Data-Q & Clk-Q Delays
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Timing Diagram for Latch
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CMOS D-Latch
Gate-level schematic Block diagram
CK : 1 Q assumes the value of the input D
CK : 0 Q preserve its state
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CMOS D-Latch : Version 1
Constructed by
Two inverter loop +
Two CMOS TG
CK:1 TG at input is
activated
CK:0 TG at inverter
loop is activated
CMOS D-Latch
(version 1)
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CMOS D-Latch : Simplified version 1
Simplified schematic Setup time & Hold time
view and timing diagram Setup time and hold time
should be met
Any violation can cause
metastability problems.
30 © CMOS Digital Integrated Circuits – 4th Edition
CMOS Master-Slave D-Latch : Version 2 (1)
Constructed by simply
cascading two D-latch
circuits
First stage (Master) : driven
by CK signal
Second stage (Slave) : driven
by inverted CK signal
Master Slave
CMOS D-Latch
(Version 2)
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Master-Slave D-latch : Version2 Simulation
Simulated input and output waveforms of version2
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Master-Slave D-latch : Setup Time Violation
Simulated waveforms master-slave D-latch circuit with
setup time violation at 0.25ns
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Master Slave D-Latch : Layout
Layout of the master-slave D-latch
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C2MOS Master-Slave D-Latch (Version 3)
Constructed by four tri-state inverters
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Pulsed Latch Based Clocked Storage Elements
Hybrid latch flip-flop Short pulse generation in
circuit (HLFF) HLFF
Advantages of HLFF : small D-Q delay, negative setup time,
logic embedding with small penalty
Minimum delay between FF should be guaranteed (due to
increased hold time)
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© CMOS Digital Integrated Circuits – 4th Edition
Semi Dynamic Flip-Flop (SDFF)
VDD
VDD
CK
SDFF to operate faster than HLFF
The back-end latch has only two stacked NMOS
Disadvantage
Short pulse generators : Always toggle =>large power consumption
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EP-SFF Circuit
EP-SFF circuit and CK generator
Advantages : Large amount of time borrowing, short output
delay, energy and area efficient
Disadvantage : Large hold time
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Sense Amplifier Based Flip Flop (SAFF)
Sensed amplifier based flip-flop circuit
Disadvantage : Large propagation delay through SR latch
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Modified SAFF
To overcome large propagation delay of SAFF
Cross-coupled Nand gates are replaced with a faster SR latch
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Delay Comparison of CSE
0.13um CMOS technology with a supply voltage of 1.2V
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Embedded Logic SDFF
D AB A+B AB+CD
Embedded 199ps 219ps 229ps 246ps
Discrete 199ps 298ps 305ps 367ps
Speedup 1.0 1.36 1.33 1.49
42 © CMOS Digital Integrated Circuits – 4th Edition
Power Consumption Portion of Chips
43 © CMOS Digital Integrated Circuits – 4th Edition
Power Consumption of Clocking
Power consumption of a particular clocking scheme
Pck scheme Pck network PFF
PCK network fCLK Cline Crep Cck tr V 2 ck swing VDD I leak , rep
(Dominated by dynamic power consumption)
Power dissipation by flip flops
PFF Pff
Pff i Ci 0C0 Clocal buf VDD 2 f CLK VDD I leak ,local buf I leak , FF
Ci : internal node Capacitance Co : output node Capacitance
αi : internal node transition ratio α0 : output node transition ratio
Clocal-buf : local clock buffer capacitance β: 1 or 2 (for double-edge)
Ileak,local-buf:leakage current of local clock buffer Ileak,FF : flip flop leakage current
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Low-Power CSEs
Clock-on-demand FF Conditional capture FF
Reduced swing clock FF Low-swing clock double-edge-triggered FF
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Appendix: Schmitt Trigger
Schmitt Trigger circuit
46 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Positive Input Sweep (1)
1) Vin=0V
M1, M2 : on
V x V y V DD 1.2V
M3, M4, M5 : off
M6 : on (saturation), let VT,6=0.62V
V z VDD VT ,6 0.58V
2) Vin=VT0,n=0.48V
M5 : starts to turn on
M4 : off
Vx 1.2V
47 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Positive Input Sweep (2)
3) Vin = 0.6V
M4 : off (assumption)
M5, M6 : on (Saturation)
kn' W EC Ln Vin VT 0,n kn' W EC Ln VDD Vz VT ,6
2 2
2 L 5 Vin VT 0,n EC Ln 2 L 6 VDD Vz VT ,6 EC Ln
2
0.4 (0.6 0.48)2 1 0.4 1.2 Vz 0.48 0.524( 1.011 Vz 1.011)
(0.6 0.48) 0.4 10 1.2 Vz 0.48 0.524( 1.011 Vz 1.011) 0.4
Vz 0.18V
VGS ,4 0.6 0.18 0.42 VT 0,n 0.48
M4 is indeed turned off
48 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Positive Input Sweep (3)
4) Vin=0.62V
M5 : on (Linear) , M6 : on (Saturation)
Vz is decreasing
k W EC Ln VDD Vz VT ,6
2
' '
k W 1 1
n
2 Vin VT 0,n Vz Vz 2
n
2(0.62 0.48) Vz Vz 2
2 L 5 Vz 2 L 6 VDD Vz VT ,6 EC Ln Vz
1 1
E L
C n
0.4
2
1 0.4 1.2 Vz 0.48 0.524( 1.011 Vz 1.011) Vz 0.1V
10 1.2 Vz [0.48 0.524( 1.011 Vz 1.011)] 0.4
VGS ,4 0.62 0.1 0.52V VT , n 4 0.51
M4 : Already on
Vth+=0.62V (Upper logic threshold voltage)
49 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Negative Input Sweep (1)
1) Vin = 1.2V 2) Vin = 0.74V
M4, M5 : on VX=0V M1 : on
M1, M2 : off M2 : off
M3 : on (Saturation) M3 : on (Saturation)
Vout : unchanged
k W EC Lp 0 Vy VT ,3
2
'
p
0
2 L 3 0 Vy VT ,3 EC Lp
Vy VT ,3 VT 0, p 0.406
0.972 VDD Vy 0.972
V y 0.573V
50 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Negative Input Sweep (2)
3) Vin=0.6V
M1, M3 : on (Saturation)
W EC Lp Vin VDD VT 0, p
2 2
2
k '
p k '
p
W E L
C p 0 V y VT ,3 1.8 0.6 1.2 ( 0.46)
2 L 1 Vin VDD VT 0, p EC Lp 2 L 3 0 Vy VT ,3 EC L p 0.6 1.2 (0.46) 1.8
2
1.8 0.6 1.2 (0.46) 1 1.8 0 Vy 0.46 0.406 0.972 1.2 Vy 0.972
2
0.6 1.2 (0.46) 1.8 10 0 Vy 0.46 0.406( 0.972 1.2 Vy 0.972) 1.8
Vy 0.92V VGS ,2 0.6 0.92 0.32 VT 0, p 0.46
M2 : off (at this point)
51 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Negative Input Sweep (3)
4) Vin=0.52V
M2 : off (Assumption)
M1 : on (Linear), M3 : on (Saturation)
kp W C p
E L 0 Vy VT ,3
2
k p' W 1
'
2 Vin VDD VT 0, p Vy VDD Vy VDD
2
2 L 0 V V E L
2 L 1 Vy 3 y T ,3 C p
1
EC L p
1 1
[2 (0.52 1.2 (0.46)) (Vy 1.2) Vy 1.2 ]
2
1.8 0 Vy 0.46 0.406 0.972 1.2 Vy 0.972
V
1 y
10 0 Vy 0.46 0.406 0.972 1.2 Vy 0.972 1.8
1.8
Vy 0.98V
M2 is already on
Vth- : 0.52V (Lower logic threshold voltage)
52 © CMOS Digital Integrated Circuits – 4th Edition
Schmitt Trigger : Simulation
53 © CMOS Digital Integrated Circuits – 4th Edition
