Payam Heydari

Neutralization
Techniques for
High-Frequency
Amplifiers
An overview

Background art—footage firm, inc.

N
eutralization tech- cathode, an anode, and a grid produces through the condenser 13, upon the grid
niques to miti­gate oscillatory currents in the circuits as­­ from the anode 11 across the capacity
the oscillatory cur- so­­ciated therewith and in some cases 12.” [See Figure 1(a).]
rents/voltages in the oscillatory currents so produced The same phenomenon was later
amplifiers due to interfere with the efficient reception, observed in transistor amplifiers. For
instability goes as far back as the era amplification and detection of the sig- example, the U.S. patent 2,901,558,
of vacuum tube amplifiers. For instan nals to be received.” It then goes on by granted on 25 August 1959 to R.R.
ce, in U.S. patent 1,334,118, granted stating that “in order to compensate for Webster “relates to semiconductor
on 16 March 1920 to C.W. Rice, it was the coupling due to the natural capac- amplifier circuits and more particu-
observed that “under certain conditions, ity between the grid 10 and anode 11 larly to a method of neutralizing the
a device employing an incandescent in Figure 1(a), which is represented by effects of interelectrode capacitance
the dotted condenser 12, an electromo- in semiconductor amplifier devices.”
Digital Object Identifier 10.1109/MSSC.2017.2745858 tive force, equal and opposite to that Next, it introduces “a neutralization
Date of publication: 16 November 2017 impressed, is applied to the grid circuit circuit, where the feedback network

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 is connected between a secondary undesired out-of-band interference, nonzero reverse transmission may
coil of the output transformer of the radio-frequency (RF) amplifiers em­­ cause stability issue in a tuned ampli-
amplifier circuit and the primary coil ploy a bandpass filter (BPF) tuned fier. To find out why this is the case,
of the input transformer of the ampli- at the RF signal’s carrier frequency. we study the input admittance of a
fier circuit.” [See Figure 1(b).] Figure 2(a) shows the general block generic tuned amplifier in Figure 2(b).
The reemergence of silicon-based diagram of an RF amplifier with a The core amplifier is represented by
millimeter (mm)-wave ICs in radio BPF load. The input/output match- its two-port model, depicted in Fig-
transceivers due to an ever-increas- ing circuits are used to facilitate ure 2(c), where the voltage across its
ing demand for bandwidth in high maximum power transfer from the input parasitic capacitance controls
data rate wireless applications has source to the amplifier’s input and a voltage-controlled current source,
recreated great interest in neutral- from the amplifier’s output to the G m Vi . The output parasitic capaci-
ization techniques in the context of load, respectively. tance C O of this amplifier is absorbed
low-noise wideband amplifier design. A simple BPF circuit is realized in the load capacitance to constitute
with a lossy LC tank circuit where an overall capacitance, C, as indi-
Tuned Amplifiers the loss is represented by the induc- cated in Figure 2(c). Solving the I-V
The baseband signal associated tors’ Q-factor (Q L = R L / (L~ 0)) . The equations for the input admittance
with a mobile user in wireless trans- core amplifier, in general, is not uni- Ydrv yields
ceivers is bandlimited. Therefore, lateral where the parasitic capacitors
the RF modulated signal has a band- of the transistor(s) contribute to non-
Ydrv ^~h = j~C I + j~C F c
YRLC + G m m
pass characteristic. To amplify this zero reverse transmission. In prac- .
YRLC + j~C F
band-pass signal, while filtering the tice, it is commonly known that this (1)

(a) (b)

Figure 1: Circuit schematics of (a) U.S. patent 1,334,118, “System for Amplification of Small Currents,” and (b) U.S. patent 2,901,558, “Tran-
sistor Amplifier Circuits.”

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 VDD

|HBPF(ω)| VDD
L, QL C
C = CL+ CO
ω CF
L, QL CL
ωRF +
Vi
BPF – CI GmVi
Ydrv
Core Amp. Core Amp.
(a) (b) (c)

Figure 2: (a) A general block diagram of a tuned RF amplifier. (b) A general schematic of a tuned amplifier with a tank RLC load. (c) The two-
port model of an amplifier with a tuned RLC tank load.

YRLC in (1) represents the admit- the parasitics of the transistor [e.g., base-collector parasitic capacitances
tance of the RLC (resistor, capacitor, C GD in a metal–oxide–semiconduc- cause nonzero reverse transmissions.
and inductor) tank, which is expressed tor (MOS) device or C n in a bipolar Therefore, techniques that neutralize
as YRLC = G L + j (C~ - 1/L~). The sus- transistor]. If an RLC circuit (i.e., the effect of these capacitances in
ceptance associated with the feedback input-matching circuit) is present at the circuit are of great interest. To
capacitance C F appears in the second the input port, it is possible for the help the flow of this article, the fol-
term of the input admittance. The sec- energy provided by the negative input lowing discussion concentrates on
ond term has a real and an imaginary conductance of this amplifier to sup- CMOS amplifiers. However, the same
part, G in = Re [Yin] and B in = Im [Yin], ply all the energy loss associated with principle can also apply to the bipo-
which are calculated to be the loss of the matching circuit. If lar counterparts.
B F (G m + G L) + B RLC G m this happens, a lossless LC circuit will
G in = BF appear at the input port and the cir- Neutralization Techniques
G L2 + (B RLC + B F ) 2
G (G + G ) + B RLC (B RLC + B F ) cuit begins to oscillate. The feedback Neutralization techniques ­primarily
B in = L m 2 L
 B F.
G L + (B RLC + B F ) 2 capacitance thus makes the amplifier ­cancel detrimental effects, described
(2) potentially unstable. in the “Tuned Amplifiers” section,
According to (2), the susceptance Second, an inspection of B in in associated with parasitic feedback
B F of the feedback capacitan­­ce bears (2) reveals that the feedback capa­­ capacitance in an amplifier. If the
two key contributions on the con­­­ citance appears across the input design constraints allow, the most
duc­­tance and susceptance of the in­­ port as an equivalent capacitance straightforward approach is to em­­ploy
put admittance. C eq = M (~) C F . M represents a frequ­ topologies with no direct capacitive
First, we study the B F effect on ency-dependent scaling factor, which is feedback from the input to the output
the conductance, G in . The tank sus- derived to be: of the amplifier. One widely known
ceptance, B RLC , becomes negative for topology is the cascode configuration.
frequencies lower than the tank re­­ M ^~h = 1 + Gm RL , (4) As will be explained in the “Cancella-
1 + (R L C eff ~) 2
sonance frequency ~ 0 (= 1/ LC ). tion of the Capacitive Feedback” sec-
Over this frequency range, if It is noted that M essentially pre­­ tion, an RF cascode amplifier at very
sents the generalized high-frequen­ high frequencies loses its promised
CF 1 G m R L C , (3) ­cy version of Miller coefficient. The advantages. The neutra­lization tech-
G m R L + 1 eff
tank load affects the input reactance niques thus pr ov ide a powerful
where through this Miller capacitance. There- pathway for stabilizing am­­plifiers at
fore, the feedback capacitance couples high frequencies.
C eff = ;`
~ 0 j2
- 1E C, the output load back onto the ampli-
~
fier’s input admittance. The design of Cascode Topology
then the conductance G in will be­­ input matching circuit for conjugate One topology that provides isola-
come a negative quantity. The in­­ matching should thus account for this tion between the input and output,
equality in (3) is easily satisfied at parasitic reactance. thus giving rise to an uncondition-
RF and mm-wave frequencies as the Complementa r y M O S (C M O S ) ally stable amplifier, is the cascode
tank capacitance is typically much common-source or bipolar common- topology. Figure 3(a) shows the basic
larger than the feedback capacitance, emitter amplifiers are obvious exam- schematic of a tuned cascode ampli-
itself predominantly contributed by ples where the gate-drain overlap or fier. If being utilized as a low-noise

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 VDD

VDD VDD
RB2 L, Q

RB2 L, Q RB2 L, Q LGG

C
M2

ZP
C C P
CGD1
CP
M.N. M.N.
M1

RB1 RB1
LS

1
Re[ZP] = (1 – LGGCGS2ω 2)
VB1 VB1 gm 2
(a) (b) 1
For ω > Re[ZP] < 0
√LGGCGS2

Figure 3: (a) The general circuit schematic of a tuned cascode amplifier. The input match- Figure 4: The core cascode circuit with para-
ing (M.N.) is shown as a black box driving this amplifier. (b) The circuit schematic of a tuned sitic capacitance CP, the gate-drain capacitance
cascode amplifier with inductive degeneration to provide noise-free input matching. CGD, and the parasitic capacitance LGG included.

amplifier, inductive degeneration is

commonly employed to provide a VDD VDD
noise-free input impedance match-
ing [1], as shown in Figure 3(b). At low
RF frequencies, a cascode topology RB2 L, Q RB2 L, Q
has larger output resistance com-
pared to a common-source configu-
C C
ration, making it possible to achieve M2 M2
higher gain. In addition, the noise
CBY,1 CBY,1
contribution of the common-gate
LC
transistor to the overall noise figure
is negligible because this transis-
tor sees a large source-degenerated LP M1
M1
resistance (i.e., ro1 of the common-
CBY,2
source device [2]).
Unfortunately, all these advan-
tages will fade away at high frequ­
(a) (b)
encies toward mm-wave frequency
range where the external passives
Figure 5: An interstage inductor to lower the noise contribution of the common-gate transis-
are in the range of device parasitics. tor in a cascode stage. (a) Parallel inductor LP and (b) series inductor LC.
For instance, the overall capacitance
C P at the cascode node, shown in One way to alleviate this issue is junctions of the common-source and
Figure 4, starts lowering the overall to place a series [3] or parallel induc- common-gate transistors are shared.
impedance at this node at high fre- tor [4] to partially resonate out C P These shared drain and source junc-
quencies. This means that the noise [cf. Figure 5(a) and (b)]. The paral- tions must inevitably be separated
contribution of the common-gate de­­­ lel inductor in Figure 5(a) creates a apart if the series interstage induc-
vice to overall noise figure is no longer band-limited high impedance at the tor, L C , is to be used. This separa-
assumed to be negligible. In fact, at resonance frequency, whereas the tion of junction regions leads to
near-fmax frequencies (loosely de­­fined series inductor in Figure 5(b) cre- additional parasitics at the inductor’s
as frequencies around and above half- ates a wideband interstage filter, terminals. In addition, when consid-
fmax ), the noise figure of the cascode extending the roll-off at the cascode ering the inductor’s parasitics, the
topology may worsen the noise figure node to higher frequencies. For a CMOS usefulness of L C in extending the
by as much as 3 dB. cascode stage, the drain and source bandwidth and lowering the noise

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 Node 1 Node 2 –∆V + +
∆V
– +
– + – ∆V – –
V1 V2 – +
CF V1 – ∆V1 +++ CF V1
Cin CF ∆V – ∆V
Cin ∆V1 = ∆V – ∆V1 ∆V1
CF + Cin CX CF
Cin

(a) (b)

Figure 6: The conceptual circuit to demonstrate the underlying idea behind the neutralization technique.

contribution of the common-gate below the resonance frequency of ing through this path destructively
transistor on the overall noise figure this inductor and the equivalent combines with the signal amplified
becomes unclear. capacitance seen from the gate ter- by the common source, as shown in
Moreover, the parasitic induc- minal, as also indicated in Figure 4. Figure 4. The effective gain of this
tance L GG of the bypass capacitor Finally, at high frequencies, the stage is thus compromised. Moreover,
and interconnects (Figure 4) con- parasitic gate-drain capacitance the real part of the output im­­pedance
nected to the gate of a cascode de­­ C GD1 of the common-source transis- of a source-degenerated c a sco de
vice can degrade the stability factor tor in a cascode configuration estab- amplifier becomes smaller than that
of the amplifier. In fact, this induc- lishes a feed-forward path from the of a common-source counterpart
tor induces a negative resistance input of this common-source stage because the intermediate node P
at the cascode node at frequencies to its output. The signal travel- becomes a short at high frequencies.
This, in turn, further lowers the cas-
code power gain.

VDD
VDD Cancellation of the
Capacitive Feedback
L, Q C
L, Q As described above, the cascode
VS topology, while providing unilateral
M.N.
gain, entails several drawbacks at
M.N. C R VS
S RB1 CB high frequencies. This notion calls
RS RB1 VBIAS for techniques that retain the origi-
VB1 nal amplifier topology and surround
VB1 the amplifier with a network which
(a) (b) cancels the feedback capacitance.
To understand the principle of
Figure 7: The use of a mutually coupled inductor for neutralization of the feedback capaci- neutralization technique, consider
tor. The neutralization is realized between (a) the drain and gate and (b) the source and gate the arrangement in Figure 6, where
of a common source amplifier. the floating and grounded capacitors
C F and C in exemplify the feedback
capacitance and the amplifier’s input
VD capacitance, respectively. A negative
CGD voltage drop at node 2 will induce a
(1–k )L (1–k )L CN negative voltage drop at node 1 due
CGD 1:1
to the presence of C F . To keep node 1
(1–k )L (1–k )L
kL CN 1:1 quiet, an opposite charge needs to be
VG created to cancel the delta-charge on
VG kL the upper and left plates of capacitors
L = LT /2 C in and C F , respectively. This can be
L = LT /2
accomplished by sampling the delta-
(a) (b)
voltage across C F and producing its
inverse with the aid of an inverting
Figure 8: The circuit models for neutralized amplifiers in Figure 7(a) and (b). The circuit
model employs a T-section model followed by ideal transformer to model the center-tapped voltage-controlled voltage source and
inductor. (a) The circuit model for the amplifier in Figure 7(a), and (b) the circuit model for the apply this delta-voltage to a capacitor
amplifier in Figure 7(b). C X [see Figure 6(b)]. Assuming equal

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 capacitances, C P = C X , the voltage at
node 1 will then remain quiet. VD
We use the aforementioned gen- CGD
eral principle to develop neutral- (1–k )L (1–k )L CN YL
CGD 1:1
izing networks around the main (1–k )L (1–k )L
1:1
amplifier. Noting that the transistor YL k L CN
is essentially a multiterminal com- VG
VG kL
ponent, this neutralizing network L = LT /2 L = LT /2
can be placed between the output
terminal (typically drain or collec- (a) (b)
tor) and any of the remaining two
terminals to cancel the feedback Figure 9: The circuit models for neutralized amplifiers with load admittance YL in Figure 7
parasitic capacitance. Shown in Fig- (a) and (b). (a) The circuit model for the amplifier in Figure 7(a), and (b) the circuit model for
the amplifier in Figure 7(b).
ure 7 are two examples in which the
neutralization is realized by forming
a passive feedback between drain
and gate [5], as in (a), or between the
drain and source [6], as in (b).
CN CN
In both examples, the neutraliz-
ing capacitor is realized using the
VS VS
gate-drain overlap region of an MOS
– +
device to ensure that its structure + –
resembles that of the gate-drain
overlap capacitance of the main
common-source transistor. There-
fore, they exhibit the same behavior
in the presence of process and tem-
perature variations. Also, in both
VDD
circuits, a center-tapped inductor is
employed to generate voltage pha-
sors of opposite signs at its up and L, Q L, Q
bottom terminals. Assuming an ideal
M.N. M.N.
magnetic coupling (i.e., k = 1) and – +
C C
equal loading on both sides of the CN CN
center-tapped inductor, the neutral-
VS VS
izing capacitance should be equal to
the parasitic gate-drain capacitance. + –
M.N. M.N.
However, in practice, the coupling
coefficient, k, is less than unity. k
will get closer to unity at very high
frequencies where a center-tapped ISS
one- or half-turn folded microstrip
line can produce the required induc-
tance. Figure 8(a) and (b) shows the Figure 10: Neutralization in differential amplifiers. A pair of cross-connected capacitors will
equivalent circuits, replacing mutu- neutralize the feedback parasitic capacitance.
ally coupled inductors in the cir-
cuits of Figure 7(a) and (b) with a
T-section equiv a lent model [7 ]. practice, however, the two sides between these two quantities. Using
With equal loadings, if the T-section of the center-tapped inductor a r e the eq­­­uivalent circuit in Figure 8(a)
model is excited from its two sides loaded by the unequal impedances. and (b), straightforward I-V equations
by a differential voltage, the circuit Figure 9(a) and (b) replicates Figure 8(a) reveals that DV1 - DV2 is calculated
will remain balanced for C N = C GD . and (b), while including the load admit- to be
As mentioned earlier, neutraliza- tance YL . Ideally, the voltage changes
tion occurs completely if the termi- DV1 and DV2 should have the same DV1 - DV2 =-~ 2 LC N (1 - k)
nal voltages of the center-tapped magnitude and opposite phase. Nev- N 
# V e j (+NV -+DV ) (5)
inductor r em a in dif fer ential. In ertheless, YL creates phase mismatch DV

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 VDD = 1.8 V

L Ls = 100 pH
1 : 1.95 CL CBY
L = 320 pH
LGG = 450 pH
RL = 50 Ω
(W/L)1 = 28.8 µm/180 nm
CBY LGG 0.89 : 1
(W/L)2 = 28.8 µm/180 nm
Ideal CL = 19.4 fF
RS = 50 Ω RB1 Transformer
LS RB1 = 1 MΩ
All Q’s = 12
Ideal VB1 = 0.9 V
Transformer
(a)

VDD = 1.8 V

LT Ls = 100 pH
LT = 640 pH
1 : 1.2 CL CBY
VS LGG = 810 pH
CBY LGG 1.3 : 1
(W/L)1 = 28.8 µm/180 nm
RL = 50 Ω
RB1 CL = 46.5 fF
RS = 50 Ω LS
RB1 = 1 MΩ
Ideal All Q’s = 12
Ideal Transformer
VB1
Transformer
(b)

Figure 11: (a) The circuit schematic of a cascode amplifier with inductive degeneration designed and simulated in a CMOS 180-nm process.
(b) The circuit schematic of a CGD -neutralized common-source amplifier. Both amplifiers have been designed to operate at a 28-GHz center
frequency. All component values have been included.

and see the equation at the bottom center-tapped inductor are perfectly between the input and the com-
of the page where G eq and B eq are coupled (k = 1) or 2) for partially mon terminal, forcing them to be
the conductance and susceptance coupled inductors (k 1 1) and when in opposite phase. This means that
of t he equiv a lent a d m i t t a n c e there is no mismatch between the ideally the transconductance will
Yeq (= YL + j~C GD f o r F i g u r e 9 (a ), loadings of two sides. be boosted by 6 dB [6]. However,
= YL + j~C N for Figure 9(b), respec- For the circuit of Figure 7(a), this g m-boosting is mainly used to
tively. Equation (5) verifies that, the neutralizing network is placed compensate for the resistive source
for two important special cases, between the input and output ter- degeneration associated with the
the gain and phase offset between minals. The inductor would also be loss of the center-tapped inductor.
DV1 and DV2 is zero, namely, 1) part of the output tank circuit. On One additional drawback regard-
for any arbitrary load admittance, the other hand, the center-tapped ing the neutralized amplifier in Fig-
YL, and when the two sides of the inductor in Fig ure 7(b) is placed ure 7(b) is that the presence of large
bypass capacitance contributes to
significant phase error between the
two terminals of the inductor. This
~L ^k + 1h G eq makes the design of a perfect neu-
\N V - \D V = tan -1 - tan -1
2 - ~L ^k + 1h^~C N + B eqh tralizing network extremely chal-
~L 61 - ~ 2 LC N ^1 - k 2h@ G eq lenging as this phase error needs to
1 - ~ LC N - ~L 61 - ~ 2 LC N ^1 - k 2h@ B eq
# 2
be accounted for during the design
R V1/2 of the center tapped inductor.
NV S ^2 - ~L ^k + 1 h^~C N + B eqhh2 + (~L (k + 1) G eq) 2 W On the other hand, neutralization
=S W
DV 1 2 2
Se - ~ LC N - ~L
o + ^~L 61 - ~ 2 LC N ^1 - k 2h@^G eqh ) W
2 in differential amplifiers can be done
S 61 - ~ 2 LC N ^1 - k 2h@ B eq W
SS WW with no explicit use of inductors. In
T X fact, the output terminals of opposite
polarity readily exist in a differential

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 topology. Figure 10 shows the core
The general concept of amplifier neutralization
differential circuit incorporating the
capacitive neutralization technique. to overcome amplifier instability has been
Capacitive neutralization of differ- around for many years, dating back to the
ential amplifiers is a wideband tech-
nique that insures the stability of the
early part of the 20th century.
amplifier. Conse­q uently, differen-
tial front-end mm-wave po­­wer ampli- frequ­ency is close to fmax of the device common-source amplifier, in a 180-nm
fiers on the transmitter side and in this process, which is around 55 GHz, CMOS process and for carrier frequency
low-noise amplifiers on the receiver the common-gate transistor contri­ of 28 GHz were presented. The common-
side use this technique to achieve butes considerably to the overall source amplifier shows higher power
wideband performance improve- noise figure. The noise figure of the cas- gain and lower noise figure compared to
ment. In addition, this technique can code amplifier is higher than that of the the cascode amplifier, as was anticipated
be used at near-fmax frequencies to neutralized common-source ampli- from the study of this article.
boost the amplifier’s power gain. fier, which is also verified with noise fig-
One important observation is that, ure simulation of these two stages [see Acknowledgments
besides stabilizing the amplifier, neu- Figure 12(b)]. This work was supported in part by
tralization essentially increases the a grant from the Samsung Advanced
maximum allowable matching band- Conclusions Institute of Technology (SAIT) Global
width of the amplifier, predicted by The general concept of amplifier Research Outreach (GRO) Program
the Bode–Fano limit [1]. This notion neutralization to overcome amplifier and NSF Award ECCS-1611575.
will be used in wideband RF or mm- instability has been around for many
wave applications. years, dating back to the early part of the References
[1] T. H. Lee, Planar Microwave Engineering:
For a better performance comparison, 20th century. This article provided an A Practical Guide to Theory, Measurement,
consider two amplifiers in the same overview of neutralization techniques and Circuits. Cambridge, U.K. Cambridge
Univ. Press, 2004.
180 -n m CMOS pr o cess, bot h de­­ for high frequency amplifiers. First, the [2] B. Razavi, Design of Analog CMOS Inte-
signed to operate at 28-GHz center fre- problem of instability in non-unilateral grated Circuits, 2nd ed. New York: Mc-
Graw-Hill, 2016.
quency. In Figure 11, (a) shows a source amplifiers driving tuned RLC tank cir- [3] P. Heydari, “Design and analysis of a per-
degenerated cascode amplifier, and (b) cuits was studied. This discussion was formance-optimized CMOS UWB distrib-
uted LNA,” IEEE J. Solid-State Circuits, vol.
indicates a common-source stage with followed by revisiting RF cascode ampli- 42, no. 9, pp. 1892–1905, Sept. 2007.
neutralization. For the sake of simplicity, fiers. The issues associated with cas- [4] M. Zargari, M. Terrovitis, S. H. M. Jen, B. J.
Kaczynski, M. Lee, M. P. Mack, S. S. Mehta,
the input and output matching circuits code topology at high frequencies were S. Mendis, K. Onodera, H. Samavati, W.
are realized with transformers. From briefly explained, which paved the way W. Si, K. Singh, A. Tabatabaei, D. Weber,
D. K. Su, and B. A. Wooley, “A single-chip
the simulated gain plots indicated in for introducing the neutralization tech- dual-band tri-mode CMOS transceiver
Figure 12(a), the neutralized common- niques in both single-ended and differ- for IEEE 802.11a/b/g wireless LAN,” IEEE
J. Solid-State Circuits, vol. 39, no. 12, pp.
source stage exhibits higher peak gain ential high-frequency amplifiers. Two 2239–2249, Dec. 2004.
and wider frequency response, which examples, a cascode amplifier with [5] V. Jain, S. Sundararaman, and P. Heydari,
“A CMOS 22-29GHz receiver front-end for
is to be expected. Since the operation source degeneration and a neutralized UWB automotive pulse-radars,” in Proc.
IEEE Custom Integrated Circuits Conf.,
Sept. 2007, pp. 757–760.
[6] A. Shameli and P. Heydari, “A novel ultra-
low power (ULP) low noise amplifier using
Cascode Neutralized differential inductor feedback,” in Proc.
32nd European Solid-State Circuits Conf.,
6 6.5 Sept. 2006, pp. 352–355.
[7] K. K. Clarke and D. T. Hess, Communica-
5.5 6 tion Circuits: Analysis and Design, 2nd ed.
5 5.5 Florida: Krieger Publishing, 1994.
Gain (dB)

Gain (dB)

4.5
5
4
4.5
About the Authors
3.5 Payam Heydari is a full professor of
4
3 electrical engineering at the Univer-
2.5 3.5
sity of California, Irvine. He is noted
2 3 for his pioneering work on silicon-
2.6 2.7 2.8 2.9 3 2.6 2.7 2.8 2.9 3
Frequency (Hz) × 1010 Frequency (Hz) × 1010 based millimeter-wave and terahertz
(a) (b) IC design. He is the author or coauthor
of two books, one book chapter, and
Figure 12: (a) Simulated gain versus frequency. (b) Simulated noise figure versus frequency more than 130 journal and conference
for both cascode and common-source amplifiers in Figure 11(a) and (b). papers. He is a Fellow of the IEEE.

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