330 Chapter 5 Synchronous Sequential Logic

A1A0 A1 A1A0 A1 A1A0 A1

A2 A2 A2
00 01 11 10 00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2 m0 m1 m3 m2
0 1 0 1 1 0 1 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6 m4 m5 m7 m6
A2 1 1 A2 1 1 1 A2 1 1 1 1 1

A0 A0 x
TA2 5 A1A0 TA1 5 A0 TA0 5 1

FIGURE 5.33
Maps for three-bit binary counter

A2 A1 A0

Clk Clk Clk

T T T

Clock

FIGURE 5.34
Logic diagram of three-bit binary counter

PROBLEMS
(Answers to problems marked with * appear at the end of the book. Where appropriate, a logic
design and its related HDL modeling problem are cross-referenced.) Unless SystemVerilog is
explicitly named, the HDL compiler for solving a problem may be Verilog, SystemVerilog, or
VHDL. Note: For each problem that requires writing and verifying an HDL model, a basic test
plan should be written to identify which functional features are to be tested during the simula-
tion and how they will be tested. For example, a reset on-the-fly could be tested by asserting the
reset signal while the simulated machine is in a state other than the reset state. The test plan is
to guide development of a testbench that will implement the plan. Simulate the model, using
the testbench, and verify that the behavior is correct. If synthesis tools are available, the HDL
descriptions developed for Problems 5.34–5.42 can be assigned as synthesis exercises. The circuit
produced by the synthesis tools should be simulated and compared to the simulation results for
the pre-synthesis model.
5.1 The D latch of Fig. 5.6 is constructed with four NAND gates and an inverter. Consider the
following three other ways for obtaining a D latch. In each case, draw the logic diagram
and verify the circuit operation.
 Problems 331

(a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter
may be needed.
(b) Use NOR gates for all four gates. Inverters may be needed.
(c) Use four NAND gates only (without an inverter). This can be done by connecting the
output of the upper gate in Fig. 5.6 (the gate that goes to the SR latch) to the input of
the lower gate (instead of the inverter output).
5.2 Construct a JK flip-flop using a D flip-flop, a two-to-one-line multiplexer, and an inverter.
(HDL—see Problem 5.34)
5.3 Show that the characteristic equation for the complement output of a T flip-flop is
Q(t + 1) = TQ′ + T′Q
5.4 A certain flip-flop has four operations: complement, set to 1, set to 0, and no change, when
inputs A and B are 00, 01, 10, and 11, respectively.
(a) Tabulate the characteristic table. (b) Tabulate the excitation table.
(c)* Derive the characteristic equation. (d) Show how the flip-flop can be
converted to a T flip-flop.
5.5 Explain the differences among a truth table, a state table, a characteristic table, and an
excitation table. Also, explain the difference among a Boolean equation, a state equation,
a characteristic equation, and a flip-flop input equation.
5.6 A sequential circuit with two D flip-flops A and B, two inputs, x and y; and one output z
is specified by the following next-state and output equations (HDL—see Problem 5.35):
A(t + 1) = xy′ + xB
B(t + 1) = xA + xB′
z = A
(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.
5.7* A sequential circuit has one flip-flop Q, two inputs x and y, and one output S. It consists of
a full-adder circuit connected to a D flip-flop, as shown in Fig. P5.7. Derive the state table
and state diagram of the sequential circuit.

x S
y Full
adder C

Clk Clock

FIGURE P5.7
332 Chapter 5 Synchronous Sequential Logic

5.8* Derive the state table and the state diagram of the sequential circuit shown in Fig. P5.8.
Explain the function that the circuit performs. (HDL—see Problem 5.36)

A9 A B9 B

Clk Clk
T T

Clock

FIGURE P5.8

5.9 A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described
by the following flip-flop input equations:
JA = x′ KA = B′
JB = A KB = x
(a)* Derive the state equations A(t + 1) and B(t + 1) by substituting the input equations
for the J and K variables.
(b) Draw the state table and state diagram of the circuit.
5.10 A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z.
The flip-flop input equations and circuit output equation are
JA = A′x + B′y KA = Bx′y′
JB = A′xy KB = A′ + B′x
z = A′x′ + B′y′
(a) Derive the simplified state equations for A and B.
(b) Tabulate the state table.
(c)* Draw the state diagram of the circuit.
5.11 For the circuit described by the state diagram of Fig. 5.16,
(a)* Determine the state transitions and output sequence that will be generated when an
input sequence of 110010100111010 is applied to the circuit and it is initially in the
state 00.
(b) Reduce the number of states in the state table corresponding to Fig. 5.16 and find the
reduced state table showing each intermediate step.
(c) Determine the state transitions and output sequence with same input sequence as (a)
applied to the reduced circuit. Verify whether the output sequence is same as (a).
 Problems 333

5.12 For the following state table

Next State Output

Present State x = 0 x = 1 x = 0 x = 1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0

(a) Draw the corresponding state diagram.

(b)* Tabulate the reduced state table.
(c) Draw the state diagram corresponding to the reduced state table.
5.13* Starting from state a, and the input sequence 01110010011, determine the output sequence for
(a) The state table of the previous problem.
(b) The reduced state table from the previous problem. Show that the same output sequence
is obtained for both.
5.14 Substitute the Gray code assignment 2 from Table 5.9 to the states in Table 5.8 and obtain
the binary state table.
5.15 Design a J′K flip-flop and a JK flip-flop with a NOT gate between the external input
and the internal J input. Obtain its state table and its characteristics equation. Show the
modifications required in Fig. 5.12(a) for this.
5.16 Design a sequential circuit with two D flip-flops A and B, and one input x_in.
(a)* When x_in = 0, the state of the circuit remains the same. When x_in = 1, the circuit
goes through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats.
(b) When x_in = 0, the state of the circuit remains the same. When x_in = 1, the circuit
goes through the state transitions from 00 to 11, to 01, to 10, back to 00, and repeats.
(HDL—see Problem 5.38)
5.17 Design a one-input, one-output serial 2’s complementer. The circuit accepts a string of
bits from the input and generates the 2’s complement at the output. The circuit can be
reset asynchronously to start and end the operation. (HDL—see Problem 5.39)
5.18* Design a sequential circuit with two JK flip-flops A and B and two inputs E and F. If
E = 0, the circuit remains in the same state regardless of the value of F. When E = 1
and F = 1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back
to 00, and repeats. When E = 1 and F = 0, the circuit goes through the state transitions
from 00 to 11, to 10, to 01, back to 00, and repeats. (HDL—see Problem 5.40)
5.19 A sequential circuit has three flip-flops A, B, and C; one input x_in; and one output
y_out. The state diagram is shown in Fig. P5.19. The circuit is to be designed by treating
the unused states as don’t-care conditions. Analyze the circuit obtained from the design
to determine the effect of the unused states. (HDL—see Problem 5.41)
(a)* Use D flip-flops in the design.
(b) Use JK flip-flops in the design.
334 Chapter 5 Synchronous Sequential Logic

0/0

001

1/1 0/0

1/0
100 011
1/1
0/0
0/0
1/1 0/0

010
1/1

000

FIGURE P5.19

5.20 Design the sequential circuit specified by the state diagram of Fig. 5.19, using D flip-flops.
5.21 What is the main difference
(a) between an initial statement and an always statement in a Verilog procedural block?
(b) between a variable assignment and a signal assignment in a VHDL process?
5.22 Draw the waveform generated by the statements below:
(a) initial begin
w = 0; #10 w = 1; # 40 w = 0; # 20 w = 1; #15 w = 0;
end
(b) initial fork
w = 0; #10 w = 1; # 40 w = 0; # 20 w = 1; #15 w = 0;
join
5.23* What are the values of RegA and RegB after the following statements, if their initial values
are RegA = 20 and RegB = 10?
Verilog
(a) RegA = RegB; (b) RegA 6 = RegB;
RegB = RegA; RegB 6 = RegA;
VHDL
(a) RegA := RegB; (b) RegA 6 = RegB;
RegB := RegA; RegB 6 = RegA;
5.24 Write and verify an HDL behavioral description of a positive-edge-sensitive D flip-flop
with asynchronous preset and clear.
5.25 A special positive-edge-triggered flip-flop circuit component has four inputs D1, D2, D3,
and D4, and a two-bit control input that chooses between them. Write and verify an HDL
behavioral description of this component.
5.26 Write and verify an HDL behavioral description of the JK flip-flop using an if-else state-
ment based on the value of the present state.
(a)* Obtain the characteristic equation when Q = 0 or Q = 1.
(b) Specify how the J and K inputs affect the output of the flip-flop at each clock tick.
 Problems 335

5.27 Rewrite and verify the description of HDL Example 5.5 by combining the state transitions
and output into (a) one Verilog always block or (b) one VHDL process.
5.28 Simulate the sequential circuit shown in Fig. 5.17.
(a) Write the HDL description of the state diagram (i.e., behavioral model).
(b) Write the HDL description of the logic (circuit) diagram (i.e., a structural model).
(c) Write an HDL stimulus with a sequence of inputs: 00, 01, 11, 10. Verify that the
response is the same for both descriptions.
5.29 Write a behavioral description of the state machine described by the state diagram shown
in Fig. P5.19. Write a testbench and verify the functionality of the description.
5.30 Draw the logic diagram for the sequential circuit described by the following HDL code:
(a) Verilog (b) VHDL

always @ (posedge CLK) process (CLK) begin

begin if CLK’event and CLK = '1' then
E <= A | B; begin
Q <= E & C; E <= A or B;
end Q <= E and C;
end process;

5.31* (a) How should the description in Problem 5.30 (a) be written to have the same behavior
when the assignments are made with = instead of with 6 = ?
(b) How should the description in Problem 5.30 (b) be written to have the same behavior if
A, B, C, D, and E are variables and the assignments are made with = instead of 6 = ?
5.32 Using (a) an initial statement with a begin . . . end block write a Verilog description of
the waveforms shown in Fig. P5.32. Repeat using a fork . . . join block. (b) Write a VHDL
process to describe the waveforms in Fig. P5.32.

enable

C
D

t
0 10 20 30 40 50 60 70 80

FIGURE P5.32
Waveforms for Problem 5.32

5.33 Explain why it is important that the stimulus signals in a testbench be synchronized to the
inactive edge of the clock of the sequential circuit that is to be tested.
336 Chapter 5 Synchronous Sequential Logic

5.34 Write and verify an HDL structural description of the machine having the circuit diagram
(schematic) obtained in Problem 5.2.
5.35 Write and verify an HDL model of the sequential circuit described in Problem 5.6.
5.36 Write and verify an HDL structural description of the machine having the circuit diagram
(schematic) shown in Fig. P5.8.
5.37 Write and verify HDL behavioral descriptions of the state machines shown in Figs. 5.25
and 5.26. Write a testbench to compare the state sequences and input–output behaviors
of the two machines.
5.38 Write and verify an HDL behavioral description of the machine described in Problem 5.16.
5.39 Write and verify a behavioral description of the machine specified in Problem 5.17.
5.40 Write and verify a behavioral description of the machine specified in Problem 5.18.
5.41 Write and verify a behavioral description of the machine specified in Problem 5.19. (Hint:
See the discussion of the default case item (Verilog) or the others case item (VHDL) pre-
ceding HDL Example 4.8 in Chapter 4.)
5.42 Write and verify an HDL structural description of the circuit shown in Fig. 5.29.
5.43 Write and verify an HDL behavioral description of the three-bit binary counter in Fig. 5.34.
5.44 Write and verify an HDL behavioral model of a D flip-flop having asynchronous reset.
5.45 Write and verify an HDL behavioral description of the sequence detector described in
Fig. 5.27.
5.46 A synchronous finite state machine has an input x_in and an output y_out. When x_in
changes from 0 to 1, the output y_out is to assert for three cycles, regardless of the value of
x_in, and then de-assert for two cycles before the machine will respond to another asser-
tion of x_in. The machine is to have active-low synchronous reset.
(a) Draw the state diagram of the machine.
(b) Write and verify a HDL model of the machine.
5.47 Write a HDL model of a synchronous finite state machine whose output is the sequence 0,
2, 4, 6, 8 10, 12, 14, 0 . . . . The machine is controlled by a single input, Run, so that counting
occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count
when Run is re-asserted. Clearly state any assumptions that you make.
5.48 Write an HDL model of the Mealy FSM described by the state diagram in Fig. P5.48.
Develop a testbench and demonstrate that the machine state transitions and output cor-
respond to its state diagram.
5.49 Write an HDL model of the Moore FSM described by the state diagram in Fig. P5.49.
Develop a testbench and demonstrate that the machine’s state transitions and output cor-
respond to its state diagram.
5.50 A synchronous Moore FSM has a single input, x_in, and a single output y_out. The machine
is to monitor the input and remain in its reset state until a second sample of x_in is detected
to be 1. Upon detecting the second assertion of x_in y_out is to assert and remain asserted
until a fourth assertion of x_in is detected. When the fourth assertion of x_in is detected
the machine is to return to its reset state and resume monitoring of x_in.
(a) Draw the state diagram of the machine.
(b) Write and verify an HDL model of the machine.
 Problems 337

0/1
a b

1/ 0 1/ 1

0/ 0
0/ 0

1/ 0

1/ 1
d c

0/ 1

FIGURE P5.48

d c
0 1 1

1 0 0

a 0 b
0 1

FIGURE P5.49
338 Chapter 5 Synchronous Sequential Logic

5.51 Draw the state diagram of the machine described by the HDL model given below.
(a) Verilog
module Prob_5_51 (output reg y_out, input x_in, clk, reset_b);
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;
reg [1:0] state, next_state;
always @ (posedge clk, negedge reset_b) begin
if (reset_b == 1'b0) state <= s0;
else state <= next_state;
always @(state, x_in) begin
y_out = 0;
next_state = s0;
case (state)
s0: begin y_out = 0; if (x_in) next_state = s1; else next_state = s0; end;
s1: begin y_out = 0; if (x_in) next_state = s2; else next_state = s1; end;
s2: begin y_out = 1; if (x_in) next_state = s3; else next_state = s2; end;
s3: begin y_out = 1; if (x_in) next_state = s0; else next_state = s3; end;
default: next_state = s0;
endcase
end
endmodule

(b) VHDL
entity Prob_5_51_vhdl is
port (y_out: out std_Logic; clk, reset_b: in Std_Logic);
end Prob_5_51;
architecture Behavioral of Prob_5_51 is
constant s0 = '00', s1 = '01', s2 = '10', s3 = '11';
signal state, next_state: Std_Logic_Vector (1 downto 0);
process (clk, reset_b) begin
if reset_b’event and reset_b = '0' then state <= s0;
else state <= next_state;
end process;

process (state, x_in) begin

y_out <= 0;
next_state <= s0;
case state is
when s0 => begin y_out <= 0; if x_in = '1' then next_state <= s1; else
next_state := s0; end if;
when s1 => begin y_out <= 0; if x_in = '1' then next_state <= s2; else
next_state := s1; end if;
when s2 => begin y_out <= 1; if x_in = '1' then next_state <= s3; else
next_state := s2; end if;
 Problems 339

when s3 => begin y_out <= 1; if x_in = '1' then next_state <= s0; else
next_state := s3; end if;
when others => next_state = s0;
end case;
end process;
end Behavioral;

5.52 Draw the state diagram of the machine described by the HDL model given below.
(a) Verilog
module Prob_5_52 (output reg y_out, input x_in, clk, reset_b);
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;
reg [1:0] state, next_state;
always @ (posedge clk, negedge reset_b) begin
if (reset_b == 1'b0) state <= s0;
else state <= next_state;
always @(state, x_in) begin
y_out = 0;
next_state = s0;
case (state)
s0: if x_in = 1 begin y_out = 0; if (x_in) next_state = s1; else next_state = s0; end;
s1: if x_in = 1 begin y_out = 0; if (x_in) next_state = s2; else next_state = s1; end;
s2: if x_in = 1 if (x_in) begin next_state = s3; y_out = 0; end;
else begin next_state = s2; y_out = 1; end;
s3: if x_in = 1 begin y_out = 1; if (x_in) next_state = s0; else next_state = s3; end;
default: next_state = s0;
endcase
end
endmodule

(b) VHDL
entity Prob_5_52_vhdl is
port (y_out: out std_Logic; clk, reset_b: in Std_Logic);
end Prob_5_51;

architecture Behavioral of Prob_5_51 is

constant s0 = '00', s1 = '01', s2 = '10', s3 = '11';
signal state, next_state: Std_Logic_Vector (1 downto 0);
process (clk, reset_b) begin
if reset_b’event and reset_b = '0' then state <= s0;
else state <= next_state;
end process;
process (state, x_in) begin
y_out <= 0;
340 Chapter 5 Synchronous Sequential Logic

next_state <= s0;

case state is
when s0 => begin y_out <= 0; if x_in = '1' then next_state <= s1; else
next_state := s0; end if;
when s1 => begin y_out <= 0; if x_in = '1' then next_state <= s2; else
next_state := s1; end if;
when s2 => if x_in = '1' then begin y_out <= 0; next_state <= s3; end; else
begin y_out <= 1; next_state := s2; end if;
when s3 => begin y_out <= 1; if x_in = '1' then next_state <= s3; else
next_state := s3; end if; end;
when others => next_state = s0;
end case;
end process;
end Behavioral;
5.53 Draw a state diagram and write an HDL model of a Mealy synchronous state machine
having a single input x_in and a single output y_out, such that y_out is asserted if the total
number of 1’s received is a multiple of 3.
5.54 A synchronous Moore machine has two inputs x1 and x2, and an output y_out. If both
inputs have the same value, the output is asserted for one cycle; otherwise, the output is 0.
Develop a state diagram and a write an HDL behavioral model of the machine. Demon-
strate that the machine operates correctly.
5.55 Develop the state diagram for a Mealy state machine that detects a sequence of three or
more consecutive 1’s in a string of bits coming through an input line.
5.56 Using manual methods, obtain the logic diagram of a three-bit counter that counts in the
sequence 0, 2, 4, 6, 0, . . . .
5.57 Write and verify an HDL behavioral model of a three-bit counter described in Problem
5.6 that counts in the sequence 0, 2, 4, 6, 0, . . . .
5.58 Write and verify an HDL behavioral model of the ones counter designed in Problem 5.55.
5.59 Write and verify an HDL structural model of the three-bit counter described in Problem 5.56.
5.60 Write and verify an HDL behavioral model of a four-bit counter that counts in the sequence
0, 1, . . . , 9, 0, 1, 2, . . . .

REFERENCES
1. Bhasker, J. 1998. Verilog HDL Synthesis. Allentown, PA: Star Galaxy Press.
2. Ciletti, M. D. 1999. Modeling, Synthesis, and Rapid Prototyping with Verilog HDL. Upper
Saddle River, NJ: Prentice Hall.
3. Dietmeyer, D. L. 1988. Logic Design of Digital Systems, 3rd ed., Boston: Allyn Bacon.
4. Hayes, J. P. 1993. Introduction to Digital Logic Design. Reading, MA: Addison-Wesley.
5. Katz, R. H. 2005. Contemporary Logic Design. Upper Saddle River, NJ: Prentice Hall.
6. Mano, M. M. and C. R. Kime. 2015. Logic and Computer Design Fundamentals & Xilinx
6.3 Student Edition, 5th ed., Upper Saddle River, NJ: Full Arc Press.
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