BCSE205L – Computer

Organization and Architecture

Module 2

1
Topics to be covered
1. Sequential Multiplication
2. Booth’s Multiplication
3. Modified Booth Multiplication
1. Sequential Multiplication
(unsigned multiplication)
Sequential Multiplication
• Unsigned multiplication
• Multiplication involves generating partial products(PP), one for each
multiplier bit.
• These partial products are summed to produce the final result
• Before summing, each PP is shifted one position to the left relative
to the preceding partial product.
• The product of 2 ‘n’ digit numbers can be accommodated in 2n
digits( Two 4 bit number multiplication results in 8 bits)
Sequential Multiplication
• This circuit performs multiplication by using a single n-bit adder n
times
• Registers A and Q are shift registers
• Together, they hold partial product PPi while multiplier bit qi
generates the signal Add/Noadd.
• This signal causes the multiplexer MUX to select 0 when qi = 0, or to
select the multiplicand M when qi = 1, to be added to PPi to generate
PP(i + 1).
• The product is computed in n cycles
• The carry-out from the adder is stored in flip-flop C
Sequential Multiplication
• At the start, the multiplier is loaded into register Q, the multiplicand
into register M, and C and A are cleared to 0.
• At the end of each cycle, C, A, and Q are shifted right one bit position
to allow for growth of the partial product as the multiplier is shifted
out of register Q.
• After n cycles, final product is stored in A and Q register . The high-
order half of the product is held in register A and the low-order half
is in register Q
Sequential Multiplier
Perform multiplication for 11 x 13 using unsigned integer 2's Start
compliment multiplication algorithm.
Multiplicand = 11 → Binary equivalent is 1011→M C,A0
Multiplier = 13 → Binary equivalent is 1101→Q M Multiplicand
Q Multiplier
A 0000 A 0010 A 0110 Count  n
M 1011 M 1011 M 1011
A 1011 A 1101 A 0001 No yes
Q0 =1?
C A Q Action Q0 Count
0 0000 1101 Initial 1
0 1011 1101 Add C,AA+M
0 0101 1110 Shift 0 4

0 0010 1111 Shift 1 3

Shift C,A,Q
0 1101 1111 Add Count  Count-1
0 0110 1111 Shift 1 2
No yes
1 0001 1111 Add Count=0?
Shift 1
0 1000 1111 1
End
2. Booth’s multiplication algorithm
2. Booth Multiplication
• reduces the number of required operations by regarding the
multiplier as the difference between two numbers
• In the Booth algorithm, −1 times the shifted multiplicand is selected
when moving from 0 to 1, and +1 times the shifted multiplicand is
selected when moving from 1 to 0, as the multiplier is scanned from
right to left.
Booth’s Algorithm
• It’s a powerful algorithm for signed number multiplication,which
treats both positive and negative numbers uniformly. It generates a
2n product.
• The algorithm suggests that “we can reduce the number of
operations required for multiplication by representing multiplier
as the difference between two numbers.”
• In this multiplier bits are encoded from right to left, before the bits
are used for getting partial products.
• To encode the multiplier bits, two adjacent bits Qi(current
bit)and Q i-1 (previous bit)is examined and replaced a value
shown in Booth recoding table.
• Assume an implied to the right of the multiplier LSB.
Booth Multiplier recoding table
Booth Multiplication
• Booth recoded multiplier(Pair 2 consecutive bits from LSB)
 START
Multiply 7 x 3 using above signed 2's complement binary multiplication.

Multiplicand =7 → Binary equivalent is 0111→M A 0 ; Q -10

Multiplier = 3 → Binary equivalent is 0011→Q MMultiplicand
Q Multiplier
-7 → Binary equivalent is 1001→ -M Countn
A 0 0 0 0 A 0 1 0 1
-M 1 0 0 1 M 0 1 1 1
=01
A1 0 0 1 A 0 0 1 0 =10
Q 0 ,Q -1

Step A Q Q-1 Action Count

1 0 0 0 0 0 0 1 1 0 Initial 4 AA-M A A+M
=11
2 1 0 0 1 0 0 1 1 0 AA-M =00
2 1 1 0 0 1 0 0 1 1 Shift 3
Arithmetic Shift right
3 1 1 1 0 0 1 0 0 1 Shift 2 A, Q, Q-1
Count Count -1
4 0 1 0 1 0 1 0 0 1 AA+M
4 0 0 1 0 1 0 1 0 0 Shift 1 N0 Yes
Count= END
5 0 0 0 1 0 1 0 1 0 Shift 0 0?
Booth Multiplication (Another example)
• The product can be generated by one addition and one subtraction of the multiplicand.
• This scheme extends to any number of blocks of 1s in a multiplier, including the case in which a single 1 is
treated as a block.
• Booth’s algorithm conforms to this scheme by performing a subtraction when the first 1 of the block is
encountered (1–0) and an addition when the end of the block is encountered (0–1).
Advantages of Booth Recoding
• Handles both positive and negative multipliers uniformly
• Achieves some efficiency in the number of additions required when
the multiplier has a few large block of 1’s.
Note
• On average the speed of the multiplication with the Booth algorithm
is the same as with the normal algorithm.
Arithmetic Right Shift
NOTE
• If the recoded bit is ‘0’put 0
• If the recoded bit is ‘1’put Multiplicand
• If the recoded bit is ‘-1’put 2’s complement of the multiplicand
3. Modified Booth Algorithm
• To speed up multiplication process, 3 consecutive bits are paired
together and recoded as per the table given in next slide.
• Also called as Bit pair recoding algorithm
• Benefit: Halves the maximum number of summands
Bit Pair Recoding
Bit Pair Recoding
• Multiplicand (M)* (+2) = Shift left multiplicand by one bit
• Multiplicand (M)* (-2) = Shift left 2’s complement multiplicand by one
bit
• +2 = Multiplicand x 2 (10)
• 10110 x 2 (10)= 10110 0(multiplying by +2 is nothing but shift left 1
bit with 0 inserted)
 1.Bit Pair Recoding or Extended Booth
Algorithm

• If the M or Q is negative,then find 2’s complement of respective

negative number.
• Find the recoded multiplier(Q’) by referring bit pair recoding table by
adding implied zero and extended sign bit.
• Multiply with 2n bit extended for each partial product Pi,where each
partial product is written with 2 bit right space.
Steps for Bit Pair Recoding or Extended Booth Algorithm

• Step1:Load A=0,Q-1=0,Q=Multiplier, Sequential Counter SC=n/2

where n is number of multiplier bits

• Step 2:Check the status of Q1Q0Q-1 .

• If Q1Q0Q-1 =100:perform A-2xM
• If Q1Q0Q-1 =101 or 110 ;perform A-1XM
• If Q1Q0Q-1 =001 or 010;perform A1XM
• If Q1Q0Q-1 =011 ;perform A2XM
• If Q1Q0Q-1 =111 ;perform No operation

• Step 3:Add the above multiplicand value to previous stored

value of A register.
Steps for Bit Pair Recoding or Extended Booth Algorithm (cont….)

• Step 4:Perform Arithmetic Shift Right(ASR) 2 times

• Step 5:Decrement Sequence counter if non zero.Repeat step 2 to 5
for n/2 times.
• Step 6:Stop
Multiply 13 X -6 using Bit Pair Recoding
Represent negative numbers in 2’s complement form
Multiplicand=M=+13=01101
Multiplier=Q=-6=0110
According to Bit Pair recoding algorithm,we should have even number
of bits and it should be same for both multiplicand and multiplier
M=+13=001101
Q=-6=111010
Multiply 13 X -6 using Bit Pair Recoding
Comment A Q Q -1 SC
000000 111010 0 3
-2 X M 100110
100110 111010 0
ASR 2 times 111001 101110 1
-1XM 110011 2
101100 101110 1
ASR 2 times 111011 001011 1
0XM:ASR 2 111110 110010 1 1
times product Ignored
Verify product by taking 2’s complement,if
it’s a negative value