Digital Electronics (18EC32) Notes

III. Registers
A single flip-flop is able to store single bit information either 0 or 1, but to store more than
one bit information, a group of flip-flops need to be connected. A group of flip-flops is called a
register. If a register contains n flip-flops, it is able to stor n bit information.
Registers can be used to generate the specified sequence and can also be used to shift the content
of flip-flop position wise, based on this the applications of registers are classified into two
categories.
1. Shift registers and
2. Counters
1. Shift registers
A shift register is an entity of flip-flops, which are capable of shifting the state of flip-flop
positionwise in one direction or two directions.
Example: To store 4-bit data 1001, four flip-flops are used.

Figure 32: Basic shift register

Based on the direction of shifting the content of flip-flop, shift registers are classified into two
types.
a) Unidirectional shift registers
The unidirectional shift registers, shifts the contents of flip-flops in only one direction either right
shift or left shift.
b) Bideirectional shift registers
The Bidirectional shift registers are capable of performing right shift as well as left shift through
a proper control signal.
c) Universal shift register
The universal shift registers are capable of performing right shift as well as left shift through a
proper control signal along with parallel loading and memory.

Shift registers further classified into four types, based on the way the input is loaded and the output
is received.
a) Serial input and serial ouptut
The information will be loaded serially through a single line and output will be received serially
through a single line is called serial input and serial output (SISO) shift register shown in figure
(33).

Figure 33: SISO Shift register

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Digital Electronics (18EC32) Notes

b) Serial input and parallel output

the information will be loaded serially through a single line and output will be received in parallel
through multiple lines is called serial input parallel output (SIPO) shift register shown in figure
(34).

Figure 34: SIPO Shift register

c) Parallel input and serial output
The information bits will be loaded in parallel through multiple lines and output will be received
through a single line is called parallel input serial output (PISO) shift register shown in figure (35).

Figure 35: SISO Shift register

d) Parallel input and parallel output
The information bits will be loaded in parallel through multiple lines and output will be taken in
parallel with multiple output lines is called parallel input parallel output (PIPO) shift register
shown in figure (36).

Figure 36: SISO Shift register

1. Serial input serial output (SISO) unidirectional shift register

Figure (37, shows the logic diagram of 4-bit sireial input serial output shift registers, designed
using four D flip-flops, all the flip-flops are positive edge triggered flip flops.
Logic Diagram:

Figure 37: SISO Shift register

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Digital Electronics (18EC32) Notes

At the every rising edge of the clock pulse, the contents of flip-flops will be shifted towards the
succeeding stages of the flip-flops position wise.

Truth table

Serial In
Serial Out

Table 24: Truth table of SISO shift register

Timing diagarm

Figure 38: Timing diagram of SISO shift register

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Digital Electronics (18EC32) Notes

2. Serial input parallel output (SIPO) unidirectional shift register

Figure (39), shows the logic diagram of 4-bit sireial input parallel output shift registers, designed
using four D flip-flops, all the flip-flops are positive edge triggered flip flops.
Logic Diagram:

Figure 39: SIPO Shift register

At the every rising edge of the clock pulse, the contents of flip-flops will be shifted towards the
succeeding stages of the flip-flops position wise.

Truth table

Serial In
Parallel Out

Table 25: Truth table of SIPO shift register

Timing diagarm

Figure 40: Timing diagram of SIPO shift register

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Digital Electronics (18EC32) Notes

3. Parallel input Parallel output (PIPO) unidirectional shift register

Figure (41), shows the logic diagram of 4-bit Parallel input parallel output shift registers, designed
using four D flip-flops, all the flip-flops are positive edge triggered flip flops.
Logic Diagram:

Figure 41: PIPO Shift register

At the every rising edge of the clock pulse, the contents of flip-flops will be shifted towards the
succeeding stages of the flip-flops position wise.

Truth table

Parallel Out

Table 26: Truth table of PIPO shift register

Timing diagram

Figure 42: Timing diagram of PIPO shift register

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Digital Electronics (18EC32) Notes

4. Parallel input Serial output (PISO) unidirectional shift register

Figure (43), shows the logic diagram of 4-bit Parallel input serial output shift registers, designed
using four D flip-flops, all the flip-flops are positive edge triggered flip flops.
̅̅̅̅̅̅̅ = 0(𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐿𝑜𝑎𝑑𝑖𝑛𝑔)
• 𝑆ℎ𝑖𝑓𝑡/𝐿𝑜𝑎𝑑
̅̅̅̅̅̅̅ = 1(𝑆ℎ𝑖𝑓𝑡𝑖𝑛𝑔)
• 𝑆ℎ𝑖𝑓𝑡/𝐿𝑜𝑎𝑑
Logic Diagram:

Figure 43: PISO Shift register

At the every rising edge of the clock pulse, the contents of flip-flops will be shifted towards the
succeeding stages of the flip-flops position wise.

Truth table
Parallel Data : D=1111

Clk Q0 Q1 Q2 Q3
0 0 0 0 0

1 1 Parallel1Load 1 1
Serial Out

2 0 1 1 1

3 0 0 1 1

4 0 0 0 1

Table 27: Truth table of PISO shift register

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Digital Electronics (18EC32) Notes

Timing diagram

Figure 44: Timing diagram of PISO shift registerS

NOTE:
• A single circuit which performs all the shift register operations in single direction shown
in figure (45).
̅̅̅̅̅̅̅ = 0(𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 − 𝑖𝑛)
• 𝑆ℎ𝑖𝑓𝑡/𝐿𝑜𝑎𝑑
̅̅̅̅̅̅̅ = 1(𝑆𝑒𝑟𝑖𝑎𝑙 − 𝑖𝑛)
• 𝑆ℎ𝑖𝑓𝑡/𝐿𝑜𝑎𝑑

Figure 45: Single circuit which performs SISO, SIPO, PIPO and PISO

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Digital Electronics (18EC32) Notes

Bidirectional Shift register

Performs both left shift and right shift
M=0 (Shift left operation), M=1 (Shift right operation)
Logic diagram

Figure 46: Logic diagram of bidirectional shift registers

Universal Shift Register
Bidirectional Shift Register + (SISO, SIPO, PIPO, PISO)+Memory

Figure 47: Logic symbol of universal shift register

S1 S0 Register
Operation
0 0 No Change
(Memory)

0 1 Shift left

1 0 Shift right

1 1 Parallel loading

Table 28: Universal shift opearions table

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Digital Electronics (18EC32) Notes

Logic Diagram

Figure 48: Logic diagram of universal shift register

NOTE: Students are asked to write the detailed working principle of all the shift registers
(Explanation for all shift registers are omitted in this notes and asked to explain).

IV. Counters
Registers can also be used to generate the specified sequence, counting the binary values
either incrementally or in decrement is an example of sequence. Hence, counter is a sequential
circuit, which counts the pulses either in ascending or descending order.
n-bit counter will be designed using n-flip-flops.

Counters are classified into two types based on the application of clock signal.

1. Synchronous counters and

2. Asynchronous counters.
3.
The clock signal is applied to all the flip-flops of a counter circuit simultaneously is called
synchronous contours.

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Digital Electronics (18EC32) Notes

Figure (49) shows the two-bit counter, the clock signal for the two flip-flops are supplied
simultaneously. ̅̅̅̅̅̅
𝐶𝐿𝑅 is an asynchronous input, logic-0 to this pin sets the initial value of all the
flip-flop to zero.

Figure 49: Example for synchronous counter

The output of the previous state flip serves as a clock input to the next state flip-flop is called
asynchronous counters.

Figure (50) shows that, the clock input for the second flip-flop will be supplied from the output of
first flip-flop.

Figure 50: Example for asynchronous counter

Similarly, counters can be designed using any type of flip-flops, depending on the counting
sequence, counters are further classified into three types.
1. Up-counter and
Counts the clock pulse incrementally.
2. Down-counter
Counts the clock pulse in decrement order.
3. Ring counter
Outputs the specified sequence in circular/ring format.

Asynchronous UP-Counter (Binary Ripple counter)

Counters whose counting sequence corresponds to that of binary numbers are called binary
counters. The modulus of binary counter is 2𝑛 , where n is the number of flip-flops required to
design the counter.
Example:
if n=3, the counter performs counting from 000 to 111 (8 combinations(0 to 2𝑛 − 1)), hence three
flip-flops are required.
Similarly

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Digital Electronics (18EC32) Notes

If n=4, the counter performs counting from 0000 to 1111 (16 combinations(0 to 2𝑛 − 1)), hence
four flip-flops are required.
Figure (51) shows the logic diagram of 4-bit up counter using positive edge triggered T flip-flops.
Each positive transition of clock makes the flip-flop to toggle.
Logic Diagram

Figure 51: Example for asynchronous counter

Output 𝑄̅ of previous order flip-flop serves clock signal for the next order flip-flops, and
clock pulse applied to all the flip-flops is not simultaneous, hence called as asynchronous counter.
T inputs of all flip-flops are connected to logic-1, which acts as a toggle device. Output of the last
stage flip-flop is MSB and the output of first stage flip-flop is LSB.
For every rising edge of the clock pulse the content of first stage(Q0) T-flip-flop will toggles, for
every falling edge of the Q0 the content of second stage(Q1) T-flip-flop will toggles, this process
continues until the last stage flip-flop.
Assume, initially, the contents of all the four T flip-flops are zero. At the rising edge of the clock
pulse Q0 becomes ‘1’ and the remaining flip-flop outputs remains zero. The later stage flip-flops
output change occurs at the next falling edge of the previous stage flip-flop outputs, shown in the
timing diagram figure (52).

Figure 52: Timing diagram of 4-bit asynchronous binary ripple up counter

Change in the state of flip-flops occurs through the outputs of the previous stage flip-flops, that is
the effect of count pulse must ripple through the counter. Hence the name ripple counter.

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Digital Electronics (18EC32) Notes

Asynchronous Down-Counter (Binary Ripple counter)

Figure (53) shows the logic diagram of 4-bit down counter using positive edge triggered T flip-
flops. Each positive transition of clock makes the flip-flop to toggle.
Logic Diagram

Figure 53: Timing diagram of 4-bit asynchronous binary ripple up counter

Output 𝑄̅ of previous order flip-flop serves clock signal for the next order flip-flops, and
clock pulse applied to all the flip-flops is not simultaneous, hence called as asynchronous counter.
T inputs of all flip-flops are connected to logic-1, which acts as a toggle device. Output ̅̅̅ 𝑄3 of the
last stage flip-flop is MSB and the output ̅̅̅𝑄0 of first stage flip-flop is LSB.
For every rising edge of the clock pulse the content of first stage(𝑄0 ̅̅̅̅) T-flip-flop will toggles, for
every falling edge of the Q0 the content of second stage(Q1) T-flip-flop will toggles, this process
continues until the last stage flip-flop.
Assume, initially, the contents of all the four T flip-flops are zero, hence complement of the outputs
is 1’s. At the rising edge of the clock pulse ̅̅̅̅
𝑄0 becomes ‘0’ and the remaining flip-flop complement
outputs remains 1. The later stage flip-flops output change occurs at the next falling edge of the
previous stage flip-flop outputs, shown in the timing diagram figure (54).

Figure 54: Timing diagram of 4-bit asynchronous binary ripple up counter

Change in the state of flip-flops occurs through the outputs of the previous stage flip-flops, that is
the effect of count pulse must ripple through the counter. Hence the name ripple counter

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Digital Electronics (18EC32) Notes

V. Miscelaneous Concepts

Flip-flops conversion

1. SR to D flip-flop

Excitation table Logic diagram

Qn D Qn+1 S R
0 0 0 0 X
0 1 1 1 0
1 0 0 0 1
1 1 1 X 0
Excitation equations
̅
𝑆 = 𝐷 𝑎𝑛𝑑 𝑅 = 𝐷
2. SR to JK flip-flop

Excitation equations
Excitation table 𝑆 = ̅̅̅̅
𝑄𝑛 𝐽 𝑎𝑛𝑑 𝑅 = 𝑄𝑛 𝐾
Qn J K Qn+1 S R
0 0 0 0 0 X
0 0 1 0 0 X
0 1 0 1 1 0
0 1 1 1 1 0
1 0 0 1 X 0
1 0 1 0 0 1
1 1 0 1 X 0
1 1 1 0 0 1

3. SR to T flip-flop

Excitation table Logic Diagram

Qn T Qn+1 S R
0 0 0 0 X
0 1 1 1 0
1 0 1 X 0
1 1 0 0 1
Excitation equations
𝑆 = 𝑇𝑄 ̅̅̅̅
𝑛 𝑎𝑛𝑑 𝑅 = 𝑇𝑄𝑛

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Digital Electronics (18EC32) Notes

4. JK to D flip-flop
Excitation table Logic diagram
Qn D Qn+1 J K
0 0 0 0 X
0 1 1 1 X
1 0 0 X 1
1 1 1 X 0
Excitation equations
̅
𝐽 = 𝐷 𝑎𝑛𝑑 𝐾 = 𝐷
5. JK to T flip-flop
Excitation table Logic diagram
Qn T Qn+1 J K
0 0 0 0 X
0 1 1 1 X
1 0 1 X 0
1 1 0 X 1
Excitation equations
𝐽 = 𝑇 𝑎𝑛𝑑 𝐾 = 𝑇
6. D to T flip-flop
Excitation table Logic diagram
Qn T Qn+1 D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
Excitation equation
𝐷 = 𝑇 ⊕ 𝑄𝑛

7. D to JK flip-flop
Excitation table Excitation equation
Qn J K Qn+1 D ̅ + ̅̅̅̅
𝐷 = 𝑄𝑛 𝐾 𝑄𝑛 𝐽
0 0 0 0 0 Logic diagram
0 0 1 0 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 0
1 1 0 1 1
1 1 1 0 0

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Digital Electronics (18EC32) Notes

8. T to D flip-flop
Excitation table Logic diagram
Qn D Qn+1 T
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
Excitation equation
𝑇 = 𝑄𝑛 ⊕ 𝐷

9. T-JK Flip-flop
Excitation table Excitation equation
Qn J K Qn+1 T 𝑇 = 𝑄𝑛 𝐾 + ̅̅̅̅
𝑄𝑛 𝐽
0 0 0 0 0 Logic diagram
0 0 1 0 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 1
1 1 0 1 0
1 1 1 0 1

NOTE: JK to SR, T to SR and D to SR conversion is not possible.

******

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Digital Electronics (18EC32) Notes

UNIT-IV : Counters design and state machines

Counters
Registers can also be used to generate the specified sequence, counting the binary values
either incrementally or in decrement is an example of sequence. Hence, counter is a sequential
circuit, which counts the pulses either in ascending or descending order.
n-bit counter will be designed using n-flip-flops.

Counters are classified into two types based on the application of clock signal.

4. Synchronous counters and

5. Asynchronous counters.
6.
The clock signal is applied to all the flip-flops of a counter circuit simultaneously is called
synchronous contours.

Figure (49) shows the two-bit counter, the clock signal for the two flip-flops are supplied
simultaneously. ̅̅̅̅̅̅
𝐶𝐿𝑅 is an asynchronous input, logic-0 to this pin sets the initial value of all the
flip-flop to zero.

Figure 49: Example for synchronous counter

The output of the previous state flip serves as a clock input to the next state flip-flop is called
asynchronous counters.

Figure (50) shows that, the clock input for the second flip-flop will be supplied from the output of
first flip-flop.

Figure 50: Example for asynchronous counter

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Digital Electronics (18EC32) Notes

Similarly, counters can be designed using any type of flip-flops, depending on the counting
sequence, counters are further classified into three types.
4. Up-counter and
Counts the clock pulse incrementally.
5. Down-counter
Counts the clock pulse in decrement order.
6. Ring counter
Outputs the specified sequence in circular/ring format.

Asynchronous UP-Counter (Binary Ripple counter)

Counters whose counting sequence corresponds to that of binary numbers are called binary
counters. The modulus of binary counter is 2𝑛 , where n is the number of flip-flops required to
design the counter.
Example:
if n=3, the counter performs counting from 000 to 111 (8 combinations(0 to 2𝑛 − 1)), hence three
flip-flops are required.
Similarly
If n=4, the counter performs counting from 0000 to 1111 (16 combinations(0 to 2𝑛 − 1)), hence
four flip-flops are required.
Figure (51) shows the logic diagram of 4-bit up counter using positive edge triggered T flip-flops.
Each positive transition of clock makes the flip-flop to toggle.
Logic Diagram

Figure 51: Example for asynchronous counter

Output 𝑄̅ of previous order flip-flop serves clock signal for the next order flip-flops, and
clock pulse applied to all the flip-flops is not simultaneous, hence called as asynchronous counter.
T inputs of all flip-flops are connected to logic-1, which acts as a toggle device. Output of the last
stage flip-flop is MSB and the output of first stage flip-flop is LSB.
For every rising edge of the clock pulse the content of first stage(Q0) T-flip-flop will toggles, for
every falling edge of the Q0 the content of second stage(Q1) T-flip-flop will toggles, this process
continues until the last stage flip-flop.
Assume, initially, the contents of all the four T flip-flops are zero. At the rising edge of the clock
pulse Q0 becomes ‘1’ and the remaining flip-flop outputs remains zero. The later stage flip-flops

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Digital Electronics (18EC32) Notes

output change occurs at the next falling edge of the previous stage flip-flop outputs, shown in the
timing diagram figure (52).

Figure 52: Timing diagram of 4-bit asynchronous binary ripple up counter

Change in the state of flip-flops occurs through the outputs of the previous stage flip-flops, that is
the effect of count pulse must ripple through the counter. Hence the name ripple counter.
Asynchronous Down-Counter (Binary Ripple counter)
Figure (53) shows the logic diagram of 4-bit down counter using positive edge triggered T flip-
flops. Each positive transition of clock makes the flip-flop to toggle.
Logic Diagram

Figure 53: Timing diagram of 4-bit asynchronous binary ripple up counter

Output 𝑄̅ of previous order flip-flop serves clock signal for the next order flip-flops, and
clock pulse applied to all the flip-flops is not simultaneous, hence called as asynchronous counter.
T inputs of all flip-flops are connected to logic-1, which acts as a toggle device. Output ̅̅̅ 𝑄3 of the
last stage flip-flop is MSB and the output ̅̅̅𝑄0 of first stage flip-flop is LSB.
For every rising edge of the clock pulse the content of first stage(𝑄0 ̅̅̅̅) T-flip-flop will toggles, for
every falling edge of the Q0 the content of second stage(Q1) T-flip-flop will toggles, this process
continues until the last stage flip-flop.
Assume, initially, the contents of all the four T flip-flops are zero, hence complement of the outputs
̅̅̅̅ becomes ‘0’ and the remaining flip-flop complement
is 1’s. At the rising edge of the clock pulse 𝑄0

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Digital Electronics (18EC32) Notes

outputs remains 1. The later stage flip-flops output change occurs at the next falling edge of the
previous stage flip-flop outputs, shown in the timing diagram figure (54).

Figure 54: Timing diagram of 4-bit asynchronous binary ripple up counter

Change in the state of flip-flops occurs through the outputs of the previous stage flip-flops, that is
the effect of count pulse must ripple through the counter. Hence the name ripple counter

State diagram.
A graphical representation of the behavior of counters or any sequential circuits is called state
diagram. State diagrams helps for the design of counters easily, which shows the transition from
present states to the next states.
Procedure to draw the state diagram.
 Each state is represented by a circle, and the present state should be mentioned inside the
circle.
 Use arrow associated lines to show the transition from present state to the next state.
NOTE: if the present state and next state is same, then connect the arrow associated line to
the same state.
Example: Two bit up-counter, four states counting from 00 to 11.

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Digital Electronics (18EC32) Notes

State table
The information contained in the state diagram is tabulated in a tabular form is called state table
also called state synthesis table.
Example: Two-bit counter
Present Next
states states
Q1 Q 0 Q1 + Q0 +
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

Procedure to design synchronous counters.

1. Identify the number of flip-flops required based on the number of bits of sequence.
2. Draw the state diagram
3. Write the excitation table of the chosen flip-flop.
4. Obtain the excitation table for the complete circuit.
5. simplify the excitation equations using K-map.
6. Draw the logic diagram.
7. Verify the logic diagram by function table and timing diagram.

In the following section, the design of two-bit synchronous counter is discussed using T flip-
flop.
1. No. of flip-flops is required =2, two-bit counter – sequence is 00, 01, 10 and 11.
2. State diagram

3. Excitation table of T-flip-flop

States Excitations
Q Q+ T
0 0 0
0 1 1

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Digital Electronics (18EC32) Notes

1 0 1
1 1 0
4. Excitation table for complete circuit

Present Next Excitations

states states
Q1 Q0 Q1 + Q0 + T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

5. K-map simplification

𝑇1 = 𝑄0

𝑇0 = 1
6. Logic diagram

7. Verification
Function table
Clock Outputs
Pulse Q1 Q0
0 0 0
1 0 1
2 1 0
3 1 1
4 0 0

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Digital Electronics (18EC32) Notes

Timing diagram

Figure: Timing diagram of two-bit counter

Similarly, counters can be designed using any type of flip-flops, depending on the counting
sequence, counters are further classified into three types.
7. Up-counter and
Counts the clock pulse incrementally.
8. Down-counter
Counts the clock pulse in decrement order.
9. Ring counter
Outputs the specified sequence in circular/ring format.

1. 4-bit synchronous up-counter using T flip-flops.

1. No. of Flip-flops required=04.
2. State diagram

3. Excitation table of T-flip-flop

States Excitations
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0

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Digital Electronics (18EC32) Notes

4. Excitation table of complete circuit

Present states Next states Excitations
Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ T3 T2 T1 T0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1
1 0 1 0 1 0 1 1 0 0 0 1
1 0 1 1 1 1 0 0 0 1 1 1
1 1 0 0 1 1 0 1 0 0 0 1
1 1 0 1 1 1 1 0 0 0 1 1
1 1 1 0 1 1 1 1 0 0 0 1
1 1 1 1 0 0 0 0 1 1 1 1
5. K-map Simplification
𝑇3 = 𝑄2 𝑄1 𝑄0, 𝑇2 = 𝑄1 𝑄0, 𝑇1 = 𝑄0 , 𝑇0 = 1
6. Logic Diagram

a. NOTE: 4-bit synchronous counter with count enable input

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Digital Electronics (18EC32) Notes

b. NOTE: 4-bit synchronous counter variation (design using only two input AND gates)

c. 4-bit synchronous counter with parallel loading using JK flip-flops

Logic Symbol

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Digital Electronics (18EC32) Notes

2. MOD counters with parallel loading

Example-1: Synchronous Mod-6 counter with parallel loading

Example-2: MOD-10 Counter

Example-3: MOD-4 Counter

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Digital Electronics (18EC32) Notes

3. Realization of 8-bit synchronous counter using two 4-bit counters

Figure : 8-bit synchronous counter

Counters based on shift registers
registers can also be used to generate the sequences repeatedly and acts as the counters, there are
two types of counters Shift based on shift registers.
1. Ring Counter
The mod of ring counter is n, where n is the number of flip-flops are used in the design.
In the following section discusses the 4-bit ring counter using four D flip-flops shown in figure ().
The previous stage outputs of flip-flops serve as the input to next stage flip-flops and last stage
flip-flop output serves as the input of first stage flip-flop, which shifts the contents of flip-flops
position wise and also in circular.

Figure: 4-bit ring counter

Truth table
Clk Q0 Q1 Q2 Q3
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0

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Digital Electronics (18EC32) Notes

Initially, the contents of flip-flops (Q0Q1Q2Q3) are assumed as (1000), at every rising edge of the
clock pulse, the content of previous stage flip-flop will be shifted to the next stage flip-flop. The
ring counter generates the four sequence and the sequence repeats after every four clock pulses,
hence the mod of this counter is four.

Timing diagram
Figure shows the timing diagram of 4-bit ring counter.

Figure: Timing diagram of 4-bit ring counter.

2. Twisted ring counter

The twisted ring counter is the modification of ring counter; complemented output of last stage
serves as the input to the first stage flip-flop. The modulus of the twisted ring counter is 2n, where
n is the number of flip-flops are used in the design. Figure () shows the logic diagram of 4-bit
twisted ring counter using D flip-flops.

Figure : 4-bit twisted ring counter

Initially, the contents of flip-flops (Q0Q1Q2Q3) are assumed as (0000), at the first rising edge of
the clock pulse 𝐷0 = ̅̅̅𝑄3 and hence, 𝑄0 = 𝐷0 , 𝑄1 = 𝐷1 , 𝑄2 = 𝐷2 , 𝑄3 = 𝐷3 this data shift position
wise at the flip-flops at every rising edge of the clock pulse, The twisted ring counter generates
the eight sequence and the sequence repeats after every eight clock pulses, hence the mod of this
counter is eight. The twisted ring counter is also called Johnson counter and switch tail counter.

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Digital Electronics (18EC32) Notes

Truth Table:
Clk Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0

Timing diagram
Figure shows the timing diagram of Johnson counter.

Figure : Timing diagram of twisted ring counter

******

NOTE: State machines, state table and state diagram concepts need to be added

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Digital Electronics (18EC32) Notes

UNIT-V : VHDL

I. Introduction to VHDL

VHDL, which stands for VHSIC Hardware Description Language.

VHSIC stands for Very High Speed Integrated Circuit.

VHDL is a Computer Aided Design (CAD) tool for the modern design and synthesis of digital
systems.

Featurs of VHDL

 HDL is a very efficient tool for implementing and synthesizing designs on chips.
 It is a high level programming language similar to C.
 Debugging is easy, since HDL packages implement simulators and test-benches.
 HDL modules follow the general structure of software languages such as C.
 VHDL is a case insensitive language
 VHDL is a platform independent language.

II. History of VHDL.

VHDL was developed in the early 1980s under the VHSIC program at U.S. Department of Defence
(DoD). Until the development of VHDL, each company used its own primitive hardware
description languages, which are only gate level design tools and they did not support very
large scale design.

To meet the need of designing large scale systems, a research team from three companies – IBM,
Texas Instruments, and Intermetrics was jointly contributed at DoD for the development
of powerful hardware description language based tools. The team produced the first
publicly available standard, VHDL version 7.2, in 1985.

In 1986, the institute of electrical and electronics engineers (IEEE) was tasked with globally
standardizing the language in 1987, the IEEE completed their mission and added several
enhancements to the language, the result was the IEEE standard 1076-1987 version of
VHDL, which was also recognized by the American National Standards Institute (ANSI).

In 1993, further updations were done with added features, the updated version is a 1076-1993
version of VHDL. One of the major enhancement is the addition of package
std_logic_1164, which supports addition seven logic levels in addition to the existing two
levels.

Nowadays VHDL is a very popular design tool among industry and academia. Additional tools
have been added to the language, such as graphics based simulators that allow the user to

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Digital Electronics (18EC32) Notes

interact graphically on the screen with simulator to compile, simulate, test and verify the
design. Also an analog extension to the language is underway.

III. Structure of VHDL module.

VHDL module has two major constructs: entity and architecture. Entity describes the input and
output signals of the system to be described. And is given a name or identifier by the user.

Architecture describes the functionality of the system to be designed. That is the relation between
input and outputs of the system, and must be bound to an entity. The structure of any VHDL
module/program as follows.

entity entity_name is

port(variable_1:mode data_type;

variable_2:mode data_type;

variable_n:mode data_type);

architecture architecture_name of entity_name is

signal declaration;

constant declaration;

component declaration;

configurations;

packages;

begin

hardware_description_Statement_1;

hardware_description_Statement_2;

hardware_description_Statement_n;

end architecture_name;

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 Digital Electronics (18EC32) Notes

entity_name and architecture_name are identitifiers, these are used to name the module. Port
declaration in entity is the listing of input and output variables of the system to be designed. Mode
indicates the direction of input and output variables of the system. VHDL supports huge set of data
types, data type of any variable indicates the type of value and range of values allowed by the
corresponding variable. Architecture, consists of set of hardware description statements for the
system to be designed. Every hardware description statements must be written after the begin
statement. Signal declaration part is the list of intermediate signals of the system to be designed,
component declaration section, lists the components to be used in the design. End statements must
be written for completeness of the module or program.

IV. Port Modes

VHDL supports four mode types, which indicates the direction of the input and output variables,
they are.

1. in : in is the port read mode. This mode is used for input signals, and these variables always
appear on right hand side at the assignment statements.
2. out : out is the port write mode. This mode is used for output signals, and these variables
always appear on left hand side at the assignment statements.
3. buffer : buffer is the port read as well as write mode with limited fan-out. These variables
appear either on right hand side or left hand side at the assignment statements.
4. inout : inout is the port read as well as write mode without any constraints. These variables
appear either on right hand side or left hand side at the assignment statements.

V. Data types
Data type of any element determines the variables allowed value with range. VHDL has a rich
set of data types, some of them are discussed as follows.
1. Scalar data type:
Scalar data type variables allows only numerical values. Scalar data type are further
categorized into many types, they are discussed as follows.
i) bit type : The only values allowed are either ‘0’ and ‘1’.
ii) boolean type : The values allowed in this type is boolen type, true or false.
Generally these boolean data type variables are used in the conditional constrcuts.
Example:
a : in boolean;
b : in boolean;
big : out bit;
if (a>b)
big<=a;
else
big<=b;

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Digital Electronics (18EC32) Notes

iii) integer type : Allows all positive and negative values including zero. The range is
from -2,147,483, 647 to +2,147,483,647. Integer data types can be used as natural,
positive etc. natural data type allows all positive values including zero, positive data
type only positive numbers.
Example:
a : in integer;

iv) real type : Allows fractional values, with range is -1.0E38 to 1.0E38.
v) character type : These variables under character type allows a single character or
group of character (string).
vi) physical type : Allows the values which are measured in units. Like time in
seconds, weight in grams, etc..
2. Composite type
Composite data type are used to declare a bus type variables. There are three types of
composite data types, they are
i) bit vector : port (a:in bit_vector (3 downto 0));
ii) array type : collection of homogeneous elements.
port (a(7 downto 0):in integer);
iii) record type : group elements of different data types.
Example:
record
student_name: in character;
sl_no:in integer;
percentage:in real;
end record;

3. Other data-types
i) std_logic type: std_logic data-type variables take nine values, they are listed in the
following table.
port (a: in std_logic);
std_logic data-type variables take nine values, they are listed in the following table.

U Uninitiated.
X Unknown
0 Low
1 High
Z High impedance
W Weak unknown
L Weak low
H Weak high
- Don’t care

ii) std_logic_vector type: bus type std_logic data-type.

port(a:in std_logic_vector(7 downto 0);

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 Digital Electronics (18EC32) Notes

iii) signed type : Numeric data type with MSB is sign bit.
iv) unsigned type : Numeric data type of positive value.

VI. Operators
The operators are used to perform operations on operands, general operations are logical,
arithmetic, relational and shift operations, these are discussed as follows.
1. Logic operators: AND, OR, NOT, NAND, NOR, XOR and XNOR are logical operators
which performs on two operands. In VHDL all these operators performs bitwise logical
operations.
Example:
A=1010, B=1011, A and B=1010.

2. Relational operators: Table below summarized the types of relational operators.

Operator Description Operand type Result type

= Equality Any type Boolean
/= Inequality Any type Boolean
< Less than Scalar Boolean
<= Less than or equal Scalar Boolean
> Greater than Scalar Boolean
>= Greater than or Scalar Boolean
equal

3. Arithmetic operators: Table below summarized the different types of arithmetic operators.

Operator Description Operand type Result Example

type
Addition A-Numeric Numeric A=5, B=3.5
+ B-numeric A+B=8.5
- Subtraction A-Numeric Numeric A=5, B=3.5
B-numeric A-B=1.5
* Multiplication A-Integer or real Same as A=5, B=3
B- Integer or A A*B=15
real

* Multiplication A-Physical Same as A=5 sec,

B- Integer or A B=3.5
real A*B=17.5sec

* Multiplication A-Integer or real Same as A=5,

B- Physical B B=3.5sec
A+B=17.5sec

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Digital Electronics (18EC32) Notes

/ Division A-Integer or real Same as A=5, B=2

B- Integer or A A/B=2
real
/ Division A-Physical Same as A=5sec,
B- Integer or A B=2.5
real A/B=2sec

/ Division A-Integer or real Same as A=5, B=2.5

B- Physical B sec
A/B=2Hz.
mod Modulus A- only Integer Integer A=5, B=2
(Quotient) B- only Integer A mod B=1

rem Remainder A- only Integer integer A=5, B=2

B- only Integer A mod B=2

abs Absoulute Numerical Positive A=-5

numeric abs(A)=5
& Concatenation A- numerical or Same as A=”DN”
array A B=’A’
B- numerical or A & B=DNA
array

4. Shift and rotate operators

VHDL shift operators are unary operators and the operand must be a bit_vector type. These
operators are summarized in the following table with examples.
Operator Operation Description Operand value Operand value
example Before shifting after shifting
sll A sll 1 Shift A one A=1110 A=1100
Shift left position left
logically
srl A srl 1 Shift A one A=1110 A=0111
Shift right position right
logically
sla A s1a 1 Shift A one A=1111 A=1110
Shift left position left
arithmetically arithmetically
NOTE: for
signed
numbers
sra A sra 1 Shift A one A=1111 A=0111
Shift left position right
arithmetically arithmetically

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Digital Electronics (18EC32) Notes

NOTE: for
signed
numbers
rol A rol 1 rotate A one A=1001 A=0011
rotate left position left
arithmetically
ror A ror 1 rotate A one A=1001 A=1100
rotate right position right
arithmetically

VII. Styles of VHDL module descriptions

1. Behavioral modeling/modeling
Describes how the output behaves with the inputs. In behavioral modeling the statements
are executed sequentially, i.e., all statements are to be written inside the process block.
Process is the keyword in VHDL, the statements under this block are executed
sequentally.

Example:

Entity of half_adder is
Port (A, B: in std_logic; S, C:out std_logic);
End half_adder;
Architecture behavioural of half_adder is
Begin
Process(A, B)
S<=A xor B;
C<=A and B;
End process;
End behavioural;

2. Structural description/modeling
The hardware will be described using components or gates through the keyword
“component”

Example:

Entity of half_adder is
Port (A, B: in std_logic; S, C:out std_logic);
End half_adder;
Architecture structural of half_adder is
Component xor2
Pot(I1, I2: in bit; O1: out bit);
End xor2;

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Digital Electronics (18EC32) Notes

Component and2
Pot(I1, I2: in bit; O1: out bit);
End and2;
Begin
Xor2 portmap(A, B, S);
And2 portmap(A, B, C);
End structural;

3. Data-flow description/modeling
The statements of the data-flow description are executed concurrently.
Example:

Entity of half_adder is
Port (A, B: in std_logic; S, C:out std_logic);
End half_adder;
Architecture dataflow of half_adder is
Begin
S<=A xor B;
C<=A and B;
End behavioural;

4. Switch level description/modeling

The system is described using switches or transistors. VHDL does not have built in switch
level primitives, but can be constructed using packages.
Example:

Entity of inverter is
Port (x: in std_logic; y:out std_logic);
End inverter;
Architecture switch_level of inverter is
Component nmos
Pot(I1, I2: in bit; O1: out bit);
End nmos;
Component pmos
Pot(I1, I2: in bit; O1: out bit);
End pmos;
For all pmos use entity work.mos(pmos_behavioural);
For all nmos use entity work.mos(pmos_behavioural);
Constant vdd: std_logic:=’1’;
Constant gnd: std_logic:=’0’;
Begin
P1=pmos portmap(y, vdd, x);
N1=(nmos portmap(y, gnd, x);
End switch_level;

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Digital Electronics (18EC32) Notes

5. Mixed level description/modeling

Combination of two or more type of descriptions. i.e., description can be written using
more than one type of modeling.
Example: Combination of behavioral and data flow modeling.

Entity of example is
Port (A, B: in integer; x, y, z:out integer);
End example;
Architecture mixed_model of example is
X<=B+A
Begin
Process(A, B)
Y<=A - B;
z<=A * B;
End process;
End mixed_model;

VIII. Simulation and synthesis

Simulation is the process of verifying the functionality of the design. Synthesis is the process
of compilation or generating netlist and map into implementation technology. The complete
synthesis and simulation process are shown in the following flowchart.

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Digital Electronics (18EC32) Notes

IX. Programming Examples

VHDL Code for a Half-Adder

VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit; sum,carry:out bit);
end half_adder;

architecture data of half_adder is

begin
sum<= a xor b;
carry <= a and b;
end data;

VHDL Code for a Full Adder

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);

end full_adder;

architecture data of full_adder is

begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

VHDL Code for a Half-Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;

architecture data of half_sub is

begin
d<= a xor c;
b<= (a and (not c));
end data;

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Digital Electronics (18EC32) Notes

VHDL Code for a Full Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(a,b,c:in bit; sub,borrow:out bit);
end full_sub;

architecture data of full_sub is

begin
sub<= a xor b xor c;
borrow <= ((b xor c) and (not a)) or (b and c);
end data;

VHDL Code for a Multiplexer

Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;

architecture data of mux is

begin
Y<= (not S0 and not S1 and D0) or
(S0 and not S1 and D1) or
(not S0 and S1 and D2) or
(S0 and S1 and D3);
end data;

VHDL Code for a Demultiplexer

Library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(S1,S0,D:in bit; Y0,Y1,Y2,Y3:out bit);
end demux;

architecture data of demux is

begin
Y0<= ((Not S0) and (Not S1) and D);
Y1<= ((Not S0) and S1 and D);
Y2<= (S0 and (Not S1) and D);
Y3<= (S0 and S1 and D);
end data;

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Digital Electronics (18EC32) Notes

VHDL Code for a 8 x 3 Encoder

library ieee;
use ieee.std_logic_1164.all;

entity enc is
port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit);
end enc;
architecture vcgandhi of enc is
begin
o0<=i4 or i5 or i6 or i7;
o1<=i2 or i3 or i6 or i7;
o2<=i1 or i3 or i5 or i7;
end vcgandhi;

VHDL Code for a 3 x 8 Decoder

library ieee;
use ieee.std_logic_1164.all;

entity dec is
port(i0,i1,i2:in bit; o0,o1,o2,o3,o4,o5,o6,o7: out bit);
end dec;

architecture vcgandhi of dec is

begin
o0<=(not i0) and (not i1) and (not i2);
o1<=(not i0) and (not i1) and i2;
o2<=(not i0) and i1 and (not i2);
o3<=(not i0) and i1 and i2;
o4<=i0 and (not i1) and (not i2);
o5<=i0 and (not i1) and i2;
o6<=i0 and i1 and (not i2);
o7<=i0 and i1 and i2;
end vcgandhi;

VHDL Code for an SR Latch

library ieee;
use ieee.std_logic_1164.all;

entity srl is
port(r,s:in bit; q,qbar:buffer bit);
end srl;

architecture virat of srl is

signal s1,r1:bit;
begin
q<= s nand qbar;
qbar<= r nand q;
end virat;

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Digital Electronics (18EC32) Notes

VHDL Code for an SR Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;

architecture virat of srflip is

signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end virat;

VHDL code for the problem statement:

A system accepts three inputs and generates output as logic ‘1’ if the decimal equivalent of
input combination is odd number else output is logic ‘0’.

Step-1: Obtain the truth table

Inputs Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Step-2: Boolean expression (use K-map simplification)

𝑌 = 𝐵𝐶̅ + 𝐴𝐶̅
Step-3: Logic diagram

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Digital Electronics (18EC32) Notes

Step-4: VHDL Code

Entity combinational_circuit is
Port(A, B, C: in bit; Y: out bit);
End combinational_circuit;

Architecture data_flow of combinational_circuit is

Signal s1,s2,s3: inout bit;
Begin
S1<=not C;
S2<=A and S1;
S3<=B and S1;
Y<=S2 and S3;
End data_flow;

******

References
1. John M Yarbrough - Digital Logic Applications and Design, Thomson Learning, 2001. ISBN
981-240-062-1.
2. Donald D. Givone, ―Digital Principles and Design‖, McGraw Hill, 2002. ISBN 978-0-07-
052906-9.
3. Nazeih M.Botros-John Weily India Pvt. Ltd. 2008. HDL Programming (VHDL and Verilog)
4. D. P. Kothari and J. S Dhillon, ―Digital Circuits and Design‖, Pearson, 2016,
ISBN:9789332543539.
5. Charles H Roth, Jr., ―Fundamentals of Logic Design, Cengage Learning.
6. K. A. Navas, ―Electronics Lab Manual‖, Volume I, PHI, 5th Edition, 2015
ISBN:9788120351424.
7. https://www.tutorialspoint.com/vlsi_design/vhdl_programming_for_combinational_circuits.htm

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