VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM

ANALOG & DIGITAL ELECTRONICS LABORATORY

18CSL37
FOR III SEMESTER B.E. (ISE)
(As per Visveswaraya Technological University Syllabus)
2021-22

Compiled By:
Mrs. Shruthi B S Mrs. Ramya P V
Asst. Prof, Asst. Prof,
Dept. of ISE Dept. of ISE

Name : _____________________

USN : _____________________

Department of Information Science & Engineering

A.P.S. COLLEGE OF ENGINEERING
Anantha Gnana Gangothri,
26th K.M., NH-209, Bangalore- Coimbatore Road, Somanahalli,
BENGALURU – 560082.
ANALOG AND DIGITAL ELECTRONICS LAB MANUAL-18CSL37

CONTENTS
Ex No. TITILE OF THE EXPERIMENT

1. Design an astable multivibrator ciruit for three cases of duty cycle (50% , <50% and
>50%) using NE 555 timer IC. Simulate the same for any one duty cycle.
2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And
simulate the same.
3. Using ua 741 opamap, design a window comparate for any given UTP and LTP. And
simulate the same.
4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using
basic gates. And implement the same in HDL.
5. Given a 4-variable logic expression, simplify it using appropriate technique and
realize the simplified logic expression using 8:1 multiplexer IC. And implement the
same in HDL.
6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
And implement the same in HDL.
7. Design and implement code converter I)Binary to Gray (II) Gray to Binary Code
using basic gates.
8. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs
and demonstrate its working.
9. Design and implement an asynchronous counter using decade counter IC to count up
from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447)

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EXPERIMENT NO: 01

To design and implement an Astable multivibrator using 555 timer, for a given f requency and
duty cycle.

MATERIAL / EQUIPMENT REQUIRED:

SL Compon en ts/Equ ip men ts Specification/No Quantity
No
1 Timer NE 555 1
2 Resisto r 3.3K, 6.8K 1 each
3 Capacito r 0.1u, 0.01u 1 each
4 DC Regu lated Power
Supply - 1
5 CRO - 1

THEORY
• Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. When 555 timer is used as astable multivibrator, it has no stable
states, which means it cannot remain indefinitely in either state. This results in
rectangular output.
• The multivibrators are classified as:
Astable or free running Multivibrator: It alternates automatically between two states (low
and high for a rectangular output) and remains in each state for a time dependent upon
the circuit constants. It is just an oscillator as it requires no external pulse for its
operation.
Monostable or one shot Multivibrator: It has one stable state and one quasi stable state.
The application of an input pulse triggers the circuit time constants. After a period of
time determined by the time constant, the circuit returns to its initial stable state. The
process is repeated upon the application of each trigger pulse.
• Bistable Multivibrators on other hand have both stable states. It requires the application
of an external triggering pulse to change the output from one state to other. After the
output has changed its state, it remains in that state until the application of next trigger
pulse.

PROCEDURE All the components are tested.

1. Circuit is rigged up according to the circuit diagram.
2. Connect CRO-CH1 to pin no.6 (or 2) and CH2 to pin no.3 (Vout) of the 555.
3. Apply a Vcc of +10V.
4. Observe the capacitor voltage waveform at pin no.6. Observe the output waveform at
pin no.3.
5. Note down the period, pulse width, UTP, LTP and V H values.
6. Plot the graph of output waveform and capacitor voltage waveform. (UTP= 2/3 Vcc,
LTP=1/3 Vcc, as per theory)

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BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:

OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE

1. Period,T = _________ms
2. Therefore frequency, f =_________Hz
3. Pulse width, W =___________ms
3. Duty cycle, D = W/T = ________%
4. UTP =_________V
5. LTP=_________V
6. High level of output, V H =__________Volts. (Low level is zero volts).

FORMULA / CALCULATIONS
When 555 timer IC is connected to run as an Astable multivibrator, it gives rectangular
output. Let T be the period of the output waveform. Then duration of T during which
output is high,

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GRAPHS / OUTPUTS

RESULTS & CONCLUSIONS

• The various values are as expected. Frequency of output waveform =_________Hz.
• Duty cycle = ___________%

APPLICATIN AREAS
• Multivibrator.
• Embedded Applications.

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EXPERIMENT NO: 02
AIM
To design and implement a rectangular waveform generator(op-amp relaxation oscillator) for a
given frequency.
To implement a rectangular waveform generator (Op-amp relaxation oscillator) using a
simulation package, and observe the change in frequency when all the resistors values are
doubled
MATERIAL / EQUIPMENT REQUIRED:
SL Compon en ts/Equ ip men ts Specification/No Quantity
No
1 Op-Amp uA741 1
2 Resisto r 1K,10K, 1.8K 1 each
3 Capacitor 0.1µ 1
4 Regulated Power Supply - 2
5 CRO - 1

THEORY
As the name indicates, here there is no input signal, but circuit produces a square wave output
that swings between +Vsat and –Vsat. The capacitor charges through the feedback resistor R,
exponentially towards +Vsat. But capacitor voltage never reaches +Vsat because the voltage
crosses the UTP. When this happens the output wave switches to –Vsat. With the output now in
negative saturation, the capacitor discharges. When the capacitor voltage crosses through zero,
the capacitor starts charging negatively toward –Vsat. When the capacitor voltage crosses the
LTP, output switches back to +Vsat. The above events repeat, resulting in rectangular output.

PROCEDURE
1. Check all the components
2. Rig-up the circuit according to the circuit diagram.
3. Apply +Vcc of say 15V and –VEE of -15V.
4. Connect the CRO channel-1 across the capacitor and channel-2 across the output.
5. Observe the output rectangular waveform and capacitor waveform.
6. Calculate the period of the waveform, T.
7. Note down the out put voltage (+Vsat and –Vsat) and UTP and LTP
voltages. (Observed Vsat will be < +Vcc and | - Vsat | < | -VEE |)
8. Draw the graph of the output waveform and the capacitor voltage waveform.

BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION

a) Hardware Implementation

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b) Simulation
CASE 1: For the original circuit

CASE 2: Circuit with all resistors doubled

OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE

a)
i) Period, T = ms
ii) +Vsat = V
iii) -Vsat = - V
iv) UTP = + V
v) LTP = - V
b) Case 1: Period of the output waveform = ___________ms
Frequency f = ___________Hz
Case 2: With all resistors doubled:
Period of the output waveform =____________ms
Frequency f = ___________Hz

FORMULA / CALCULATIONS
The output is a rectangular wave with a duty cycle of 50 %. (i.e., high duration = low
duration). The period of the output wave is given by,

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Let us choose R1= 1.8KΩ.

The maximum voltage across the capacitor is the UTP and minimum voltage across
the capacitor is the LTP.
UTP = +BVsat
LTP = -BVsat
The output waveform swings between +Vsat and -Vsat)

GRAPHS/OUTPUTS

RESULTS & CONCLUSIONS

• Frequency of output waveform =1/T =___________ Hz
• Frequency of output waveform in simulation=1/T =___________Hz

APPLICATIN AREAS
• Voltage controlled oscillators (VCOs)
• Switching power supplies.
• Dual-slope analog to digital converters.
• Function generators.

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EXPERIMENT NO: 01
AIM:
• To design and implement an inverting Schmitt trigger using Op -Amp for a given UTP
and LTP values.
• To implement a Schmitt trigger using Op-amp using a simulation package for two sets of
UTP and LTP values.
MATERIAL / EQUIPMENT REQUIRED:
SL Compon en ts/Equ ip men ts Specification/No Quantity
No
1 Op-Amp uA741 1
2 10K 1
Resisto r 1K 2
3 DC Regu lated Power Supply - 1
5 Signal Generato r - 1
6 CRO - 1

THEORY / HYPOTHESIS
Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here, the
input voltage triggers the output voltage every time it exceeds certain voltage levels called the
upper threshold voltage V UTP and lower threshold voltage V LTP. The input voltage is applied to
the inverting input. Because the feedback voltage is aiding the input voltage, the feedback is
positive. A comparator using positive feedback is usually called a Schmitt Trigger. Schmitt
Trigger is used as a squaring circuit, in digital circuitry, amplitude comparator, etc.

PROCEDURE
1. Test all the components.
2. Rig up the circuit according to the circuit diagram.
3. Apply VCC =12V, VEE = -12V.
4. Apply a sinusoidal signal of peak voltage say 5V, with a frequency of 500Hz.
5. Observe the rectangular output on the CRO, measure the UTP and LTP values,
compare them with the design values.
6. Keep the CRO in X-Y mode (Vin to X-channel, Vout to Y-channel). Observe the
transfer curve which is called the Hysteresis curve.
BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:
a) Hardware Implementation

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b) Simulation
Case 1: UTP =_____V, LTP = ______V

Case 2: UTP =_____V, LTP = ______V

OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE

a)
1. Vin-p =_________ V
2. Input period T =________ mS
3. UTP = _________ V
4. LTP =__________ V
5. +Vsat =___________V
6. –Vsat =_________ V
b)
Case 1: UTP = V , LTP =
Case 2: UTP = V , LTP =

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FORMULA / CALCULATIONS
UTP(Upper Trip Point) is the point in the raising part of input waveform, at which the output
voltage changes state . LTP (Lower Trip Point) is the point in the falling part of the input
waveform, at which the output changes state. The above state change of ou tput occurs when the
input voltage crosses V ref
UTP = BVsat
LTP = -BVsat
Where B is called the feedback fraction. It is the part of the output voltage fed back to the input
(pin 3)
B = R2/ (R1+R2)(by potential divider principle)
+Vsat : It is the output voltage. Ideally it is either +V cc or –VEE respectively. (Practically it will
be a little less than this value)
Let us design an inverting Schmitt trigger for a UTP =+1V and LTP = -1V. Let
VCC = +12V (= +Vsat)
VEE = -12V (= -Vsat) , R2 =1K
We know UTP = +BVsat ,
1V= (R 2 /(R1 + R2))12V
1 = 1K/ (R1 + 1K )* 12
R1 + 1K =12K R1 =12K -1K = 11K
The above design will set an LTP = -1V
GRAPHS / OUTPUTS

RESULTS & CONCLUSIONS

a) The difference between UTP and LTP is defined as
Hysteresis is:
H=UTP – LTP =_______V - ______ V = __________V
APPLICATIN AREAS
• Function Generator.
• Noise immunity and Oscillator.

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EXPERIMENT NO: 04
AIM:
• To realize Half Adder and Full Adder using Basic gates.
• To realize Half Substractor and Full Substractor using Basic gates.
MATERIAL / EQUIPMENT REQUIRED:
• IC7404,7408,7432.
• Patch Cords, IC Trainer Kit
THEORY
Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical
adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output.
Adder circuits are of two types: Half adder ad Full adder.
• Half-Adder: A combinational logic circuit that performs the addition of two data bits, A
and B, is called a half-adder.
• Full-Adder: The half-adder does not take the carry bit from its previous stage into
account. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit,
Cin , is called a full-adder.
• Subtractor is the one which used to subtract two binary number(digit) and provides
Difference and Borrow as a output.
• Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit from
another single bit binary digit.
• Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary
digit is known as Full Subtractor.
PROCEDURE
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.
APPLICATIN AREAS
• Used in the design of ripple counters.
• Half adders can be used to design full adders.

BLOCK DIAGRAM/ TRUTH TABLE/ CIRCUIT DIAGRAM :

IC 7404 PIN DIAGRAM IC 7408 PIN DIAGRAM

IC 7432 PIN DIAGRAM IC 7411 PIN DIAGRAM

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B. Simulation
Verilog Code:
Dataflow model
module fulladder(a_in,b_in,c_in, sum,carry);
input a_in,b_in,c_in;
output sum,carry;
assign sum = a_in ^ b_in ^ c_in;
assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in);
endmodule

Simulation of Half Adder

Verilog Code:
module halfadder(a_in,b_in, sum,carry);
input a_in,b_in;
output sum,carry;
assign sum = a_in ^ b_in ;
assign carry = (a_in & b_in);
endmodule

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Simulation of Half subtractor

Verilog Code:
module halfsub(a_in,b_in, diff,bout);
input a_in,b_in;
output diff,bout;
assign diff = a_in ^ b_in ;
assign bout = (a_in’ & b_in);
endmodule
Simulation of Full subtractor
module fullsub(a_in,b_in,c_in, diff,bout);
input a_in,b_in,c_in;
output diff,bout;
assign diff = a_in ^ b_in ^ c_in;
assign bout = c_in’|(b_in^ b_in) &(b_in | c_in);
endmodule

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EXPERIMENT NO: 05

AIM:
• To simplify 4 variable logic expression, simplify it using Entered Variable Map and
realize the simplified logic expression using 8:1 Multiplexer IC.
• To develop the Verilog / VHDL code for an 8:1 multiplexer, simulate and verify its
working.

MATERIAL
• IC 74151, IC 7404
• Patch Cords & IC Trainer Kit
• PC with Windows XP, XILINX software.

THEORY / HYPOTHESIS
• Multiplexer means many into one. A ‘multiplexer’ is a circuit with many inputs, but
only one output. By using control signals, we can connect any input to the output.
Hence, it is also known as Data Selector.
• Map Entered Variable

Rules for entering values in a MEV K-map

Rule no MEV(F) Entry in Comments
MEV map
1 0 0 0 If function equals 0 for both values of MEV, enter
1 0 0 in appropriate cell of MEV Map
2 0 1 1 If function equals 1 for both values of MEV, enter
1 1 1.
3 0 0 MEV If function equals MEV enter MEV
1 1
4 0 1 MEV’ If the function is compliment of MEV, enter MEV.
1 0
5 0 X X If function equals don't care for both values of
1 X MEV, enter X.
6 0 0 0 If f = 0 for MEV= 0 and f=0 for MEV=1,
1 X enter 0.
7 0 X 0 If f = 0 for MEV= 0 and f= X for MEV=l,
1 0 enter 0.
8 0 X 1 If f = X for MEV= 0 and f=1 for MEV=1,
1 1 enter 1.
9 0 1 1 If f = 1 for MEV= 0 and f=X for MEV= X,
1 X enter X.

PROCEDURE
Assume that the following 4-variable Boolean function is to be implemented using 8:1
multiplexer IC 74151.
Y = F(A,B,C,D) = ∑ (0,1,2,4,5,6,8,9,12,13,14)

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The Entered Variable Map Truth-Table corresponding to the above expression is shown below:

• IC 74151 is an 8-channel digital multiplexer having 8- data inputs D0…D7, three select
lines (MSB)ABC(LSB) and two complementary outputs designated as Y and Y’. IC 7404
contains 6-inverters. IC 74151 and IC 7404 are inserted into the separate sockets in th e
digital trainer. In IC 74151 Pin 16 is Vcc and Pin 8 is Ground. In IC 7404 in 14 is Vcc
and Pin 7 is Ground.
• Vcc pins of both the ICs are connected to +5V dc power source pin. Ground pins of both
the ICs are connected the Ground points in the trainer.
• The circuit is rigged up as shown in the following diagram.
• Inputs D0 through D7 are connected as shown in the diagram and as required by the
function to be implemented. Output Y (Pin 5) is connected to LED. To enable the IC
74151, Pin 7 (Enable Pin) which is active low is connected to GND. Additional input D
(LSB) derived from a switch is connected to Pin 1 of IC 7404. Pin 2 (output) of IC 7404
is D’ and hence connected to Pin 3, Pin 1 and Pin 12 of IC 74151constituting D1, D3, and
D7 respectively. Pin 14 (D5) of IC 74151 is grounded remaining D input pins to the Vcc.
• Inputs ABCD are varied by making the corresponding switches ON or OFF, according to
the truth table below and the output observed in the LED (ON =1; OFF = 0) is verif ied
for correctness.
BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION
(a) Hardware Implementation
IC 74151 (8:1 MUX) IC 7404(NOT Gate)

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B. Simulation
module MUX8to1(D0,D1,D2,D3,D4,D5,D6,D7, EN, SEL,Y);
input D0,D1,D2,D3,D4,D5,D6,D7, EN, SEL;
output Y;
regY;
always @ (D0,D1,D2,D3,D4,D5,D6,D7, EN, SEL)
begin
if(EN)
Y=1`b0
else
begin
case(SEL)
3` b000 :Y = D0;
3` b000 :Y = D1;
3` b000 :Y = D2;
3` b000 :Y = D3;
3` b000 :Y = D4;
3` b000 :Y = D5;
3` b000 :Y = D6;
3` b000 :Y = D7;
endcase
endmodule
GRAPHS/OUTPUTS

9. APPLICATIN AREAS
• Programmable Logic Devices.
• Multiplexing.
• Digital Subscriber Line Access Multiplexer.

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EXPERIMENT NO: 06
AIM:
• To study the truth table of J-K Master Slave flip flop and verify the same.
• To develop Verilog/VHDL code for positive edge triggered D Flip-Flop and simulate its
working.
MATERIAL / EQUIPMENT REQUIRED
• IC 7410 (2)
• IC 7400
• Patch Cords & IC Trainer Kit
• PC with Windows XP, XILINX software
THEORY
• A flip-flop is a circuit that can maintain a binary state until directed by an input signal to
switch states. JK flip-flop is the most generally used flip-flop, which is edge triggered
and has got two data inputs J & K, and a clock input.
• Normal data inputs to a flip-flop are referred to as synchronous inputs, because they
effect the output in steps synchronous with the clock signal.
• Preset and Clear are asynchronous inputs, because they can set / reset the flip-flop
regardless of the status of clock. When Preset is activated, the flip -flop will be set and
when Clear is activated, the flip-flop will be reset. Preset and Clear find use when
multiple flip-flops are ganged together to perform a function.
• In Master-Slave JK flip-flop, two flip-flops are arranged such that, when the clock pulse
enables the first (the Master) latch, it disables the second (the Slave) latch. When the
clock changes the state again (on its falling edge), the output of the Master latch is
transferred to the Slave latch.
• The output of MS JK flip-flop is: Qnext = JQ’ + K’Q
PROCEDURE
• Flip-flop is a sequential circuit used as memory element in other sequential circuits as it
is capable of storing a single bit of information. Every flip-flop has two complementary
outputs (Q and Q’). Numbers of inputs to a JK flip-flop is 2 and are usually designated as
J and K. The circuit does not respond to the change in the inputs unless an additional
input called the clock input is applied.
• NAND gates of both the 3-input and 2-input ICs are connected as shown below. It is
ensured that the Vcc and GNDs of both the ICs are connected to +5V dc power source
and Ground points respectively in the trainer. Outputs Q and Q’ are connected to the
LEDs.
• Inputs J and K are connected to the switches and the CP input is connected to the
monopulser slot in the trainer.
• Initially J=0 and K = 0. Observe the Q. If it is 0, apply the clock pulse. Otherwise
make clear LOW (to make Q=0) and again HIGH (for normal operation) and then
apply theclock pulse. Observe the output listed in the column captioned Q(t+1).
• If Q=1 is to be established, make preset LOW (to make Q=1) and again HIGH (for
normal operation).
• Likewise obtain all the input combinations according the sequence in the table and
verify corresponding outputs.

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BLOCK / CIRCUIT
a) Hardware Implementation
Pin Diagram:
IC 7400(2-input NAND Gate) IC 7410 (3-input NAND)

7. Circuit Diagram: 8. TRUTH TABLE :

10. APPLICATIN AREAS

• Data Storage
• Data Transfer
• Counter, Registers
• Frequency Division.

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b) Simulation
module jkff (clk, reset, j, k, q, qb);
input clk,reset;
input j;
input k;
output q;
output qb;
reg temp;
always@(negedge reset, posedge clk)
begin
if(!reset)
temp<=1’b0;
else
begin
case({j,k})
2'b01:temp=1’b0;
2'b10:temp=1’b1;
2'b11:temp=~temp;
2'b00:temp=temp;
default:temp<=1’bz;
endcase
end

end
assign q=temp;
assign qb=~temp;

endmodule

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EXPERIMENT NO: 07
AIM:
• Design and implement code converter I)Binary to Gray II)Gray to Binary Code using
basic gates.
MATERIAL / EQUIPMENT REQUIRED:
• IC 7404 (1), IC 7432 (2), IC 7411 (2) or IC 7486 (2)
• Patch Cords & IC Trainer Kit
THEORY
• Binary Codes: A symbolic representation of data/ information is called code. The base or
radix of the binary number is 2. Hence, it has two independent symbols. The symbols
used are 0 and 1. A binary digit is called as a bit. A binary number consists of sequence
of bits, each of which is either a 0 or 1. Each bit carries a weight based on its position
relative to the binary point. The weight of each bit position is one power of 2 greater than
the weight of the position to its immediate right. e. g. of binary number is 100011 which
is equivalent to decimal number 35
• Gray Codes: It is a non-weighted code; therefore, it is not a suitable for arithmetic
operations. It is a cyclic code because successive code words in this code differ in one bit
position only i.e. it is a unit distance code.
Applications of Gray Code:
In instrumentation and data acquisition system where linear or angular displacement is
measured.
In shaft encoders, input-output devices, A/D converters and the other peripheral
equipment.
• Code Converters: The availability of a large variety of codes for the same discrete
elements of information results in the use of different codes by different digital systems.
It is some time necessary to use the output of one system as the input to the other. The
conversion circuit must be inserted between the two systems if each uses different codes
for the same information. Thus a code converter is a circuit that makes the two systems
compatible even though each uses the different code.
PROCEDURE
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and onserve the output
BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION
IC 7411 Pin Diagram

IC 7486 Pin Diagram

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Binary to Gray code converter

Gray to binary code converter

APPLICATIN AREAS
• Code conversion.
• Encoding and decoding.

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EXPERIMENT NO: 08

AIM:
• To Design and implement mod n (n<8) synchronous up-counter using J-K Flip Flop.
• To develop Verilog/VHDL code for mod-8 up counter and simulate its working.
MATERIAL / EQUIPMENT REQUIRED
• IC 7476 (2)
• IC 7408 (1)
• Patch Cords & IC Trainer Kit
• PC with Windows XP, XILINX software
THEORY
• A Counter is a sequential circuit that goes through a prescribed sequence of states up on
application of input pulse. Counter are in two categories –
Ripple Counter (Asynchronous Counter) – consists of a series connection of
complementing flip-flops (T / JK type), with the output of each flip-flop connected to the
clock pulse input of the next higher order flip-flop. The flip-flop holding the LSB
receives the clock pulses.
Synchronous Counter – the input pulses / clock pulses are applied to all clock pulse
inputs of all the flip-flops simultaneously.
PROCEDURE
• The counter with n flip-flops has maximum mod number 2n. For example, 3 -bit binary
counter is a mod 8 counter. This basic counter can be modified to produce MOD
numbers less than 2n by allowing the counter to skip states those are not normally part of
counting sequence.
• MOD-5 synchronous counter is designed below using JK flip-flops and the circuit is
• implemented as shown in the circuit diagram. A timing diagram is also constructed
below.
• Number of Flip-flops required = 3 as 3 is the minimum number for which 5<8. Let the
inputs of the three Flip-flops be JA, KA JB, KB, JC, KC. Let the normal outputs be QA,
QB, QC and the complementary outputs be QA’, QB’, QC’.
• Preset and Clear are the active low direct inputs (asynchronous inputs) to set or reset the
counter (means to set or reset all the flip-flops contained in the counter) before to the
application of the clock pulse to obtain the next state of the counter.
• The Characteristic table is useful for analysis and defining operation of flip-flops. The
• characteristic table of JK flip-flop is given below.

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• But during design, we normally know the transition from the present state to the next
state, called
Transition table. The transition table is derived using the truth table. Truth table is
constructed using the given counter.
• Here, given counter is mod-5. i.e., the given sequence is: 0, 1, 2, 3, 4, 0, . . .
• First draw the State Diagram:

Then construct the expected Truth table. From the truth table, construct Transition table.

Now, construct the Excitation table of JK flip-flop using the State diagram / Characteristic table
of JK flip flop. A table that lists the required inputs for a given change of state is called
‘Excitation table’

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Now by using the excitation table and the transition table, evaluate the flip-flop inputs as shown
below.

Go for K-Map simplification, and after K-Map simplification, expressions for the flip-flop inputs
are as shown below:

1. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION

IC 7476 (J K Flip Flop) IC 7408(2-input AND Gate)

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Circuit Diagram

APPLICATION AREAS
• Data Storage
• Data Transfer
• Frequency Division.

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EXPERIMENT NO: 9
AIM:
• Design and implement an asynchronous counter using decade counter IC to count up
from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
MATERIAL
• IC 7490 (1)
• IC 7411 (1)
• IC 7447 (1)
• Patch Cords & IC Trainer Kit
THEORY
• A Counter is a sequential circuit that goes through a prescribed sequence of states up on
application of input pulse. Counter are in two categories –
• Ripple Counter (Asynchronous Counter) – consists of a series connection of
complementing flip-flops (T / JK type), with the output of each flip-flop connected to the
clock pulse input of the next higher order flip-flop. The flip-flop holding the LSB
receives the clock pulses.
• Synchronous Counter – the input pulses / clock pulses are applied to all clock pulse
inputs of all the flip-flops simultaneously.
• A counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal. In
asynchronous counter a clock signal is provided for one flip-flop and its output is
provided as clock source for next flip-flop. The output of asynchronous counter is not
synchronized with clock signal.
• A decade counter follows a sequence of 10 states and returns to zero after the count of
nine. Such a counter must have at least 4 flip flops to represent each decimal digit since a
decimal digit is represented by a binary code with at least 4 bits.
BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION
Pin Diagram
IC 7411 (3-input AND Gate) IC 7447 7 Segment Display

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IC 7490 (Decade counter) Internal Diagram of 7490

Circuit Diagram: (General decade counter [mod 10])

1. APPLICATION AREAS
• Binary Coded Decimal.
• Finite State Machines.

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Appendix A: Creating & simulating Projects using Xilinx ISE 7.1 IDE

Step 1:

Step 2:

Step 3

After entering project name Press Enter Next.

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Step 4:

Press Next Button.

Step 5:

Press button New Source

Step 6:

Select Verilog module, Enter type of modeling on File Name ,Press Next.

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Step 7:

Enter the pin Names & type of pin required by model. Press Next.
Step 8:

Press Finish.
Step 9:

Press Next

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Press Next

Press Finish.
Step 10:

Type Module information.

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Step 11:
After defining functionality of module Double Click on Check Syntax

If the program is Error Free go to next step else check error message on window of project
navigator.
Step 12:
Once the program is error free, perform following steps.

Go to wave default window of Modelsim simulator force the input to logic 0’s or 1’s by right
clicking the mouse on particular variable to be forced. Once input is forced simulatethe design by
clicking run button.

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Appendix B: Creating &running Projects on ORCAD Pspice

Step 1:
Goto Start → Programs → Orcad family Release 9.2 Lite Edition → Capture Lite Edition
Step 2:

Step 3:

Step 4:

Select Create a Blank Object and enter OK.

Step 5:

Place the required component on schematic window by clicking on component button indicated
in figure above. Connect components using wire by clicking on wire button.

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Step 6:
To place the parts, click PLACE PART(Shift+P).

Step 7:
Select the part you wish to place in the schematic. Insert as many as needed, Right Click and
select END MODE to stop inserting the parts

Step 8:
To wire parts together click PLACE WIRE (Shift + W). Place cursor over boxes at ends of parts
and draw wires connecting parts. When done, right click and select END WIRE.

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NOTE : always select 0/ source for ground node of an analog circuit

- Every analog circuit must contain at least ond 0 ground .
- This is not a requirement for digital circuits.
Step 9 :
To change component values those are displayed
- Double click on displayed value.
- Change desired value in the dialog box that appears.

Step 10 : To set up simulation profile.

- Select PSPICE→ NEW SIMULATION PROFILE.
- Give discriptive name to the type of simulation

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Step 11 :
Place voltage,current,and power markers from the
PSPICE-→ MARKERS menu where needed as shown below

Step 12:
Run Program by selecting Pspice → Run, to get output waveform.

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VIVA QUESTIONS
1. Draw the basic structure of an N channel junction field effect transistor.
2. Why is FET known as a unipolar device?
3. What are the advantages and disadvantages of JFET over BJT?
4. What is a channel?
5. Distinguish between JFET and MOSFET.
6. What is an effect of cascading?
7. What are all the factors affecting the bandwidth of the RC Coupled amplifier?
8. Explain bypass capacitor?
9. What is meant by coupling capacitor?
10. Why does amplifier gain reduce?
11. Explain the different regions in frequency response?
12. State the types of distortions in amplifier?
13. What is cross over distortion? How it can be eliminated?
14. Define noise?
15. Draw the symbol of JFET and MOSFET.
16. What are the two modes of MOSFET?
17. Define pinch-off voltage
18. What is feedback and what are feedback amplifiers?
19. What is meant by positive and negative feedback?
20. What are the advantages and disadvantages of negative feedback?
21. Differentiate between voltage and current feedback in amplifiers?
22. What is the type of feedback used in an op- amp Schmitt trigger?
23. Give the expression for the frequency of oscillations in an op -amp sine wave oscillator?
24. What are the conditions for sustained oscillations or or what is Barkhausen criterion
25. What are the classifications of Oscillators?
26. What are the types of feedback oscillators?
27. Define Piezo-electric effect?
28. Draw the equivalent circuit of crystal oscillator?
29. How does an oscillator differ from an amplifier?
VIVA QUESTIONS ON LOGIC DESIGN
1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. Compare TTL logic family with CMOS family?
5. Which logic family is fastest and which has low power dissipation?
6. What are the different methods to obtain minimal expression?
7. What is a Min term and Max term
8. State the difference between SOP and POS.
9. What is meant by canonical representation?
10. What is K-map? Why is it used?
11. What is a multiplexer?
12. What is a de-multiplexer?
13. What are the applications of multiplexer and de-multiplexer?
14. Derive the Boolean expression for multiplexer and de-multiplexer.
15. In a 2n to 1 multiplexer how many selection lines are there?

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16. Implement an 8:1 mux using 4:1 mux?

17. What is a comparator?
18. What are the applications of comparator?
19. Derive the Boolean expressions of one bit comparator and two bit comparators.
20. How do you realize a higher magnitude comparator using lower bit comparator?
21. Design a 2 bit comparator using a single Logic gates?
22. Design an 8 bit comparator using a two numbers of IC 7485?
23. What are the applications of decoder?
24. What is the difference between decoder & encoder?
25. For n- 2n decoder how many i/p lines & how many o/p lines?
26. Using 3:8 decoder and associated logic, implement a full adder
27. What is the difference between decoder and de-mux?
28. What are the different types of LEDs?
29. What are the applications of LEDs?
30. What is a priority encoder?
31. What is the difference between Flip-Flop & latch?
32. Give examples for synchronous & asynchronous inputs?
33. What are the applications of different Flip-Flops?
What is the advantage of Edge triggering over level triggering?
35. What is the relation between propagation delay & clock frequency of flip -flop?
36. What is race around in flip-flop & how to overcome it?
37. Convert the J K Flip-Flop into D flip-flop and T flip-flop
38. List the functions of asynchronous inputs?
39. What is the necessity for sequence generation?
40. What are PISO, SIPO, and SISO with respect to shift register?
41. Differentiate between serial data & parallel data
42. What is the significance of Mode control bit?
43. What is a ring counter?
44. What is a Johnson counter?
45. How many Flip-flops are present in IC 7495?
46. What is an asynchronous counter?
47. How is it different from a synchronous counter?
48. Realize asynchronous counter using T flip-flop
49. What are synchronous counters?
50. What are the advantages of synchronous counters?
51. What is an excitation table?
52. Write the excitation table for D, T FF
53. Design mod-5 synchronous counter using T FF
54. What is a presettable counter?
55. What are the applications of presettable counters?
56. Write the circuit for preset value of 0100 and N=5 (up counter)
57. What is a decade counter?
58. What do you mean by a ripple counter?

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