STM32F070CB STM32F070RB

STM32F070C6 STM32F070F6
ARM®-based 32-bit MCU, up to 128 KB flash, USB FS 2.0,
11 timers, ADC, communication interfaces, 2.4 - 3.6 V
Datasheet - production data

Features
• Includes ST state-of-the-art patented
technology
LQFP64 (10 × 10 mm) TSSOP20 (6.4 × 4.4 mm)
• Core: Arm® 32-bit Cortex®-M0 CPU, frequency LQFP48 (7 × 7 mm)
up to 48 MHz
• Memories • Communication interfaces
– 32 to 128 Kbytes of flash memory – Up to two I2C interfaces
– 6 to 16 Kbytes of SRAM with HW parity – Fast Mode Plus (1 Mbit/s) support, with
20 mA current sink
• CRC calculation unit
• Reset and power management – SMBus/PMBus support (on single I/F)
– Digital & I/Os supply: VDD = 2.4 V to 3.6 V – Up to four USARTs supporting master
– Analog supply: VDDA = VDD to 3.6 V synchronous SPI and modem control; one
with auto baud rate detection
– Power-on/Power down reset (POR/PDR)
– Up to two SPIs (18 Mbit/s) with 4 to 16
– Low power modes: Sleep, Stop, Standby
programmable bit frames
• Clock management – USB 2.0 full-speed interface with BCD and
– 4 to 32 MHz crystal oscillator LPM support
– 32 kHz oscillator for RTC with calibration
• Serial wire debug (SWD)
– Internal 8 MHz RC with x6 PLL option
• All packages ECOPACK 2 compliant
– Internal 40 kHz RC oscillator
• Up to 51 fast I/Os
– All mappable on external interrupt vectors
– Up to 51 I/Os with 5V tolerant capability
• 5-channel DMA controller
• One 12-bit, 1.0 µs ADC (up to 16 channels)
– Conversion range: 0 to 3.6 V
– Separate analog supply: 2.4 V to 3.6 V
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby
• 11 timers
– One 16-bit advanced-control timer for
six-channel PWM output
– Up to seven 16-bit timers, with up to four
IC/OC, OCN, usable for IR control
decoding
– Independent and system watchdog timers
– SysTick timer

April 2024 DS10697 Rev 4 1/84

www.st.com
Contents STM32F070CB/RB/C6/F6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Arm® Cortex®-M0 core with embedded flash memory
and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2 General-purpose timers (TIM3, TIM14...17) . . . . . . . . . . . . . . . . . . . . . 19
3.11.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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STM32F070CB/RB/C6/F6 Contents

3.14 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 21

3.15 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 40
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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Contents STM32F070CB/RB/C6/F6

6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.2 TSSOP20 package information (YA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.4 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4/84 DS10697 Rev 4

STM32F070CB/RB/C6/F6 List of tables

List of tables

Table 1. STM32F070CB/RB/C6/F6 family device features and peripheral counts . . . . . . . . . . . . . . 10

Table 2. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. STM32F070CB/RB/C6/F6 I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. STM32F70x0 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. STM32F070CB/RB/C6/F6 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. STM32F070xB/6 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 30
Table 12. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 31
Table 13. Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 32
Table 14. Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 32
Table 15. STM32F070CB/RB/C6/F6 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . 34
Table 16. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 20. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 42
Table 24. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 42
Table 25. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 43
Table 26. Typical current consumption in Run mode, code with data processing
running from flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 27. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 34. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 36. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 37. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 38. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 39. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 40. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 41. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 42. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 43. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 44. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 45. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 46. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 47. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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List of tables STM32F070CB/RB/C6/F6

Table 48. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 49. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 50. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 51. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 52. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 53. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 54. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 55. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 56. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 57. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 58. TSSOP20 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 59. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 60. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 61. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 62. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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STM32F070CB/RB/C6/F6 List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. TSSOP20 20-pin package pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. LQFP48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. LQFP64 64-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. STM32F070CB/RB/C6/F6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 12. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 15. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 16. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 19. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 20. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 21. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 22. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 23. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 24. TSSOP20 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 25. TSSOP20 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 26. LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27. LQFP48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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Introduction STM32F070CB/RB/C6/F6

1 Introduction

This document provides information on STM32F070CB/RB/C6/F6 microcontrollers, such as

description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32F070CB/RB/C6/F6 errata sheet ES0291.
Information on memory mapping and control registers is the subject of the reference manual
RM0360 available from the STMicroelectronics website www.st.com.
Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32F070CB/RB/C6/F6 Description

2 Description

The STM32F070CB/RB/C6/F6 microcontrollers incorporate the high-performance Arm®

Cortex®-M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded
memories (up to 128 Kbytes of flash memory and up to 16 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. All devices offer standard
communication interfaces (up to two I2Cs, up to two SPIs and up to four USARTs), one USB
Full speed device, one 12-bit ADC, seven general-purpose 16-bit timers and an advanced-
control PWM timer.
The STM32F070CB/RB/C6/F6 microcontrollers operate in the -40 to +85 °C temperature
range from a 2.4 to 3.6V power supply. A comprehensive set of power-saving modes allows
the design of low-power applications.
The STM32F070CB/RB/C6/F6 microcontrollers include devices in three different packages
ranging from 20 pins to 64 pins. Depending on the device chosen, different sets of
peripherals are included. The description below provides an overview of the complete range
of STM32F070CB/RB/C6/F6 peripherals proposed.
These features make the STM32F070CB/RB/C6/F6 microcontrollers suitable for a wide
range of applications such as application control and user interfaces, handheld equipment,
A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and
HVACs.

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Description STM32F070CB/RB/C6/F6

Table 1. STM32F070CB/RB/C6/F6 family device features and peripheral counts

Peripheral STM32F070F6 STM32F070C6 STM32F070CB STM32F070RB

Flash memory (Kbytes) 32 128

SRAM (Kbytes) 6 16
Advanced
1 (16-bit)
control
Timers General
4 (16-bit) 5 (16-bit)
purpose
Basic - 2 (16-bit)
SPI 1 2
2C
Comm. I 1 2
interfaces USART 2 4
USB 1
12-bit ADC 1 1 1 1
(number of channels) (9 ext. + 2 int.) (10 ext. + 2 int.) (10 ext. + 2 int.) (16 ext. + 2 int.)
GPIOs 15 37 37 51
Max. CPU frequency 48 MHz
Operating voltage 2.4 to 3.6 V
Ambient operating temperature: -40°C to 85°C
Operating temperature
Junction temperature: -40°C to 105°C
Packages TSSOP20 LQFP48 LQFP48 LQFP64

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STM32F070CB/RB/C6/F6 Description

Figure 1. Block diagram

POWER
SWCLK Serial Wire
SWDIO VOLT.REG VDD = 2.4 to 3.5 V
Debug VDD18
as AF 3.3 V to 1.8 V VSS

Obl

interface
Flash GPL

memory
32 KB / 128 KB

Flash
CORTEX-M0 CPU @ VDD
32-bit
fMAX = 48 MHz SUPPLY
SUPERVISION
POR NRST
SRAM

Bus matrix

controller
Reset VDDA

SRAM
6 KB / 16 KB
Int POR/PDR VSSA
NVIC @ VDDA VDD
HSI14
RC 14 MHz
HSI
RC 8 MHz @ VDDA
PLLCLK @ VDD
PLL
LSI
GP DMA RC 40 kHz XTAL OSC OSC_IN
5 channels 4-32 MHz OSC_OUT
Ind. Window WDG

PA[15:0] GPIO port A Power

RESET & CLOCK Controller
CONTROL
PB[15:0] GPIO port B
AHB decoder

PC[15:0] GPIO port C XTAL32 kHz OSC32_IN

System and peripheral
OSC32_OUT
clocks
PD2 GPIO port D 3 TAMPER-RTC
RTC
(ALARM OUT)
PF[1:0] GPIO port F
RTC interface

CRC 4 channels
PWM TIMER 1 3 compl. channels
BRK, ETR input as AF
AHB
APB
TIMER 3 4 ch., ETR as AF
51 AF EXT. IT WKUP
TIMER 14 1 channel as AF

2 channels
USB TIMER 15 1 compl, BRK as AF
D+, D- USB
PHY
1 channel
TIMER 16 1 compl, BRK as AF
@ VDD
SRAM Window WDG 1 channel
1024 B TIMER 17 1 compl, BRK as AF
IR_OUT as AF
DBGMCU
MOSI, MISO, RX, TX,CTS, RTS,
USART1 CK, as AF
SCK, NSS, SPI1
as AF
RX, TX,CTS, RTS,
USART2 CK, as AF
MOSI, MISO, RX, TX,CTS, RTS,
SCK, NSS, SPI2 USART3 CK, as AF
as AF
RX, TX,CTS, RTS,
USART4 CK, as AF

SYSCFG IF
SCL, SDA, SMBA
TIMER 6 I2C1
(20 mA FM+), as AF

Temp. TIMER 7 I2C2 SCL, SDA, as AF

sensor

16x
AD input 12-bit ADC IF

VDDA
VSSA
@ VDDA

Power domain of analog blocks : VDD VDDA

MSv35597V3

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Functional overview STM32F070CB/RB/C6/F6

3 Functional overview

3.1 Arm® Cortex®-M0 core with embedded flash memory

and SRAM
The Arm® Cortex®-M0 processor is the latest generation of Arm processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Arm® Cortex®-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an Arm core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F0xx family has an embedded Arm core and is therefore compatible with all Arm
tools and software.
Figure 1 shows the general block diagram of the device family.

3.2 Memories
The device has the following features:
• 6 to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-
critical applications.
• The non-volatile memory is divided into two arrays:
– 32 to 128 Kbytes of embedded flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and boot
in RAM selection disabled

3.3 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• Boot from user flash memory
• Boot from system Memory
• Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the flash memory by
using USART on pins PA14/PA15 or PA9/PA10, or I2C on pins PB6/PB7, or USB on pins
PA11/PA12 (USB can be used only with HSE external clock equal to 24MHz, 18MHz,
16MHz, 12MHz, 8MHz, 6MHz, or 4MHz).

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3.4 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
generated polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

3.5 Power management

3.5.1 Power supply schemes

• VDD = 2.4 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
• VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs
and PLL. The VDDA voltage level must be always greater or equal to the VDD voltage
level and must be provided first.
For more details on how to connect power pins, refer to Figure 9: Power supply scheme.

3.5.2 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
• The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
• The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.

3.5.3 Voltage regulator

The regulator has two operating modes and it is always enabled after reset.
• Main (MR) is used in normal operating mode (Run).
• Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).

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3.5.4 Low-power modes

The STM32F070CB/RB/C6/F6 microcontrollers support three low-power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines and RTC.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.

3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

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Figure 2. Clock tree

FLITFCLK Flash memory

programming
I2C1SW interface
8 MHz HSI HSI HSI
HSI RC I2C1
SYSCLK

AHB, core, memory, DMA,

HCLK Cortex FCLK free-run clock
PREDIV
SW SYSCLK
PLLSRC PLLMUL Cortex
/8
HSI system timer
PLL /1,/2,… /1,/2,/4, PCLK
/1,/2,.. PLLCLK APB
x2,x3,.. …/512 /8,/16
../16 HSE peripherals
...x16
HPRE PPRE

CSS
PPRE

x1, x2 TIM1,3,6,7
OSC_OUT HSE 14,15,16,17
4-32 MHz
HSE OSC USART1SW
OSC_IN PCLK
LSE SYSCLK
USART1
HSI
/32 LSE
OSC32_IN RTCCLK
32.768 kHz LSE RTC
LSE OSC
OSC32_OUT
RTCSEL USB

40 kHz LSI IWDG

LSI RC
PLLNODIV ADC
14 MHz HSI14
HSI14 RC asynchronous
MCOPRE PLLCLK clock input
/1,/2
Main clock HSI
output HSI14
/1,/2,/4,..
MCO ../128 HSE Legend
SYSCLK
LSI black clock tree element
LSE
white clock tree control element
to TIM14
MCO clock line
control line

MSv35598V2

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.

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3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMA manages memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, all TIMx timers (except
TIM14) and ADC.

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4
priority levels.
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 51
GPIOs can be connected to the 16 external interrupt lines.

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3.10 Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and two internal (temperature
sensor, voltage reference measurement) channels and performs conversions in single-shot
or scan modes. In scan mode, automatic conversion is performed on a selected group of
analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

Table 2. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V (± 10 mV)

3.10.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.

Table 3. Internal voltage reference calibration values

Calibration value name Description Memory address

Raw data acquired at a

VREFINT_CAL temperature of 30 °C (± 5 °C), 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V (± 10 mV)

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3.11 Timers and watchdogs

The STM32F070CB/RB/C6/F6 devices include up to five general-purpose timers, two basic
timers and one advanced control timer.
Table 4 compares the features of the different timers.

Table 4. Timer feature comparison

Timer Counter Counter Prescaler DMA request Capture/compare Complementary
Timer
type resolution type factor generation channels outputs

Up, Any integer

Advanced
TIM1 16-bit down, between 1 Yes 4 3
control
up/down and 65536
Up, Any integer
TIM3 16-bit down, between 1 Yes 4 -
up/down and 65536
Any integer
TIM14 16-bit Up between 1 No 1 -
General and 65536
purpose Any integer
TIM15(1) 16-bit Up between 1 Yes 2 1
and 65536
Any integer
TIM16,
16-bit Up between 1 Yes 1 1
TIM17
and 65536
Any integer
TIM6,(1)
Basic 16-bit Up between 1 Yes 0 -
TIM7(1)
and 65536
1. Not available on STM32F070x6 devices.

3.11.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes)
• One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.

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3.11.2 General-purpose timers (TIM3, TIM14...17)

There are five synchronizable general-purpose timers embedded in the
STM32F070CB/RB/C6/F6 devices (see Table 4 for differences). Each general-purpose
timer can be used to generate PWM outputs, or as simple time base.

TIM3
STM32F070CB/RB/C6/F6 devices feature one synchronizable 4-channel general-purpose
timer. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. It
features four independent channels each for input capture/output compare, PWM or
one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM3 general-purpose timer can work with the TIM1 advanced-control timer via the
Timer Link feature for synchronization or event chaining.
TIM3 has an independent DMA request generation.
This timer is capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.
The counter can be frozen in debug mode.

TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.

3.11.3 Basic timers TIM6 and TIM7

These timers can be used as a generic 16-bit time base.

3.11.4 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It

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Functional overview STM32F070CB/RB/C6/F6

can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.

3.11.5 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.

3.11.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source (HCLK or HCLK/8)

3.12 Real-time clock (RTC)

The RTC is an independent BCD timer/counter. Its main features are the following:
• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.
• Programmable alarm with wake up from Stop and Standby mode capability.
• Periodic wakeup unit with programmable resolution and period.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Tow anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
The RTC clock sources can be:
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 40 kHz)
• The high-speed external clock divided by 32

20/84 DS10697 Rev 4

STM32F070CB/RB/C6/F6 Functional overview

3.13 Inter-integrated circuit interfaces (I2C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s). I2C1 also
supports Fast Mode Plus (up to 1 Mbit/s), with 20 mA output drive.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). They also include programmable analog and
digital noise filters.

Table 5. Comparison of I2C analog and digital filters

- Analog filter Digital filter

Pulse width of Programmable length from 1 to 15

≥ 50 ns
suppressed spikes I2C peripheral clocks
1. Extra filtering capability vs.
Benefits Available in Stop mode standard requirements.
2. Stable length
Variations depending on
Drawbacks -
temperature, voltage, process

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management.
The I2C interfaces can be served by the DMA controller.
Refer to Table 6 for the differences between I2C1 and I2C2.

Table 6. STM32F070CB/RB/C6/F6 I2C implementation(1)

I2C features I2C1 I2C2(2)

7-bit addressing mode X X

10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s), with 20mA output drive I/Os X -
Independent clock X -
SMBus X -
Wakeup from STOP - -
1. X = supported.
2. Only available on STM32F070xB devices.

3.14 Universal synchronous/asynchronous receiver/transmitter

(USART)
The device embeds up to four universal synchronous/asynchronous receivers/transmitters
that communicate at speeds of up to 6 Mbit/s.

DS10697 Rev 4 21/84

23
Functional overview STM32F070CB/RB/C6/F6

Table 7 gives an overview of features as implemented on the available USART interfaces.

All USART interfaces can be served by the DMA controller.

Table 7. STM32F70x0 USART implementation(1)

STM32F070x6 STM32F070xB
USART modes/
features USART1
USART1 USART2 USART3 USART4
USART2

Hardware flow control for modem X X X X X

Continuous communication using

X X X X -
DMA
Multiprocessor communication X X X X X

Synchronous mode X X X X X

Smartcard mode - - - - -

Single-wire Half-duplex
X X X X X
communication
IrDA SIR ENDEC block - - - - -

LIN mode - - - - -

Dual clock domain and wakeup

- - - - -
from Stop mode
Receiver timeout interrupt X - X - -

Modbus communication - - - - -

Auto baud rate detection

4 - 4 - -
(supported modes)
Driver Enable X X X X X

USART data length 7, 8 and 9 bits

1. X = supported.

3.15 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
SPI1 and SPI2 are identical and implement the set of features shown in the following table.

22/84 DS10697 Rev 4

STM32F070CB/RB/C6/F6 Functional overview

Table 8. STM32F070CB/RB/C6/F6 SPI implementation(1)

SPI features SPI1 SPI2(2)

Hardware CRC calculation X X

Rx/Tx FIFO X X
NSS pulse mode X X
TI mode X X
1. X = supported.
2. Available on STM32F070xB only.

3.16 Universal serial bus (USB)

The STM32F070CB/RB/C6/F6 embeds a full-speed USB device peripheral compliant with
the USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.
It requires a precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use an HSE crystal oscillator).

3.17 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.

DS10697 Rev 4 23/84

23
Pinouts and pin descriptions STM32F070CB/RB/C6/F6

4 Pinouts and pin descriptions

Figure 3. TSSOP20 20-pin package pinout (top view)

BOOT0 1 20 PA14
PF0-OSC_IN 2 19 PA13
PF1-OSC_OUT 3 18 PA10 [PA12]
NRST 4 17 PA9 [PA11]
VDDA 5 16 VDD
PA0 6 15 VSS
PA1 7 14 PB1
PA2 8 13 PA7
PA3 9 12 PA6
PA4 10 11 PA5

MS36401V1

Figure 4. LQFP48 48-pin package pinout (top view)

BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PF0-OSC_IN 5 32 PA11
PF1-OSC_OUT 6 31 PA10
LQFP48
NRST 7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10

VSS
VDD
PB11

MS36400V1

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STM32F070CB/RB/C6/F6 Pinouts and pin descriptions

Figure 5. LQFP64 64-pin package pinout (top view)

BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PF0-OSC_IN 5 44 PA11
PF1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
LQFP64
PC1 9 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VDD
PB11
VDD

PB1
PB2
PB10

VSS
VSS

PC4
PC5
PB0
PA3

PA4
PA5
PA6
PA7

MS35599V1

Table 9. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and
Pin name
after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure
TC Standard 3.3 V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions

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29
Pinouts and pin descriptions STM32F070CB/RB/C6/F6

Table 10. STM32F070xB/6 pin definitions

Pin numbers Pin functions

I/O structure
Pin name

Notes
Pin
TSSOP20
LQFP64

LQFP48

(function after
type
reset) Alternate functions Additional functions

1 1 - VDD S - - Digital power supply

WKUP2,
(1)
RTC_TAMP1,
2 2 - PC13 I/O TC (2) -
RTC_TS,
RTC_OUT
(1)
PC14-OSC32_IN
3 3 - I/O TC (2) - OSC32_IN
(PC14)
PC15- (1)
4 4 - OSC32_OUT I/O TC (2) - OSC32_OUT
(PC15)
PF0-OSC_IN
5 5 2 I/O FT - I2C1_SDA(3) OSC_IN
(PF0)
PF1-OSC_OUT
6 6 3 I/O FT - I2C1_SCL(3) OSC_OUT
(PF1)
7 7 4 NRST I/O RST - Device reset input / internal reset output (active low)
8 - - PC0 I/O TTa - EVENTOUT ADC_IN10
9 - - PC1 I/O TTa - EVENTOUT ADC_IN11
10 - - PC2 I/O TTa - SPI2_MISO, EVENTOUT ADC_IN12
11 - - PC3 I/O TTa - SPI2_MOSI, EVENTOUT ADC_IN13
12 8 - VSSA S - - Analog ground
13 9 5 VDDA S - - Analog power supply

(4) USART2_CTS, RTC_ TAMP2,

14 10 6 PA0 I/O TTa
USART4_TX WKUP1, ADC_IN0,
USART2_RTS,
15 11 7 PA1 I/O TTa (4)
TIM15_CH1N, ADC_IN1
USART4_RX, EVENTOUT
16 12 8 PA2 I/O TTa (4)
USART2_TX, TIM15_CH1 ADC_IN2, WKUP4
(4)
17 13 9 PA3 I/O TTa USART2_RX, TIM15_CH2 ADC_IN3
18 - - VSS S - - Ground
19 - - VDD S - - Digital power supply
SPI1_NSS, TIM14_CH1,
20 14 10 PA4 I/O TTa - USART2_CK, ADC_IN4
USB_NOE(3)
21 15 11 PA5 I/O TTa - SPI1_SCK ADC_IN5

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STM32F070CB/RB/C6/F6 Pinouts and pin descriptions

Table 10. STM32F070xB/6 pin definitions (continued)

Pin numbers Pin functions

I/O structure
Pin name

Notes
TSSOP20 Pin
LQFP64

LQFP48

(function after
type
reset) Alternate functions Additional functions

SPI1_MISO, TIM3_CH1,
(4) TIM1_BKIN,
22 16 12 PA6 I/O TTa ADC_IN6
TIM16_CH1, EVENTOUT,
USART3_CTS
SPI1_MOSI, TIM3_CH2,
TIM14_CH1,
23 17 13 PA7 I/O TTa - ADC_IN7
TIM1_CH1N, TIM17_CH1,
EVENTOUT
(4)
24 - - PC4 I/O TTa EVENTOUT, USART3_TX ADC_IN14
(4)
25 - - PC5 I/O TTa USART3_RX ADC_IN15, WKUP5
TIM3_CH3, TIM1_CH2N,
26 18 - PB0 I/O TTa (4)
EVENTOUT, ADC_IN8
USART3_CK
TIM3_CH4,
27 19 14 PB1 I/O TTa (4) USART3_RTS, ADC_IN9
TIM14_CH1, TIM1_CH3N
28 20 - PB2 I/O FT - - -

(4) I2C2_SCL, SPI2_SCK,

29 21 - PB10 I/O FT -
USART3_TX

(4) USART3_RX,
30 22 - PB11 I/O FT -
EVENTOUT, I2C2_SDA
31 23 15 VSS S - - Ground
32 24 16 VDD S - - Digital power supply
TIM1_BKIN, TIM15_BKIN,
33 25 - PB12 I/O FT (4)
SPI2_NSS, EVENTOUT, -
USART3_CK
SPI2_SCK, I2C2_SCL,
34 26 - PB13 I/O FTf (4)
TIM1_CH1N, -
USART3_CTS
SPI2_MISO, I2C2_SDA,
35 27 - PB14 I/O FTf (4)
TIM1_CH2N, TIM15_CH1, -
USART3_RTS
SPI2_MOSI, TIM1_CH3N,
(4) WKUP7,
36 28 - PB15 I/O FT TIM15_CH1N,
RTC_REFIN
TIM15_CH2
37 - - PC6 I/O FT - TIM3_CH1 -
38 - - PC7 I/O FT - TIM3_CH2 -
39 - - PC8 I/O FT - TIM3_CH3 -

DS10697 Rev 4 27/84

29
Pinouts and pin descriptions STM32F070CB/RB/C6/F6

Table 10. STM32F070xB/6 pin definitions (continued)

Pin numbers Pin functions

I/O structure
Pin name

Notes
TSSOP20 Pin
LQFP64

LQFP48

(function after
type
reset) Alternate functions Additional functions

40 - - PC9 I/O FT - TIM3_CH4 -

USART1_CK, TIM1_CH1,
41 29 - PA8 I/O FT - -
EVENTOUT, MCO
USART1_TX, TIM1_CH2,
(4)
42 30 17 PA9 I/O FT TIM15_BKIN, -
I2C1_SCL(3)
USART1_RX, TIM1_CH3,
43 31 18 PA10 I/O FT - TIM17_BKIN, -
I2C1_SDA(3)
USART1_CTS,
44 32 17(5) PA11 I/O FT - USB_DM
TIM1_CH4, EVENTOUT
USART1_RTS,
45 33 18(5) PA12 I/O FT - USB_DP
TIM1_ETR, EVENTOUT

(6) IR_OUT, SWDIO,

46 34 19 PA13 I/O FT -
USB_NOE
47 35 - VSS S - - Ground
48 36 - VDD S - - Digital power supply
49 37 20 PA14 I/O FT - USART2_TX, SWCLK -
SPI1_NSS, USART2_RX,
50 38 - PA15 I/O FT (4)
USART4_RTS, -
EVENTOUT

(4) USART3_TX,
51 - - PC10 I/O FT -
USART4_TX

(4) USART3_RX,
52 - - PC11 I/O FT -
USART4_RX

(4) USART3_CK,
53 - - PC12 I/O FT -
USART4_CK

(4) TIM3_ETR,
54 - - PD2 I/O FT -
USART3_RTS
55 39 - PB3 I/O FT - SPI1_SCK, EVENTOUT -
SPI1_MISO, TIM17_BKIN,
56 40 - PB4 I/O FT - -
TIM3_CH1, EVENTOUT
SPI1_MOSI, I2C1_SMBA,
(4)
57 41 - PB5 I/O FT TIM16_BKIN, WKUP6
TIM3_CH2
I2C1_SCL, USART1_TX,
58 42 - PB6 I/O FTf - -
TIM16_CH1N

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STM32F070CB/RB/C6/F6 Pinouts and pin descriptions

Table 10. STM32F070xB/6 pin definitions (continued)

Pin numbers Pin functions

I/O structure
Pin name

Notes
TSSOP20 Pin
LQFP64

LQFP48

(function after
type
reset) Alternate functions Additional functions

I2C1_SDA, USART1_RX,
(4)
59 43 - PB7 I/O FTf USART4_CTS, -
TIM17_CH1N
60 44 1 BOOT0 I B - Boot memory selection
61 45 - PB8 I/O FTf - I2C1_SCL, TIM16_CH1 -
SPI2_NSS, I2C1_SDA,
(4)
62 46 - PB9 I/O FTf IR_OUT, -
TIM17_CH1, EVENTOUT
63 47 - VSS S - - Ground
64 48 - VDD S - - Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the reference manual.
3. Available on STM32F070C6/F6 devices only.
4. TIM15, I2C2, WKUP4, WKUP5, WKUP6, WKUP7, SPI2, USART3 and USART4 are available on STM32F070CB/RB
devices only.
5. On STM32F070C6/F6 devices, pin pair PA11/12 can be remapped instead of pin pair PA9/10 using SYSCFG_CFGR1
register.
6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO
pin and the internal pull-down on the SWCLK pin are activated.

DS10697 Rev 4 29/84

29
30/84
Table 11. Alternate functions selected through GPIOA_AFR registers for port A
Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
name

PA0 - USART2_CTS - - USART4_TX(1) - - -

PA1 EVENTOUT USART2_RTS - - USART4_RX(1) TIM15_CH1N (1)
- -
(1)
PA2 TIM15_CH1 USART2_TX - - - - - -
PA3 TIM15_CH2(1) USART2_RX - - - - - -
PA4 SPI1_NSS USART2_CK USB_NOE(2) - TIM14_CH1 - - -
PA5 SPI1_SCK - - - - - - -
(1)
PA6 SPI1_MISO TIM3_CH1 TIM1_BKIN - USART3_CTS TIM16_CH1 EVENTOUT -
PA7 SPI1_MOSI TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 EVENTOUT -
DS10697 Rev 4

PA8 MCO USART1_CK TIM1_CH1 EVENTOUT - - - -

(1) I2C1_SCL (2)
PA9 TIM15_BKIN USART1_TX TIM1_CH2 - - - -
PA10 TIM17_BKIN USART1_RX TIM1_CH3 - I2C1_SDA (2) - - -
PA11 EVENTOUT USART1_CTS TIM1_CH4 - - - - -
PA12 EVENTOUT USART1_RTS TIM1_ETR - - - - -
PA13 SWDIO IR_OUT USB_NOE - - - - -
PA14 SWCLK USART2_TX - - - - - -
PA15 SPI1_NSS USART2_RX - EVENTOUT USART4_RTS(1) - - -
1. Available on STM32F070CB/RB devices only.

STM32F070CB/RB/C6/F6
2. Available on STM32F070C6/F6 devices only.
 Table 12. Alternate functions selected through GPIOB_AFR registers for port B

STM32F070CB/RB/C6/F6
Pin name AF0 AF1 AF2 AF3 AF4 AF5

PB0 EVENTOUT TIM3_CH3 TIM1_CH2N - USART3_CK(1) -

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - USART3_RTS(1) -
PB2 - - - - - -
PB3 SPI1_SCK EVENTOUT - - - -
PB4 SPI1_MISO TIM3_CH1 EVENTOUT - - TIM17_BKIN
PB5 SPI1_MOSI TIM3_CH2 TIM16_BKIN I2C1_SMBA - -
PB6 USART1_TX I2C1_SCL TIM16_CH1N - - -
(1)
PB7 USART1_RX I2C1_SDA TIM17_CH1N - USART4_CTS -
PB8 - I2C1_SCL TIM16_CH1 - - -
PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT - SPI2_NSS(1)
DS10697 Rev 4

PB10 - I2C2_SCL(1) - - USART3_TX(1) SPI2_SCK(1)

PB11 EVENTOUT I2C2_SDA(1) - - USART3_RX(1) -
PB12 SPI2_NSS(1) EVENTOUT TIM1_BKIN - USART3_CK(1) TIM15_BKIN(1)
PB13 SPI2_SCK(1) - TIM1_CH1N - USART3_CTS(1) I2C2_SCL(1)
PB14 SPI2_MISO(1) TIM15_CH1 TIM1_CH2N - USART3_RTS(1) I2C2_SDA(1)
PB15 SPI2_MOSI(1) TIM15_CH2 TIM1_CH3N TIM15_CH1N(1) - -
1. Available on STM32F070xB devices only.
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 STM32F070CB/RB/C6/F6

Table 13. Alternate functions selected through GPIOC_AFR registers for port C
Pin name AF0(1) AF1(1)

PC0 EVENTOUT(1) -
PC1 EVENTOUT(1) -
(1)
PC2 EVENTOUT SPI2_MISO(1)
PC3 EVENTOUT(1) SPI2_MOSI(1)
PC4 EVENTOUT(1) USART3_TX(1)
PC5 - USART3_RX(1)
PC6 TIM3_CH1(1) -
PC7 TIM3_CH2(1) -
(1)
PC8 TIM3_CH3 -
PC9 TIM3_CH4(1) -
(1)
PC10 USART4_TX USART3_TX(1)
PC11 USART4_RX(1) USART3_RX(1)
PC12 USART4_CK(1) USART3_CK(1)
PC13 - -
PC14 - -
PC15 - -
1. Available on STM32F070xB devices only.

Table 14. Alternate functions selected through GPIOD_AFR registers for port D
Pin name AF0(1) AF1(1)

PD2 TIM3_ETR(1) -
1. Available on STM32F070xB devices only.

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STM32F070CB/RB/C6/F6 Memory mapping

5 Memory mapping

Figure 6. STM32F070CB/RB/C6/F6 memory map

0xFFFF FFFF

0x4800 17FF
Reserved
AHB2
7
0x4800 0000
0xE010 0000
Cortex-M0 internal
0xE000 0000 peripherals

Reserved
6 Reserved

0xC000 0000

0x4002 43FF
AHB1
5 Reserved
0x4002 0000

Reserved
0xA000 0000
0x4001 8000

4 Reserved 0x1FFF FFFF APB

Reserved
0x1FFF FC00 0x4001 0000
Option Bytes
0x8000 0000 0x1FFF F800

Reserved
System memory
0x4000 8000
3 Reserved
0x1FFF Cx00(1)
APB

0x6000 0000
0x4000 0000

Reserved
2 Reserved

0x4000 0000 Peripherals

0x0802 0000
Reserved
1
Flash memory

0x2000 0000 SRAM

0x0800 0000

Reserved
0 CODE
0x0002 0000

Flash, system
memory or SRAM,
0x0000 0000
depending on BOOT
configuration
0x0000 0000

MSv39021V2

1. The start address of the system memory is 0x1FFF C800 on STM32F070xB devices and 0x1FFF C400 on STM32F070x6
devices.

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35
Memory mapping STM32F070CB/RB/C6/F6

Table 15. STM32F070CB/RB/C6/F6 peripheral register boundary addresses

Bus Boundary address Size Peripheral

- 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 1000 - 0x4800 13FF 1 KB Reserved
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
AHB2
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
- 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
0x4002 3400 - 0x4002 43FF 4 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2400 - 0x4002 2FFF 3 KB Reserved
0x4002 2000 - 0x4002 23FF 1 KB FLASH Interface
AHB1
0x4002 1400 - 0x4002 1FFF 3 KB Reserved
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 0FFF 3 KB Reserved
0x4002 0000 - 0x4002 03FF 1 KB DMA
- 0x4001 8000 - 0x4001 FFFF 32 KB Reserved
0x4001 5C00 - 0x4001 7FFF 9 KB Reserved
0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
APB
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB Reserved
0x4001 2400 - 0x4001 27FF 1 KB ADC
0x4001 0800 - 0x4001 23FF 7 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG
- 0x4000 8000 - 0x4000 FFFF 32 KB Reserved

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STM32F070CB/RB/C6/F6 Memory mapping

Table 15. STM32F070CB/RB/C6/F6 peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral

0x4000 7400 - 0x4000 7FFF 3 KB Reserved

0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB Reserved
0x4000 6400 - 0x4000 67FF 2 KB Reserved
0x4000 6000 - 0x4000 63FF 1 KB USB RAM
0x4000 5800 - 0x4000 5BFF 1 KB I2C2(1)
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 5000 - 0x4000 53FF 3 KB Reserved
0x4000 4C00 - 0x4000 4FFF 1 KB USART4(1)
0x4000 4800 - 0x4000 4BFF 1 KB USART3(1)
0x4000 4400 - 0x4000 47FF 1 KB USART2
0x4000 3C00 - 0x4000 43FF 2 KB Reserved
APB 0x4000 3800 - 0x4000 3BFF 1 KB SPI2(1)
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 2400 - 0x4000 27FF 1 KB Reserved
0x4000 2000 - 0x4000 23FF 1 KB TIM14
0x4000 1800 - 0x4000 1FFF 2 KB Reserved
0x4000 1400 - 0x4000 17FF 1 KB TIM7
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0800 - 0x4000 0FFF 2 KB Reserved
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB Reserved
1. Available on STM32F070CB/RB devices only.

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6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.

Figure 7. Pin loading conditions Figure 8. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V1 MS19211V1

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6.1.6 Power supply scheme

Figure 9. Power supply scheme

LSE, RTC,
Wake-up logic
Power switch

VDD VCORE
5 x VDD
Regulator

VDDIO1
OUT

Level shifter
Kernel logic
5 x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)

4 x VSS

VDDA
VDDA

10 nF VREF+ Analog:
+1 μF ADC
VREF- (RCs, PLL, …)

VSSA

MSv39026V1

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.

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6.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

IDD
VDD

IDDA
VDDA

MS32142V2

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics,
Table 17: Current characteristics and Table 18: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Table 16. Voltage characteristics(1)

Symbol Ratings Min Max Unit

VDD–VSS External main supply voltage -0.3 4.0 V

VDDA–VSS External analog supply voltage -0.3 4.0 V
VDD–VDDA Allowed voltage difference for VDD > VDDA - 0.4 V
Input voltage on FT and FTf pins VSS −0.3 VDDIOx + 4.0 (3) V
Input voltage on TTa pins VSS −0.3 4.0 V
VIN(2)
(3)
BOOT0 0 VDDIOx + 4.0 V
Input voltage on any other pin VSS − 0.3 4.0 V
|ΔVDDx| Variations between different VDD power pins - 50 mV
Variations between all the different ground
|VSSx − VSS| - 50 mV
pins
Electrostatic discharge voltage see Section 6.3.12: Electrical
VESD(HBM) -
(human body model) sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 17: Current characteristics for the maximum
allowed injected current values.
3. VDDIOx is internally connected with VDD pin.

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Table 17. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD Total current into sum of all VDD power lines (source)(1) 120
(1)
ΣIVSS Total current out of sum of all VSS ground lines (sink) -120
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100
Output current sunk by any I/O and control pin 25
IIO(PIN)
Output current source by any I/O and control pin -25
(2) mA
Total output current sunk by sum of all I/Os and control pins 80
ΣIIO(PIN)
Total output current sourced by sum of all I/Os and control pins(2) -80
Injected current on FT and FTf pins -5/+0(4)
IINJ(PIN)(3) Injected current on TC and RST pin ±5
(5)
Injected current on TTa pins ±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 16: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 50: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).

Table 18. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

6.3 Operating conditions

6.3.1 General operating conditions

Table 19. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 48

MHz
fPCLK Internal APB clock frequency - 0 48
VDD Standard operating voltage - 2.4 3.6 V

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Table 19. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Must have a potential equal

VDDA Analog operating voltage 2.4 3.6 V
to or higher than VDD
TC and RST I/O -0.3 VDDIOx+0.3
TTa I/O -0.3 VDDA+0.3(2)
VIN I/O input voltage V
FT and FTf I/O -0.3 5.5(2)
BOOT0 0 5.5
LQFP64 - 455

Power dissipation at TA = 85 °C LQFP48 - 364

PD mW
for suffix 6 (1) TSSOP20 - 263

Ambient temperature for the Maximum power dissipation -40 85

TA °C
suffix 6 version Low power dissipation (2)
-40 105
TJ Junction temperature range Suffix 6 version -40 105 °C
1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5:
Thermal characteristics).

6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 20 are derived from tests performed under the ambient
temperature condition summarized in Table 19.

Table 20. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0 ∞

tVDD -
VDD fall time rate 20 ∞
µs/V
VDDA rise time rate 0 ∞
tVDDA -
VDDA fall time rate 20 ∞

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 21 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 19: General operating
conditions.

Table 21. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Power on/power down Falling edge(2) 1.80 1.88 1.96(3) V

VPOR/PDR(1)
reset threshold Rising edge 1.84(3) 1.92 2.00 V

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Table 21. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

VPDRhyst PDR hysteresis - - 40 - mV

tRSTTEMPO(4) Reset temporization - 1.50 2.50 4.50 ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.

6.3.4 Embedded reference voltage

The parameters given in Table 22 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 19: General operating
conditions.

Table 22. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

Internal reference
VREFINT -40°C < TA < +85°C 1.2 1.23 1.25 V
voltage
ADC_IN17 buffer startup
tSTART - - - 10(1) µs
time
ADC sampling time when
tS_vrefint reading the internal - 4 (1) - - µs
reference voltage
Internal reference
ΔVREFINT voltage spread over the VDDA = 3 V - - 10(1) mV
temperature range

TCoeff Temperature coefficient - -100(1) - 100(1) ppm/°C

1. Guaranteed by design, not tested in production.

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.

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Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted to the fHCLK frequency:
– 0 wait state and Prefetch OFF from 0 to 24 MHz
– 1 wait state and Prefetch ON above 24 MHz
• When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 23 to Table 25 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 19: General
operating conditions.

Table 23. Typical and maximum current consumption from VDD supply at VDD = 3.6 V
All peripherals enabled
Symbol

Parameter Conditions fHCLK Max @ TA(1) Unit

Typ
85 °C

Supply current in 48 MHz 24.1 27.6

Run mode, code HSI or HSE clock, PLL on
IDD 24 MHz 12.4 14.4 mA
executing from flash
memory HSI or HSE clock, PLL off 8 MHz 4.52 5.28
48 MHz 23.1 25.0
Supply current in HSI or HSE clock, PLL on
IDD Run mode, code 24 MHz 11.5 13.6 mA
executing from RAM
HSI or HSE clock, PLL off 8 MHz 4.34 5.03
Supply current in 48 MHz 15.0 17.3
Sleep mode, code HSI or HSE clock, PLL on
IDD 24 MHz 7.53 8.87 mA
executing from flash
memory or RAM HSI or HSE clock, PLL off 8 MHz 2.95 3.41
1. Data based on characterization results, not tested in production unless otherwise specified.

Table 24. Typical and maximum current consumption from the VDDA supply
VDDA = 3.6 V

Symbol Parameter Conditions(1) fHCLK Max @ TA Unit

Typ
85 °C

HSE bypass, PLL on 48 MHz 165 196

Supply current in
8 MHz 3.6 5.2
Run or Sleep mode, HSE bypass, PLL off
IDDA code executing from 1 MHz 3.6 5.2 µA
flash memory or
HSI clock, PLL on 48 MHz 245 279
RAM
HSI clock, PLL off 8 MHz 83.4 95.3

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1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from
the frequency.

Table 25. Typical and maximum consumption in Stop and Standby modes
Typ @VDD
Max(1)
(VDD = VDDA)
Symbol Parameter Conditions Unit
3.6 V TA = 85 °C

Regulator in run mode, all oscillators OFF 15.9 49

Supply current in
Stop mode
IDD Regulator in low-power mode, all oscillators OFF 3.7 33

Supply current in
LSI ON and IWDG ON 1.5 -
Standby mode
Regulator in run or low-
Supply current in
power mode, all 2.8 3.6
Stop mode
oscillators OFF
VDDA monitoring ON
LSI ON and IWDG ON 3.5 - µA
Supply current in
Standby mode
LSI OFF and IWDG OFF 2.6 3.6
IDDA
Regulator in run or low-
Supply current in
power mode, all 1.5 -
Stop mode
oscillators OFF
VDDA monitoring OFF
LSI ON and IWDG ON 2.2 -
Supply current in
Standby mode
LSI OFF and IWDG OFF 1.4 -

1. Data based on characterization results, not tested in production unless otherwise specified.

Typical current consumption

The MCU is placed under the following conditions:
• VDD = VDDA = 3.3 V
• All I/O pins are in analog input configuration
• The flash memory access time is adjusted to fHCLK frequency:
– 0 wait state and Prefetch OFF from 0 to 24 MHz
– 1 wait state and Prefetch ON above 24 MHz
• When the peripherals are enabled, fPCLK = fHCLK
• PLL is used for frequencies greater than 8 MHz
• AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively

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Table 26. Typical current consumption in Run mode, code with data processing
running from flash memory
Typ
Symbol Parameter Conditions fHCLK Unit
Peripherals Peripherals
enabled disabled

Supply current in Run Running from 48 MHz 23.5 13.5

IDD mode from VDD HSE crystal mA
supply 8 MHz 4.8 3.1
clock 8 MHz,
Supply current in Run code executing 48 MHz 163.3 163.3
IDDA mode from VDDA from flash µA
supply memory 8 MHz 2.5 2.5

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 44: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously, the I/Os
used by an application also contribute to the current consumption. When an I/O pin
switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal or external) connected to the pin:

I SW = V DDIOx × f SW × C

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where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

Table 27. Switching output I/O current consumption

I/O toggling
Symbol Parameter Conditions(1) Typ Unit
frequency (fSW)

4 MHz 0.18

VDDIOx = 3.3 V 8 MHz 0.37

CEXT = 0 pF 16 MHz 0.76
C = CINT + CEXT+ CS 24 MHz 1.39
48 MHz 2.188
4 MHz 0.49
I/O current
ISW VDDIOx = 3.3 V mA
consumption 8 MHz 0.94
CEXT = 22 pF
16 MHz 2.38
C = CINT + CEXT+ CS
24 MHz 3.99
VDDIOx = 3.3 V 4 MHz 0.81
CEXT = 47 pF 8 MHz 1.7
C = CINT + CEXT+ CS
C = Cint 16 MHz 3.67

1. CS = 7 pF (estimated value).

6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 28 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 19: General operating conditions.

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Table 28. Low-power mode wakeup timings

Typ @VDD =
VDDA
Symbol Parameter Conditions Max Unit
= 3.3 V

tWUSTOP Wakeup from Stop mode Regulator in run mode 2.8 5

tWUSTANDBY Wakeup from Standby mode - 51 -
µs
4 SYSCLK
tWUSLEEP Wakeup from Sleep mode - -
cycles

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 11: High-speed external clock
source AC timing diagram.

Table 29. High-speed external user clock characteristics

Symbol Parameter(1) Min Typ Max Unit

fHSE_ext User external clock source frequency - 8 32 MHz

VHSEH OSC_IN input pin high level voltage 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(HSEH)
OSC_IN high or low time 15 - -
tw(HSEL)
ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
1. Guaranteed by design, not tested in production.

Figure 11. High-speed external clock source AC timing diagram

tw(HSEH)

VHSEH
90%
10%
VHSEL

tr(HSE) t
tf(HSE) tw(HSEL)
THSE

MS19214V2

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 12.

Table 30. Low-speed external user clock characteristics

Symbol Parameter(1) Min Typ Max Unit

fLSE_ext User external clock source frequency - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time 450 - -
tw(LSEL)
ns
tr(LSE)
OSC32_IN rise or fall time - - 50
tf(LSE)
1. Guaranteed by design, not tested in production.

Figure 12. Low-speed external clock source AC timing diagram

tw(LSEH)

VLSEH
90%
10%
VLSEL

tr(LSE) t
tf(LSE) tw(LSEL)
TLSE

MS19215V2

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 31. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 31. HSE oscillator characteristics

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit

fOSC_IN Oscillator frequency - 4 8 32 MHz

RF Feedback resistor - - 200 - kΩ

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Table 31. HSE oscillator characteristics

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
(3)
During startup - - 8.5
VDD = 3.3 V,
Rm = 45 Ω, - 0.5 -
IDD HSE current consumption CL = 10 pF@8 MHz mA
VDD = 3.3 V,
Rm = 30 Ω, - 1.5 -
CL = 20 pF@32 MHz
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 13. Typical application with an 8 MHz crystal

Resonator with integrated

capacitors
CL1

OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain

REXT (1) OSC_OUT

CL2

MS19876V1

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results

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obtained with typical external components specified in Table 32. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz)

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit

low drive capability - 0.5 0.9

LSE current medium-low drive capability - - 1

IDD µA
consumption medium-high drive capability - - 1.3
high drive capability - - 1.6
low drive capability 5 - -

Oscillator medium-low drive capability 8 - -

gm µA/V
transconductance medium-high drive capability 15 - -
high drive capability 25 - -
tSU(LSE) (3)
Startup time VDDIOx is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 14. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

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6.3.8 Internal clock source characteristics

The parameters given in Table 33 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19: General operating
conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI) RC oscillator

Table 33. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - - 8 - MHz

TRIM HSI user trimming step - - - 1(2) %
DuCyHSI Duty cycle - 45(2) - 55(2) %

Accuracy of the HSI oscillator TA = -40 to 85°C - ±5 - %

ACCHSI
(factory calibrated) TA = 25°C - ±1(3) - %
tSU(HSI) HSI oscillator startup time - 1(2) - 2(2) µs
HSI oscillator power
IDDA(HSI) - - 80 - µA
consumption
1. VDDA = 3.3 V, TA = -40 to 85°C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. With user calibration.

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 34. HSI14 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI14 Frequency - - 14 - MHz

(2)
TRIM HSI14 user-trimming step - - - 1 %
DuCy(HSI14) Duty cycle - 45(2) - 55(2) %
Accuracy of the HSI14
ACCHSI14 TA = –40 to 85 °C - ±5 - %
oscillator (factory calibrated)
tsu(HSI14) HSI14 oscillator startup time - 1(2) - 2(2) µs
HSI14 oscillator power
IDDA(HSI14) - - 100 - µA
consumption
1. VDDA = 3.3 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.

Low-speed internal (LSI) RC oscillator

Table 35. LSI oscillator characteristics(1)

Symbol Parameter Min Typ Max Unit

fLSI Frequency 30 40 50 kHz

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Table 35. LSI oscillator characteristics(1)

Symbol Parameter Min Typ Max Unit

tsu(LSI)(2) LSI oscillator startup time - - 85 µs

IDDA(LSI)(2) LSI oscillator power consumption - 0.75 - µA
1. VDDA = 3.3 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.

6.3.9 PLL characteristics

The parameters given in Table 36 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19: General operating
conditions.

Table 36. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max

PLL input clock(1) 1(2) 8.0 24(2) MHz

fPLL_IN
PLL input clock duty cycle 40(2) - 60(2) %
fPLL_OUT PLL multiplier output clock 16(2) - 48 MHz
tLOCK PLL lock time - - 200(2) µs
JitterPLL Cycle-to-cycle jitter - - 300(2) ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.

6.3.10 Memory characteristics

Flash memory
The characteristics are given at TA = -40 to 85 °C unless otherwise specified.

Table 37. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

tprog 16-bit programming time TA = -40 to +85 °C - 53.5 - µs

tERASE Page erase time (2) TA = -40 to +85 °C - 30 - ms
tME Mass erase time TA = -40 to +85 °C - 30 - ms
Write mode - - 10 mA
IDD Supply current
Erase mode - - 12 mA
Vprog Programming voltage - 2.4 - 3.6 V
1. Guaranteed by design, not tested in production.
2. Page size is 1KB for STM32F070x6 devices and 2KB for STM32F070xB devices.

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Table 38. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = -40 to +85 °C 1 kcycle

(2)
tRET Data retention 1 kcycle at TA = 85 °C 20 Years
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 39. They are based on the EMS levels and classes
defined in application note AN1709.

Table 39. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3V, LQFP48, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 48 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3V, LQFP48, TA = +25°C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 48 MHz, 4B
pins to induce a functional disturbance conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations

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The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 40. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8/48 MHz

0.1 to 30 MHz -3
VDD = 3.6 V, TA = 25 °C,
LQFP100 package 30 to 130 MHz 23 dBµV
SEMI Peak level
compliant with 130 MHz to 1 GHz 17
IEC 61967-2
EMI Level 4 -

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

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Table 41. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)

Electrostatic discharge voltage TA = +25 °C, conforming

VESD(HBM) All 2 2000 V
(human body model) to JESD22-A114
Electrostatic discharge voltage TA = +25 °C, conforming
VESD(CDM) All C4 500 V
(charge device model) to ANSI/ESD STM5.3.1
1. Data based on characterization results, not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 42. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II level A

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 43.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.

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Table 43. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0 and PF1 pins -0 NA

Injected current on PA9, PB3, PB13, PF11 pins with induced
-5 NA
leakage current on adjacent pins less than 50 µA
Injected current on PA11 and PA12 pins with induced
-5 NA
leakage current on adjacent pins less than -1 mA
IINJ mA
Injected current on all other FT and FTf pins -5 NA
Injected current on PB0 and PB1 pins -5 NA
Injected current on PC0 pin -0 +5
Injected current on all other TTa, TC and RST pins -5 +5

6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 19: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Table 44. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

TC and TTa I/O - - 0.3 VDDIOx+0.07(1)

FT and FTf I/O - - 0.475 VDDIOx–0.2(1)
Low level input
VIL BOOT0 - - 0.3 VDDIOx–0.3(1) V
voltage
All I/Os except
- - 0.3 VDDIOx
BOOT0 pin
TC and TTa I/O 0.445 VDDIOx+0.398(1) - -
FT and FTf I/O 0.5 VDDIOx +0.2(1) - -
High level input
VIH BOOT0 0.2 VDDIOx+0.95 (1)
- - V
voltage
All I/Os except
0.7 VDDIOx - -
BOOT0 pin
TC and TTa I/O - 200(1) -
Schmitt trigger (1)
Vhys FT and FTf I/O - 100 - mV
hysteresis
(1)
BOOT0 - 300 -

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Table 44. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

TC, FT and FTf I/O

TTa in digital mode - - ± 0.1
VSS ≤ VIN ≤ VDDIOx
TTa in digital mode
Input leakage - - 1
Ilkg VDDIOx ≤ VIN ≤ VDDA µA
current(2)
TTa in analog mode
- - ± 0.2
VSS ≤ VIN ≤ VDDA
FT and FTf I/O (3)
- - 10
VDDIOx ≤ VIN ≤ 5 V
Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 kΩ
(4)

Weak pull-down
RPD equivalent VIN = VDDIOx 25 40 55 kΩ
resistor(4)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 43:
I/O current injection susceptibility.
3. To sustain a voltage higher than VDDIOx + 0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 15 for standard I/Os, and in Figure 16 for
5 V tolerant I/Os. The following curves are design simulation results, not tested in
production.

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Figure 15. TC and TTa I/O input characteristics

2.5
TESTED RANGE
TTL standard requirement
2 ent)
requirem
n dard
S sta
VIN (V) (CMO
1.5 V DDIOx
= 0.7
V IHmin
0.398 UNDEFINED INPUT RANGE
0.445 VDDIOx +
VIHmin =
1

0.07
3 VDDIOx +
VILmax = 0. quiremen
t) TTL standard requirement
andard re
(CMOS st
0.5 3 VDDIOx
VILmax = 0.
TESTED RANGE

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

VDDIOx (V)
MSv32130V4

Figure 16. Five volt tolerant (FT and FTf) I/O input characteristics

2.5
TESTED RANGE
TTL standard requirement
2 ent)
equ irem
nd ard r
S sta
VIN (V) (CMO
1.5 V DDIOx
= 0.7
V IHmin UNDEFINED INPUT RANGE
x+
0.2
0.5 VDDIO
1 VIHmin =
0.2
VDDIOx -
VILmax = 0.475 TTL standard requirement
t)
quiremen
andard re
(CMOS st
0.5 3 VDDIOx
VILmax = 0.
TESTED RANGE

0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

VDDIOx (V)
MSv32131V4

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 16: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 16: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 19: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).

Table 45. Output voltage characteristics(1)

Symbol Parameter Conditions Min Max Unit

VOL Output low level voltage for an I/O pin |IIO| = 8 mA - 0.4
V
VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–0.4 -
VOL(2) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
V
VOH(2) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–1.3 -
VOL(2) Output low level voltage for an I/O pin - 0.4
|IIO| = 6 mA V
VOH(2) Output high level voltage for an I/O pin VDDIOx–0.4 -
|IIO| = 20 mA
- 0.4 V
VOLFm+(2)
Output low level voltage for an FTf I/O pin in VDDIOx ≥ 2.7 V
Fm+ mode
|IIO| = 10 mA - 0.4 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 16:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. Data based on characterization results. Not tested in production.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 17 and
Table 46, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 19: General
operating conditions.

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Table 46. I/O AC characteristics(1)(2)

OSPEEDRy
Symbol Parameter Conditions Min Max Unit
[1:0] value(1)

fmax(IO)out Maximum frequency(3) - 2 MHz

x0 tf(IO)out Output fall time CL = 50 pF, VDDIOx ≥ 2.4 V - 125
ns
tr(IO)out Output rise time - 125
fmax(IO)out Maximum frequency(3) - 10 MHz
01 tf(IO)out Output fall time CL = 50 pF, VDDIOx ≥ 2.4 V - 25
ns
tr(IO)out Output rise time - 25
CL = 30 pF, VDDIOx ≥ 2.7 V - 50
fmax(IO)out Maximum frequency(3) CL = 50 pF, VDDIOx ≥ 2.7 V - 30 MHz
CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V - 20
CL = 30 pF, VDDIOx ≥ 2.7 V - 5
11 tf(IO)out Output fall time CL = 50 pF, VDDIOx ≥ 2.7 V - 8
CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V - 12
ns
CL = 30 pF, VDDIOx ≥ 2.7 V - 5
tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2.7 V - 8
CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V - 12
fmax(IO)out Maximum frequency(3) - 2 MHz
Fm+
configuration tf(IO)out Output fall time CL = 50 pF, VDDIOx ≥ 2.4 V - 12
(4) ns
tr(IO)out Output rise time - 34
Pulse width of external
- tEXTIpw signals detected by the - 10 - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0360 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 17.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0360
for a detailed description of Fm+ I/O configuration.

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Figure 17. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

0D[LPXPIUHTXHQF\LVDFKLHYHGLI WW 2
r f ” 3 T and if the duty cycle is (45-55%)
when loaded by CL (see the table I/O AC characteristics definition)
MS32132V3

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 19: General operating conditions.

Table 47. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1)

V
VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) - -
NRST Schmitt trigger voltage
Vhys(NRST) - - 200 - mV
hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 40 55 kΩ
resistor(2)
VF(NRST) NRST input filtered pulse - - - 100(1) ns
2.7 < VDD < 3.6 300(3) - -
VNF(NRST) NRST input not filtered pulse ns
2.4 < VDD < 3.6 500(3) - -
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.

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Figure 18. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF(3)

MS19878V4

1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 47: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

6.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 48 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 19: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 48. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA - 2.4 - 3.6 V
ADC ON
Current consumption of
IDDA (ADC) VDD = VDDA = 3.3 V - 0.9 - mA
the ADC(1)

fADC ADC clock frequency - 0.6 - 14 MHz

fS(2) Sampling rate - 0.05 - 1 MHz

fADC = 14 MHz - - 823 kHz

External trigger
fTRIG(2)
frequency
- - - 17 1/fADC

VAIN Conversion voltage range - 0 - VDDA V

See Equation 1 and

RAIN(2) External input impedance - - 50 kΩ
Table 49 for details
Sampling switch
RADC(2) - - - 1 kΩ
resistance
Internal sample and hold
CADC(2) - - - 8 pF
capacitor

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Table 48. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

fADC = 14 MHz 5.9 µs

tCAL(2)(3) Calibration time
- 83 1/fADC

1.5 ADC 1.5 ADC

ADC clock = HSI14 cycles + 2 - cycles + 3 -
fPCLK cycles fPCLK cycles
ADC_DR register write
WLATENCY(2)(4) fPCLK
latency ADC clock = PCLK/2 - 4.5 -
cycle
fPCLK
ADC clock = PCLK/4 - 8.5 -
cycle
fADC = fPCLK/2 =
0.196 µs
14 MHz

fADC = fPCLK/2 5.5 1/fPCLK

Trigger conversion fADC = fPCLK/4 =
tlatr(2) 0.219 µs
latency 12 MHz

fADC = fPCLK/4 10.5 1/fPCLK

fADC = fHSI14 = 14 MHz 0.188 - 0.259 µs

ADC jitter on trigger

JitterADC fADC = fHSI14 - 1 - 1/fHSI14
conversion

fADC = 14 MHz 0.107 - 17.1 µs

tS(2) Sampling time
- 1.5 - 239.5 1/fADC

tSTAB(2) Stabilization time - 14 1/fADC

fADC = 14 MHz,
1 - 18 µs
Total conversion time 12-bit resolution
tCONV(2)
(including sampling time) 14 to 252 (tS for sampling +12.5 for
12-bit resolution 1/fADC
successive approximation)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

Equation 1: RAIN max formula

TS
R AIN < ---------------------------------------------------------------
N+2
- – R ADC
f ADC × C ADC × ln ( 2 )

The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

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Table 49. RAIN max for fADC = 14 MHz

Ts (cycles) tS (µs) RAIN max (kΩ)(1)

1.5 0.11 0.4

7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
1. Guaranteed by design, not tested in production.

Table 50. ADC accuracy(1)(2)(3)

Symbol Parameter Test conditions Typ Max(4) Unit

ET Total unadjusted error ±3.3 ±4

EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8
fADC = 14 MHz, RAIN < 10 kΩ
EG Gain error ±2.8 ±3 LSB
VDDA = 2.7 V to 3.6 V
ED Differential linearity error TA = −40 to 85 °C ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.

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Figure 19. ADC accuracy characteristics

VSSA EG (1) Example of an actual transfer curve

4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET EO = offset error: maximum deviation
(3)
7 between the first actual transition and
(1)
6 the first ideal one.
EG = gain error: deviation between the last
5
EO EL
ideal transition and the last actual one.
4 ED = differential linearity error: maximum
3 deviation between actual steps and the ideal ones.
ED
EL = integral linearity error: maximum deviation
2
between any actual transition and the end point
1 LSB IDEAL
1 correlation line.

0
1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA

MS19880V2

Figure 20. Typical connection diagram using the ADC

V DDA

Sample and hold ADC

VT con ver ter

R AIN (1) R ADC

AINx 12-bit
con ver ter
IL ±1 μA
C par asitic VT
VAIN
CADC

MS33900V1

1. Refer to Table 48: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme.
The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as
possible to the chip.

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6.3.17 Temperature sensor characteristics

Table 51. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope 4.0 4.3 4.6 mV/°C
(2)
V30 Voltage at 30 °C (± 5 °C) 1.34 1.43 1.52 V
tSTART(1) ADC_IN16 buffer startup time - - 10 µs
ADC sampling time when reading the
tS_temp(1) 4 - - µs
temperature
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 2:
Temperature sensor calibration values.

6.3.18 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 52. TIMx characteristics

Symbol Parameter Conditions Min Typ Max Unit

- - 1 - tTIMxCLK
tres(TIM) Timer resolution
fTIMxCLK = 48 MHz - 20.8 - ns
Timer external clock - - fTIMxCLK/2 - MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 48 MHz - 24 - MHz

16-bit timer maximum - - 216 - tTIMxCLK

period fTIMxCLK = 48 MHz - 1365 - µs
tMAX_COUNT
32-bit timer maximum - - 232 - tTIMxCLK
period fTIMxCLK = 48 MHz - 89.48 - s

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Table 53. IWDG min/max timeout period at 40 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF

/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Table 54. WWDG min/max timeout value at 48 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906

6.3.19 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:

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Table 55. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that

tAF 50(2) 260(3) ns
are suppressed by the analog filter
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered

SPI characteristics
Unless otherwise specified, the parameters given in Table 56 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 19: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 56. SPI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fSCK Master mode - 18

SPI clock frequency MHz
1/tc(SCK) Slave mode - 18
tr(SCK) SPI clock rise and fall
Capacitive load: C = 15 pF - 6 ns
tf(SCK) time
tsu(NSS) NSS setup time Slave mode 4Tpclk -
th(NSS) NSS hold time Slave mode 2Tpclk + 10 -
tw(SCKH) Master mode, fPCLK = 36 MHz,
SCK high and low time Tpclk/2 -2 Tpclk/2 + 1
tw(SCKL) presc = 4

tsu(MI) Master mode 4 -

Data input setup time
tsu(SI) Slave mode 5 -
th(MI) Master mode 4 -
Data input hold time ns
th(SI) Slave mode 5 -
ta(SO)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
tdis(SO)(3) Data output disable time Slave mode 0 18
tv(SO) Data output valid time Slave mode (after enable edge) - 22.5
tv(MO) Data output valid time Master mode (after enable edge) - 6
th(SO) Slave mode (after enable edge) 11.5 -
Data output hold time
th(MO) Master mode (after enable edge) 2 -
SPI slave input clock
DuCy(SCK) Slave mode 25 75 %
duty cycle
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

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Figure 21. SPI timing diagram - slave mode and CPHA = 0

NSS input
SCK input

MISO MSB OUT BIT6 OUT LSB OUT

OUTPUT
(SI)

MOSI
MSB IN BIT1 IN LSB IN
INPUT
(SI)

Figure 22. SPI timing diagram - slave mode and CPHA = 1

NSS input

tSU(NSS) tc(SCK) th(NSS)

SCK input

CPHA=1
CPOL=0 tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tr(SCK)
tv(SO) th(SO) tdis(SO)
ta(SO) tf(SCK)
MISO
MSB OUT BIT6 OUT LSB OUT
OUTPUT
tsu(SI) th(SI)
MOSI
INPUT MSB IN BIT 1 IN LSB IN

ai14135b

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

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Figure 23. SPI timing diagram - master mode

High
NSS input
tc(SCK)
SCK Output

CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT

tv(MO) th(MO)

ai14136c

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

USB characteristics
The STM32F070CB/RB/C6/F6 USB interface is fully compliant with the USB specification
version 2.0 and is USB-IF certified (for Full-speed device operation).

Table 57. USB electrical characteristics

Symbol Parameter Conditions Min. Typ Max. Unit

USB transceiver operating

VDD - 3.0(1) - 3.6 V
voltage
tSTARTUP(2) USB transceiver startup time - - - 1.0 µs
Embedded USB_DP pull-up
RPUI - 1.1 1.26 1.5
value during idle
kΩ
Embedded USB_DP pull-up
RPUR - 2.0 2.26 2.6
value during reception
Driving high
ZDRV(2) Output driver impedance(3) 28 40 44 Ω
and low
1. The STM32F070CB/RB/C6/F6 USB functionality is ensured down to 2.7 V, but the USB electrical
characteristics are degraded in the 2.7-to-3.0 V voltage range.
2. Guaranteed by design, not tested in production.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.

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7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.

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7.2 TSSOP20 package information (YA)

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch.

Figure 24. TSSOP20 – Outline

20 11
c

E1 E
SEATING 0.25 mm
PLANE GAUGE PLANE
C
1 10

PIN 1
IDENTIFICATION
k
aaa C A1 L
A A2
L1

b e

YA_ME_V3

1. Drawing is not to scale.

Table 58. TSSOP20 – Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
D(2) 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.

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Figure 25. TSSOP20 – Footprint example

0.25
6.25
20 11

1.35

0.25

7.10 4.40

1.35

1 10

0.40 0.65 YA_FP_V1

1. Dimensions are expressed in millimeters.

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7.3 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 26. LQFP48 - Outline(15)

BOTTOM VIEW

4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1

H
R2

B
B-
D 1/4

N
O
(6)

TI
C
SE
B GAUGE PLANE
E 1/4

0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)

A A2 C SECTION A-A

(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING

1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)

SECTION B-B

TOP VIEW

5B_LQFP48_ME_V1

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Table 59. LQFP48 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 27. LQFP48 - Footprint example

0.50
1.20

36 25
37 24 0.30

0.20

9.70 7.30

48 13
1 12

5.80

9.70
5B_LQFP48_FP_V1

1. Dimensions are expressed in millimeters.

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7.4 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 28. LQFP64 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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Table 60. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
E1(2)(5) 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
q 0° 3.5° 7° 0° 3.5° 7°
q1 0° - - 0° - -
q2 10° 12° 14° 10° 12° 14°
q3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
bbb(1) 0.20 0.0079
(1)
ccc 0.08 0.0031
(1)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 29. LQFP64 - Footprint example

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

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7.5 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 19: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDD - VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 61. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

44
LQFP64 - 10 mm x 10 mm
Thermal resistance junction-ambient
ΘJ 55 °C/W
LQFP48 - 7 mm x 7 mm
Thermal resistance junction-ambient
76
TSSOP20 - 6.5 mm x 6.4 mm

7.5.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

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8 Ordering information
+

Example: STM32 F 070 C 6 T 6 x

Device family
STM32 = Arm-based 32-bit microcontroller

Product type
F = General-purpose

Sub-family
070 = STM32F070xx

Pin count
F = 20 pins
C = 48 pins
R = 64 pins

Code size
6 = 32 Kbyte of flash memory
B = 128 Kbyte of flash memory

Package
P = TSSOP
T = LQFP

Temperature range
6 = –40 to 85 °C

Option
xxx = programmed parts
TR = tape and reel

For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.

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STM32F070CB/RB/C6/F6 Important security notice

9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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10 Revision history

Table 62. Document revision history

Date Revision Changes

27-Nov-2014 1 Initial release.

Updated the number of SPI in Features and Section:
Description.
Updated Section: Serial peripheral interface (SPI).
Updated the fourth footnote of Table: STM32F070xB/i
pin definitions, and added the reference to PB9 pin.
Moved the AF3 data to AF4 for PA9 and PA10 pins in
Table: Alternate functions selected through GPIOA_AFR
15-Jan-2015 2 registers for port A.
Added the reference to footnote 1 to AF0 data for PB12,
PB13, PB14 and PB15, and to AF5 data for PB9 and
PB10 in Table: Alternate functions selected through
GPIOB_AFR registers for port B.
Added the reference to footnote 1 to SPI2 in Table:
STM32F070xB/6 peripheral register boundary
addressesF070.
Updated:
– Removal of Table 1 from cover page (all part numbers
put in the header)
– Table 1: STM32F070CB/RB/C6/F6 family device
features and peripheral counts; number of int. ADC
channels corrected
– Figure 1: Block diagram
– Figure 2: Clock tree
– Table 7: STM32F70x0 USART implementation
– Figure 6: STM32F070CB/RB/C6/F6 memory map and
added the note related to the start address of the
system memory
– Figure 9: Power supply scheme
07-Feb-2016 3 – Section 3.5.1: Power supply schemes
– Section 3.11: Timers and watchdogs - number of
complementary outputs in the table
– Table 10: STM32F070xB/6 pin definitions - TSSOP20
pinout correction, pins 10, 15 and 16
– Table 22: Embedded internal reference voltage:
added tSTART, changed VREFINT and tS_vrefint
values and notes
– Table 32: LSE oscillator characteristics (fLSE =
32.768 kHz) LSEDRV[1:0] values removed (see ref.
manual)
– Table 48: ADC characteristics - tSTAB defined relative
to clock frequency; notes 3. and 4. added
– Table 51: TS characteristics: removed the min. value
for tSTART

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STM32F070CB/RB/C6/F6 Revision history

Table 62. Document revision history (continued)

Date Revision Changes

– Figure 15 and Figure 16 improved

– Section 7: Package information name and structure
07-Feb-2016 3 change
– Section 8: Ordering information renamed from Part
numbering; removed undue code sizes
– Cover image updated
– Updated Section 1: Introduction, Section 3.3: Boot
modes, Section 3.4: Cyclic redundancy check
calculation unit (CRC), Section 4: Pinouts and pin
26-Apr-2024 4 descriptions (packages reorder from lowest to highest
pincount), Section 7: Package information (marking
information removed, packages reordered from lowest
to highest pincount, package references added)
– Added Section 9: Important security notice

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 STM32F070CB/RB/C6/F6

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