IRFP460A

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Vishay Siliconix
Power MOSFET
D
FEATURES
• Low gate charge Qg results in simple drive
TO-247
requirement
Available
• Improved gate, avalanche and dynamic dV/dt
ruggedness
G
• Fully characterized capacitance and avalanche voltage
and current
S
D
• Effective Coss specified
G S
• Material categorization: for definitions of compliance
N-Channel MOSFET please see www.vishay.com/doc?99912
Note
PRODUCT SUMMARY * This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
VDS (V) 500 example, parts with lead (Pb) terminations are not RoHS-compliant.
RDS(on) (Ω) VGS = 10 V 0.27 Please see the information / tables in this datasheet for details
Qg (max.) (nC) 105
APPLICATIONS
Qgs (nC) 26
• Switch mode power supply (SMPS)
Qgd (nC) 42
• Uninterruptable power supply
Configuration Single
• High speed power switching

TYPICAL SMPS TOPOLOGIES

• Full bridge
• PFC boost

ORDERING INFORMATION
Package TO-247
Lead (Pb)-free IRFP460APbF

ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 500
V
Gate-source voltage VGS ± 30
TC = 25 °C 20
Continuous drain current VGS at 10 V ID
TC = 100 °C 13 A
Pulsed drain current a IDM 80
Linear derating factor 2.2 W/°C
Single pulse avalanche energy b EAS 960 mJ
Repetitive avalanche current a IAR 20 A
Repetitive avalanche energy a EAR 28 mJ
Maximum power dissipation TC = 25 °C PD 280 W
Peak diode recovery dV/dt c dV/dt 3.8 V/ns
Operating junction and storage temperature range TJ, Tstg -55 to +150
°C
Soldering recommendations (peak temperature) for 10 s 300 d
10 lbf · in
Mounting torque 6-32 or M3 screw
1.1 N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 4.3 mH, Rg = 25 Ω, IAS = 20 A (see fig. 12)
c. ISD ≤ 20 A, dI/dt ≤ 125 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case

S22-0058-Rev. C, 31-Jan-2022 1 Document Number: 91234

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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient RthJA - 40
Case-to-sink, flat, greased surface RthCS 0.24 - °C/W
Maximum junction-to-case (drain) RthJC - 0.45

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 500 - - V
VDS temperature coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.61 - V/°C
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 30 V - - ± 100 nA
VDS = 500 V, VGS = 0 V - - 25
Zero gate voltage drain current IDSS µA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-source on-state resistance RDS(on) VGS = 10 V ID = 12 A b - - 0.27 Ω
Forward transconductance gfs VDS = 50 V, ID = 12 Ab 11 - - S
Dynamic
Input capacitance Ciss - 3100 -
VGS = 0 V,
Output capacitance Coss VDS = 25 V, - 480 -
f = 1.0 MHz, see fig. 5
Reverse transfer capacitance Crss - 18 -
pF
VDS = 1.0 V, f = 1.0 MHz 4430
Output capacitance Coss
VGS = 0 V VDS = 400 V, f = 1.0 MHz 130
Effective output capacitance Coss eff. VDS = 0 V to 400 Vc 140
Total gate charge Qg - - 105
ID = 20 A, VDS = 400 V,
Gate-source charge Qgs VGS = 10 V - - 26 nC
see fig. 6 and 13 b
Gate-drain charge Qgd - - 42
Turn-on delay time td(on) - 18 -
Rise time tr VDD = 250 V, ID = 20 A, - 55 -
ns
Turn-off delay time td(off) RG = 4.3 Ω, RD = 13 Ω, see fig. 10 b - 45 -
Fall time tf - 39 -
Drain-Source Body Diode Characteristics
MOSFET symbol
Continuous source-drain diode current IS D
- - 20
showing the
integral reverse G
A
Pulsed diode forward current a ISM p - n junction diode S
- - 80

Body diode voltage VSD TJ = 25 °C, IS = 20A, VGS = 0 V b - - 1.8 V

Body diode reverse recovery time trr - 480 710 ns
TJ = 25 °C, IF = 20 A, dI/dt = 100 A/μs b
Body diode reverse recovery charge Qrr - 5.0 7.5 μC
Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS

S22-0058-Rev. C, 31-Jan-2022 2 Document Number: 91234

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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

RDS(on), Drain-to-Source On Resistance

102 3.0
VGS ID = 20 A
Top 15 V VGS = 10 V
ID, Drain-to-Source Current (A)

10 V 2.5
8.0 V
7.0 V
10 6.0 V 2.0

(Normalized)
5.5 V
5.0 V
Bottom 4.5 V 1.5

1 1.0
4.5 V

0.5
20 µs Pulse Width
TC = 25 °C
0.1 0.0
0.1 1 10 102 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160

91234_01 VDS, Drain-to-Source Voltage (V) 91234_04 TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

102 105
VGS VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
ID, Drain-to-Source Current (A)

10 V Crss = Cgd
8.0 V 104 Coss = Cds + Cgd
7.0 V
Capacitance (pF)

6.0 V
5.5 V Ciss
5.0 V 103
Bottom 4.5 V
10
102
Coss
4.5 V

10
20 µs Pulse Width Crss
TC = 150 °C
1 1
1 10 102 1 10 102 103

91234_02 VDS, Drain-to-Source Voltage (V) 91234_05 VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

102 20
ID = 20 A
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)

VDS = 400 V
16
150 °C
VDS = 250 V
10
25 °C 12 VDS = 100 V

8
1

4
20 µs Pulse Width For test circuit
VDS = 50 V see figure 13
0.1 0
4.0 5.0 6.0 7.0 8.0 9.0 0 20 40 60 80 100

91234_03 VGS, Gate-to-Source Voltage (V) 91234_06 QG, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S22-0058-Rev. C, 31-Jan-2022 3 Document Number: 91234

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102 20
ISD, Reverse Drain Current (A)

ID, Drain Current (A)

15
150 °C
10
25 °C

10

1
5

VGS = 0 V
0.1 0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 25 50 75 100 125 150

91234_07 VSD, Source-to-Drain Voltage (V) 91234_09 TC, Case Temperature (°C)

Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature

103 RD
Operation in this area limited VDS
by RDS(on)
VGS
D.U.T.
ID, Drain Current (A)

RG
102 +
- VDD
10 µs
10 V
Pulse width ≤ 1 µs
100 µs
Duty factor ≤ 0.1 %
10

1 ms
TC = 25 °C
Fig. 10 - Switching Time Test Circuit
TJ = 150 °C
10 ms
Single Pulse
1 VDS
10 102 103 104
90 %
91234_08 VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area

10 %
VGS
td(on) tr td(off) tf

Fig. 11 - Switching Time Waveforms

1
Thermal Response (ZthJC)

D = 0.5

0.1 0.2
0.1
0.05 PDM

0.02
10-2 0.01 Single Pulse t1
(Thermal Response) t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1

91234_11 t1, Rectangular Pulse Duration (S)

Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

S22-0058-Rev. C, 31-Jan-2022 4 Document Number: 91234

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15 V QG
10 V

QGS QGD
L Driver
VDS

VG
RG D.U.T. +
- VDD
A
IAS
20 V Charge
tp 0.01 Ω

Fig. 13 - Unclamped Inductive Test Circuit Fig. 16 - Basic Gate Charge Waveform

620

VDS

VDSav, Avalanche Voltage (V)

tp 600

580

560
IAS

540
Fig. 14 - Unclamped Inductive Waveforms 0 4 8 12 16 20

91234_12d IAV, Avalanche Current (A)

EAS, Single Pulse Avalanche Energy (mJ)

2400 Fig. 17 - Typical Drain-to-Source Voltage vs.

ID Avalanche Current
Top 8.9 A
2000 13 A
Bottom 20 A Current regulator
1600 Same type as D.U.T.

1200 50 kΩ

12 V 0.2 µF
0.3 µF
800
+
VDS
D.U.T. -
400

VGS
0
25 50 75 100 125 150 3 mA

91234_12c Starting TJ, Junction Temperature (°C)

IG ID
Fig. 15 - Maximum Avalanche Energy vs. Drain Current Current sampling resistors

Fig. 18 - Gate Charge Test Circuit

S22-0058-Rev. C, 31-Jan-2022 5 Document Number: 91234

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Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 19 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91234.

S22-0058-Rev. C, 31-Jan-2022 6 Document Number: 91234

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 Package Information
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Vishay Siliconix
TO-247AC (High Voltage)
VERSION 1: FACILITY CODE = 9

MILLIMETERS MILLIMETERS
DIM. MIN. NOM. MAX. NOTES DIM. MIN. NOM. MAX. NOTES
A 4.83 5.02 5.21 D1 16.46 16.76 17.06 5
A1 2.29 2.41 2.55 D2 0.56 0.66 0.76
A2 1.17 1.27 1.37 E 15.50 15.70 15.87 4
b 1.12 1.20 1.33 E1 13.46 14.02 14.16 5
b1 1.12 1.20 1.28 E2 4.52 4.91 5.49 3
b2 1.91 2.00 2.39 6 e 5.46 BSC
b3 1.91 2.00 2.34 L 14.90 15.15 15.40
b4 2.87 3.00 3.22 6, 8 L1 3.96 4.06 4.16 6
b5 2.87 3.00 3.18 ØP 3.56 3.61 3.65 7
c 0.40 0.50 0.60 6 Ø P1 7.19 ref.
c1 0.40 0.50 0.56 Q 5.31 5.50 5.69
D 20.40 20.55 20.70 4 S 5.51 BSC
Notes
(1) Package reference: JEDEC® TO247, variation AC
(2) All dimensions are in mm
(3) Slot required, notch may be rounded
(4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body
(5) Thermal pad contour optional with dimensions D1 and E1
(6) Lead finish uncontrolled in L1
(7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition

Revision: 31-Oct-2022 1 Document Number: 91360

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 Package Information
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VERSION 2: FACILITY CODE = Y
A A
4
E 7 ØP (Datum B)
B
E/2 S A2 Ø k M DBM
3 R/2 ØP1
A
D2
Q

4 4
2xR
D D1
(2)

1 2 3 D 4
Thermal pad
5 L1

C L 4
E1
See view B A
0.01 M D B M
2 x b2 C View A - A
2x e
3xb
b4 A1
0.10 M C A M
(b1, b3, b5)
Planting Base metal
Lead Assignments
1. Gate D DE E
2. Drain
3. Source (c) c1
C C
4. Drain
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B

MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.58 5.31 D2 0.51 1.30
A1 2.21 2.59 E 15.29 15.87
A2 1.17 2.49 E1 13.72 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 Øk 0.254
b2 1.53 2.39 L 14.20 16.25
b3 1.65 2.37 L1 3.71 4.29
b4 2.42 3.43 ØP 3.51 3.66
b5 2.59 3.38 Ø P1 - 7.39
c 0.38 0.86 Q 5.31 5.69
c1 0.38 0.76 R 4.52 5.49
D 19.71 20.82 S 5.51 BSC
D1 13.08 -
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7) Outline conforms to JEDEC outline TO-247 with exception of dimension c

Revision: 31-Oct-2022 2 Document Number: 91360

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VERSION 3: FACILITY CODE = N
A
A

D2
B E P1
R/2 P
N A2

K M D BM
R

D1
D

D
L1

L
b4 C E1
b2 e A1
b 0.01 M D B M

0.10 M C A M
b1, b3, b5
Base metal

c1
c

b, b2, b4
Plating

MILLIMETERS MILLIMETERS
DIM. MIN. MAX. DIM. MIN. MAX.
A 4.65 5.31 D2 0.51 1.35
A1 2.21 2.59 E 15.29 15.87
A2 1.17 1.37 E1 13.46 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 k 0.254
b2 1.65 2.39 L 14.20 16.10
b3 1.65 2.34 L1 3.71 4.29
b4 2.59 3.43 N 7.62 BSC
b5 2.59 3.38 P 3.56 3.66
c 0.38 0.89 P1 - 7.39
c1 0.38 0.84 Q 5.31 5.69
D 19.71 20.70 R 4.52 5.49
D1 13.08 - S 5.51 BSC
ECN: E22-0452-Rev. G, 31-Oct-2022
DWG: 5971
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")

Revision: 31-Oct-2022 3 Document Number: 91360

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Revision: 01-Jan-2025 1 Document Number: 91000

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