Freescale Semiconductor Document Number: MC9S08AC128

Data Sheet: Advanced Information Rev. 1, 9/2008

MC9S08AC128 8-Bit MC9S08AC128

Microcontroller Data Sheet 917A-03 824D-02
840B-01
This document contains information on a new
product. Specifications and information herein
are subject to change without notice.

8-Bit HCS08 Central Processor Unit (CPU) Power-Saving Modes

• 40-MHz HCS08 CPU (central processor unit) • Wait plus two stops
• 20-MHz internal bus frequency Peripherals
• HC08 instruction set with added BGND, CALL and • ADC — 16-channel, 10-bit resolution, 2.5 μs
RTC instructions conversion time, automatic compare function,
• Memory Management Unit to support paged temperature sensor, internal bandgap reference
memory. channel
• Linear Address Pointer to allow direct page data • SCIx — Two serial communications interface
accesses of the entire memory map modules supporting LIN 2.0 Protocol and SAE J2602
Development Support protocols; Full duplex non-return to zero (NRZ);
• Background debugging system Master extended break generation; Slave extended
• Breakpoint capability to allow single breakpoint break detection; Wakeup on active edge
setting during in-circuit debugging (plus two more • SPIx — One full and one master-only serial
breakpoints in on-chip debug module) peripheral interface modules; Full-duplex or
• On-chip in-circuit emulator (ICE) Debug module single-wire bidirectional; Double-buffered transmit
containing three comparators and nine trigger and receive; Master or Slave mode; MSB-first or
modes. Eight deep FIFO for storing change-of-flow LSB-first shifting
addresses and event-only data. Supports both tag • IIC — Inter-integrated circuit bus module; Up to 100
and force breakpoints. kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt
Memory Options
driven byte-by-byte data transfer; supports broadcast
• Up to 128K FLASH — read/program/erase over full
mode and 10 bit addressing
operating voltage and temperature
• TPMx — One 2-channel and two 6-channel 16-bit
• Up to 8K Random-access memory (RAM)
timer/pulse-width modulator (TPM) modules:
• Security circuitry to prevent unauthorized access to
Selectable input capture, output compare, and
RAM and FLASH contents
edge-aligned PWM capability on each channel. Each
Clock Source Options timer module may be configured for buffered,
• Clock source options include crystal, resonator, centered PWM (CPWM) on all channels
external clock, or internally generated clock with • KBI — 8-pin keyboard interrupt module
precision NVM trimming using ICG module
Input/Output
System Protection • Up to 70 general-purpose input/output pins
• Optional computer operating properly (COP) reset • Software selectable pullups on input port pins
with option to run from independent internal clock • Software selectable drive strength and slew rate
source or bus clock control on ports when used as outputs
• CRC module to support fast cyclic redundancy
Package Options
checks on system memory
• 80-pin low-profile quad flat package (LQFP)
• Low-voltage detection with reset or interrupt
• 64-pin quad flat package (QFP)
• Illegal opcode detection with reset
• 44-pin low-profile quad flat package (LQFP)
• Master reset pin and power-on reset (POR)

This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.

Preliminary — Subject to Change

 Table of Contents
Chapter 1 3.9.1 ICG Frequency Specifications . . . . . . . . . . . . . 25
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 2 3.10.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . 28
Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.11 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.12 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 3 3.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical Characteristics and Timing Specifications . . . . . . .11 3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 34
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.13.2 Conducted Transient Susceptibility . . . . . . . . . 34
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .11 Chapter 4
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .11 Ordering Information and Mechanical Drawings . . . . . . . . . . 37
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14 4.2 Orderable Part Numbering System . . . . . . . . . . . . . . . 37
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18 Chapter 5
3.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 Internal Clock Generation Module Characteristics . . . .24

Related Documentation

MC9S08AC128 Series Reference Manual (MC9S08AC128RM)

contains extensive product information including modes of operartion, memory, resets and interrupts, reg-
ister definitions, port pins, CPU, and all peripheral module information.

For the latest version of the documentation, check our website at:
http://www.freescale.com
MC9S08AC128 MCU Series Data Sheet, Rev. 1
2 Freescale Semiconductor

Preliminary — Subject to Change

Chapter 1
Device Overview
The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core.

1.1 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU.

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 3

Preliminary — Subject to Change

Chapter 1 Device Overview

HCS08 CORE DEBUG

MODULE (DBG) PTA7
PTA6
PTA5

PORT A
BKGD/MS BDC CPU CYCLIC REDUNDANCY PTA4
PTA3
CHECK MODULE (CRC)
PTA2
PTA1
HCS08 SYSTEM CONTROL PTA0
INTERNAL CLOCK
RESET
GENERATOR (ICG) PTB7/AD1P7
RESETS AND INTERRUPTS
MODES OF OPERATION PTB6/AD1P6
POWER MANAGEMENT EXTAL PTB5/AD1P5
LOW-POWER OSC

PORT B
RQ/TPMCLK XTAL PTB4/AD1P4
PTB3/AD1P3
RTI COP PTB2/AD1P2
8-BIT KEYBOARD KBI1P7–KBI1P0 PTB1/TPM3CH1/AD1P1
IRQ LVD INTERRUPT MODULE (KBI1) PTB0/TPM3CH0/AD1P0

VDDAD PTC6
10-BIT PTC5/RxD2
VSSAD AD1P15–AD1P0
ANALOG-TO-DIGITAL PTC4

PORT C
VREFL
CONVERTER (ADC) PTC3/TxD2
VREFH
PTC2/MCLK
USERMEMORY SCL PTC1/SDA1
FLASH, RAM IIC MODULE (IIC1) SDA
PTC0/SCL1
(BYTES)
(AW128 = 128K, 8K)
(AW96 = 96K, 6K) SERIAL COMMUNICATIONS RXD1 PTD7/KBI1P7/AD1P15
INTERFACE MODULE (SCI1) TXD1 PTD6/TPM1CLK/AD1P14
VDD PTD5/AD1P13
VOLTAGE REGULATOR

PORT D
PTD4/TPM2CLK/AD1P12
VSS SERIAL COMMUNICATIONS RXD2
PTD3/KBI1P6/AD1P11
INTERFACE MODULE (SCI2) TXD2 PTD2/KBI1P5/AD1P10
PTJ7
PTJ6 PTD1/AD1P9
PTJ5 SPSCK1 PTD0/AD1P8
PORT J

PTJ4 MOSI1
PTJ3 SERIAL PERIPHERAL PTE7/SPSCK1
MISO1
PTJ2 INTERFACE MODULE (SPI1)
SS1 PTE6/MOSI1
PTJ1
PTJ0 SPSCK2 PTE5/MISO1
SERIAL PERIPHERAL MOSI2 PTE4/SS1
PORT E

PTH6/MISO2 INTERFACE MODULE (SPI2) MISO2

PTH5/MOSI2 PTE3/TPM1CH1
PORT H

PTH4/SPSCK2 PTE2/TPM1CH0
PTH3/TPM2CH5 TPM1CLK or TPMCLK PTE1/RxD1
PTH2/TPM2CH4 6-CHANNEL TIMER/PWM
MODULE (TPM1) TPM1CH0–TPM1CH5 PTE0/TxD1
PTH1/TPM2CH3
PTH0/TPM2CH2
PTF7
TPM2CLK or TPMCLK
PTG6/EXTAL 6-CHANNEL TIMER/PWM PTF6
PTG5/XTAL TPM2CH0–TPM2CH5 PTF5/TPM2CH1
PORT F

MODULE (TPM2)
PTF4/TPM2CH0
PORT G

PTG4/KBI1P4
PTG3/KBI1P3 PTF3/TPM1CH5
TPMCLK PTF2/TPM1CH4
PTG2/KBI1P2 2-CHANNEL TIMER/PWM
PTG1/KBI1P1 TPM3CH1 PTF1/TPM1CH3
MODULE (TPM3) PTF0/TPM1CH2
PTG0/KBIP0 TPM3CH0

- Pin not connected in 64-pin and 48-pin packages - Pin not connected in 48-pin package

Figure 1-1. MC9S08AC128 Series Block Diagram

MC9S08AC128 MCU Series Data Sheet, Rev. 1

4 Freescale Semiconductor

Preliminary — Subject to Change

Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.

2.1 Device Pin Assignment

Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device.

PTD6/TPM1CLK/AD1P14

PTD4/TPM2CLK/AD1P12
PTD7/KBI1P7/AD1P15

PTD5/AD1P13

PTG4/KBI1P4
PTH5/MIOSI2
PTH4/SPCK2
PTH6/MISO2

PTG6/EXTAL
PTC2/MCLK

PTC1/SDA1
PTC5/RxD2

PTC0/SCL1

PTG5/XTAL
PTC3/TxD2

BKGD/MS
VDD (NC)

VREFH
VREFL
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTC4 1 60 PTG3/KBI1P3
IRQ/TPMCLK 2 59 PTD3/KBI1P6/AD1P11
RESET 3 58 PTD2/KBI1P5/AD1P10
PTF0/TPM1CH2 4 57 VSSAD
PTF1/TPM1CH3 5 56 VDDAD
PTF2/TPM1CH4 6 55 PTD1/AD1P9
PTF3/TPM1CH5 7 54 PTD0/AD1P8
PTF4/TPM2CH0 8 53 PTB7/AD1P7
PTC6 9 52 PTB6/AD1P6
PTF7 10 80-Pin 51 PTB5/AD1P5
PTF5/TPM2CH1 11 LQFP 50 PTB4/AD1P4
PTF6 12 49 PTB3/AD1P3
PTJ0 13 48 PTB2/AD1P2
PTJ1 14 47 PTB1/TPM3CH1/AD1P1
PTJ2 15 46 PTB0/TPM3CH0/AD1P0
PTJ3 16 45 PTH3/TPM2CH5
PTE0/TxD1 17 44 PTH2/TPM2CH4
PTE1/RxD1 18 43 PTH1/TPM2CH3
PTE2/TPM1CH0 19 42 PTH0/TPM2CH2
PTE3/TPM1CH1 20 41 PTA7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Note: Pin names in bold

are lost in lower pin count
PTE4/SS1
PTE5/MISO1
PTE6/MOSI1
PTE7/SPSCK1
VSS
VDD

PTJ6
PTJ7
PTG0/KBI1P0
PTG1/KBI1P1
PTG2/KBI1P2
PTA0
PTJ4
PTJ5

PTA1
PTA2
PTA3
PTA4
PTA5
PTA6

packages.

Figure 2-1. MC9S08AC128 Series in 80-Pin LQFP Package

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 5

Preliminary — Subject to Change

Chapter 2 Pins and Connections

Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices.

PTD4/AD1P12/TPM2CLK
PTD7/AD1P15/KBI1P7

PTD6//TPM1CLK

PTD5/AD1P13

PTG4/KBI1P4
PTG6/EXTAL
PTC2/MCLK
PTC5/RxD2

PTC1/SDA1

PTC0/SCL1

PTG5/XTAL
PTC3/TxD2

BKGD/MS

VREFH
VREFL
VSS
64 49
63 62 61 60 59 58 57 56 55 54 53 52 51 50
PTC4 1 48 PTG3/KBI1P3

IRQ/TPMCLK 2 47 PTD3/KBI1P6/AD1P11

RESET 3 46 PTD2KBI1P5/AD1P10

PTF0/TPM1CH2 4 45 VSSAD

PTF1/TPM1CH3 5 44 VDDAD

PTF2/TPM1CH4 6 43 PTD1/AD1P9

PTF3/TPM1CH5 7 42 PTD0/AD1P8

PTF4/TPM2CH0 8 41 PTB7/AD1P7
64-Pin QFP
PTC6 9 40 PTB6/AD1P6

PTF7 10 39 PTB5/AD1P5

PTF5/TPM2CH1 11 38 PTB4/AD1P4

PTF6 12 37 PTB3/AD1P3

PTE0/TxD1 13 36 PTB2/AD1P2

PTE1/RxD1 14 35 PTB1/TPM3CH1/AD1P1

PTE2/TPM1CH0 15 34 PTB0/TPM3CH0/AD1P0

PTE3/TPM1CH1 16 33 PTA7
18 19 20 21 22 23 24 25 26 27 28 29 30 31
17 32
Note: Pin names in bold
PTA4

PTA5

PTA6
PTA3
PTG2/KBI1P2

PTA0

PTA1

PTA2
PTE7/SPSCK1

VDD

PTG0/KBI1P0

PTG1/KBI1P1
PTE4/SS1

PTE5/MISO1

PTE6/MOSI1

VSS

are lost in lower pin count

packages.

Figure 2-2. MC9S08AC128 Series in 64-Pin QFP Package

MC9S08AC128 MCU Series Data Sheet, Rev. 1

6 Freescale Semiconductor

Preliminary — Subject to Change

 Chapter 2 Pins and Connections

Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device.

PTG6/EXTAL
PTC2/MCLK
PTC5/RxD2

PTC1/SDA1

PTC0/SCL1

PTG5/XTAL
PTC3/TxD2

BKGD/MS

VREFH
VREFL
VSS
44 34
43 42 41 40 39 38 37 36 35
PTC4 1
33 PTG3/KBI1P3
IRQ/TPMCLK 2 32 PTD3/KBI1P6/AD1P11
RESET 3 31 PTD2/KBI1P5/AD1P10
PTF0/TPM1CH2 4 30 VSSAD
PTF1/TPM1CH3 5 29 VDDAD
PTF4/TPM2CH0 6
44-Pin LQFP
28 PTD1/AD1P9
PTF5/TPM2CH1 7 27 PTD0/AD1P8
PTE0/TxD1 8 26 PTB3/AD1P3
PTE1/RxD1 9 PTB2/AD1P2
25
PTE2/TPM1CH0 10 PTB1/TPM3CH1/AD1P1
24
PTE3/TPM1CH1 11
23 PTB0/TPM3CH0/AD1P0
13 14 15 16 17 18 19 20 21
12 22
PTE4/SS1

PTE5/MISO1

PTE6/MOSI1

PTE7/SPSCK1

VSS

VDD

PTG0/KBI1P0

PTG1/KBI1P1

PTG2/KBI1P2

PTA0

PTA1

Figure 2-3. MC9S08AC128 Series in 44-Pin LQFP Package

Table 2-4. Pin Availability by Package Pin-Count

Pin Number Lowest <-- Priority --> Highest

80 64 44 Port Pin Alt 1 Alt 2

1 1 1 PTC4
2 2 2 IRQ TPMCLK1
3 3 3 RESET
4 4 4 PTF0 TPM1CH2
5 5 5 PTF1 TPM1CH3
6 6 — PTF2 TPM1CH4
7 7 — PTF3 TPM1CH5
8 8 6 PTF4 TPM2CH0

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 7

Preliminary — Subject to Change

Chapter 2 Pins and Connections

Table 2-4. Pin Availability by Package Pin-Count (continued)

Pin Number Lowest <-- Priority --> Highest

80 64 44 Port Pin Alt 1 Alt 2

9 9 — PTC6
10 10 — PTF7
11 11 7 PTF5 TPM2CH1
12 12 — PTF6
13 — — PTJ0
14 — — PTJ1
15 — — PTJ2
16 — — PTJ3
17 13 8 PTE0 TxD1
18 14 9 PTE1 RxD1
19 15 10 PTE2 TPM1CH0
20 16 11 PTE3 TPM1CH1
21 17 12 PTE4 SS1
22 18 13 PTE5 MISO1
23 19 14 PTE6 MOSI1
24 20 15 PTE7 SPSCK1
25 21 16 VSS
26 22 17 VDD
27 — — PTJ4
28 — — PTJ5
29 — — PTJ6
30 — — PTJ7
31 23 18 PTG0 KBI1P0
32 24 19 PTG1 KBI1P1
33 25 20 PTG2 KBI1P2
34 26 21 PTA0
35 27 22 PTA1
36 28 — PTA2
37 29 — PTA3
38 30 — PTA4
39 31 — PTA5
40 32 — PTA6
41 33 — PTA7
42 — — PTH0 TPM2CH2
43 — — PTH1 TPM2CH3
44 — — PTH2 TPM2CH4
45 — — PTH3 TPM2CH5
46 34 23 PTB0 TPM3CH0 AD1P0
47 35 24 PTB1 TPM3CH1 AD1P1
48 36 25 PTB2 AD1P2
49 37 26 PTB3 AD1P3

MC9S08AC128 MCU Series Data Sheet, Rev. 1

8 Freescale Semiconductor

Preliminary — Subject to Change

 Chapter 2 Pins and Connections

Table 2-4. Pin Availability by Package Pin-Count (continued)

Pin Number Lowest <-- Priority --> Highest

80 64 44 Port Pin Alt 1 Alt 2

50 38 — PTB4 AD1P4
51 39 — PTB5 AD1P5
52 40 — PTB6 AD1P6
53 41 — PTB7 AD1P7
54 42 27 PTD0 AD1P8
55 43 28 PTD1 AD1P9
56 44 29 VDDAD
57 45 30 VSSAD
58 46 31 PTD2 KBI1P5 AD1P10
59 47 32 PTD3 KBI1P6 AD1P11
60 48 33 PTG3 KBI1P3
61 49 — PTG4 KBI1P4
62 50 — PTD4 TPM2CLK AD1P12
63 51 — PTD5 AD1P13
64 52 — PTD6 TPM1CLK AD1P14
65 53 — PTD7 KBI1P7 AD1P15
66 54 34 VREFH
67 55 35 VREFL
68 56 36 BKGD MS
69 57 37 PTG5 XTAL
70 58 38 PTG6 EXTAL
71 59 39 VSS
72 — — VDD(NC)
73 60 40 PTC0 SCL1
74 61 41 PTC1 SDA1
75 — — PTH4 SPSCK2
76 — — PTH5 MOSI2
77 — — PTH6 MISO2
78 62 42 PTC2 MCLK
79 63 43 PTC3 TxD2
80 64 44 PTC5 RxD2
1
TPMCLK, TPM1CLK, and TPM2CLK options are
configured via software; out of reset, TPM1CLK,
TPM2CLK, and TPMCLK are available to TPM1,
TPM2, and TPM3 respectively.

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 9

Preliminary — Subject to Change

Chapter 2 Pins and Connections

MC9S08AC128 MCU Series Data Sheet, Rev. 1

10 Freescale Semiconductor

Preliminary — Subject to Change

Chapter 3
Electrical Characteristics and Timing Specifications
3.1 Introduction
This section contains electrical and timing specifications.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 3-1. Parameter Classifications

P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a
C
statistically relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from
T typical devices under typical conditions unless otherwise noted. All values shown in
the typical column are within this category.
D Those parameters are derived mainly from simulations.

NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that
normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either
VSS or VDD).

MC9S08AC128 Series Data Sheet, Rev. 1

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Chapter 3 Electrical Characteristics and Timing Specifications

Table 3-2. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage VDD –0.3 to + 5.8 V
Input voltage VIn – 0.3 to VDD + 0.3 V
Instantaneous maximum current
ID ± 25 mA
Single pin limit (applies to all port pins)1, 2, 3
Maximum current into VDD IDD 120 mA
Storage temperature Tstg –55 to +150 °C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.

MC9S08AC128 Series Data Sheet, Rev. 1

12 Freescale Semiconductor

Preliminary — Subject to Change

 Chapter 3 Electrical Characteristics and Timing Specifications

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 3-3. Thermal Characteristics

Rating Symbol Value Unit

Operating temperature range (packaged) TL to TH
TA °C
–40 to 125

Maximum junction temperature TJ 150 °C

Thermal resistance 1,2,3,4

80-pin LQFP
1s 61
2s2p 47
64-pin QFP
1s θJA 57 °C/W
2s2p 43

44-pin LQFP
1s 73
2s2p 56

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2 Junction to Ambient Natural Convection
3 1s - Single Layer Board, one signal layer
4 2s2p - Four Layer Board, 2 signal and 2 power layers

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA) Eqn. 3-1

where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:

PD = K ÷ (TJ + 273°C) Eqn. 3-2

Solving equations 1 and 2 for K gives:

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 13

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Chapter 3 Electrical Characteristics and Timing Specifications

K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3-3

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and
JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed
for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 3-4. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series Resistance R1 1500 Ω
Human Body Storage Capacitance C 100 pF
Number of Pulse per pin – 3

Series Resistance R1 0 Ω
Machine Storage Capacitance C 200 pF
Number of Pulse per pin – 3
Minimum input voltage limit – 2.5 V
Latch-up
Maximum input voltage limit 7.5 V

Table 3-5. ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit

1 C Human Body Model (HBM) VHBM ± 2000 – V

2 C Machine Model (MM) VMM ± 200 – V

3 C Charge Device Model (CDM) VCDM ± 500 – V

4 C Latch-up Current at TA = 125°C ILAT ± 100 – mA

3.6 DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.

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Table 3-6. DC Characteristics

Num C Parameter Symbol Min Typ1 Max Unit

1 — Operating Voltage VDD 2.7 — 5.5 V
2 P Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –2 mA VDD – 1.5 — —
3 V, ILoad = –0.6 mA VDD – 1.5 — —
5 V, ILoad = –0.4 mA VDD – 0.8 — —
3 V, ILoad = –0.24 mA VDD – 0.8 — —
P Output high voltage — High Drive (PTxDSn = 1) VOH V
5 V, ILoad = –10 mA VDD – 1.5 — —
3 V, ILoad = –3 mA VDD – 1.5 — —
5 V, ILoad = –2 mA VDD – 0.8 — —
3 V, ILoad = –0.4 mA VDD – 0.8 — —
3 P Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA — — 1.5
3 V, ILoad = 0.6 mA — — 1.5
5 V, ILoad = 0.4 mA — — 0.8
3 V, ILoad = 0.24 mA — — 0.8
P Output low voltage — High Drive (PTxDSn = 1) VOL V
5 V, ILoad = 10 mA — — 1.5
3 V, ILoad = 3 mA — — 1.5
5 V, ILoad = 2 mA — — 0.8
3 V, ILoad = 0.4 mA — — 0.8
4 P Output high current — Max total IOH for all ports
5V IOHT — — 100 mA
3V — — 60
5 P Output low current — Max total IOL for all ports
5V IOLT — — 100 mA
3V — — 60
6 P Input high 2.7v ≤ VDD 4.5v VIH 0.70xVDD — —
voltage; all 4.5v ≤ VDD ≤ 5.5v VIH 0.65xVDD — — V
digital inputs
7 P Input low voltage; all digital inputs VIL — — 0.35 x VDD
8 P Input hysteresis; all digital inputs Vhys 0.06 x VDD mV
2
9 P Input leakage current; input only pins |IIn| — 0.1 1 μA
10 P High Impedance (off-state) leakage current2 |IOZ| — 0.1 1 μA
11 P Internal pullup resistors3 RPU 20 45 65 kΩ
4
12 P Internal pulldown resistors RPD 20 45 65 kΩ
13 C Input Capacitance; all non-supply pins CIn — — 8 pF
14 D RAM retention voltage VRAM — 0.6 1.0 V
15 P POR rearm voltage VPOR 0.9 1.4 2.0 V
16 D POR rearm time tPOR 10 — — μs
17 P Low-voltage detection threshold — high range
VDD falling VLVDH 4.2 4.3 4.4 V
VDD rising 4.3 4.4 4.5
Low-voltage detection threshold — low range
18 P VDD falling VLVDL 2.48 2.56 2.64 V
VDD rising 2.54 2.62 2.7

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Table 3-6. DC Characteristics (continued)

Num C Parameter Symbol Min Typ1 Max Unit

Low-voltage warning threshold — high range
19 P VDD falling VLVWH 4.2 4.3 4.4 V
VDD rising 4.3 4.4 4.5

Low-voltage warning threshold — low range

20 P VLVWL 2.48 2.56 2.64 V
VDD falling
2.54 2.62 2.7
VDD rising

21 Low-voltage inhibit reset/recover hysteresis

P 5V Vhys — 100 — mV
3V — 60 —
1
Typical values are based on characterization data at 25°C unless otherwise stated.
2
Measured with VIn = VDD or VSS.
3 Measured with V = V .
In SS
4 Measured with V = V .
In DD

VDD–VOH (V)
Average of IOH
–6.0E-3

–5.0E-3 –40°C
25°C
–4.0E-3 125°C

IOH (A)
–3.0E-3

–2.0E-3

–1.0E-3

000E+0
0 0.3 0.5 0.8 0.9 1.2 1.5
VSupply–VOH
Figure 3-1. Typical IOH (Low Drive) vs VDD–VOH at VDD = 3 V

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Average of IOH VDD–VOH (V)

–20.0E-3
–18.0E-3
–16.0E-3 –40°C
25°C
–14.0E-3 125°C
–12.0E-3

IOH (A)
–10.0E-3
–8.0E-3
–6.0E-3
–4.0E-3
–2.0E-3
000.0E-3
0 0.3 0.5 0.8 0.9 1.2 1.5
VSupply–VOH
Figure 3-2. Typical IOH (High Drive) vs VDD–VOH at VDD = 3 V

Average of IOH

–7.0E-3

–6.0E-3 –40°C
25°C
–5.0E-3 125°C

–4.0E-3

IOH (A)
–3.0E-3

–2.0E-3

–1.0E-3

000E+0
0.00 0.30 0.50 0.80 1.00 1.30 2.00
VDD–VOH (V)
VSupply–VOH
Figure 3-3. Typical IOH (Low Drive) vs VDD–VOH at VDD = 5 V

Average of IOH VDD–VOH (V)

–30.0E-3

–25.0E-3

–20.0E-3 –40°C
25°C
125°C
IOH (A)

–15.0E-3

–10.0E-3

–5.0E-3

000.0E+3
0.00 0.30 0.50 0.80 1.00 1.30 2.00
VSupply–VOH
Figure 3-4. Typical IOH (High Drive) vs VDD–VOH at VDD = 5 V

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3.7 Supply Current Characteristics

Table 3-7. Supply Current Characteristics
VDD Temp
Num C Parameter Symbol
(V) Typ1 Max Unit (°C)
2 5 0.750 0.9503
1 C Run supply current measured at
RIDD mA –40 to 125°C
(CPU clock = 2 MHz, fBus = 1 MHz) 3 0.570 0.770

4 5 4.9 5.105
2 C Run supply current measured at
RIDD mA –40 to 125°C
(CPU clock = 16 MHz, fBus = 8 MHz) 3 3.5 3.70

Stop2 mode supply current 25 –40 to 85°C

5 μA
1.0 160 –40 to 125°C
3 C
23 –40 to 85°C
S2IDD 3 μA
0.8 150 –40 to 125°C
Stop3 mode supply current 27 –40 to 85°C
5 μA
1.2 1803 –40 to 125°C
4 C
S3IDD 25 –40 to 85°C
3 μA
1.0 170 –40 to 125°C
500 –40 to 85°C
5 300 nA
500 –40 to 125°C
5 C RTI adder to stop2 or stop36 S23IDDRTI 500 –40 to 85°C
3 300 nA
500 –40 to 125°C
180 –40 to 85°C
5 110 μA
180 –40 to 125°C
6 C LVD adder to stop3 (LVDE = LVDSE = 1) S3IDDLVD
160 –40 to 85°C
3 90 μA
160 –40 to 125°C

Adder to stop3 for oscillator enabled7 8 μA –40 to 85°C

7 C 5,3 5
(OSCSTEN =1) S3IDDOSC 8 μA –40 to 125°C
1 Typical values are based on characterization data at 25°C unless otherwise stated. See Figure 3-5 through Figure 3-7 for
typical curves across voltage/temperature.
2 All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
3 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
4 All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
5
Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
6 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 560 μA at 3 V with fBus = 1 MHz.
7
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal, low power mode
(HGO = 0), clock monitor disabled (LOCD = 1).

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18

16 20 MHz, ADC off, FEE, 25°C

20 MHz, ADC off, FBE, 25°C

14

12

10
IDD

8 8 MHz, ADC off, FEE, 25°C

8 MHz, ADC off, FBE, 25°C

6

4
1 MHz, ADC off, FEE, 25°C

1 MHz, ADC off, FBE, 25°C

2

0
2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4

VDD

Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 MHz
Figure 3-5. Typical Run IDD for FBE and FEE Modes, IDD vs. VDD

MC9S08AC128 MCU Series Data Sheet, Rev. 1

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Chapter 3 Electrical Characteristics and Timing Specifications

–40°C
Stop2 IDD (A) 25°C
55°C
85°C
Average of Measurement IDD
–8.0E-3
–7.0E-3

–6.0E-3

–5.0E-3
IDD (A)

–4.0E-3

–3.0E-3

–2.0E-3

–1.0E-3

000E+0
1.8 2 2.5 3 3.5 4 4.5 5
VDD (V)
Figure 3-6. Typical Stop 2 IDD

–40°C
Stop3 IDD (A) 25°C
55°C
85°C
Average of Measurement IDD
–8.0E-3
–7.0E-3

–6.0E-3

–5.0E-3
IDD (A)

–4.0E-3

–3.0E-3

–2.0E-3

–1.0E-3

000E+0
1.8 2 2.5 3 3.5 4 4.5 5
VDD (V)
Figure 3-7. Typical Stop3 IDD

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3.8 ADC Characteristics

Table 3-8. 5 Volt 10-bit ADC Operating Conditions

Characteristic Conditions Symb Min Typ1 Max Unit

Supply voltage Absolute VDDAD 2.7 — 5.5 V

Delta to VDD (VDD–VDDAD)2 ΔVDDAD –100 0 +100 mV

Ground voltage Delta to VSS (VSS–VSSAD)2 ΔVSSAD –100 0 +100 mV

Ref voltage high VREFH 2.7 VDDAD VDDAD V

Ref voltage low VREFL VSSAD VSSAD VSSAD V

Supply current Stop, reset, module off IDDAD — 0.011 1 μA

Input voltage VADIN VREFL — VREFH V

Input capacitance CADIN — 4.5 5.5 pF

Input resistance RADIN — 3 5 kΩ

Analog source resistance 10-bit mode

External to MCU fADCK > 4MHz — — 5
fADCK < 4MHz RAS — — 10 kΩ

8-bit mode (all valid fADCK) — — 10

ADC conversion clock frequency High speed (ADLPC = 0) 0.4 — 8.0

fADCK MHz
Low power (ADLPC = 1) 0.4 — 4.0

Temp Sensor –40 °C to 25 °C 3.266 — mV/°

Slope m —
25 °C to 125 °C 3.638 — C

Temp Sensor
25 °C VTEMP25 — 1.396 — V
Voltage
1
Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 dc potential difference.

MC9S08AC128 MCU Series Data Sheet, Rev. 1

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Chapter 3 Electrical Characteristics and Timing Specifications

SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
SIMPLIFIED
Pad
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
input ENGINE
RAS RADIN
protection
+
VADIN
–
CAS
VAS +
–

RADIN

INPUT PIN
RADIN

INPUT PIN
RADIN

INPUT PIN CADIN

Figure 3-8. ADC Input Impedance Equivalency Diagram

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 Chapter 3 Electrical Characteristics and Timing Specifications

Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)

Characteristic Conditions C Symb Min Typ1 Max Unit

Supply current T IDDAD — 133 — μA

ADLPC = 1
ADLSMP = 1
ADCO = 1

Supply current T IDDAD — 218 — μA

ADLPC = 1
ADLSMP = 0
ADCO = 1

Supply current T IDDAD — 327 — μA

ADLPC = 0
ADLSMP = 1
ADCO = 1

Supply current T IDDAD — 582 — μA

ADLPC = 0
ADLSMP = 0 VDDAD < 5.5 V P — — 1 mA
ADCO = 1

ADC asynchronous clock source High speed (ADLPC = 0) P fADACK 2 3.3 5 MHz
tADACK = 1/fADACK
Low power (ADLPC = 1) 1.25 2 3.3

Conversion time Short sample (ADLSMP = 0) P tADC — 20 — ADCK

(Including sample time) cycles
Long sample (ADLSMP = 1) — 40 —

Sample time Short sample (ADLSMP = 0) P tADS — 3.5 — ADCK

cycles
Long sample (ADLSMP = 1) — 23.5 —

Total unadjusted error 10-bit mode P ETUE — ±1 ±2.5 LSB2

Includes quantization
8-bit mode — ±0.5 ±1.0

Differential non-linearity 10-bit mode P DNL — ±0.5 ±1.0 LSB2

8-bit mode — ±0.3 ±0.5

Monotonicity and no-missing-codes guaranteed

Integral non-linearity 10-bit mode C INL — ±0.5 ±1.0 LSB2

8-bit mode — ±0.3 ±0.5

Zero-scale error 10-bit mode P EZS — ±0.5 ±1.5 LSB2

VADIN = VSSA
8-bit mode — ±0.5 ±0.5

Full-scale error 10-bit mode P EFS — ±0.5 ±1.5 LSB2

VADIN = VDDA
8-bit mode — ±0.5 ±0.5

Quantization error 10-bit mode D EQ — — ±0.5 LSB2

8-bit mode — — ±0.5

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Chapter 3 Electrical Characteristics and Timing Specifications

Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)

Characteristic Conditions C Symb Min Typ1 Max Unit

Input leakage error 10-bit mode D EIL — ±0.2 ±2.5 LSB2

Pad leakage3 * RAS
8-bit mode — ±0.1 ±1
1
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH – VREFL)/2N
3 Based on input pad leakage current. Refer to pad electricals.

3.9 Internal Clock Generation Module Characteristics

ICG
EXTAL XTAL

RS
RF

Crystal or Resonator
C1
C2

Table 3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient)

Characteristic Symbol Min Typ1 Max Unit

Load capacitors C1
See Note 2
C2
Feedback resistor
Low range (32k to 100 kHz) RF 10 MΩ
High range (1M – 16 MHz) 1 MΩ
Series resistor
Low range
Low Gain (HGO = 0) — 0 —
High Gain (HGO = 1) — 100 —
High range
RS kΩ
Low Gain (HGO = 0) — 0 —
High Gain (HGO = 1)
≥ 8 MHz — 0 —
4 MHz — 10 —
1 MHz — 20 —
1 Typical values are based on characterization data at VDD = 5.0V, 25°C or is typical recommended value.
2 See crystal or resonator manufacturer’s recommendation.

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 Chapter 3 Electrical Characteristics and Timing Specifications

3.9.1 ICG Frequency Specifications

Table 3-11. ICG Frequency Specifications
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient)

Num C Characteristic Symbol Min Typ1 Max Unit

Oscillator crystal or resonator (REFS = 1)
(Fundamental mode crystal or ceramic resonator)
Low range flo 32 — 100 kHz
High range
1
High Gain, FBE (HGO = 1,CLKS = 10) fhi_byp 1 — 16 MHz
High Gain, FEE (HGO = 1,CLKS = 11) fhi_eng 2 — 10 MHz
Low Power, FBE (HGO = 0, CLKS = 10) flp_byp 1 8 MHz
Low Power, FEE (HGO = 0, CLKS = 11) flp_eng 2 8 MHz
Input clock frequency (CLKS = 11, REFS = 0)
2 Low range flo 32 — 100 kHz
High range fhi_eng 2 — 10 MHz

3 Input clock frequency (CLKS = 10, REFS = 0) fExtal 0 — 40 MHz

4 Internal reference frequency (untrimmed) fICGIRCLK 182.25 243 303.75 kHz
5 Duty cycle of input clock (REFS = 0) tdc 40 — 60 %
Output clock ICGOUT frequency
CLKS = 10, REFS = 0 fExtal (max)
6 fICGOUT fExtal (min) —
All other cases fICGDCLKmax( MHz
flo (min) —
max)
7 Minimum DCO clock (ICGDCLK) frequency fICGDCLKmin 3 — MHz
8 Maximum DCO clock (ICGDCLK) frequency fICGDCLKmax — 40 MHz
2
9 Self-clock mode (ICGOUT) frequency fSelf fICGDCLKmin fICGDCLKmax MHz
10 Self-clock mode reset (ICGOUT) frequency fSelf_reset 5.5 8 10.5 MHz
3
Loss of reference frequency
11 Low range fLOR 5 25
kHz
High range 50 500
12 Loss of DCO frequency 4 fLOD 0.5 1.5 MHz
5, 6
Crystal start-up time t
CSTL
13 Low range — 430 —
t ms
High range CSTH — 4 —
FLL lock time , 7 tLockl
14 Low range — 2 ms
tLockh
High range — 2
15 FLL frequency unlock range nUnlock –4*N 4*N counts
16 FLL frequency lock range nLock –2*N 2*N counts
, 8 measured
ICGOUT period jitter, at fICGOUT Max
17 CJitter
Long term jitter (averaged over 2 ms interval) — 0.2 % fICG
Internal oscillator deviation from trimmed
frequency9 ± 0.5
18 — ±2
VDD = 2.7 – 5.5 V, (constant temperature) ACCint ±0.5 %
— ±2
VDD = 5.0 V ±10%, –40° C to 125°C
1
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
2
Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.

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3
Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it
is not in the desired range.
4
Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode
(if an external reference exists) if it is not in the desired range.
5
This parameter is characterized before qualification rather than 100% tested.
6
Proper PC board layout procedures must be followed to achieve specifications.
7
This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes.
If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
9
See Figure 3-9

Average of Percentage Error

Variable
3V
5V

Figure 3-9. Internal Oscillator Deviation from Trimmed Frequency

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 Chapter 3 Electrical Characteristics and Timing Specifications

3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the
bus are generated, see Chapter 10, “Internal Clock Generator (S08ICGV4).”

3.10.1 Control Timing

Table 3-12. Control Timing

Num C Parameter Symbol Min Typ1 Max Unit

1 Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz

2 Real-time interrupt internal oscillator period tRTI 700 1300 μs
3 External reset pulse width2 1.5 x
textrst — ns
(tcyc = 1/fSelf_reset) tSelf_reset

4 Reset low drive3 trstdrv 34 x tcyc — ns

5 Active background debug mode latch setup time tMSSU 25 — ns
6 Active background debug mode latch hold time tMSH 25 — ns
IRQ pulse width
7 Asynchronous path2 tILIH, tIHIL 100 — — ns
Synchronous path4 1.5 x tcyc
8 KBIPx pulse width
Asynchronous path2 tILIH, tIHIL 100 — — ns
Synchronous path3 1.5 x tcyc

Port rise and fall time (load = 50 pF)5

9 Slew rate control disabled (PTxSE = 0) tRise, tFall — 3 ns
Slew rate control enabled (PTxSE = 1) — 30
1
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3 When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on

the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.

textrst

RESET PIN

Figure 3-10. Reset Timing

MC9S08AC128 MCU Series Data Sheet, Rev. 1

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Chapter 3 Electrical Characteristics and Timing Specifications

BKGD/MS

RESET

tMSH

tMSSU

Figure 3-11. Active Background Debug Mode Latch Timing

tIHIL

IRQ/KBIP7-KBIP4

IRQ/KBIPx

tILIH

Figure 3-12. IRQ/KBIPx Timing

3.10.2 Timer/PWM (TPM) Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 3-13. TPM Input Timing

Function Symbol Min Max Unit

External clock frequency fTPMext dc fBus/4 MHz

External clock period tTPMext 4 — tcyc

External clock high time tclkh 1.5 — tcyc

External clock low time tclkl 1.5 — tcyc

Input capture pulse width tICPW 1.5 — tcyc

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tTPMext
tclkh

TPMxCLK

tclkl

Figure 3-13. Timer External Clock

tICPW

TPMxCHn

TPMxCHn

tICPW

Figure 3-14. Timer Input Capture Pulse

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Chapter 3 Electrical Characteristics and Timing Specifications

3.11 SPI Characteristics

Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system.
Table 3-14. SPI Electrical Characteristic

Num1 C Characteristic2 Symbol Min Max Unit

Operating frequency3
Master fop fBus/2048 fBus/2 Hz
Slave fop dc fBus/4
1 Cycle time
Master tSCK 2 2048 tcyc
Slave tSCK 4 — tcyc

2 Enable lead time

Master tLead — 1/2 tSCK
Slave tLead 1/2 — tSCK
3 Enable lag time
Master tLag — 1/2 tSCK
Slave tLag 1/2 — tSCK
4 Clock (SPSCK) high time
Master and Slave tSCKH 1/2 tSCK – 25 — ns

5 Clock (SPSCK) low time Master

and Slave tSCKL 1/2 tSCK – 25 — ns

6 Data setup time (inputs)

Master tSI(M) 30 — ns
Slave tSI(S) 30 — ns

7 Data hold time (inputs)

Master tHI(M) 30 — ns
Slave tHI(S) 30 — ns

8 Access time, slave4 tA 0 40 ns

9 Disable time, slave5 tdis — 40 ns

10 Data setup time (outputs)

Master tSO 25 — ns
Slave tSO 25 — ns

11 Data hold time (outputs)

Master tHO –10 — ns
Slave tHO –10 — ns
1
Refer to Figure 3-15 through Figure 3-18.
2
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
4
Time to data active from high-impedance state.
5 Hold time to high-impedance state.

MC9S08AC128 Series Data Sheet, Rev. 1

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 Chapter 3 Electrical Characteristics and Timing Specifications

SS1
(OUTPUT)

2 1 3
SCK 5
(CPOL = 0)
(OUTPUT) 4

SCK 5
(CPOL = 1)
(OUTPUT) 4

6 7

MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

10 10 11

MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT

NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 3-15. SPI Master Timing (CPHA = 0)

SS(1)
(OUTPUT)

1
2 3
SCK
(CPOL = 0) 5
(OUTPUT) 4

SCK 5
(CPOL = 1)
4
(OUTPUT)
6 7
MISO
(INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN

10 11
MOSI
(OUTPUT) MSB OUT(2) BIT 6 . . . 1 LSB OUT

NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 3-16. SPI Master Timing (CPHA = 1)

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Chapter 3 Electrical Characteristics and Timing Specifications

SS
(INPUT)

1 3
SCK
(CPOL = 0) 5
(INPUT) 4
2
SCK
(CPOL = 1) 5
(INPUT) 4 9
8 10 11

MISO SEE
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE

6 7

MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE:
1. Not defined but normally MSB of character just received
Figure 3-17. SPI Slave Timing (CPHA = 0)

SS
(INPUT)

1 3
2
SCK
(CPOL = 0) 5
(INPUT) 4

SCK 5
(CPOL = 1) 4
(INPUT)
10 11 9
MISO SEE
(OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

8 6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE:
1. Not defined but normally LSB of character just received
Figure 3-18. SPI Slave Timing (CPHA = 1)

MC9S08AC128 Series Data Sheet, Rev. 1

32 Freescale Semiconductor

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 Chapter 3 Electrical Characteristics and Timing Specifications

3.12 FLASH Specifications

This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see Chapter 4, “Memory.”

Table 3-15. Flash Characteristics

Num C Characteristic Symbol Min Typ1 Max Unit

1 P Supply voltage for program/erase Vprog/erase 2.7 5.5 V

2 P Supply voltage for read operation VRead 2.7 5.5 V

3 P Internal FCLK frequency2 fFCLK 150 200 kHz

4 P Internal FCLK period (1/FCLK) tFcyc 5 6.67 μs

5 P Byte program time (random location)(2) tprog 9 tFcyc

6 C Byte program time (burst mode)(2) tBurst 4 tFcyc

7 P Page erase time3 tPage 4000 tFcyc

8 P Mass erase time(2) tMass 20,000 tFcyc

Program/erase endurance4
9 C TL to TH = –40°C to + 125°C 10,000 — — cycles
T = 25°C — 100,000 —

10 C Data retention5 tD_ret 15 100 — years

1 Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated.
2
The frequency of this clock is controlled by a software setting.
3
These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on

how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical
Endurance for Nonvolatile Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 33

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Chapter 3 Electrical Characteristics and Timing Specifications

3.13 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.

3.13.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 3-16. Radiated Emissions

Level1
Parameter Symbol Conditions Frequency fOSC/fBUS Unit
(Max)

VRE_TEM VDD = 5.0 V 0.15 – 50 MHz 32kHz crystal 30 dBμV

TA = +25oC 20MHz Bus
package type 50 – 150 MHz 32
80 LQFP 150 – 500 MHz 19
Radiated emissions,
electric field 500 – 1000 MHz 7

IEC Level 1 —

SAE Level 4 —

1 Data based on qualification test results.

3.13.2 Conducted Transient Susceptibility

Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below the table.

MC9S08AC128 Series Data Sheet, Rev. 1

34 Freescale Semiconductor

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 Chapter 3 Electrical Characteristics and Timing Specifications

Table 3-17.

Parameter Symbol Conditions fOSC/fBUS Result Amplitude1 Unit

(Min)
A TBD
VDD = 5.5V 4MHz
B TBD
Conducted susceptibility, electrical TA = +25oC crystal
VCS_EFT kV
fast transient/burst (EFT/B) package type 20MHz Bus
C TBD
80 LQFP
D TBD

1
Data based on qualification test results. Not tested in production.

The susceptibility performance classification is described in Table 3-18.

Table 3-18. Susceptibility Performance Classification

Result Performance Criteria

A No failure The MCU performs as designed during and after exposure.

B Self-recovering The MCU does not perform as designed during exposure. The MCU returns
failure automatically to normal operation after exposure is removed.

C Soft failure The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.

D Hard failure The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.

E Damage The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 35

Preliminary — Subject to Change

Chapter 3 Electrical Characteristics and Timing Specifications

MC9S08AC128 Series Data Sheet, Rev. 1

36 Freescale Semiconductor

Preliminary — Subject to Change

Chapter 4
Ordering Information and Mechanical Drawings
4.1 Ordering Information
This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering
system.
Table 4-1. Device Numbering System

Memory Available Packages2

Device Number1
FLASH RAM Type
MC9S08AC128 128K 8K 80 LQFP, 64 QFP, 44-LQFP
MC9S08AC96 96K 6K 80 LQFP, 64 QFP, 44-LQFP
1 See Table 1-1 for a complete description of modules included on each device.
2
See Table 4-2 for package information.

4.2 Orderable Part Numbering System

MC 9 S08 AC 128 C XX E

Status Pb free indicator

(MC = Fully Qualified) Package designator (See Table 4-2)
Memory Temperature range
(9 = FLASH-based) (C = –40°C to 85°C)
Core (M = –40°C to 125°C)
Family Approximate memory size (in KB)

4.3 Mechanical Drawings

Table 4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 4-2, or
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from
Table 4-2) in the “Enter Keyword” search box at the top of the page.

Table 4-2. Package Information

Pin Count Type Designator Document No.

80 LQFP LK 98ASS23237W
64 QFP FU 98ASB42844B
44 LQFP FG 98ASS23225W

MC9S08AC128 Series Data Sheet, Rev. 1

Freescale Semiconductor 37

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 MC9S08AC128 MCU Series Data Sheet, Rev. 1
38 Freescale Semiconductor

Preliminary — Subject to Change

Chapter 5
Revision History
To provide the most up-to-date information, the version of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/

The following revision history table summarizes changes contained in this document.

Revision Revision Description of Changes

Number Date

Initial release of a separate data sheet and reference manual. Removed PTH7,
clarified SPI as one full and one master-only, added missing RoHS logo, updated
1 9/2008
back cover addresses, and incorporated general release edits and updates.
Added some finalized electrical characteristics.

MC9S08AC128 MCU Series Data Sheet, Rev. 1

Freescale Semiconductor 39

Preliminary — Subject to Change

Chapter 5 Revision History

MC9S08AC128 MCU Series Data Sheet, Rev. 1

40 Freescale Semiconductor

Preliminary — Subject to Change

Preliminary — Subject to Change
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Preliminary — Subject to Change
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