EE344 DIGITAL

SYSTEMS DESGIN


REFERENCE:



Verilog Syntax
CE303 DIGITAL SYSTEMS II

16 October 2009

Abdullah Mansoor
Dept of Electrical Engineering
NUST School of Electrical Engineering and Computer Sciences (SEECS)
Verilog Syntax
Syntax are rules!! Basic Verilog rules are
similar to Syntax of C language.
Syntax is learned by practice practice
practice Cant be memorized at once!
Synthesis
Automatic refinement and optimization of a
model at a higher level of abstraction to a
structural model at a lower level of abstraction
Currently, synthesis is usually performed from
register-transfer level to gate level, as CAD tool
technology for this level of refinement is quite
mature
Behavioral synthesis (also called high-level
synthesis), from higher levels of abstraction to
RTL, is much less mature, though the subject of
much active development work.

Synthesizable Verilog Syntax
During Synthesis Verilog Code is
transferred to hardware
Only small subset of Verilog Syntax is
synthesizable
Example of non synthesizable Verilog
syntax:
Real data type variables
Loop statement
Commenting
Two Methods similar to C
Commenting a Line: Add // before your line
Example:
//this is code for myMux
module myMux(out, a ,b);
..
endmodule
Commenting a pragraph/line: Add /* in the beginning and */ at the end of the
paragraph which is to be commented
Example:
/*this is code for myMux
It implements 2-to1 Mux*/
module myMux(out, a ,b);
..
endmodule


Logic Values in Verilog
Verilog has 4 logic Values
Value
Level
Condition in
Hardware
Circuit
Example
0 Logic Low 1b0
1 Logic High 1b1
x Unknown 1bx
z High Impedance,
Open Circuit
1bz
Number Specification
There are two type of number specification in Verilog:
Sized and Unsized
Sized: Represented in terms of number of bits
<size><base format><numbers>
Base format:
b or B binary Example: 4b1111 //4 bit binary
d or D decimal Example: 6d32 //6 bit decimal
h or H hexadecimal Example: 12habc //12 bit hexadecimal
o or O Octal Example: 1o7 // 1 bit octal
Unsized: Default number of bits that aresmulator or machine
specific are specified i.e 32
23 // This is a 32 bit number . Default base format is decimal
hc3 // This is a 32 bit hexadecimal
o21 // This is a 32 bit octal


Negative Numbers
Negative numbers stored as 2s
complement
Example:
-6d3 // 8 bit Negative number stored as 2s complement of 3
Data Types
To represent intermediate interconnects,
numbers, or variables different kinds of
Data types are available:
Nets
Registers
Vectors
Integer, Real, Time
Nets
Net represent the class of data types which are
used to represent interconnection between
hardware elements
wire: most commonly/simple interconnect
Example: wire a, b;
tri, trireg: for wires with multiple drivers
Example: tri out;
triand, trior, wand, wor: for wires with multiple drivers
with different set of logic preference
Advance type of nets used
in specific applications only
Nets are commonly used
as wires for interconnects
Registers
Registers are used to represent data storage element.
Register type data varaibles can hold its value untill
another value is placed onto them
From hardware/synthesis perspective it could be either
latch or flip flop depending on the code
Example:
reg reset; // declare a variable reset that can hold its value
initial begin
reset=1b1;
#100 reset=1b0;
end
Nets and registers are the
most commonly used data
types in RTL and Gate
level modeling
Registers are commonly
used as variables
Vectors
Registers or Nets can be defined as vector
or arrays (multiple bit widths)
Example:
wire [7:0] bus1; //wire[7] is MSB and wire[0] is LSB
//Litte Endian Notation
wire [0:7]bus2; //wire[0] is MSB and wire[7] is LSB
//Big Endian Notation
reg [7:0] mem1; //same rules as discussed above
Integer and Real
Same as C
Example:
integer i;
for (i=1; i<10; i++) begin
//code
End

Synthesis tools
typically do not
support use of
real numeric
values and
operations, since
the hardware
required to
implement them is
much more
complex than that
for integer types

Time
Time Data type can be used to access
Verilog Simulation time
Example:
time save_sim_time;
initial begin
save_sim_time = $time;
end

Arrays
Arrays data type can be used to define one-
dimension or multi-dimension array of any of the
above data types e.g. nets, registers, integer, real,
time etc.
Examples:
integer count[0:7];
integer matrix[0:7][0:10];
wire [7:0] wirearray [5:0]; // Declare an array of 8 bit vector wire
reg [7:0] mem1 [0:31]; //32 lines memory with 8 bit Word size



Strings
Strings are used to represent ASCII characters
Example:
reg [18*8:1] string_Value;
initial begin
string_value=Hello Verilog World;
end
Strings can be set in different format using following
syntax
%d or %D display decimal Example: $display(no . Of students = %d, count);
%b or %B display binary Example: $display(binary code of 4 is %b, 4);
%s or %S display string Example: $display(%s, array_of_chs);
%c or %C display character Example: $display(%s, character)



Parameters
Like constants in C
Parameters can only initialized when instantiating modules and they
cannot be used as variables
Example:
module memory (dataout, datain);
Parameter size=2**5-1;
Reg [7:0] mem [size:0];
/*here is the implementation of memory circuit */
endmodule
Now if we want to instantiate memory with different size then can use
two methods to initialize different values of the parameter
Method1: memory Mem1 #(63) (dataout, datain);
Method2: defparam Mem1.size=63
memory Mem1 (dataout, datain);

System Task
System Tasks
$display: for display data on computer window during
simulation Example: $display(Hello World);
$display can also be used to display values of variables
or strings using Format Specifiers
%d or %D display decimal Example: $display(no . Of students = %d,
count);
%b or %B display binary Example: $display(binary code of 4 is %b, 4);
%s or %S display string Example: $display(%s, array_of_chs);
%c or %C display character Example: $display(%s, character)
System Task
$time: displays simulation time Example:
$display($time);
$monitor: display variable whenever it changes its
value Example: $monitor(%b, outwire);
$monitoroff: disables $monitor system task
$stop: stops simulation time
$finish: terminates simulation
Compiler Directive
Compiler Directives
define: for defining constants unlike
parameter it can never be changed
Example: define size 24
include: for including verilog code writing in
another file in to the current file
Example: include myMux.v
Operator Types

Operator Types

Conditional Statements
If else statements: Syntax
if (<expression>) begin
//multiple statements
end else if (<expression>)
//single statement
else
//single statement
end
Loops
While Loop
while (<expression is true>) begin
//statements
end
For Loop
integer i;
for (i=1; i<10; i++) begin
//statements
end
Repeat Loop
repeat (<No of times>) begin
//statements
end
Forever Loop
#10 forever clock=~clock;

Reference
Verilog HDL by Samir Palnitkar
Sec 3.1, 3.2, 3.3
Sec 6.4
Sec 7.4, 7.5, 7.6
Thank you!