1 2-

Agenda
2006 Synopsys, Inc. All Rights Reserved Synopsys 30-I-011-SSG-009
Understanding Scan Testing
1
DFTC User Interfaces
2
DFT for Clocks and Resets
4
Creating Test Protocols
3
DAY
1
2 2-
Unit Objectives
After completing this unit, you should be able to:
Create the setup file for DFTC
Specify the target library
Read an RTL design into DFTC
Explore a DFTC design in Design Vision

3 2-
Step 1: Read RTL Design
DFT Check
Test-Ready Compile
Timing, Area
Read RTL Design
Violations? Create Test Protocol
Constraints
Met?
DFT Check
Specify Scan Paths
Preview
Coverage
Insert Scan Paths
Read Design and
Test Protocol Violations?
Violations?
Handoff Design
Unmapped
DFT Flow
Mapped
DFT Flow
Start
End
4 2-
DFTC has Four Tool Environments
DC Shell
Design Vision (GUI)
PC Shell
PC GUI
In classic DB and
new XG mode
5 2-
Chapter Overview
Technology
Libraries
DC Setup File
6 2-
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] = 16h0000;
HDL Source
Generic Boolean
(GTECH)
Translate (read_verilog
read_vhdl
acs_read_hdl)
Target Technology
Optimize + Map
(compile)
Synthesis = Translation + Logic Optimization + Mapping
What is Logic Synthesis
Timing and
Area
constraints
source
7 2-
Your ASIC vendor must provide a DC-compatible
technology library for synthesis!
Technology Library
3 steps involved in synthesis:
Translation
Logic Optimization
Mapping

When DC maps a circuit, how will it know
which cell library you are using?
How will it know the timing of your cells?
8 2-
set target_library my_tech.db
Target Library Variable
The Target Library is the library used by Design
Compiler for building a circuit
During mapping, DC will:
Choose functionally correct gates from this library
Calculate the timing of the circuit using vendor supplied
timing data for these gates
target_library is a reserved variable in DC:
Set it to point to the library file provided by your silicon
vendor
9 2-
1. DC loads the files specified by the link_library
variable when reading netlist, .db or .ddc files.
2. During link, DC searches its memory for designs with
names matching the subdesign and DC searches for
library cells with names matching the leaf-cells.
3. If link still cannot resolve the reference, DC searches all
the UNIX directories defined in the search_path variable
for a .db or .ddc file whose name matches the leaf-cell or
subdesign name.
"*" is
DC Memory
Target
Library
Link Library Variable
set link_library "* my_tech.db"
Is used to resolve netlist leaf-cells and subdesign
references.
10 2-
Example
UNIX% cd risc_design
UNIX% dc_shell-xg-t
dc_shell-xg-t> set target_library my_tech.db
dc_shell-xg-t> set link_library "* my_tech.db"
dc_shell-xg-t> read_verilog rtl/ALU.v
Loading db file standard.sldb
Loading db file gtech.db
Loading db file my_tech.db
Loading verilog file rtl/ALU.v
Current design is now ALU
ALU.v
module ALU (A,B,OUT1);
input A, B;
output [1:0] OUT1;
always @(A or B)
begin . . .
bob/ my_tech.db
DECODE.ddc
rtl/
TOP.v
ALU.v
risc_design
11 2-
How do you tell DC to find DECODE.ddc in bob?
dc_shell-xg-t> set target_library my_tech.db
dc_shell-xg-t> set link_library "* my_tech.db"
dc_shell-xg-t> read_verilog rtl/ALU.v
dc_shell-xg-t> read_verilog rtl/TOP.v
dc_shell-xg-t> current_design TOP
dc_shell-xg-t> link
Unable to resolve reference DECODE in TOP
TOP.v
module TOP (A,B,OUT1);
input A, B;
output [1:0] OUT1;
ALU U1 (.AIN (A), . .
DECODE U2 (.A (BUS0), . .
bob/ my_tech.db
DECODE.ddc
rtl/
TOP.v
ALU.v
risc_design
Use link to Resolve Design References
12 2-
Set the search_path Variable
TOP.v
module TOP (A,B,OUT1);
input A, B;
output [1:0] OUT1;
ALU U1 (.AIN (A), . .
DECODE U2 (.A (BUS0), . .
dc_shell-xg-t> set target_library my_tech.db
dc_shell-xg-t> set link_library "* my_tech.db"
dc_shell-xg-t> lappend search_path bob
dc_shell-xg-t> read_verilog rtl/ALU.v
dc_shell-xg-t> read_verilog rtl/TOP.v
dc_shell-xg-t> current_design TOP
dc_shell-xg-t> link
Loading ddc file bob/DECODE.ddc
bob/ my_tech.db
DECODE.ddc
rtl/
TOP.v
ALU.v
risc_design
link only automatically loads db and ddc files,
not Verilog or VHDL files.
!
13 2-
Chapter Overview
Technology
Libraries
DC Setup File
14 2-
.synopsys_dc.setup
.synopsys_dc.setup .synopsys_dc.setup
$SYNOPSYS/admin/setup ~user
DC startup directory
Users Specific
Project Setup
Users General
Setup
Standard
Setup
1
3
2
./command.log
command
log
% design_vision >& dv.log &
complete
log of DV
session
Design Compiler Three Initialization Files
15 2-
# synopsys setup file
set target_library core_slow.db
set link_library "* core_slow.db"

set symbol_library core.sdb
lappend search_path ./unmapped

alias h history

Commands in .synopsys_dc.setup
are executed upon tool startup.
.synopsys_dc.setup
16 2-
From the above specification, define the library
setup variables:

set target_library __________________

set link_library __________________

set symbol_library __________________
Clock Speed 250 MHz (4ns)
Voltage 1.8V 0.18V
Operating Temperature 0 C to 125 C
Technology Library core_slow.db
Symbol Library core.sdb
Exercise: Specifications
17 2-
DFTC UI Enhancements in XG Mode
Streamlined command set for DFT specifications
and execution
One command for DFT signal specification for scan
signals, test clocks, resets: set_dft_signal
DRC, Preview and DFT insertion commands remain
the same
Test design rule checking: dft_drc
DFT architecture preview: preview_dft
DFT insertion: insert_dft
18 2-
Command Consolidation in DFTC XG Mode
set_scan_signal
create_test_clock
set_test_hold
set_dft_signal
set_signal_type
set_dft_signal
DB Mode XG Mode
check_scan
check_test
check_dft
dft_drc
rtldrc
dft_drc
insert_scan
insert_test
insert_dft
insert_dft
19 2-
Set/Reset/Remove Command Convention
Ability to remove and reset specifications
All DFT specification commands in XG mode have
corresponding reset_* and remove_* commands
reset_* restores settings back to default
remove_* removes the specification
Examples:
set_dft_configuration reset_dft_configuration
set_dft_signal remove_dft_signal
set_scan_path remove_scan_path
This enables easier debug and DFT architecture exploration
20 2-
Report/Set Command Correspondence
Ability to report specifications
All DFT specification commands in XG mode
have corresponding report_* commands
Examples:
set_dft_configuration report_dft_configuration
set_dft_signal report_dft_signal
set_scan_path report_scan_path
This makes it easy to report on whether the specification was
accepted
21 2-
DFT Views: New Flexibility for XG
In the context of DFT Compiler, there are two views
Specification: DFT structures that DFT Compiler should
use for insert_dft ( -view spec )
Existing_DFT: DFT structures which already exist that
must be understood for the design to pass DRC
dft_drc ( -view exist )
DFT views used extensively in XG-mode command
(set_dft_signal)
The default is -view spec

22 2-
existing_dft View in XG Mode
The existing_dft view describes structures
which already exist that must be understood for the
design to pass DRC (dft_drc)
Clocks, Resets,Constants or scan_in,out,enable.

test_so test_si
test_se
clock
atpgmode
resetn
black box
23 2-
How to Specify a Scan In
set_dft_signal \
-type ScanDataIn \
-port test_si \
-hookup_pin U1/Z
The DFT Signal type
Top level port to use
Hookup point: omit if you want
to connect directly to port





Old command was
set_scan_signal
test_si
test_se
test_so
U1
Z
24 2-
How to Specify a Scan Out
set_dft_signal \
-type ScanDataOut \
-port test_so \
-hookup_pin U2/A
The DFT Signal type
Top level port to use
Connection point



Old command was
set_scan_signal
test_si
test_se
test_so
U2
A
25 2-
How to Specify a Scan Enable
set_dft_signal \
-type ScanEnable \
-port test_se \
-hookup_pin U3/Z \
-active_state 1
The DFT Signal type
Top level port to use
Connection point
optional (default is 1)
Old command was
set_scan_signal
test_si
test_se
test_so
U3
Z
26 2-
How to Specify a Clock
set test_default_delay 100
set_dft_signal view existing_dft \
-type ScanClock \
-port clock timing [list 45 55]

Old command was
create_test_clock
test_si
test_se
test_so
clock
atpgmode
resetn
black box
27 2-
How to Specify a Reset
set_dft_signal view existing_dft \
-type Reset \
-port resetn active_state 0
Old command was
set_signal_type
test_so
clock
resetn
black box
test_si
test_se
28 2-
How to Specify a Constant
set_dft_signal view existing_dft \
-type Constant \
-port atpgmode active_state 1
Old command was
set_test_hold
test_so
clock
resetn
black box
test_si
test_se
atpgmode
29 2-
How to specify an existing scan_enable
set_dft_signal view existing_dft \
-type ScanEnable -port test_se \
active_state 1 (default is active 1)
test_se
clock
clock
gate cell
Old command was
set_signal_type
30 2-
Tying Things Together
read_file -f verilog rtl.v
current_design top
link
set_scan_configuration -style multiplexed_flip_flop
compile -scan
set_dft_signal view existing_dft -type ScanClock \
-port clk -timing [list 45 55]
set_dft_signal -view existing_dft -type Reset \
-port resetn -active_state 0
set_dft_signal -type ScanDataIn -port test_si
set_dft_signal -type ScanDataOut -port test_so
set_dft_signal -type ScanEnable -port test_se
create_test_protocol
dft_drc
preview_dft
insert_dft
change_names rules verilog -hier
write f ddc hier o scanned.ddc
write f verilog hier o scanned.v
write_test_protocol o scanned.spf
dft_drc
report_scan_path view existing_dft chain all
31 2-
Converting Old Scripts to DFTC XG Mode
Migrate to TCL
Migrate to Unified TestDRC
this workshop uses the UDRC TCL flow throughout
Use translation utility (db2xg) to assist in
converting DB-mode scripts to XG-mode
Utility translates commands, not flows
Translates set_test_hold, set_scan_signal
Will not translate insert_scan, check_scan, check_dft
32 2-
db2xg Conversion Utility
Perl translation utility available from:
SolvNet
Using db2xg to convert DFT Compiler command scripts
from regular mode to DC-XG mode SolvNet Id: 013060
https://solvnet.synopsys.com/retrieve/013060.html
2005.09 Synthesis release tree
$SYNOPSYS/auxx/syn/dftc/db2xg
Notes:
Needs Perl installed and in search path
Review and verify results after using translation utility
33 2-
Unit Objectives Review
You should now be able to:
Specify the target library
Create the setup file for DC
Read an RTL design into DFTC
Explore a DFTC design in Design Vision
Name at least two XG UI commands
34 2-
Lab 2: Introduction to Design Vision
After completing this lab, you should be able to:
Read a design and related files into Design
Vision, the graphical interface to Design for
Test Compiler (DFTC)
Compile that design into a test-ready design
Explore that design in Design Vision
Save the test-ready design
45 minutes