Overview
Why VLSI?
Moores Law.
The VLSI design process.
Why VLSI?
Integration improves the design:
lower parasitics = higher speed;
lower power;
physically smaller.
Integration reduces manufacturing
cost-(almost) no manual assembly.
VLSI and you
Microprocessors:
personal computers;
microcontrollers.
DRAM/SRAM.
Special-purpose processors.
Moores Law
Gordon Moore: co-founder of Intel.
Predicted that number of transistors
per chip would grow exponentially
(double every 18 months).
Exponential improvement in
technology is a natural trend: steam
engines, dynamos, automobiles.
Moores Law plot
The cost of fabrication
Current cost: $2-3 billion.
Typical fab line occupies about 1 city
block, employs a few hundred
people.
Most profitable period is first 18
months-2 years.
Cost factors in ICs
For large-volume ICs:
packaging is largest cost;
testing is second-largest cost.
For low-volume ICs, design costs may
swamp all manufacturing costs.
The VLSI design process
May be part of larger product design.
Major levels of abstraction:
specification;
architecture;
logic design;
circuit design;
layout.
Challenges in VLSI design
Multiple levels of abstraction:
transistors to CPUs.
Multiple and conflicting constraints:
low cost and high performance are
often at odds.
Short design time: Late products are
often irrelevant.
Dealing with complexity
Divide-and-conquer: limit the number
of components you deal with at any
one time.
Group several components into larger
components:
transistors form gates;
gates form functional units;
functional units form processing elements;
etc.
Hierarchical name
Interior view of a component:
components and wires that make it up.
Exterior view of a component = type:
body;
pins.
cout
a
b
Full
adder
cin
sum
Instantiating component
types
Each instance has its own name:
add1 (type full adder)
add2 (type full adder).
Each instance is a separate copy of
the type:
cout Add2.a
Add1.a
a Add1(Full
adder)
b
sum
a Add2(Full
adder)
b
cin
cin
sum
A hierarchical logic design
box1
box2
Net lists and component
lists
Net list:
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Component list:
top: in1=net1
n1=topin1 n2=topin2
n3=topine
out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1
xin2=topin2
xin3=botin1 B=net2
out=net3
i2: in=net3 out=outnet
Component hierarchy
top
i1
xxx
i2
Hierarchical names
Typical hierarchical name:
top/i1.foo
component
pin
Layout and its abstractions
Layout for dynamic latch:
Stick diagram
Transistor schematic
Mixed schematic
inverter
Levels of abstraction
Specification: function, cost, etc.
Architecture: large blocks.
Logic: gates + registers.
Circuits: transistor sizes for speed,
power.
Layout: determines parasitics.
Circuit abstraction
Continuous voltages and time:
Digital abstraction
Discrete levels, discrete time:
Register-transfer abstraction
Abstract components, abstract data types:
0010
+
0001
+
0100
0011
Top-down vs. bottom-up
design
Top-down design adds functional
detail.
Create lower levels of abstraction from
upper levels.
Bottom-up design creates
abstractions from low-level behavior.
Good design needs both top-down
and bottom-up efforts.
Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
registertransfer
logic
transistors
circuit
rectangles
layout
Throughput,
design time
Function units,
clock cycles
Literals,
logic depth
nanoseconds
microns
cost
Design validation
Must check at every step that errors
havent been introduced-the longer
an error remains, the more expensive
it becomes to remove it.
Forward checking: compare results of
less- and more-abstract stages.
Back annotation: copy performance
numbers to earlier stages.
Manufacturing test
Not the same as design validation:
just because the design is right
doesnt mean that every chip coming
off the line will be right.
Must quickly check whether
manufacturing defects destroy
function of chip.
Must also speed-grade.
