Synchronous

Sequential Logic

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Sequential logic circuit

State Machine (SM)
Finite State Machine (FSM)

NS

Combinational
Circuit

Clock

n
Flip-Flops

PS

Outputs

Inputs

2n possible states

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Memory
0
Q

1
Q

0
Q

Flip-flop circuits are binary cells capable of storing one bit

of information.
Flip-flop circuits can maintain a binary state indefinitely (as
long as power is connected to the circuit) 4
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Latches
Q
1

Q'

1
2

Q'

Q
Q

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RS Latch
R

PS/NS table

Q'

S Set Store 1
R Reset Store 0
PS Present State Q
NS Next State what will next
be stored in the flip-flop
Q+

S R PS
(Q)
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

NS
(Q+)
0
1
0
0
1
1
In determinate
In determinate
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Characteristic Table

Q
Q

S R

Operation

0 0
0 1

hold
reset

1 0
1 1

set
Not allowed

Characteristic Equation:
Q+ = [(Q + S) + R] =(Q+S) . R = Q . R + S . R

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S'

1
2

R'

S R

Operation

Q'

0 0
0 1

Not allowed
set

1 0
1 1

reset
hold

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RS Latch application
switch debouncing
VCC

Switch is closed
At this moment

Switch
debounces
for several
milliseconds

In many applications contact bounce cannot be tolerated.

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S'
VCC

SPDT

1
2

1
2

Q'

R'
S
R

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Gated

G
0
1

Y
0
X

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Gated RS Latch
1

Q'

G
1

1
3

G
S

1
2

S'

1
2

Q'

G
1

1
4

R'
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Timing diagram
G

R
S
Q

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Gated D Latch
Transparent D Latch
Level-sensitive flip-flop
S

1
2

S'

1
2

Q'

G
1
1

G
Q

1
4

R'
Characteristic Table

G D operation
0x
hold
10
reset
11
set

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Timing diagram
G
D
Q

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module D_latch(D, G, Q);

input D, G;
output Q;
reg Q;
always @(D or G)
if (G)
Q = D;
endmodule

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Synchronous sequential circuits

In the level-sensitive latches, the state of the latches keep
changing according to the input signals while the gate is
asserted. However in synchronous sequential circuits the
storage elements must not change their states more than
once during one clock cycle.
NS

Combinational
Circuit
Inputs

Clock

PS

n
G Flip-Flops
Outputs

There is a feedback from flip-flops to the combinational

circuit. This path can produce instability if the output of flipflops are changing while the output of the combinational
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Circuit that go to flip-flop inputs are being sampled by

the clock pulse. This timing problem can be prevented if
the output of flip-flops do not start changing until the
pulse input has returned to zero. To ensure such an
operation, a flip-flop must have a signal propagation
delay from input to output in access of the pulse
duration.
One way to satisfy the requirement of synchronous
sequential circuits is to narrow the clk pulse. The pulse
must be long enough to allow the output to obtain a new
value but not too long for a new output signal to be
generated and fed back.

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Pulse-narrowing
1

clk

pulse

clk'
clk
Clk
pulse

= gate delay

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clk

pulse

clk'

clk
Q

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Edge-Triggered D flip-flop using Master-Slave

The second method of ensuring that the D storage element
will change state only once during each clock cycle is using
the Master-slave circuit.
master
D

clk

slave

Qm

Qs

clk
Q

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master
D

clk

Qm

D
G

slave

Qs

clk
Q

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clk
D
Qm
Q

Regardless of the number of changes in the D input to the master stage

during one clock cycle, the Qs will see only the change that corresponds to
the D input at the negative edge of the clock. The setup and hold times
constrains must be observed when using this device, Notice that while the
master is responding to the input the slave holds the current content of the
flip-flop. This is important when the output of one flip-flop (first) is feeding
into another flip-flop (second). Thus the second flip-flop will respond to what
was stored in the first flip-flop not the new value.
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Edge-Triggered D flip-flop using three SR Latches

The third method of ensuring that the D storage element will change state
only once during each clock cycle is the following circuit. This circuit uses less
transistors than the master-slave flip-flop

clk
Q

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If the clock is low, both the output signals of the input stage are high
regardless of the data input; the output latch is unaffected and it stores the
previous state. When the clock signal changes from low to high, only one of
the output voltages (depending on the data signal) goes low and sets/resets
the output latch: if D = 0, the lower output becomes low; if D = 1, the upper
output becomes low. If the clock signal continues staying high, the outputs
keep their states regardless of the data input and force the output latch to stay
in the corresponding state as the input logical zero remains active while the
clock is high. Hence the role of the output latch is to store the data only while
the clock is low.

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Typically a crystal oscillator produces a fixed sine wavethe frequency

reference signal. Electronic circuitry translates that into a square wave at
the same frequency for digital electronics applications

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Gated latch versus Edge-Triggered

flip-flop
D

Qa

clk

G
D

Q
D
D

Qa
Qb

clk

Qb
Q
Qc

D
clk

clk

Qc

Q
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Excitation table of D flip flop

D

clk
Q

PS
0
0
1
1

NS
0
1
0
1

D
0
1
0
1

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Verilog Description
module flipflop(D, Clk, Q);
input D, Clk;
output Q;
reg Q;
always @(posedge Clk)
Q<= D;

clk
Q

endmodule

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D flip-flop with asynchronous reset

module flipflop(D, Clk, Reset, Q);
input D, Clk, Reset;
output Q;
reg Q;

clk
Reset

always @(negedge Reset or posedge Clk)

if (!Reset)
Q <= 0;
else
Q <= D;
endmodule
If one signal in the sensitivity list uses posedge/negedge, then all signals
must.
Assign any signal or variable from only one always block, always blocks
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execute in parallel
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D flip-flop with synchronous reset

module flipflop(D, Clk, Reset, Q);
input D, Clk, Reset;
output Q;
reg Q;
always @(posedge Clock)
if (!Reset)
Q <= 0;
else
Q <= D;

clk
Reset

endmodule
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State Diagram and ASM chart

A graphical way of describing a sequential logic circuit
State Diagram

State
name
State

transition

Algorithmic State Machine

(ASM) chart
State name
condition
State box

Decision box

Conditional output box

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State-diagram and ASM chart

of a D flip-flop
0
1

D
1

0
State diagram

1
D
0
ASM chart
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1-bit register
data
Q
load 1-bit
clk

load

data

Load data
0x

clk

Q+

0x

11
1

0
10

11

10

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State/Excitation table
P.S.

inputs

N.S.

load

data

Lo
ad Q
da
ta

00

01

11

10

D load Q loaddata

data
load

I0
I1
s

clk

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n-bit register
Data[0]
load
n
data
Q
load n-bit
clk

I0
I1
s

D
clk

Data[n-1]
load

Q[0]

I0
I1
s

Q[n-1]

clk
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Register
A flip-flop stores one bit of information. When a set of n flipflops is used to store n bits of information, we refer to these
flip-flops as a register
L clk operation

QQ
QI

0
1
I2

I3

I1 I0
S

I1 I0
S

D Q

I0

I1

I1 I0
S

I1 I0
S

D Q

D Q

D Q

clk
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Q3

Q2

Q1

Q0

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Verilog Description
module reg4(I,L,clk,Q);
input L, clk;
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
always @ (posedge clk)
begin
if(L)
Q <= I;
else
Q <= Q;
end
endmodle

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Shift Register
clk operation
SHR(Q)

D Q

D Q

D Q

D Q

clk
Q3

Q2

Q1

I clk Q3 Q2 Q1 Q0
0

Initial state

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Q0

Verilog Description
module reg4(I,clk,Q);
input I, clk;
output [3:0] Q;
reg [3:0] Q;
always @ (posedge clk)
Q < = {I,Q[3:1};
endmodle

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Shift Register
SHL clk operation
0
QQ
1
SHL(Q)
SISHL

SHL

I1 I0
S

I1 I0
S

D Q

I1 I0
S

I1 I0
S

D Q

D Q

D Q

clk
Q3

Q2

Q1
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Q0

Verilog Description
module reg4(SISHL,SHL,clk,Q);
input SISHL, SHL, clk;
output [3:0] Q;
reg [3:0] Q;
always @ (posedge clk)
begin
if(SHL)
Q <={Q[2:0] , SISHL} ;
else
Q <= Q;
end
endmodle
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Shift Register
S

clk

I
4

operation

00

QQ

01

SHL(Q)

10

SHR(Q)

11

Load

SISHR

SISHL

clk

SISHR

I3

SISHL

I3 I2 I1 I0
S

I2

I1

I0

I3 I2 I1 I0
S

I3 I2 I1 I0
S

I3 I2 I1 I0
S

D Q

D Q

D Q

D Q

clk
Q3

Q2

Q1

Q0

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module GPR(clk,SISHL,SISHR,S,I,Q );
parameter n=4;
input clk,SISHL,SISHR;
input [1:0] S;
input [n-1:0]I;
output reg [n-1:0] Q=0;
always@(posedge clk)
case(S)
0: Q<=Q;
1: Q<= {Q[n-2:0],SISHL};
2: Q<= {SISHR,Q[n-1:1]};
3: Q<= I;
endcase
endmodule
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module testregister;
// Inputs
reg clk;reg SISHL;reg SISHR;reg [1:0] S;reg [3:0] I;
// Outputs
wire [3:0] Q;
localparam [7:0] period=1;
// Instantiate the Unit Under Test (UUT)
GPR uut (.clk(clk),.SISHL(SISHL),.SISHR(SISHR),.S(S),.I(I),.Q(Q));
//clk
initial
begin
clk=0;
forever # (period/2.0) clk=~clk;
end
//testing
initial
begin
// Initialize Inputs
SISHL = 0;SISHR = 0;S = 0;I = 0;
# period S = 3;I = 14; //load
# period S=0; I=0;
//hold
# period S=2;
//Shift right
# (period*2) S=1;
//Shift left
# (period*2) S=0;
//hold
end

always
begin
clk<=0; #(period/2.0);
clk<=1; #(period/2.0);
end

endmodule

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Register Applications
1. Store Data
2. Shift Data left (Multiply by powers of 2)
3. Shift Data right (Divide by powers of 2)
4. Convert parallel data to serial
5. Convert serial data to parallel

>>

logical right shift (filling the most significant bit with 0)

<<

logical left shift (filling the least significant bit with 0)

>>>

arithmetic right shift (filling the most significant bit with the original
value of the most significant bit, in order to retain the sign)

<<<

arithmetic left shift (filling the least significant bit with 0)

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Analysis
1

2
1
2

4
1
4

Q
D

clk
Q

clk

D = Q.T + Q . T

This circuit is called the T flip-flop

T
0
0
1
1

PS
0
1
0
1

D NS
0 0
1 1
1 1
0 0

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T flip-flop
T

Q
clk
Q

Excitation table

PS NS
0
0
1
1

0
1
0
1

T
0
1
1
0

Characteristic Table

operation

hold

toggle
Truth table or

Characteristic equation
Q+ = T Q + T Q

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0
1

0
0

T
1

State diagram
0
T

clk
T

1
ASM chart

Q
Timing diagram

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2-bit Binary Counter using T flip-flops

clk

Binary Counter

11

10

01

00

2
Q

T1= Q0 , T0=1
T

clk

VCC

clk

Q1

Q0

clk
Q1
Q0
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PS
Q1 Q0

NS
Q1 Q0

T1 T0

0 1

1 1

0 1

1 1

Verilog description
2-bit Counter
module upcount(Clk, Q);
input Clk, ;
output [1:0] Q;
reg [1:0] Q;
always @(posedge Clk)
Q <= Q + 1;
endmodule

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clk
reset

Binary Counter

n
Q

//n-bit counter
module counter(reset,clk,Q);
parameter n=4;
input clk,reset;
output [n-1:0] Q;
reg [n-1:0]Q;
initial Q=0;
always@(posedge clk)
if(reset)
Q<=0;
else
Q <= Q + 1;
endmodule
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`timescale 1ns/10ps
module counter_test_v_tf();
// Inputs
reg reset;
reg clk;
// Outputs
wire [1:0] Q;
// Instantiate the UUT
counter uut (
.reset(reset),
.clk(clk),
.Q(Q)
);

// Initialize Inputs
initial
begin
reset = 0;
clk = 0;
forever
#1 clk=~clk;
end
initial
begin
#2 reset=1;
#2 reset=0;
end
endmodule

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Describing counters using Verilog

4-bit up-counter with parallel load
4

I
Q

clk

L
E
Reset
Asynchronous reset

Reset
0
1
1
1

L
x
1
0
0

E CLK Q
x x
0
x
I
1 Q+1
0
Q

module upcount(I, Reset, Clk, E, L, Q);

input [3:0] I;
input Reset, Clk, E, L;
output [3:0] Q;
reg [3:0] Q;
always @(negedge Reset or posedge Clk)
if (!Reset)
Q <= 0;
else if (L)
Q <= I;
else if (E)
Q <= Q + 1;
endmodule

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Describing counters using Verilog

8-bit down-counter with parallel load
8

I
clk

module downcount(I, Clk, E, L, Q);

parameter n=8;
input [n-1:0] I;
input Clk, L, E;
output [n-1:0] Q;
reg [n-1:0] Q;

L
E

L
1
0
0

E CLK
x

Q
I
Q-1
Q

always @(posedge Clk)

if (L)
Q <= I;
else if (E)
Q <= Q - 1;
endmodule
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Describing counters using Verilog

8-bit up/down counter with parallel load
8

I
clk

L
E
UD

L
1
0
0
0

E
x
0
1
1

UD CLK Q
x

I
x
Q
1
Q+1
0
Q-1

`timescale 1ns / 1ps

module UDCounter(I, Clk, L, E, UD, Q);
parameter n=3;
input [n-1:0] I;
input Clk, L, E, UD;
output [n-1:0] Q;
reg [n-1:0] Q=0;
always @(posedge Clk)
begin
if (L)
Q <= I;
else if (E)
if (UD)
Q <= Q + 1;
else
Q <= Q - 1;
end
endmodule
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`timescale 1ns / 1ps

module testud;
reg [2:0] I;reg Clk;reg L;reg E;reg UD;
wire [2:0] Q;
UDCounter uut (I,Clk,L,E,UD,Q);
initial begin
Clk = 0;
forever #0.5 Clk=~Clk;
end
initial begin
I = 0;L = 0;E = 0;UD = 0;
#2 UD=1; E=1;
#5 UD=0;
#3 L=1; I=6;
#1 L=0;
end
endmodule
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Counter
S

clk

module GPC(clk, S, I, Q);

parameter n=4;
input clk;
input [1:0] S;
input [n-1:0]I;
output reg [n-1:0] Q;

operation

00

Hold

01

QQ+1

10

QQ-1

11

Load

I
n

clk
n

always @(posedge clk)

case(S)
0: Q<= Q;
1: Q<= Q + 1;
2: Q<= Q - 1;
3: Q<= I;
endcase
endmodule

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module testcounter;
// Inputs
reg clk; reg [1:0] S;reg [3:0] I;
// Outputs
wire [3:0] Q;
localparam [7:0] period=1;
// Instantiate the Unit Under Test (UUT)
GPC uut (.clk(clk), .S(S), .I(I), .Q(Q));
// clock
initial begin
clk=0;
forever #(period/2.0) clk=~clk;
end
//testing
initial
begin
S = 0;I = 0;
#period S=3; I=4'd6; //load
#period S=0;
//hold
#period S=2;
//decrement
#(period *2) S=1;
//increment
#(period *2) S=0;
end
endmodule

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Applications of Counters:
1. Count Events
2. Change the rate of change of a signal, such as clk
dividers
3. Time the generation of events
4. Time events
5. Time the time between events

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Analysis
1

J
K

4
1

Q
D

clk
Q

clk

D = J.Q + K.Q

This circuit is called the JK flip-flop

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D = J.Q + K.Q

J
0
0
0
0
1
1
1
1

K PS
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1

D NS
0 0
1 1
0 0
0 0
1 1
1 1
1 1
0 0

Characteristic equation
Q+ = JQ + K Q

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JK flip-flop
J

Q
clk

Characteristic Table
Q

Excitation table

PS NS J K
0
0
1
1

0
1
0
1

0x
1x
x1
x0

J K operation
00

hold

01
10
11

reset
set
toggle
Truth table

Characteristic equation
Q+ = JQ + K Q

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10, 11

00, 01

Inputs=JK

0
00, 10
JK

01, 11

0x

1x

State diagram

JK

clk
J

x0

x1

ASM chart

Timing diagram

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Setup time and hold time

If two inputs are changed nearly simultaneously, a bistable
device may either fail to make the intended PS to NS
transition or go into a temporarily unstable state called a
metastable state and stay in it for an undetermined time.
Vo1
Vi2

Vi1

Vo1, Vi2
Q

Q=1
Metastable state

Vo2

Q=0
Q
Vi1
Vo2

To prevent this from happening, device manufacturers

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Specify a setup time, tsu, and hold time, th, requirements. The
setup time is the time that the D input to a gated D Latch
circuit must be held stable prior to the G input going low. The
hold time is the time that the D input must be held stable after
the G input goes low. If the D input changes too soon before
or after the C input changes from high to low, then the latch
may fail to store the intended value of D.
G
D
Q

tsu

th

For CMOS technology, tsu=3 ns and th = 2 ns.

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