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Switch Level Modeling

Verilog allows modeling circuits at the transistor level using switches defined by keywords like nmos, pmos, cmos, tran, tranif0, tranif1. Switches can be instantiated and connected like logic gates. Power and ground sources supply1 and supply0 are needed. Delays can optionally be specified for switches. More complex circuits like multiplexers, inverters, and XOR gates can be built using a combination of switches.

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venkatesh kumar
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315 views

Switch Level Modeling

Verilog allows modeling circuits at the transistor level using switches defined by keywords like nmos, pmos, cmos, tran, tranif0, tranif1. Switches can be instantiated and connected like logic gates. Power and ground sources supply1 and supply0 are needed. Delays can optionally be specified for switches. More complex circuits like multiplexers, inverters, and XOR gates can be built using a combination of switches.

Uploaded by

venkatesh kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Switch Level Modeling

ECE-419
Switch-Level Modeling
 Verilog provides the ability to design at a MOS-transistor level.
 Design at this level is becoming rare with the increasing complexity of circuits
(millions of transistors) and with the availability of sophisticated CAD tools.
Switch-Modeling Elements:
Two types of MOS switches can be defined with the keywords, nmos and pmos.

data out data out

control control
Contd.
 Instantiation of NMOS and PMOS Switches
 nmos n1 (out, data, control) ; //instantiate a nmos switch
 pmos p1(out, data, control); //instantiate a pmos switch

 Since switches are Verilog primitives, like logic gates, the name of the instance is
optional
Contd.
 CMOS Switches: CMOS switches are declared with the keyword cmos
 A cmos device can be modeled with a nmos and a pmos device.

ncontrol

data out

pcontrol

 cmos c1(out, data, ncontrol, pcontrol); //instantiate cmos


gate.
Contd.
 Bidirectional Switches
 NMOS, PMOS and CMOS gates conduct from drain to source.
 It is important to have devices that conduct in both directions.
 In such cases, signals on either side of the device can be the driver signal.
 Three keywords are used to define bidirectional switches: tran, tranif0, and
tranif1 control
inpout1 inpout2 control inpout1 inpout2
tran tranif0
inpout1 inpout2
tranif1
Instantiation of Bidirectional Switches
 tran t1(inout1, inout2); //instance name t1 is optional
 tranif0(inout1, inout2, control); //instance name is not
specified
 tranif1(inout1, inout2, control); //instance name is not
specified

 Power and Ground:


 The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when
transistor-level circuits are designed
 Power and ground sources are defined with keywords supply1 and supply0.
Power and Ground:
 The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when
transistor-level circuits are designed
 Power and ground sources are defined with keywords supply1 and supply0.

 supply1 vdd;
 supply0 gnd;
 assign a = vdd; //Connect a to vdd
 assign b = gnd; //Connect b to gnd
Example: Inverter

//Define an inverter using MOS switches


module my_not(out, in);
output out;
input in;
//declare power and ground
supply1 pwr;
supply0 gnd;
//instantiate nmos and pmos switches
pmos (out, pwr, in);;
nmos (out, gnd, in);
endmodule
Example: NOR gate

//Define our own nor gate, switchnor


module switchnor (out, a, b) ;
output out;
input a, b;
//internal wires
wire c;
supply1 vdd; //pwr is connected to Vdd (power supply)
supply0 gnd ; //gnd is connected to Vss(ground)
pmos (c, vdd, b);
pmos (out, c, a);
nmos (out, gnd, a);
nmos (out, gnd, b);
endmodule
//stimulus to test the gate
module switchnortb;
reg a, b;
wire out;
switchnor n1(out, a, b);
initial
begin
a= 1'b0; b = 1'b0;
#5 a = 1'b0; b = 1'b1;
#5 a = 1'b1; b = 1'b0;
#5 a = 1'b1; b = 1'b1;
#5 $stop;
end
initial
$monitor($time, " out = %b, a = %b, b = %b",out, a, b);
endmodule
Resistive Switches
 MOS, CMOS, and bidirectional switches discussed before can be modeled as
corresponding resistive devices.
 Resistive devices have a high source-to-drain impedance. Regular switches have a
low source-to-drain impedance.
 Resistive switches are declared with keywords that have an "r“ prefixed to the
corresponding keyword for the regular switch

 rnmos rpmos //resistive nrnos and pmos switches


 rcmos //resistive cmos switch
 rtran rtranif0 rtranif1 //resistive bidirectional
switches.
Delay Specification on Switches
 MOS and CMOS switches
 Delays can be specified for signals that pass through these switch-level elements.
 Delays are optional and appear immediately after the keyword for the switch.
 Example:
 pmos p1(out, data, control);
 pmos #(1) p1(out, data, control);
 nmos #(1, 2) p2(out, data, control);
 nmos #(1, 3, 2) p2(out, data, control);
 cmos #(5) c2(out, data, nctrl, pctrl);
module switchmux(out,s, i0, i1); //Define a 2-to-1 mux using switches
output out;
input s,i0,i1;
wire sbar; //complement of S instantiate cmos switches
snot u(sbar,s);
cmos (out,i0,sbar,s);
cmos (out,i1,s,sbar);
endmodule
module snot(sbar, s);
output sbar;
input s;
supply1 vdd;
supply0 gnd;
nmos (sbar,gnd,s);
pmos (sbar,vdd,s);
endmodule
module switchxor(f,a,b);
module inv(w1,a);
// switch xor input a,b;
input a;
output f;
output w1;
wire w1,w2,w3,w4,w5;
supply1 vdd;
supply1 vdd;
supply0 gnd;
supply0 gnd;
nmos (w1,gnd,a);
nmos (w3,gnd,w2);
pmos (w1,vdd,a);
nmos (f,w3,w1);
endmodule
nmos (w4,gnd,b);
nmos (f,w4,a);
pmos (f,w5,a);
pmos (f,w5,b);
pmos (w5,vdd,w1);
pmos (w5,vdd,w2);
inv n1(w1,a);
inv n2(w2,b);
endmodule

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