18CS2102R

Operating Systems
Session 16
Translation Look aside Buffer

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 1
TLB
• Part of the chip’s memory-management unit(MMU).
• A hardware cache of popular virtual-to-physical address translation.

TLB
Lookup MMU TLB Hit Physical
Logical
Address TLB Address
popular v to p
TLB Miss
Page 0
CPU Page Table
Page 1
all v to p entries
Page 2
…
Page n
Address Translation with MMU
Physical Memory

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TLB Basic Algorithms
1: VPN = (VirtualAddress & VPN_MASK ) >> SHIFT
2: (Success , TlbEntry) = TLB_Lookup(VPN)
3: if(Success == Ture){ // TLB Hit
4: if(CanAccess(TlbEntry.ProtectBit) == True ){
5: offset = VirtualAddress & OFFSET_MASK
6: PhysAddr = (TlbEntry.PFN << SHIFT) | Offset
7: AccessMemory( PhysAddr )
8: }else RaiseException(PROTECTION_ERROR)

• (1 lines) extract the virtual page number(VPN).

• (2 lines) check if the TLB holds the transalation for this VPN.
• (5-8 lines) extract the page frame number from the relevant TLB entry, and form the
desired physical address and access memory.

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TLB Basic Algorithms (Cont.)
11: }else{ //TLB Miss
12: PTEAddr = PTBR + (VPN * sizeof(PTE))
13: PTE = AccessMemory(PTEAddr)
14: (…)
15: }else{
16: TLB_Insert( VPN , PTE.PFN , PTE.ProtectBits)
17: RetryInstruction()
18: }
19:}

• (11-12 lines) The hardware accesses the page table to find the translation.
• (16 lines) updates the TLB with the translation.

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 Example: Accessing An Array
 How a TLB can improve its performance.

OFFSET
00 04 08 12 16

VPN = 00
0: int sum = 0 ;
VPN = 01
1: for( i=0; i<10; i++){
VPN = 03

VPN = 04
2: sum+=a[i];
VPN = 05 3: }
VPN = 06 a[0] a[1] a[2]

VPN = 07 a[3] a[4] a[5] a[6] The TLB improves performance

VPN = 08 a[7] a[8] a[9]
due to spatial locality
VPN = 09
3 misses and 7 hits.
VPN = 10 Thus TLB hit rate is 70%.
VPN = 11

VPN = 12

VPN = 13

VPN = 14

VPN = 15

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Locality
• Temporal Locality
• An instruction or data item that has been recently accessed will likely be re-
accessed soon in the future. 1 access is page1.
st

2nd access is also page1.

Page n
Page 6

Page 7
Page 1

Page 2

Page 3

Page 4

Page 5
…

Virtual Memory
• Spatial Locality
• If a program accesses memory at address x, it will likely soon access memory
near x.
1st access is page1.
2nd access is near by page1.

Page n
Page 1

Page 2

Page 3

Page 4

Page 5
…

Virtual Memory

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Who Handles The TLB Miss?
• Hardware handle the TLB miss entirely on CISC.
• The hardware has to know exactly where the page tables are located in
memory.
• The hardware would “walk” the page table, find the correct page-table entry
and extract the desired translation, update and retry instruction.
• hardware-managed TLB.

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Who Handles The TLB Miss? (Cont.)
• RISC have what is known as a software-managed TLB.
• On a TLB miss, the hardware raises exception( trap handler ).
• Trap handler is code within the OS that is written with the express purpose of handling
TLB miss.

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TLB Control Flow algorithm(OS Handled)
1: VPN = (VirtualAddress & VPN_MASK) >> SHIFT
2: (Success, TlbEntry) = TLB_Lookup(VPN)
3: if (Success == True) // TLB Hit
4: if (CanAccess(TlbEntry.ProtectBits) == True)
5: Offset = VirtualAddress & OFFSET_MASK
6: PhysAddr = (TlbEntry.PFN << SHIFT) | Offset
7: Register = AccessMemory(PhysAddr)
8: else
9: RaiseException(PROTECTION_FAULT)
10: else // TLB Miss
11: RaiseException(TLB_MISS)

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TLB entry
• TLB is managed by Full Associative method.
• A typical TLB might have 32,64, or 128 entries.
• Hardware search the entire TLB in parallel to find the desired translation.
• other bits: valid bits , protection bits, address-space identifier, dirty bit

VPN PFN other bits

Typical TLB entry look like this

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TLB Issue: Context Switching
Page 0
Page 1
Page 2 Insert TLB Entry
access VPN10
Process A …
Page n TLB Table
Virtual Memory VPN PFN valid prot
10 100 1 rwx
- - - -
Page 0 - - - -
Page 1 - - - -
Process B Page 2
…
Page n
Virtual Memory

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 TLB Issue: Context Switching
Page 0
Page 1
Page 2
Process A …
Page n TLB Table
Virtual Memory VPN PFN valid prot
Context 10 100 1 rwx
Switching - - - -
Page 0 10 170 1 rwx
Page 1 - - - -
access VPN10
Process B Page 2
Insert TLB Entry
…
Page n
Virtual Memory

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TLB Issue: Context Switching
Page 0
Page 1
Page 2
Process A …
Page n TLB Table

Virtual Memory VPN PFN valid prot

10 100 1 rwx
- - - -
Page 0 10 170 1 rwx
Page 1 - - - -
Process B Page 2
…
Can’t Distinguish which entry is
Page n meant for which process
Virtual Memory

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To Solve Problem
• Provide an address space identifier(ASID) field in the TLB.
Page 0
Page 1
Page 2
Process A …
TLB Table
Page n
VPN PFN valid prot ASID
Virtual Memory
10 100 1 rwx 1
- - - - -
10 170 1 rwx 2
Page 0
- - - - -
Page 1
Process B Page 2
…
Page n
Virtual Memory

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Another Case
• Two processes share a page.
• Process 1 is sharing physical page 101 with Process2.
• P1 maps this page into the 10th page of its address space.
• P2 maps this page to the 50th page of its address space.

VPN PFN valid prot ASID

10 101 1 rwx 1 Sharing of pages is useful as it
- - - - - reduces the number of physical
50 101 1 rwx 2 pages in use.
- - - - -

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 TLB Replacement Policy
• LRU(Least Recently Used)
• Evict an entry that has not recently been used.
• Take advantage of locality in the memory-reference stream.

Reference Row

7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1

7 7 7 2 7 4 7 7 0 1 1
0 0 0 0 0 0 3 3 3 0
Page Frame:
1 1 3 3 2 2 2 2 2

Total 11 TLB miss

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A Real TLB Entry
All 64 bits of this TLB entry(example of MIPS R4000)
0 1 2 3 4 5 6 7 8 9 10 11 … 19 … 31
VPN G ASID

PFN C D V

Flag Content
19-bit VPN The rest reserved for the kernel.
24-bit PFN

Global bit(G) Used for pages that are globally-shared among processes.
ASID OS can use to distinguish between address spaces.
Coherence bit(C) determine how a page is cached by the hardware.
Dirty bit(D) marking when the page has been written.
Valid bit(V) tells the hardware if there is a valid translation present in the entry.

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