I/O port structure

By
B. Prasanthi,
Assistant Professor
Department. of ECE
AITS, Rajampet
 Unit -I
MICROCONTROLLER & INTERFACING 8051:
Introduction, Architecture, Register Organization, Internal and
External Memory, Pin diagram, I/O port structure, Addressing
modes, Instruction Set, simple programs. On-Chip Peripherals-
8051 Interrupt Structure, Timer/Counter features, modes and
programming. MSP 430 Low power Micro Controller ( A
Quantitative study only).Applications- Interfacing with switches,
display – LED, seven segment display, LCD. Keyboard interfacing,
D/A and A/D interfacing, Stepper motor interfacing, Handling
External Interrupts, serial communications.
• Course Outcome: Understand basic concepts to design
embedded applications.
 Introduction
• As we know Microprocessor doesn't have inbuilt Input/output ports.
• It must add an additional chip (8255) to interface with the external
devices.
• The microcontroller 8051 has four ports P0,P1,P2 & P3. All ports are
bidirectional.
• The four ports are required for i/o operations.
• Out of the 40 pin,32 pins are set aside for the four ports
P0,P1,P2&P3.
• Total 32 input/output pins allow the microcontroller to be connected
with the peripheral devices.
• Each port has 8 pins.
• All the ports are configured as input upon Reset.
• To configure it as an output port, ‘0’ needs to be sent to the port
(When zero is written to a port , it becomes an output).
• To configure it as an input port, ‘1’ needs to be sent to the port.
• The function of a pin performs at any given instant
depends,
 first, on what is physically connected to it and,
then on what software commands are used to
“program” the pin. Both of these factors are under
the complete control of the 8051 programmer and
circuit designer.
• Each port has a D-type output latch for each pin.
• The SFR for each port made up of these eight latches,
which can be addressed at the SFR address for that
port.
• The port latches should not be confused with the
port pins; the data on the port latches does not have
to be the same as the on the port pins.
 Port ‘0’
• The port ‘0’ (P0) is characterized by two
functions.
• It can be used as a normal bidirectional I/O
port or it can be used as bidirectional
address/data bus for accessing external
memory.
• Control logic decides what it is using for.
• Whenever we write any data on to pin the data first written on to the latch and
then it is transfer to the output.
• Latch is D-type. We write either 1/0 to the input when we enable this latch
through CLK pin the input is visible at the output. At Q’ we get inverted output.
• When control logic is ‘1’, the port is used for Lower order
address/data bus.
• When the control logic is ‘0’, the port can be used as a
bidirectional I/O port.
• FETs acts as switches.
• Whenever a high input is given acts as close switch.
• Whenever a low input is given acts as open switches.
• There are two data paths are presented in a
circuit that read the latch or pin data using
two entirely separate buffers.
• The top buffer ( latch buffer) is used to read
latch value.
• The lower buffer (input buffer) used to read
pin data value.
• The status of latch and pin may be read
independently.
• To configure port 0 as an input port the internal bus writes 1 to
the D flip flop and the control pin is set to 0(Upper FET is OFF).
• The Mux is connected to Q'(0) of the D flip flop as the control pin
is 0. In this situation both the output MOSFETs are ‘off’.
• Hence the output pin have floats hence whatever data written on
pin is directly read by read pin.
PORT 0 as an Output Port
• Suppose we want to
• If we want to write ‘0’ on pin of port 0 , when
‘0’ is written to the latch, the pin is pulled
down by the lower FET. Hence the output
becomes zero.
• To use the port ‘0’ as an output port 0 is written to the
D flip flop with the control signal being set to 0.
• This enables the lower FET and disables the upper FET
due to this the pin gets connected to the ground and a
zero is written to the output device.
• Write 1 on pin of Port 0, a ‘1’ written to the latch which
turns ‘off’ the lower FET while due to ‘0’ control signal
upper FET also turns off as shown in fig. above.
• Here we wants logic ‘1’ on pin but we getting a high
impedance state as it is not connected to either VCC or
ground. so to convert that high impedance state into
logic ‘1’ we need to connect the pull up resistor
parallel to upper FET .
• To use the pins of port ‘0’ as both output
ports, each pin must be connected externally
to 10k-ohm pull up resistor.
• When the control logic is '1', address/data bus
controls the FETs.
• If the address/data bus (internal) is '0', the
upper FET is 'off' and the lower FET is 'on'. The
output becomes '0'.
• If the address/data bus is '1', the upper FET is
'on' and the lower FET is 'off'. Hence the
output is '1'.
• Hence for normal address/data interfacing (for
external memory access) no pull-up resistors
are required.
• Port-1 dedicated only for I/O interfacing.
• When used as output port, not needed to
connect additional pull-up resistor like port 0. It
have provided internally pull-up resistor as
shown in fig. Below.
• When port ‘1’ is used as an output port, the latch
pins that are programmed to 0, will cause the
lower FET turn on, the internal pull up to turn off
and pin value is logic 0.
• If ‘1’ is written onto the latch pin then it will drive
the pin value high through the pull up. The lower
FET turns off.
• When port 1 is used as an input port, ‘1’ must
be written to the corresponding port ‘1’ latch.
This causes the lower FET turn off. The pin and
input to input buffer (pin buffer) are pulled to
logic HIGH by the internal pull up load.
• It can be used as i/p or o/p which is similar in
operation of Port 1 .
• The alternate use of port 2 is to supply a high-
order address byte in conjunction with port 0
low-order byte to address external memory
• When port 2 is used as output port, the latch
pins that are programmed to 0, will cause the
lower FET turn on and the control logic 0.
• When port 2 is used as an input port,’1’ must
be written to the corresponding latch bit. This
cause the FET turn off.
• It’s operation similar to port 1,but has
alternate Uses.
• Each pin may be individually Programmed as
I/O or for alternate Functions as shown