CMOS VLSI

Integrated Circuits

 An IC is a combination of interconnected circuit elements

inseparably associated on or within a continuous substrate.

Why Design Integrated circuits ?

 IC Circuits are much smaller.

 IC Circuits consume less Power.

 Easier to design and manufacture.

 They are more reliable.

 Integrated Circuits

 Some terminology associated with IC are

 Substrate : It is supporting material upon or within
which an IC is fabricated
 Monolithic IC : An IC whose elements are formed in
place upon or within a semiconductor
with at least on element formed within
the substrate.
 Hybrid IC : Consist of two or more IC types
 Wafer : It is the basic physical unit used in
processing. Typically the wafer is
circular
 Chip : one of the repeated ICs on a wafer.
 Integrated Circuits

 Advantage of IC circuits over discrete components are.

 Size : Smaller – both wires and transistor are shrunk

to micro as compared to millimeter or
centimeter of discrete components.

 Speed : Hundred times faster than PCB.

 Power : Less power due to small size of circuits on

chip.
 History of IC Technology

 The IC technology can be categorized ,depending on the

number of transistors, as :

IC No.of active FUNCTION YEAR

Devices (BJT/FET)

SSI 1-100 Gates, Op-amps, Linear 1960

app

MSI 100-1000 Registers, Filters 1965

LSI 1000-10,000 Microprocessors, ADC 1970

VLSI 10,000-100,000 Memory, Computers, 1975

Signal Processors
 History of IC Technology
Date of Feature size
Microprocessor # transistors
introduction ( microns )

80286 2 / 82 134,000 1.5

80386 10 / 85 275,000 1.5

80486 4 / 89 1,200,000 1.0

Pentium 3 / 93 3,100,000 0.8

Pentium Pro 11 / 95 5,500,000 0.6

Pentium lll – 0.18

  Pentium IV – 0.13
 Feature Size

 Typically L=1 to 10 micro m, W=2 to 500 micro m and

the thickness of the oxide layer is in the range 0.02 to
0.1 micro m.
 Feature Size

 Value of the gate length is called as the feature size of

manufacturing technology.
 Thus feature size is function of IC technology.

N-MOSFET
layout
 Microelectronics
Two basic technologies used for manufacturing IC’s are
• Bipolar
• MOS

• Bipolar : The main technology is low-power-schottky TTL

Disadvantage: High power dissipation.
Used for SSI and MSI.

• MOS : LSI technology uses MOSFETS since these can be packed

in small area.
• P-MOS Technology : It uses P-MOSFET ’s.
Mobility of holes - 240 cm2/v*sec
Holes are majority carriers & hence this is relatively slow.
• N-MOS Technology : It uses N-MOSFET ’s
Mobility of electrons -650 cm2 /v*sec
Since electrons are majority carriers this technology is
faster than P-MOS.
• CMOS Technology : It uses combination of P-channel
and N-channel MOS.
 CMOS Technology
CMOS Technology :

• Simultaneously provides both NMOS and PMOS.

• Characteristics of CMOS technology lies between that of

P-MOS and N-MOS.

• It is faster than P-MOS but slower than N-MOS.

• Provides more flexibility

• It is mainly used in systems that require portability or

less static power consumption.

• It needs more processing steps as compared to N-MOS

or P-MOS.
CMOS Technology
 CMOS Technology
• Wide supply voltage range from 3 to 15 volt.
• Voltage required to switch gate is fixed percentage of VDD.
• Packaging density : Requires 2n devices for n input gate
• Fully restored logic level : Output settles at VDD or Vss. Therefore
called as restoring logic.
• Characteristics of CMOS technology lies between that of P-
MOS and N-MOS. It is faster than P-MOS but slower than N-
MOS.
• Mainly used in systems that require portability or less power
consumption.
• It needs more processing steps as compared to N-MOS or P-
MOS.
 CMOS vs BIPOLAR

FACTORS CMOS BIPOLAR

 Static power dissipation Low High

 Input impedance High Low

 Noise margin High Low

 Packaging density High Low

 Fan-out Low High

 Direction Bi-directional Unidirectional

devices devices
 Trends in VLSI

 Minimum geometrical feature size.

 Increase in speed of digital circuit. Use of GaAs for very
high frequency.
 Increase in complexity of a circuit function and device
count.
 Increasing designer productivity and ever–growing
dependence on the computer in the design process.
 Continual shift of where design, production, and
markets are geographically located.
 Growing coupling of specific process and its processing
equipment.
 MOS transistors
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS
Enhancement NMOS with
Bulk Contact
 MOS transistors

Top View

Drain

L
W Moat

Source
Gate
 MOS transistors
n-Channel p-Channel
D D

Id Id
Ig Vdg + + Vds Ig Vdg + + Vds
G - B G - B
+ - + + - +
Vgs Vbb Vgs Vbb
- Is - - Is -

S S
 Metal Oxide Semiconductor Field
Effect Transistor
Gate
oxide Drain
Source Gate

Length

substrate

 MOS stands for the Metal Oxide Semiconductor

 Consist of four terminals Gate, Source, Drain and

substrate
 MOS transistors

Some common terms used in the MOS Transistor

 Vgs : The gate-to–source Voltage.
 Vds : The drain-to–source Voltage. (Vds = - Vsd).
 Id : The current flowing between the drain to
source.

The constants that determine the magnitude are

 Vt : The transistor threshold voltage,which is
positive for n-type and negative for p-type.
 K’ : The transistor transcoductance, which is
positive for both types.
 W/L : The width-to-length ratio of the transistor.
 Metal Oxide Semiconductor Field
Effect Transistor
• For P-channel MOS substrate is of N type and source, drain are
formed with P type material.
• For N-channel MOS substrate is of P type while source & drain
are formed with N type material.
• Gate is polycrystalline silicon electrode and is insulated from
substrate by thin layer of silicon dioxide SiO2
• Since the gate is insulated, MOSFET’s are also called as
Insulated Gate Field Effect Transistors ( IGFET )
• It is a voltage controlled device, the current through channel is
controlled by voltage applied to gate.
• MOSFET’s can be configured either as
Enhancement type MOSFET OR
Depletion type MOSFET
 Depletion type MOS

• In Depletion MOS structure, the source & drain are diffused

on P- substrate as shown above.
• Positive voltages enhances number of electrons from
source to drain.
• Negative voltage applied to gate reduces the drain current
This is called as ‘ normally ON ’ MOS.
 Enhancement NMOS

• It consists of lightly doped p-type substrate into which

two highly doped n+ regions are diffused.
• When the gate voltage VGS = 0 volt, there is no
conduction path between source and drain, hence the
drain current is zero.
• Since the gate is insulated positive voltage may be
applied to gate, it will produce electric field across
substrate.
 Enhancement NMOS
• This field will end on induced negative charges in p
substrate.

• These negatively charged electrons, which are minority

carriers in p substrate, form an inversion layer. Current
flows from source to drain through this induced
channel.

• More the positive voltage, More is the induced charge

& hence more current flows from source to drain.

• This is also called ‘Normally Off ’ MOS, since drain

current is zero for zero gate voltage.

• CMOS integrated circuits use enhancement type

transistors only.
 Enhancement MOS Cross-section

• As VDS is increased, the induced Channel acquires a

tapered shape and its resistance increases with
Increase in VDS.
Here VGS is kept constant at value > VT
Enhancement NMOS-Operation

Gate
oxide Drain
Source Gate

n+ channel n+
holes electrons
P-substrate

substrate
 Enhancement NMOS-Operation
Cut-off Region
Cutoff region (Vgs = 0 and Vds = 0 )

Gate
oxide Drain
Source Gate

n+ n+
holes electrons
No
channel
P-substrate

substrate
no current flows between Source and Drain
Current-voltage relation : IDS = 0 VGS < VT
 Enhancement NMOS-Operation
Cut-off Region
Depletion Region (0< Vgs < Vt and Vds = 0 )

Gate
oxide Drain
Source Gate

n+ n+
holes electrons Depletion
Region
P-substrate

substrate
 When positive gate voltage is applied,electron will start to deplete
the substrate near the surface under gate.
 This deplete the p-type substrate in this region and form the
depletion region
 Enhancement NMOS-Operation
Linear Region
 Inversion region (Vgs > Vt and Vds = 0 )
Gate
oxide Drain
Source Gate

n+ n+
holes electrons
Inversion
P-substrate
region

substrate
n region
 Enhancement NMOS-Operation
Linear Region
 Inversion region
 As gate voltage is increased number of electrons will be
attracted to the substrate surface under the gate to make
n-type.

 The n-type region which is created electrically in the p

substrate is called the inversion layer.

 The gate-to-source voltage necessary to create the

inversion layer is called the threshold voltage (Vt).

 After formation of inversion layer the current flow from

drain to source or source to drain if small voltage is
applied
 Enhancement NMOS-Operation
Linear Region
 Increase in gate-source voltage(Vgs) beyond threshold
voltage (Vt)brings additional electrons under gate
causing increase in inversion layer.

 If large drain-source voltage is applied ,this voltage

itself will tend to deplete the inversion layer due to
potential drop across the region formed by current flow
 Enhancement NMOS-Operation
Linear Region
 (Vgs > Vt, Vds < Vgs- Vt) Gate
oxide Drain
Source Gate

n+ n+
holes electrons
P-substrate

substrate
n region
 Enhancement NMOS-Operation
Saturated Region
Vgs > Vt and Vds > Vgs - Vt
Gate
Source Gate oxide Drain

n+ n+
holes electrons
P-substrate

substrate
n region
• When VDS > VGS – VT, VGD < VT, the channel becomes pinched- off &
transistor is said to be in saturation.
• Conduction is brought by drift mechanism of electrons under the
influence of positive drain voltage and effective channel length is
modulated.
 Enhancement NMOS-Operation
 some equation
Ig = 0

0 Vgs < Vt (cutoff), Vds > 0

( K’ W (Vgs – Vt- Vds/2) Vds) / L

Id = when[Vgs > Vt, 0 < Vds <Vgs – Vt(Linear) ]

( K’ W (Vgs – Vt)**2 (1 + Vds)) / 2 L

when[Vgs > Vt, Vds > Vgs – Vt(saturation)

channel length modulation

Enhancement NMOS-Operation
 Inverter

 Symbol:

In Out logic function

Out = In

 Truth Table of an Inverter:

In Out
0 1
1 0
 STATIC LOAD INVERTERS

• Static load inverter are Rationed logic gates where logic levels
are determined by relative dimensions of composing transistors.
• Transfer function of inverter varies with load.

• When I = 1, inverter dissipates static

power
• Switching point of inverter depends
on ratio of R to RON (on resistance of
I
NMOS device.)
 STATIC LOAD INVERTERS

 Problems with static load inverters

 On chip resistors are large

 Static power consumption
 VOL = 0
 Large tpLH
 ACTIVE-RESISTIVE LOAD
• Load device is always on, looks like a load resistor.
Dissipates static power when I = 1, VGS = 0V always
• VOH = 5V; VOL nearly 0V, depending on ratio of RON_dep
to RON_enh.
• Depletion-mode devices were used before it was
economical to put both p-type and n-type devices on
the same die.

Problems with this

Extra process step

Static power consumption
VOL = 0
Large tpLH
The CMOS Inverter

# No static power
consumption (almost)
# VOH = VDD; VOL = 0
# tpLH = tpLH If properly
designed
# Low Impedance connection
to ground and VDD

- More fab. stages

- Lower hole mobility
The CMOS Inverter

Complementary i.e. output

have always a low impedance
connection to GND or VDD

VOH = VDD
VOL = 0

VM = f(Ron-n,Ron-p)
VM = VDD/2 if Ron-n = Ron-p
 The CMOS Inverter

Actual characteristics
Rin=infinite ,Rout=0
NML = VIL - VOL = 0.75 - 0.50 = 0.25V
Noise Margin = VDD/2,
NMH = VOH - VIH = 3.50 - 2.25 = 1.25V
Gain = infinite
VM = 1.75V
 The CMOS Inverter-
Voltage Operation
REGION OF P-DEVICE N-DEVICE
OPERATION
VGS >VT VGS < VT
CUT-OFF VIN > VT + VDD VIN < VT
VGS< VT , VIN <VT+ VDD VGS > VT , VIN > VT
NON- VDS > VGS - VT VDS < VGS - VT
SATURATED
VOUT > VIN - VT VOUT < VIN - VT

VGS< VT , VIN <VT+ VDD VGS > VT , VIN > VT

SATURATED VDS < VGS - VT VDS > VGS - VT

VOUT < VIN - VT VOUT > VIN - VT

 Inverter Load Characteristics

Vinp Vinn

Vds(Vdd - Vdsp)

 Taking the absolute value of the p – device , Vds , and

superimposing yields the following curve.
 The input/output transfer curve may be determined by
the points of common Vgs intersection
CMOS Inverter Voltage Transfer
Characteristic

VTC graphically
extracted from the
load lines

High noise margin

NMH=VOH-VIH ~ 5-3 = 2V
NML =VIL-VOL ~ 2-0 = 2V
Region: Linear - Saturation

A B

D
E
 Region: Linear - Saturation

REGION A B

CONDITIO 0 < Vin < VT[n] VT[n] < Vin <VDD/2

N

N-DEVICE Cut-off since Vin < VT[n] Saturated as (VDS[n] = VOUT) >
VDD/2 &
(VGS[n] = Vin) < VDD/2
P-DEVICE Non-saturated (linear) Non-saturated (linear-region)
since VSD[p] < VSG[p] - | since VSD[p] < VSG[p] - |VT[p]|
VT[p]|
OUTPUT VOUT = VDD as VDS[P] = 0
As VDS[P] = VOUT –VDD
 Region: Linear - Saturation

REGION C D E
CONDITIO Vin = VDD / 2 VDD/2 < Vin < VDD - Vin>VDD-||
N VT[p]| VT[p]|

N-DEVICE Saturated since Non Non-

VDS[n] > VGS[n] – VT[n] & saturated. saturated
VOUT > Vin – VT[n]
P-DEVICE Saturated Saturated Cut-off
VSD[p] > VSG[p] - |VT[p]|
VOUT < Vin + |VT[p]|
OUTPUT VOUT  f(Vin) VOUT = VSS
Vin - VT[n] < VOUT < Vin +
VT[p]|
 n/p RATIO
The ratio ßn (gain of NMOS) / ßp (gain of PMOS) determines the
switching point of the CMOS inverter.
 Switching characteristics of
CMOS inverter
The switching speed of the CMOS gate is limited by time taken
to charge and discharge the load capacitance
 Calculation of rise & fall time

Fall Time : The time required for output to fall from 90% to 10%
of its steady state value.

Tfall = Rfall * CLOAD

Rfall = k * 1/βn
Tfall  3 CL/VDD βn

• k is a constant that depends on threshold voltage and VDD.

• k = 3 to 4 for values of VDD = 3 to 5 volts & VT = 0.5 to 1 volt.

• The gain factor = nox/tox W/L

 Calculation of rise & fall time
Rise Time : The time required for the output to rise from 10%
to 90% of its steady state value and is given as

Trise = Rrise * CLOAD

Rrise = k * 1/βp
Trise  3 CL/VDD βP

• Thus to achieve high speed circuits, the load capacitance should

be minimized.
• Lowering the supply voltage on a circuit will reduce the speed
of the gates in that circuit.
 Calculation of rise & fall time

• The delay of transistor decreases as the width of transistor is

increased or length is decreased..

• For equally sized n and p transistors βn = 2βp

Hence Tfall = Trise /2

• To equalize the rise and fall times of an inverter I.e Trise = Tfall
must have ßn = ßp

• This means, that channel width for the p-device must be

increased to twice of the n-device. Hence if Lin = Lp then Wp=
2*Wn

• Thus ßn = ßp provides equal current source and sink capabilities.

• Thus equal charge and discharge times
 DELAY TIME

Delay time : It defines the response of gate for change in input.

• Is measured between 50% transition points of input and

output waveforms.

• Gate displays different response times for rising and falling

waveforms.

• Tplh Defines response time of gate for low to high output

transition
• Tphl Defines response time of gate for high to low output
transition

• The overall propagation delay is average of these two

TD = (Tphl + Tplh)/2
 CMOS Inverter - Summary

• CMOS inverter uses actively driven P-channel transistor is used as

pull-up drive.

• It allows maximum logic voltage level swing.

• Eliminates the static power dissipation as no current flows from

VDD to ground in steady state.

• No of transistors is 2N.

• It is ratio-less logic I.e.

• Output logic levels are independent of ratio of pull-up and
pull-down transistor sizes.
 CMOS Inverter - Summary

• Resistance of N-channel transistor is Rn α Ln /Wn * Kn

• Resistance of P-channel transistor is Rp α Lp /Wp * Kp

• But μn = 2.5 μp, hence βn = 2.5 βp .

• Hence in order to achieve symmetrical operation(equal rise

& all time ) we must have (Ln * Wp)/ (Lp * Wn )= kn/kp

=2.5. Thus with this sizing N & P transistors have equal
I-V characteristics.
 NOISE MARGIN
Logic High
Logic High input range
Output VOH(MIN)
range
VIH(MIN)

VIL(MAX)
VOL(MAX) Logic low
Logic low input range
output
range

Output characteristics Input characteristics

 NOISE MARGIN

• Determines the allowable variation in input

voltage of gate so that output is not affected.

• Is specified in terms of two parameters

• Low noise margin - NML = VIL(MAX) - VOL(MAX)

• High noise margin - NMH = VOH(MIN) - VIH(MIN)
 
MOS Transistors As Switch

• N-MOS source is tied to ground,

used to pull signals down

Control output
G= ‘1’ D=‘0’
G= ‘0’ D=‘Z’

• P-MOS source is tied to VDD, used

to pull signals up.

Control Output
G= ‘0’ D= ‘1’
G= ‘1’ D=‘ Z’
Why N-MOS Transistor Produces
Weak ‘1’?

• When G= ‘0’, output is ‘0’ since

transistor is non-conducting
irrespective of ‘Vin’.

• As source goes from 0V 5V

VGS goes from 5V 0V

• When Vs < 4.3 V then VGS < VT

• Hence VD is left at 5V – VT .
Why PMOS Transistor produces
weak ‘0 ?
• PMOS will conduct if VGS < VT

• If VT = - 0.7V then VGS = 0V – 5V &

C is charged towards VDD since
| VGS | > | VT | (5V >0.7V)

• When source goes from 5V to 0V,

• PMOS will stop conducting when

| VGS | < | - 0.7 V | and VD will be left
at 0.7V, thus produces weak ‘0’.
 MOS Transistors as Switch
SWITCH G INPUT (SOURCE) OUTPUT(DRAIN
)
I/P O/P
X Z
G=0
VDD STRONG 0

G=1 VSS WEAK 1

X Z
G=0
VDD STRONG 1

G=0 VSS WEAK 0

• Thus NMOS transistor produces active low logic at output.

• While PMOS gives active high logic at output.
Series Connection Of
Switches
• If N switches are placed in
series Y=‘0’ if A & B are ‘1’.

•Thus yields an AND function.

Y=A*B

• If P switches are placed in

series Y=‘1’ if A & B are ‘0’.

• Thus yields an NOR

function.
Y = /A * /B
Parallel Connection Of Switches

• When N switches are placed in

parallel Y=‘0’ if either A or B is ‘1’.

• Thus yields an OR function.

Y=A+B

• When P switches are placed in

parallel Y=‘1’ if either A or B is ‘0’.

• Thus yields an NAND function.

Y = /A +/B
 Complementary Logic Gate
Design
A CMOS gate is combination of two networks as shown
below
VDD
• Pull Up Network (PUN) consists of
I/P P-MOS transistors. Thus implements
PUN
the logic function F
Y= /F
•Pull Down Network(PDN) consists of
I/P N-MOS transistors. Thus implements
PDN
the logic function /F.
VSS
 NAND Gate Design

•PDN network consists of two parallel P-MOS transistors

•PUN network consists of two series N-MOS transistors
WHY ???
NAND Circuit
 NOR gate design

Y = /(A + B)

PDN = /A * /B PUN = A +
B
NOR circuit
 AND Gate Design

Poorly Designed AND gate !!!

 AND Gate Design

Instead use this !

 Designing compound gates

• To implement the function F = /((A+B+C)*D)

• PDN will provide 0’s of function F.

• Hence equation of PDN is (A+B+C) * D.

• For PUN network will provide

1’s of function F
• Equation for PUN is (/A*/B*/C)
+/D
 Transmission gate
• By combining an N-switch and P-Switch in parallel perfect
transmission of both ‘1’s and ‘0’s is achieved.

When I=0 both N & P

devices are OFF
VIN VOUT

X Z
When I=1 both N & P
devices are ON
VIN VOUT

VDD VDD
VSS VSS
 Transmission gate
• Schematic icons for transmission gate

Most widely used

 Transmission Gate
Characteristics
2:1 multiplexer

Y = SA +/SB

• This implementation will need total 6 Transistors

• 4 Transistors for two pass gates
• 2 Transistors for inversion of S

• Thus transmission gate logic uses less gates than the design

with normal gates.

 Transmission Gate
Characteristics
But it has got Demerits !

• It is non restoring logic output levels may or may not settle

at VDD or VSS (as it passes logic level at input to output )
where as CMOS gates provides restoring logic.

• It has no drive capability, drive comes from original A, B

inputs What about CMOS gate?

• Transmission gates provide no isolation between input and

output.

•Then Why & Where Transmission gates are used ?

 Logic Design Using Transmission
gate

2:1 Multiplexer Y = SA + /SB

A B S Y

X 0 0 0(B)
X 1 0 1(B)
0 X 1 0(A)
1 X 1 1(A)
• When S= 1, S1 is ON and S2 is OFF. Hence input A is connected

to the output.
• When S= 0, S1 is OFF and S2 is ON. Hence input B is
connected to the output.
 2:1 Multiplexer

• Multiplexer may also be constructed using logic gates

• However these implementations are larger and consume more
power than a transmission gate implementation

Comparison of Design Style Transistor Count

Multiplexers
Static CMOS Gates 12 Why ?

Transmission Gates 4
TRISTATE INVERTER

EN I O
0 X Z
1 0 1
1 1 0

Total 6 transistors !
D LATCH Positive level sensitive

EN Q
1 D
0 Qold

How will the circuit function ?

 D-LATCH WITH EN = 1

• When EN = 1, switch S1 is closed and S2 is open.

• Hence Output-Q follows Input D
 D-LATCH WITH EN = 0

• When EN = 0, switch S1 is open and S2 is closed.

• Hence,
•Output-Q is isolated from Input D.
•Output retains the value of D at the falling edge of EN
[WHY ???]
 D-latch with asynchronous reset

• How to implement asynchronous clear?

 Edge Triggered D - Register
• By combining two latches in master-slave arrangement,
edge triggered register can be constructed.
• For positive edge triggered first latch(master) is negative
level- sensitive latch
 Rising Edge Triggered D
register

How will the the circuit function ?

 D-REGISTER WITH CLK = 0

• When CLK= 0 , S1 and S4 are closed /Qm follows D, and Q is

stored in the inverter loop.

Qm
Qm
 D-REGISTER WITH CLK = 1

• When CLK= 1.
• S1 is open and S2 is closed
Hence /Qm LATCHES the value of D, that existed on the rising edge of CLK.
[ Does it remind you of set-up hold and Metastability]
• S3 is closed and S4 is open,
Hence Q gets the value of /Qm [ I.e. the value of D on the rising edge of CLK].
• Q is isolated from changes on D input.
 EDGE TRIGGERED D-
REGISTER
• In case of negative edge triggered register master is positive
level-sensitive latch.
 Guess The
Functionality ?
 Sizing of NAND and NOR Gates

• Symmetrical drive capability of CMOS allows comparable

transition time for output voltages irrespective of direction of
transition.

• Primary effect of sizes of pull-up and pull-down transistors is

on equivalent resistance of transistors in conduction state.

• To obtain symmetrical characteristics at output rise and fall time

should be same which says RN = RP

• Resistance of N-channel is given as RN  LN/WN*KN

• Resistance of P-channel is given as RP  LP/WP*KP

 Sizing of NAND and NOR gates

• In case of NAND gate equivalent pull-down resistance is twice

that of either pull-down alone RDN = Rn3 + Rn4= 2* Lp/Wp *
Kp.
• To obtain symmetrical characteristics we must have
Kn/Kp = 1.25 ??
 Sizing Of NAND and NOR gates

• In case of NOR gate the equivalent pull up resistance is twice that of

either pull up alone Rup = Rp3 + Rp4= 2* Lp /Wp * Kp
• Hence for NOR gate Kn/Kp = 5 will give symmetrical output ??
• NOR gates require greater silicon area than NAND gate for symmetric
drive operation.
• Hence NAND gates are always preferred than NOR
 Where Does Power Go In CMOS

Power dissipated in a CMOS circuit is categorised as follows,

• Static dissipation :
Due to leakage currents

• Dynamic dissipation :
Due to charging and discharging of internal & load
capacitance.

• Short circuit dissipation :

Due to short circuit path between VDD and GND during
switching
 STATIC DISSIPATION

Static dissipation is due to,

• Leakage currents in the reversed-biased diodes formed
between the substrate (or well) and source/drain regions.
• Sub threshold conduction, also contributes to static
dissipation. Sub threshold leakage increases exponentially as

threshold voltage decreases.

• Total static power dissipation is given as

pstatic= Σ
n
leakage current * VDD
Where n is the number of devices in a CMOS Circuit.
 STATIC DISSIPATION

LOWER BOUND ON THRESHOLD TO PREVENT LEAKAGE

 DYNAMIC POWER DISSIPATION

• During low to high transition part of energy drawn from supply

is dissipated in PMOS. During high to low transition stored

• Dynamic power dissipation gives measure of this energy

consumption
 DYNAMIC POWER DISSIPATION

• The average dynamic power consumption for input frequency

of F is Pdynamic = CL * VDD2 * F
• Power dissipation is independent of device parameters
• This can be reduced by decreasing CL , VDD or F
 SHORT CIRCUIT DISSIPATION

• It is the DC power consumed during switching.

• A direct current path from VDD to ground exists when both N

and P transistors are conducting simultaneously during

switching.
• Short circuit consumption is given by
Psc = Imean * VDD
• Thus for an inverter without load, assuming Tr = Tf = Trf
Psc = β/12 (VDD – 2 VT) 3 Trf * F
• Short- circuit power depends on W/ L ratios of the transistors
• Greater the rise-fall time of the signals, larger is the power
consumed.
 SHORT CIRCUIT DISSIPATION

Input switching waveform & model for short circuit

is determined by the current.
• Ipeak saturation current of devices,
hence is proportional to the sizes of the transistor.
 Impact of rise/fall times on short-
circuit currents

• Power dissipation due to short circuit current is minimized by

mminimizing the rise and fall time of input and output signal.
 MOS Device Capacitance Estimation
Junction Cap. Bulk Cap.
Overlap Cap.

• Two types of capacitances - Junction & Gate capacitance.

 MOS Device Capacitance
Estimation

Gate capacitance :- CG = bulk capacitance + overlap capacitance

CG = CGB + CGD + CGS
CG = COX * W* Leff
 MOS Device Capacitance Estimation
• COX is oxide capacitance & is inversely proportional to oxide
thickness COX = eOX/tOX

• But both source and drain tend to extend somewhat below the
oxide by an amount XD called lateral diffusion. Hence
effective channel of transistor Leff becomes shorter than the length,
the transistor was designed

• It also gives rise to parasitic capacitance between gate and source

(drain) & is called overlap capacitance. This is strictly linear & has
fixed value.

• The reverse biased source-bulk & drain-bulk pn junctions

contribute to junction capacitance.
 STAGE RATIO

- The object is to maximize the speed with minimum area overhead.

- Option I will be slow, since Gate1 will not have drive capability to drive
the large inverter.
- In Option II, we have a chain of inverters of increasing size (by an order
of a)
- Gate I will be fast, since it drives a minimum sized inverter (Inverter 1)
 STAGE RATIO

• When It is desired to drive large load capacitances such as long

buses, I/O buffers and off-chip capacitive loads.

• This is achieved by using a chain of inverters where each

successive inverter is made larger than the previous one.

• The ratio by which each stage is increased in size is called

‘ stage ratio ‘.

• The signal delays encountered in driving the off chip load directly
from a minimum sized inverter is unacceptable.

• The optimisation to be achieved here is to minimize the delay

between input and output while minimizing the area and power
dissipation.
STAGE RATIO
 Stage Ratio
• Inverter 1 is a minimum- sized device.
• Subsequent inverter device sizes increase by a factor of ‘a’

• Delay of each stage is ‘a * Td ’, where Td =delay of minimum

sized inverter driving an identically sized inverter
• Hence total delay ( delay through the n stages ) is n * a * Td

• Cg is load of first driver which is minimum- sized device

• If CgN is the load capacitance of the Nth inverter then CgN = Cg *

aN
• To guarantee that none of capacitances internal to the chain of
inverters exceed Cload [ why ?? ] we must have Cg * an = CL
here n = N +1

I.e an = CL/ Cg
 Stage Ratio
Hence a = [CL/ Cg]1/n
Total delay = n * [CL/ Cg]1/n * Td
The optimum value of n is
nopt = ln [CL/ Cg]
• Now optimum value of a i.e aopt can be calculated as;
an = CL/ Cg
aln [CL/ Cg] = CL/ Cg
Taking natural log of both sides we get a = 2.7
• But the actual stage ratio is given by
aopt = exp[(k+aopt)/aopt]
Where k = Cdrain/Cgate
• For 1µ process k = 0.215, hence aopt = 2.93
• For 2.5µ process k = 3.57 which gives aopt = 5.32
 Stage Ratio Graph

•Different processes will have different stage ratios from 2 to

10.
SIZING OF TRANSISTOR

- The speed of a CMOS gate depends on

how fast the load capacitance can be
charged/ discharged
- Load capacitance depends on the fan- out
of the gate, and the size of the gates
connected to the output
- Increasing the size of the p- transistors
decreases the rise- time of the gate
- Increasing the transistor sizes of the N
and P- block also increases the input
capacitance of the gate (i. e. the input
delays will increase at the expense of the
output delays)
SIZING OF TRANSISTOR

Progressive Sizing:

I.e. Increase size downwards

m1>m2 > m3 >m4

m 4 discharge CL
m 3 discharge CL + C3
m 2 discharge CL + C3 + C2
m 1 discharge CL + C3 + C2 + C1
SIZING OF TRANSISTOR
SCALING OF MOS TRANSISTOR
DIMENSIONS
 Sub-micron Considerations

• When dimensions of MOS device go below 1µ then it’s

behaviour deviates substantially than actual MOS operation
that
has been discussed so far.

• For sub-micron range the channel length becomes comparable

to other device parameters such as depth of drain and source
junctions, and width of their depletion regions.

• Such devices are called ‘ short channel transistors ’ & represents

the deviation form ideal model.
 Sub-micron
Considerations
 Variation in I-V characteristics

• The I-V characteristics of short channel device deviate

considerably from the ideal equations.
• ID= {( VGS -VT)VDS – (VDS2)/2} -----Linear region

• ID= (kn/2) W/L(VGS -VT)2 (1+ VDS) ----Saturation region

• The most important reasons for this difference are the Velocity
saturation and mobility degradation.
• Velocity saturation : Carrier velocity is given as;
• n = n Ex = n*dv/dx
• This states that carrier velocity is proportional to electric field &

is independent of value of that field, i.e it is constant.

 Variation in I-V characteristics
• But when the electric field along the channel reaches a critical

value Emax , velocity of carriers tend to saturate( i.e carriers

reach their maximum limited velocity ).
• Current under the velocity saturated condition is
IDSAT = SAT* Cox * W (VGS - VDSAT - VT)
• Thus the saturation current linearly depends on the gate-
source voltage.
• Also, ID is independent of L in velocity saturated devices.
• Reduction in the channel length causes reduction in the
electron mobility even at normal electric field levels. This is
called ‘ mobility degradation ‘
 Mobility Variation
• The mobility ‘M’ describes the ease with which carriers drift in

the substrate material

• It is defined as ratio of average carrier drift velocity ‘V’ to the

Electric field ‘E’.

• Mobility can vary in number of ways viz :

• According to the type of charge carrier. [ WHY ??]

• Increase in doping concentration decreases mobility.

• Increase in temperature decreases mobility.

 Threshold Voltage
Variation

• As device dimensions are reduced threshold voltage becomes

function of L,W and VDS

• The threshold voltage is not constant with respect to the

voltage difference between the substrate and the source of
the MOS transistor. This is known as ‘ substrate bias effect’
or ‘ body- effect ’.
 Impact Ionization
• As the length of the gate decreases, electric field intensity
at the drain increases.
• In sub- micron devices, the field intensity can become
very high, to an extent that electrons are imparted with
enough energy to become ‘hot’.
• These hot electrons can impact the drain, dislodging holes.
• These free holes will escape into the substrate creating a
substrate current. This effect is known as impact
ionization
• This will degrade the transistor performance and can
trigger latch-up.
 Impact Ionization

• The high- energy (hot) electrons can also penetrate the gate
oxide causing a gate current.
• This can lead to degradation of MOS device parameters.
• Hot- electron effects can be minimized by decreasing the supply

voltage in smaller devices.

 Tunnelling
• The gate is separated from the substrate by an oxide of
thickness tox , Generally the gate current in a MOS Transistor
is zero

• When the gate oxide is very thin, a current can flow from gate

to source/drain

• This happens due to electron tunnelling through the gate

oxide

• This gate-current is proportional to the area of the gate.

• This effect puts a limit on the minimum thickness of the gate

oxide layer, as processes are scaled
 Drain Punch-Through
• If the drain is at a very high voltage with respect to source ,
the depletion regions around the drain and source will meet
• This will cause a channel current to flow, irrespective of the
gate voltage, even if it is zero. This is known as punch-through
condition.
• Punch-through can be avoided with,
• Thinner Oxides.
• Larger Substrate Doping.
• Shallower Junctions.
• Longer Channels.
 Channel Length Modulation

• In the saturation region, the ideal characteristics of a MOS

transistor shows a constant current region, i.e.drain current

IDS remains constant, with increase in VDS.

• This characteristics assumes that carrier mobility is
constant.It does not take into account the variation in
channel length due to change in VDS.
• However, in saturation, as VDS increases, channel- length L
decreases by a very small amount such that Leff = L - DL
• This decrease in L, increases the [W/ L] ratio, and hence
increases IDS due to increase in ß.
• For long channel lengths, influence of channel variation is
of little consequence, but as devices are scaled down this
 Scaling Methods

• Scaling is method in which device geometries migrate to

lower sizes while still maintaining the same device
characteristics.
• This is done by scaling the critical parameters of a device
in accordance to a given criteria.
• Scaling methods include
 Lateral scaling
 Constant field scaling
 Constant voltage scaling
 Lateral Scaling
LATERAL SCALING :
- Here the only parameter that is scaled is the gate length L

- This method of scaling is also called gate- shrink

- It can be easily done to an existing mask design

- Power dissipation increases by the factor 

- Input capacitance of the transistor decreases by the factor 

 CONSTANT FIELD SCALING
- A dimensionless scaling factor  is applied to,
• All dimensions (including vertical dimensions such as tox )
are decreased by .
• Device voltages are decreased by 
• Concentration densities are increased by 
• As a result,
• Depletion thickness d.
• Threshold voltage VT
• Drain Current IDS
also get scaled by the same factor 
• Since the voltage VDD is scaled, the electric field in the device
remains constant
• Hence, the operating characteristics of the device remain the
same even after scaling
• Power dissipation decreases by 2
 CONSTANT VOLTAGE SCALING

• Similar to constant field scaling, except that voltage VDD is kept

Constant
• The current I DS increases by the factor 
• Speed of the device increases by the factor 
• Number of transistors per unit area increases by the factor 2
• As a result, the current density increases by the factor 3
• Proportionately wider metal wires are required for more densely
packed structures
• Power dissipation increases by the factor 
• This will increase the need for cooling devices/ structures for the
IC
• Power dissipation of above 1- 2 Watts require specialized cooling
fins or packaging
CMOS PROCESSING
TECHNOLOGY
 IC Fabrication
• An IC fabrication process contains a series of masking steps to
Create successive layers of insulating, conducting and semi-
conducting material that define the transistors and metal
interconnect.
• Techniques such as oxidation, implantation,deposition are
used to build these layers.
• The starting material used for IC fabrication is silicon wafer.

Wafer is a disk of silicon, 4" to 8" in diameter, < 1mm thick,

• Wafers are very brittle, the larger the diameter, the more
susceptible to damage. Surface of the wafer is polished to a
very flat, scratch free surface.
• The single crystal silicon used as substrate is obtained from
polycrystalline silicon generally by CZ (czochralski ) process.
Controlled amount of impurities are added to the melt to
provide
 IC Fabrication
• The crystal with required electrical characteristics. After the
crystal has been developed several steps are involved to
achieve mirror like structure.

• Oxidation is used to deposit Silicon Dioxide (SiO2) on surface of

wafer to be used as insulting material - heat wafers inside of an
oxidation atmosphere such as oxygen or water vapour.

• To build the micro(semiconductor) devices, we need junctions

formed by N and P type region. To create these regions on
silicon wafer what we need is process to introduce impurity
atoms into the substrate.This may be achieved by using Epitaxy,

Deposition and Ion-implantation.

 IC Fabrication

• Epitaxy involves growing single crystal film (of the required

dopant) on silicon surface by heating wafer and exposing it to
a
source of the dopant.

• Deposition is to evaporate the dopant onto the surface, then

heat the surface to drive the impurities in the wafer

• Ion implantation involves exposing surface to highly

energized dopant atoms. When these atoms impinge on the
surface, they travel below the surface forming the regions with

varying doping concentration.

• During fabrication of the transistors or other structures it is

needed to block some regions from receiving the dopants.
Hence special material called as mask is used to block the
 MASK
 Common material used for masks are Photoresist,
Polysilicon, Silicon dioxide, Silicon nitride.
 To create mask:
(a) deposit mask material over entire surface
(b) cut windows in the mask to create exposed areas
(c) deposit dopant
(d) remove un-required mask material
• Masks plays important role in process called selective
diffusions.
• The selective diffusion involves
1. Patterning windows in a mask material on the
surface of the wafer.
2. Subjecting the exposed areas to a dopant source.
3. Removing any un-required mask material.
 Fabrication of CMOS Devices

Technologies used for CMOS fabrications include

• N-well process

• P-well process

• Twin-tub process

• Silicon on insulator.
 P-Wells and N-Wells

IN
P substrate N substrate
contact
G OUT G contact
D S

n+ n+ p+ p+
p+ n+

P-well N-well

• A p- transistor is built on an n- substrate and an n- transistor

is built on a p-substrate
 P-Wells and N-Wells
• In order to have both types of transistors on the same
substrate, the substrate is divided into “well” regions (Shaded
region in the standard cells)
• Two types of wells are available - n- well and p- well
• In a p- substrate, an n- well is used to create a local region of
n
type Substrate, wherein the designer can create p- transistors
• In a n- substrate, a p- well creates a local p- type substrate
region, to accommodate the n- transistors.
• Hence, every p- device is surrounded by an n- well, that must
be connected to VDD via a VDD substrate contact.
• Similarly, n- devices are surrounded by p- well connected to
GND using a GND substrate contact.
 The P-Well Process
• Mask1 – Defines the areas in which the deep P-Well diffusions
are to take place.
• Mask2 – Defines the thinox regions, namely those areas where
the thick oxide is to be stripped & thin oxide grown to
accommodate p & n transistors and diffusion wires.
• Mask3 – Used to pattern poly-silicon layer which is deposited
after the thin oxide.
• Mask4 - A p+ mask is now used to define all areas where p-
diffusion is to take place.
• Mask5 – This is usually performed using the negative form of
p+ mask & with mask2 defines those areas where n-type
diffusion is to take place.
• Mask6 –Contact cuts are now defined.
• Mask7 _ The metal layer pattern is defined by this mask
• Mask8- It is needed to define the openings for access to
bonding pads.
 The N-Well Process

• Typical fabrication processes for n-well are similar to that of

p-well process except that n-well is implanted rather than p-

well.

• N–well CMOS circuits are superior to P-well because of lower

substrate bias effects on transistor threshold voltage &

inherently low parasitic capacitances associated with source
& drain regions.
 The N-Well Process

• Steps in N-well process :

1. Formation of n-well regions
2. Define N-MOS and P-MOS active areas.
3. Field and gate oxidations (thinox)
4. Form and pattern poly-silicon.
5. P+ diffusion
6. N+ diffusion
7. Contact cuts
8. Deposit and pattern metallization
9. Over glass with cuts for bonding pads
 LATCH-UP IN CMOS Circuits

• Latch-up is condition in which parasitic components gives rise

to establishment of low-resistance conducting path between
VDD & VSS

• This results in chip self-destruction or system failure.

• Latch-up may be induced by the glitches on the supply rails or

by incident radiation.
Physical Origin Of Latch-up

Vss IN OUT
Physical Origin Of Latch-up

VSS
 Latch-up Mechanism
• If sufficient current is drawn from NPN
emitter then NPN ( Q2 )turns on when
VBE  0.7V.
Rwell
• When NPN turns on, note that emitter
Q1 current increases exponentially with VBE
• Current flowing through the parasitic n-
well resistors will eventually turn on the
Q2 parasitic PNP.
• As PNP turns on, the NPN base current

increases and voltage drop across Rsubstrate

Rsubstrate
also increases, further increasing the NPN
emitter current (Q2 turns on “harder”),
which further increases the PNP base
current, which again further increases
 Remedies for the latch-up
problem

•One way is to keep the p-substrate tied very closely (i.e.close

proximity) to GND (most negative supply) to reduce substrate
resistance (RS1 &RS2), and the n-well tied very closely to VDD
to reduce RW1 & RW2.
• Each well must have a substrate contact of appropriate type (n-

type for n-well).

• Place substrate contacts as close as possible to the source
connection of transistors connected to the supply rails.
• Place a substrate contact for every 5- 10 transistors
• Lay out n and p- transistors with packing of n- devices towards
Gnd and p- devices towards VDD
 CMOS Process Layers

Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black
 STICK DIAGRAM

• Before the cell can be constructed from a transistor schematic it

is necessary to develop a strategy for the cell's basic layout.

• Stick Diagrams are a means for the design engineer to visualize

the cell routing and transistor placement.

•Steps involved in stick diagram construction.

•STEP 1 :       
•Identify each transistor by a unique name of its gate signal
•Identify each connection to the transistor by a unique name  
 
STICK DIAGRAM

Figure 1:
Schematic
and Graph
STICK DIAGRAM

Figure.2
Euler path
 STICK DIAGRAM
STEP2 :

• Euler’s paths : A path the traverses each node in the path, such

that each edge is visited only once.

• The path is defined by the order of each transistor name.

• The Euler path of the Pull up network must be the same as the
path of the Pull down network.

• Euler paths are not necessarily unique.

It may be necessary to redefine the function to find a Euler
path.
   F = E + (CD) + (AB) = (AB) +E + (CD)
 STICK DIAGRAM

• Next step is to lay out the stick diagram :

• Trace two green lines horizontally to represent the

NMOS and PMOS devices.

• The gate contact to the devices are represented by

vertical strips.

• Surround the NMOS device in a yellow box to

represent the surrounding Pwell material.
STICK DIAGRAM

Figure 3: Connection
label layout
 STICK DIAGRAM

• Surround the PMOS device in a green box to represent the

surrounding N-well material.

• Trace a blue line horizontally, above and below the PMOS and

NMOS lines to represent the Metal 1 of VDD and VSS.

• Label each Poly line with the Euler path label, in order from
left to right.

• Place the connection labels upon the NMOS and PMOS

devices.

• Place the VDD, VSS and all output names upon the NMOS and
PMOS devices
STICK DIAGRAM

Figure 3: Connection
label layout
Figure 4: Stick Diagram,
STICK Interconnected
DIAGRAM
SCHEMATIC
STICK-DIAGRAM NAND GATE
STICK DIAGRAM NOR GATE
 Layout Design Rules

• Design rules provide guidelines for preparing the photo masks

used in the fabrication of IC & consists of minimum-width ( line

widths ) and minimum-spacing ( interlayer ) constraints.

• The main goal of layout rules gives a circuit with optimum
yield in as small an area as possible without compromising
reliability of the circuit.

• Design rules specify the fundamental unit as minimum line

width.
• It stands for the minimum mask dimension that can be
safely transferred to the semiconductor material. The
minimum line width is set by resolution of the patterning
process ( lithographic process )
• The interaction between different layers.
Even for the same minimum dimension, design rules tend
 Layout Design Rules
• One approach to address this is to use scalable design rules.
These include
1. Lambda (  ) based rules.
2. Micron rules.
Lambda (  ) based rules : These defines all the rules as function
of single parameter called .

• Scaling of the minimum dimension is accomplished simply by

changing the value of .. This results in linear of all dimensions.
•When mapping the transistor schematic/layout to a particular
technology, the actual W, L will be calculated as:
W' (actual, microns (µ)) = W ´ (microns)
L' (actual, microns) = L ´  (microns)
 (lambda ) is dimensionless unit called as scaling factor.
 Layout Design Rules

• Scaling factor allows transistor W/L values specified in

schematic to be technology independent.(feature-size
independent way of setting out mask dimensions to scale.)
• Scaling factor allows transistor W/L values specified in
schematic to be technology independent.(feature-size
independent way of setting out mask dimensions to scale.)
• Scaling factor lambda is foundry/silicon vendor dependent
• For MOSIS foundry vendors,
1.2µ technology Þ  = 0.6
0.8µ technology Þ  = 0.4.
• Typically the minimum gate length is set to 2  and width is
varied.
 Layout Design Rules

• But linear scaling is possible over a limited range of dimensions,

hence these rules are not used by industry. Normal industrial

practice is to deal with ‘ micron rules ‘.

• Micron rules expresses the design rules in absolute dimensions

and hence can exploit the features of a given process to a
maximum degree.

• These are usually given as list of minimum feature sizes and

spacing for al the masks required in an given process.
 Design Rules

Examples
from AMS
0.6micron
technology
Intra-Layer Design Rules
Via’s and Contacts
N Transistor – Layout

Bulk Source Gate

Drain

Thin-Oxide
P Transistor - Layout

Bulk Source Gate Drain

n-
Thin-Oxide
Parallel/Series Transistors
Large MOS Transistors
AND Gate Layout
AND Gate - Layout
Inverter Layout
Inverter Layout
4-Input NAND Gate
Pseudo NMOS NAND
Gate
Logic Graph for F = (A+B)C
Layout F = (A+B)C
Logic Graph for
F = /(AB+CD)
Pass Transistor Based
Multiplexer

F
Pass Transistor Based
Multiplexer
 Pass Transistor Based
Multiplexer

Gate Gate
Source oxide Drain

substrate

n+ channel n+
holes electrons
P-substrate