CS/EE 3700 : Fundamentals of

Digital System Design

Chris J. Myers
Lecture 2: Intro. to Logic Circuits
Chapter 2
 Binary Logic Circuits
• Logic circuits perform operations on digital
signals.
• Implemented using electronic circuits.
• Binary logic circuits take only two values:
– 0 and 1.
x = 0 x = 1

(a) Two states of a switch

(b) Symbol for a switch

Figure 2.1 A binary switch

 L(x) = x

S
Battery x L Light

(a) Simple connection to a battery

S
Power
supply x L

(b) Using a ground connection as the return path

Figure 2.2 A light controlled by a switch

 S S L(x1, x2) = x1  x2
Power
supply x
1
x
2
L Light L = 1 if x1 = 1 and x2 = 1
L = 0 otherwise
(a) The logical AND function (series connection)

x
1 L(x1, x2) = x1 + x2
Power
L Light L = 1 if x1 = 1 or x2 = 1
supply S
L = 0 otherwise
x
2
(b) The logical OR function (parallel connection)

Figure 2.3 Two basic functions

 S

x1 S
Power
supply S x3 L Light

x2

L(x1, x2, x3) = (x1 + x2)  x3

Figure 2.4 A series-parallel connection

 R

Power
supply x S L

L(x) = x

L = 1 if x = 0
L = 0 if x = 1

Figure 2.5 An inverting circuit

Figure 2.6 A truth table for AND and OR
Figure 2.7 Three-input AND and OR
 x1
x2
x1
x1 x2 x1 x2 xn
x2

xn

(a) AND gates

x1
x2
x1
x1 + x2 x1 + x2 + + xn
x2

xn

(b) OR gates

x x

(c) NOT gate

Figure 2.8 The basic gates
x
1
x
2 f = x + x   x
x 1 2 3
3

Figure 2.9 An OR-AND function

 0011 1100
x
1 A
1101
f
0001 B
0101
x
2

(a) Network that implements f = x +x x

1 1 2

x x f (x , x )
1 2 1 2

0 0 1
0 1 1
1 0 0
1 1 1

(b) Truth table for f

Figure 2.10 a Logic network

 1
x
1 0

x 1
2 0

1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram

0011 1100
x
1
1101
0101 g
x
2

(d) Network that implements g = x +x

1 2

Figure 2.10 b Logic network

 Boolean Algebra
• 1849, George Boole published a scheme for
describing logical thought and reasoning.
• In 1930s, Claude Shannon applied Boolean
algebra to describe circuits built w/switches.
• Boolean algebra provides the theoretical
foundation for digital design.
 Axioms of Boolean Algebra
1. 00=0 1+1=1
2. 11=1 0+0=0
3. 01=10=0 1+0=0+1=1
4. if x = 0 then x = 1 if x = 1 then x
=0
 Single-Variable Theorems
5. x0=0 x+1=1
6. x1=x x+0=x
7. xx=x x+x=x
8. xx=0 x+x=1
9. x=x
 Principle of Duality
• Axioms and theorems listed in pairs to
show principle of duality.
• Given a logic expression, its dual is found
by exchanging + operators and  operators
and 0s ands 1s.
• The dual of any true statement is true.
 2- and 3-Variable Properties
10a. x  y = y  x Commutative
10b. x + y = y + x
11a. x  (y  z) = (x  y)  z Associative
11b. x + (y + z) = (x + y) + z
12a. x  (y + z) = x  y + x  z Distributive
12b. x + y  z = (x + y)  (x + z)
 2- and 3-Variable Properties
13a. x + x  y = x Absorption
13b. x  (x + y) = x
14a. x  y + x  y = x Combining
14b. (x + y)  (x + y) = x
15a. x  y = x + y DeMorgan’s Thm
15b. x + y = x  y
16. x + x  y = x + yx  (x + y) = x  y
Figure 2.11 Proof of DeMorgan’s theorem
(x1 + x3)  (x1 + x3) = x1  x3 + x1  x3
x1  x3 + x2  x3 + x1  x3 + x2  x3 = x1  x2 + x1  x2 + x1  x2
 x x

(a) Constant 1 (b) Constant 0 (c) Variable x

x x x y x y

(d) x (e) x y (f) x + y

x y
x y
z

(g) x y (h) x y + z

Figure 2.12 The Venn diagram representation

 x y x y

z z

(a) x (d) x y

x y x y

z z

(b) y + z (e) x z

x y x y

z z

(c) x y + z  (f) x y + x z

Figure 2.13 Verification of the distributive property

 x y

z
x y x y

x y
z z

x y y z x y

z
x y
x y
x z
z
z

x z x y
x y + x z + y z

x y + x z
Figure 2.14 Verification example
 Notation
• x = x’ = !x = NOT x
• f(x1,x2) = x1 + x2 = (x1 + x2)’ = !(x1 + x2)
= NOT(x1 + x2)
• x 1  x2 = x1  x 2 = x 1 x 2
• x 1 + x 2 = x1  x2
 Precedence of Operations
• In absence of parentheses, operations are
performed in this order: NOT, AND, OR.
x1 x2 + x1’ x2’ = (x1 x2) + ((x1’) (x2’))
Figure 2.15 A function to be synthesized
x1
x2

(a) Canonical sum-of-products

x1
f
x2

(b) Minimal-cost realization

Figure 2.16 Two implementations of a function

Figure 2.17 Three-variable Minterms and Maxterms
Figure 2.18 A three-variable function
x2

f
x3
x1

(a) A minimal sum-of-products realization

Figure 2.18 A three-variable function
x1
x3
f

x2

(b) A minimal product-of-sums realization

Figure 2.20 Truth table for a three-way light controller
 f

x
1
x
2
x
3

(a) Sum-of-products realization

Figure 2.21 SOP implementation of the three-way light controller

x
3
x
2
x
1

(b) Product-of-sums realization

Figure 2.21 POS implementation of the three-way light controller

 s x1 x2 f (s, x1, x2)
000 0
001 0 x1
010 1
011 1 f
100 0 s
101 1 x2
110 0
111 1

(a)Truth table (b) Circuit

s
s f (s, x1, x2)
x1 0 0 x1
f
x2 1 1 x2

(c) Graphical symbol (d) More compact truth-table representation

Figure 2.22 Multiplexer

 Design Entry
• Truth tables
– Practical for only small circuits.
• Schematic capture
– Interconnect symbols in some library.
– Facilitates hierarchical design.
– Good for larger circuits.
– Difficult to use for very large circuits.
Figure 2.23 Screen capture of the Waveform Editor
Figure 2.24 Screen capture of the Graphic Editor
 Design Entry (cont)
• Hardware description languages (HDLs).
– Similar to a programming language.
– VHDL and Verilog HDL are IEEE standards.
– Provide design portability.
– Allow for sharing and design reuse.
– Support hierarchical design.
– Can be combined with schematics.
 Synthesis
• Logic synthesis, or logic optimization, is process
to translate a truth table, schematic, or VHDL
code into a network of logic gates.
• What makes a circuit good depends on the
application.
• Converting logic description to a physical design
entails technology mapping and layout synthesis.
 Functional Simulation
• A functional simulator is used to determine
if designed circuit operates correctly.
• User provides inputs values to the circuit.
• Simulator determines circuits response.
• User checks responses against required.
• A timing simulator can be used to check the
performance of a design.
 Design conception

Figure 2.25
DESIGN ENTRY

Truth table Schematic capture VHDL

Simple synthesis
Translation
(see section 2.8.2)

Merge

The first stages of a CAD system

INITIAL SYNTHESIS TOOLS Boolean equations

Functional simulation

No
Design correct?

Yes

Logic synthesis, physical design, timing simulation

(see section 4.12)
 VHDL - Very high speed integrated
circuit hardware description language
• Original IEEE standard adopted in 1987.
• Revised standard in 1993.
• Originally used for documentation and
simulation.
• Now, it is also used for synthesis.
• Very complex language, but only a subset is
needed to design wide range of circuits.
 Representing Digital Signals
• Each logic signal in a circuit is a data object
in the VHDL code.
• Data objects in VHDL are assigned types.
• A simple type is BIT which is used for
objects that can only take 2 values: 0 and 1.
• Other data types are introduced later.
 x1
x2
f

x3

Figure 2.26 A simple logic function and corresponding VHDL code

Figure 2.30 VHDL code for a four-input function
x1
x3

x2

x4

Figure 2. 31 Logic circuit for four-input function

How NOT to Write VHDL Code
• Novice tempted to write code with lots of
variables and loops.
• This code style is difficult to relate to the
circuit and should be avoided.
• Good guideline is that if designer cannot
determine what circuit is doing from code,
then circuit synthesized likely will be wrong
 Concluding Remarks
• Introduced concept of logic circuits.
– Implemented using logic gates.
– Described with Boolean algebra.
• Briefly introduced CAD tools.