MICROPROCESSORS AND

MICROCONTROLLERS

Vikas Kumar Tiwari

Assistant Professor – ECE
Vignan Institute of Technology & Sciences
Email: [email protected]
Linkedin: linkedin.com/in/vikas-tiwari-9a5b7843
Lecture Content
(We shall be discussing the following for today)

Overview of 8051 Microcontroller

Architecture of 8051

8051 Pin Diagram

Registers in 8051

Memory organization of 8051

Addressing Modes

Instruction set of 8051

Interrupts of 8051

Timer Interrupts

External Hardware Interrupts

Serial Communication Interrupts

8051 Timers and Counters

Serial Communication in 8051

 Overview of
8051
Microcontroller
Microcontroller
A microcontroller is a compact integrated
circuit designed to govern a specific
operation in an embedded system. A
typical microcontroller includes a
processor, memory and input/output
(I/O) peripherals on a single chip.
 Integrated Circuits
(Microprocessors and Microcontrollers)
Microprocessor
General-purpose microprocessor
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example ： Intel’s x86, Motorola’s 680x0
 Microcontroller
A smaller computer
On-chip RAM, ROM, I/O ports...
Example ： Motorola’s 6800, Intel’s 8051, Zilog’s
Z8 and PIC 16X

CPU RAM ROM

A single chip

Serial COM
I/O Port Timer Port

Microcontroller
Microprocessors Versus Microcontroller
Microprocessors Versus Microcontroller
Microprocessors Versus Microcontroller

Microprocessor Microcontroller
CPU is stand-alone, CPU, RAM, ROM, I/O
RAM, ROM, I/O, timer and timer are all on a
are separate single chip
Designer can decide on Fix amount of on-chip
the amount of ROM, ROM, RAM, I/O ports
RAM and I/O ports. For applications in
Expansive which cost, power and
Versatility space are critical
General-purpose Single-purpose
 Three criteria in Choosing a
Microcontroller
1. Meeting the computing needs of the
task efficiently and cost effectively
 Speed, the amount of ROM and
RAM, the number of I/O ports and
timers, size, packaging, power
consumption
 Easy to upgrade
 Cost per unit
 Three criteria in Choosing a
Microcontroller

2. Availability of software development

tools
 Assemblers, debuggers, C
compilers, emulator, simulator,
technical support
 Three criteria in Choosing a
Microcontroller

3. Wide availability and reliable sources of

the microcontrollers.
 FEATURES OF 8051
 8-bit CPU optimized for control
applications

 Extensive Boolean processing (Single-bit

logic) capabilities

 64K Memory address space (Addressing

Capability)

 4K bytes of on-chip Program Memory

(ROM)

 128 bytes of on-chip Data Memory

 FEATURES OF 8051
 32 bidirectional and individually
addressable I/O lines

 Two 16-bit timer/counters

 Full duplex UART
 6-source/5-vector interrupt
structure with two priority levels

 On-chip clock oscillator

 BLOCK DIAGRAM
Interrupt Timer 0
Control
4K 128
ROM RAM Timer 1

CPU

OSC Bus Serial

Control 4 I/O Ports
Port

P0 P1 P2 P3 TXD RXD
 Architecture
Diagram of 8051
Microcontroller
Architecture of 8051
Architecture of 8051
 Pin Diagram of 8051

XTAL
P3
P1
P0

P2
_
+
 Pins of 8051 （ 1/4 ）

Vcc （ pin 40 ）： Vcc provides

supply voltage to the chip. The
voltage source is +5V.

GND （ pin 20 ）： Ground

XTAL1 and XTAL2 （ pins 19,18 ）

 XTAL Connection to 8051
 8051 has On-chip Oscillator but requires an
external clock to run it.
 A quartz crystal oscillator is connected to
XTAL inputs

C2
XTAL2
30pF

C1

XTAL1
30pF

GND
 Pins of 8051 （ 2/4 ）
RST （ pin 9 ）： RESET
It is an input pin and is active high
（ normally low).
The high pulse must be high at least
2 machine cycles.
It is a power-on reset.
Upon applying a high pulse to RST,
the microcontroller will reset and all
values in registers will be lost.
Reset values of some 8051 registers
 Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
X1
30 pF 19
11.0592 MHz
8.2 K
X2
18
30 pF
RST
9
 Pins of 8051 （ 3/4 ）
 ΕΑ (pin 31 ）： External Access
The /EA pin is connected to GND to indicate
the code is stored externally. (Used in 8031
and 8032, as no internal ROM in 8031/32)
For 8051, this pin is connected to Vcc.

 PSEN（ pin 29 ）： Program Store Enable

This is an output pin and is connected to the
OE pin of the ROM.

These above mentioned two pins are used for

external ROM.
 Pins of 8051 （ 4/4 ）
ALE （ pin 30 ）： Address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and
data.
The ALE pin is used for de-multiplexing
the address and data by connecting to
the G pin of the 74LS373 latch.

I/O port pins

The four ports P0, P1, P2, and P3.
Each port has 8 pins.
All I/O pins are bi-directional.
 Pins of I/O Port
The 8051 has four I/O ports
Port 0 （ pins 32-39) ： P0 （ P0.0 ～ P0.7 ）
Port 1 （ pins 1-8) ： P1 （ P1.0 ～ P1.7 ）
Port 2 （ pins 21-28 ） ： P2 （ P2.0 ～ P2.7 ）
Port 3 （ pins 10-17 ） ： P3 （ P3.0 ～ P3.7 ）

Each port has 8 pins.

 Named P0.X, P1.X, P2.X, P3. （ X=0,1,...,7 ）
• Ex ： P0.0 is the bit 0 （ LSB ） of P0
• Ex ： P0.7 is the bit 7 （ MSB ） of P0
 These 8 bits form a byte.

Each port can be used as input or output (bi-

direction).
 Hardware Structure of I/O Pin
Each pin of I/O ports

Internal CPU bus

A D latch

2 Tri-state buffer

A transistor M1 gate
A Pin of Port 1
 Hardware Structure of I/O Pin

Internal CPU bus ： communicate with

CPU

A D latch store the value of this pin

 D latch is controlled by “Write to
latch”
• Write to latch ＝ 1 ： write data
into the D latch
D Latch:
 Hardware Structure of I/O Pin
2 Tri-state buffer ：
 TB1: controlled by “Read pin”
• Read pin ＝ 1 ： really read the data
present at the pin
 TB2: controlled by “Read latch”
• Read latch ＝ 1 ： read value from
internal latch

A transistor M1 gate
 Gate=0: open
 Gate=1: close
Writing “1” to Output Pin P1.X
Writing “0” to Output Pin P1.X
Reading “High” at Input Pin
Reading “Low” at Input Pin
 Other Pins
P1, P2, and P3 have internal pull-up
resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and
does not connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the
same to program P0, P1, P2 and P3.
All the ports upon RESET are
configured as output.
 A Pin of Port 0

A Pin of Port 1
 Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0
P0.1

Port 0
P0.2
DS5000 P0.3
P0.4
8751 P0.5
P0.6
8951 P0.7
Port 3 Alternate Functions
RESET Value of Some 8051 Registers
Register Reset Value
PC 0000H
ACC 00H
B 00H
PSW 00H
SP 07H
DPTR 0000H
RAM are all zero
All the Ports are configured as
Output on Reset
 Memory
Organization in
8051
INTERNAL RAM STRUCTURE

Indirect Direct SFR

Addressing Addressing (Special Function
Only Only Register)

Direct &
Indirect
128 Byte
Addressing Internal RAM
 128 BYTE RAM
7FH
General Purpose
Area
30H
2FH
BIT Addressable
Area
20H 128 BYTE
1FH INTERNAL RAM
Reg Bank 3

Reg Bank 2
Register Banks
Reg Bank 1

Reg Bank 0
00H
 REGISTERS OF 8051
A
DPH DPL Data Pointer
B
R0
R1 PC Program
Counter
R2 16-bit Registers of 8051
R3
R4
R5
R6
R7
Some 8-bitt Registers of
the 8051

CY AC F0 RS1 RS0 OV - P

Program Status Word - PSW

 REGISTER BANK STRUCTURE

Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7

CY AC F0 RS1 RS0 OV - P
RAM memory space allocation in the 8051
7FH

Scratch pad RAM

30H
2FH
Bit-Addressable RAM
20H
1FH

18H Register Bank 3

17H

10H
Register Bank 2
0FH
Register Bank 1 )Stack(
08H
07H
Register Bank 0
00H
 SFR
(Special Function Registers)
F8 FF
F0 B F7
E8 EF
E0 Acc E7
D8 DF
D0 PSW D7
C8 CF
C0 C7
B8 IP BF
B0 P3 B7
A8 IE AF
A0 P2 A7
98 SCON SBUF 9F
90 P1 97
88 TCON TMOD TL0 TL1 TH0 TH1 8F
 Memory mapping in 8051
ROM memory map in 8051 family

4K 8K 32K
0FFFH 1FFFH 7FFFH

0000H
DS5000-32
0000H
8751
AT89C51 8752
0000H
AT89C52

from Atmel Corporation

from Dallas Semiconductor
Stack in the 8051

The register used to

access the stack is
called SP (stack
pointer) register.

The stack pointer in

the 8051 is only 8
bits wide, which
means that it can
take value 00 to FFH.
When 8051 powered
up, the SP register
contains value 07.
Addressing Modes
Addressing Modes
Immediate Addressing
Register Addressing
Direct Addressing
Register Indirect Addressing
Indexed Addressing
Register Indexed Addressing
 Addressing Modes
Immediate Mode –
 Specify data by its value

MOV A, #0 ;put 0 in the accumulator

;A = 00000000

MOV R4, #11H ;put 11hex in the R4 register

;R4 = 00010001

MOV B, #11 ;put 11 decimal in b register

;B = 00001011

MOV DPTR,#7521H ;put 7521 hex in DPTR

;DPTR = 0111010100100001
 Addressing Modes
Immediate Mode (Contd…)

MOV DPTR,#7521h
MOV DPL,#21H
MOV DPH, #75

COUNT EGU 30
~
~
MOV R4, #COUNT

MOV DPTR,#MYDATA
~
~
0RG 200H
MYDATA:DB “INDIA”
 Addressing Modes
Register Addressing –
 Either source or destination is one of CPU register

MOV R0,A
MOV A,R7
ADD A,R4
ADD A,R7
MOV R5,DPL
MOV B,DPH
 Addressing Modes
Direct Mode –
 Specify data by its 8-bit address, Usually for 30h-7Fh
of RAM

Mov A, 70h ;copy contents of RAM at 70h to A

Mov R0,40h ;copy contents of RAM at 40h to A

Mov 56h,A ;put contents of A at 56h

Mov 0D0h,A ;put contents of A into PSW

 Addressing Modes
Direct Mode –
 Play with R0-R7 by direct address

MOV A,4  MOV A,R4

MOV A,7  MOV A,R7

MOV R2,#5 ;Put 5 in R2

MOV R2,5 ;Put content of RAM at 5 in R2

 Addressing Modes
Register Indirect –
 The address of the source or destination is specified in
registers

Uses registers R0 or R1 for 8-bit address:

MOV PSW, #0 ; use register bank 0
MOV R0, #0X3C
MOV @R0, #3 ; memory at 3C gets #3
; M[3C]  3

Uses DPTR register for 16-bit addresses:

MOV DPTR, #0X9000 ; dptr  9000h
MOVX A, @DPTR ; a  M[9000H]

Note that 9000h is an address in external memory

 Addressing Modes

Indexed Mode –
 Source or destination address is the sum of the base
address and the accumulator(Index)

Base address can be DPTR or PC

MOV DPTR, #4000H

MOV A, #5
MOVC A, @A + DPTR ;A  M[4005]
 Addressing Modes

Register Indexed Mode

 Base address can be DPTR or PC

ORG 1000h
PC 1000 MOV A, #5
1002 MOVC A, @A + PC ;a  M[1008]
1003 NOP

 Table Lookup
 MOVC only can read internal code memory
Instruction Set
Instruction Set
Arithmetic Operation Group
Logical Operation Group
Data Transfer Group
Boolean Variable Manipulation
Group
Program Branching Group
Instruction Set

 Arithmetic Operation Group

 Logical Operation Group
 Data Transfer Group
 Boolean Variable Manipulation Group
 Program Branching Group
Instruction Set

 Arithmetic Operation Group

 Logical Operation Group
 Data Transfer Group
 Boolean Variable Manipulation Group
 Program Branching Group
Arithmetic Operation Group

ADDC A,Direct
ADDC A,Rn
ADDC A,@Ri
ADDC A,#Data
Arithmetic Operation Group

ADD A,Direct
ADD A,Rn
ADD A,@Ri
ADD A,#Data
Arithmetic Operation Group

SUBB A,Direct
SUBB A,Rn
SUBB A,@Ri
SUBB A,#Data
Arithmetic Operation Group

INC A
INC Direct
INC Rn
INC @Ri
Arithmetic Operation Group

DEC A
DEC Direct
DEC Rn
DEC @Ri
Arithmetic Operation Group

INC DPTR
MUL AB
DIV AB
DA A
Instruction Set

 Arithmetic Operation Group

 Logical Operation Group
 Data Transfer Group
 Boolean Variable Manipulation Group
 Program Branching Group
 Logical Operation Group

ANL A,Direct
ANL A,Rn
ANL A,@Ri
ANL A,#Data
ANL Direct,A
ANL Direct,#Data
 Logical Operation Group

ORL A,Direct
ORL A,Rn
ORL A,@Ri
ORL A,#Data
ORL Direct,A
ORL Direct,#Data
 Logical Operation Group

XRL A,Direct
XRL A,Rn
XRL A,@Ri
XRL A,#Data
XRL Direct,A
XRL Direct,#Data
 Logical Operation Group

CLRA
CPL A
RLA
RLCA
RRA
RRCA
SWAP A
Instruction Set

 Arithmetic Operation Group

 Logical Operation Group
 Data Transfer Group
 Boolean Variable Manipulation Group
 Program Branching Group
 Data Transfer Group

MOV A,Direct
MOV A,Rn
MOV A,@Ri
MOV A,#Data
MOV Rn,Direct
MOV Rn,@Ri
MOV Rn,#Data
 Data Transfer Group

MOV Direct,Direct
MOV Direct,Rn
MOV Direct,@Ri
MOV Direct,#Data
MOV Direct,A
MOV @Ri,A
MOV @Ri,#Data
 Data Transfer Group

MOV @Ri,Direct
MOV DPTR,#DATA16
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX @Ri,A
MOVX @DPTR,A
 Data Transfer Group

PUSH Direct
POP Direct
XCH A,Rn
XCH A,Direct
XCH A,@Ri
Instruction Set

 Arithmetic Operation Group

 Logical Operation Group
 Data Transfer Group
 Boolean Variable Manipulation Group
 Program Branching Group
 Boolean Variable
Manipulation Group

CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
Instruction Set

 Arithmetic Operation Group

 Logical Operation Group
 Data Transfer Group
 Boolean Variable Manipulation Group
 Program Branching Group
 Program Branching Group

ACALLaddr11
LCALL addr16
RET
RETI
AJMPaddr11
LJMP addr16
SJMP rel
 Program Branching Group

JZ rel
JNZ rel
CJNE A,Direct,rel
CJNE A,#Data,rel
CJNE Rn,#Data,rel
CJNE @Ri,#Data,rel
 Program Branching Group

DJNZ Rn,rel
DJNZ Direct,rel
NOP
 8051
Interrupts
8051 Interrupts
An interrupt is an external or internal event
that disturbs the microcontroller to inform
it that a device needs its service.
A Microcontroller can serve various devices.
 There are two ways to do that:
interrupts &
polling.
The program which is associated with the
interrupt is called the interrupt service
routine (ISR) or interrupt handler.
Steps in executing an interrupt
Upon receiving the interrupt signal the
Microcontroller , finish current instruction and
saves the PC on stack.
Jumps to a fixed location in memory depending on
type of interrupt
Starts to execute the interrupt service routine until
RETI (return from interrupt)
Upon executing the RETI the microcontroller
returns to the place where it was interrupted. Get
pop PC from stack
 Interrupt Sources
Original 8051 has 6 sources of interrupts
 Reset
Timer 0 overflow
 Timer 1 overflow
 External Interrupt 0
 External Interrupt 1
 Serial Port events (buffer full, buffer empty, etc)

Enhanced version has 22 sources

More timers, programmable counter array, ADC,
more external interrupts, another serial port
(UART)
 Interrupt Vectors
Each interrupt has a specific place in code memory where
program execution (interrupt service routine) begins.
External Interrupt 0: 0003h
Timer 0 overflow: 000Bh
External Interrupt 1: 0013h
Timer 1 overflow: 001Bh
Serial : 0023h
Timer 2 overflow(8052+): 002Bh
 INTERRUPTS
The Interrupt structure has the following
features:

• 6 sources / 5 vectored interrupts

• Each interrupts can be individually programmable
• Each interrupts can have two priority levels
• Priority levels can be programmed
• All interrupts can be masked by a single bit - EA
• External interrupt type can be programmed
 Edge triggered
 Level Triggered
Interrupt Enable Register :

EA : Global enable/disable.

 --- : Undefined.
ET2 :Enable Timer 2 interrupt.
ES :Enable Serial port interrupt.
ET1 :Enable Timer 1 interrupt.
EX1 :Enable External 1 interrupt.
ET0 : Enable Timer 0 interrupt.
EX0 : Enable External 0 interrupt.
 SFRs Related to INTERRUPTS
IE
EA - - ES ET1 EX1 ET0 EX0

IP
- - - PS PT1 PX1 PT0 PX0

Priority Within Level

 SFRs Related to INTERRUPTS
SCON
SM0 SM1 SM2 REN TB8 RB8 TI RI

Interrupt

TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Interrupt
 Interrupt Priority
RI / TI TF1 IE1 TF0 IE0

LOW HIGH
Enabling and disabling an Interrupt
 Interrupt Priorities
 What if two interrupt sources interrupt at the
same time?
 The interrupt with the highest PRIORITY gets
serviced first.
 All interrupts have a power on default priority
order.
1. External interrupt 0 (INT0)
2. Timer interrupt0 (TF0)
3. External interrupt 1 (INT1)
4. Timer interrupt1 (TF1)
5. Serial communication (RI+TI)
 Priority can also be set to “high” or “low” by IP reg.
Interrupt Priorities (IP) Register
- -_-- -- -- -_-- - PT2 PS PT1 PX1 PT0 PX0

IP.7: reserved
IP.6: reserved
IP.5: Timer 2 interrupt priority bit (8052 only)
IP.4: Serial port interrupt priority bit
IP.3: Timer 1 interrupt priority bit
IP.2: External interrupt 1 priority bit
IP.1: Timer 0 interrupt priority bit
IP.0: External interrupt 0 priority bit
Interrupt Priorities Example
-_-- -- -_-- - PT2 PS PT1 PX1 PT0 PX0

 MOV IP , #00000100B or SETB IP.2 gives

priority order
1. Int1
2. Int0
3. Timer0
4. Timer1
5. Serial
 MOV IP , #00001100B gives priority order
1. Int1
2. Timer1
3. Int0
4. Timer0
5. Serial
Interrupt inside an interrupt
- -_-- - -_-- -- PT2 PS PT1 PX1 PT0 PX0

 A high-priority interrupt can

interrupt a low-priority interrupt
 All interrupt are latched internally
 Low-priority interrupt wait until
8051 has finished servicing the
high-priority interrupt
 INTERRUPTS

IE0
IN T 0

TF 0
INTERRUPT
IN T 1 IE1 SOURCES

TF1
TI
RI
Over all Interrupt Block Diagram
High Priority
IE Reg IP Reg Interrupt
0

IN T 0 IT 0 IE0
1

TF 0
0
Interrupt
IN T 1 IT 1 IE1
1 Polling
Sequence

TF1
TI
RI

Global
Individual
Disable
Enable
Low Priority
Interrupt
PROGRAM AND VERIFY INTERRUPT
HANDLING IN 8051(EXAMPLE-1)
1. ORG 0000H
1. MOV TH0,#0B6H
2. LJMP MAIN
2. MOV IE,#82H
3. ORG 000BH
3. SETB TR0
4. CPL P1.2
4. BACK:
5. RETI
5. MOV P0, #'A'
6. ORG 0030H
6. MOV P2, #'B'
7. MAIN:
7. SJMP BACK
8. MOV TMOD,#02H
8. END
PROGRAM AND VERIFY INTERRUPT
HANDLING IN 8051(EXAMPLE-2)
1. ORG 0000H 10. LED2:
2. LJMP MAIN 11. MOV P2,#00H
3. ORG 0003H 12. MOV R0,#0255
4. LED1: 13. DJNZ R0,LED2
5. MOV P0,#00H 14. RETI
6. MOV R0,#0255 15. ORG 0030H
7. DJNZ R0,LED1 16. MAIN:
8. RETI 17. MOV IE,#85H
9. ORG 0013H 18. HERE:SJMP HERE
19. END
8051 Timers and
Counters
 TMOD Register:

Gate : When set, timer only runs while INT(0,1) is

high.
When reset, timer is independent of INT(0,1).
C/T : Counter/Timer select bit.
M1 : Mode bit 1.
M0 : Mode bit 0.
TCON Register:

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit.
TF0: Timer 0 overflow flag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag.
IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag.
IT0: External interrupt 0 type flag.
TCON
IE1/0: External interrupt 1 edge flag.
(External interrupt 1 Edge flag. Set to 1 when a
high-to-low edge signal is received on port 3.3
(/INT1). Cleared when processor vectors to
interrupt service routine at program address
0013h. Not related to timer operations.)
IT1/0: External interrupt 1 type flag.
(External interrupt 1 signal type control bit. Set to 1
by program to enable external interrupt 1 to be
triggered by a falling edge signal. Set to 0 by
program to enable a low-level signal on external
interrupt 1 to generate an interrupt.)
 SFRs Related to TIMER
TMOD
Gate C/T M1 M0 Gate C/T M1 M0

Timer 1 Timer 0

TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timers
 TIMERS

Timer 0 Timer 1

Mode 0 Mode 0
Mode 1 Mode 1
Mode 2 Mode 2
Mode 3
 PROGRAM AND VERIFY
TIMER/COUNTER IN 8051
1. ORG 0000H 12. SETB TR1
2. RPT: 13. BACK:
3. MOV TMOD,#15H 14. JNB TF1,BACK
4. SETB P3.4 15. CLR TF1
5. MOV TL0,#00H 16. CLR TR1
6. MOV TH0,#00H 17. DJNZ R0,AGAIN
7. SETB TR0 18. CPL P3.0
8. MOV R0,#70 19. MOV A,TL0
9. AGAIN: 20. MOV P2,A
10. MOV TL1,#00 21. SJMP RPT
11. MOV TH1,#00 22. END
Serial Communication
in 8051
 SFRs Related to SERIAL PORT
SCON
SM0 SM1 SM2 REN TB8 RB8 TI RI

PCON
SMOD - - - GF1 GF0 PD IDL
SMOD
PROGRAM FOR SERIAL COMMUNICATION
- UART OPERATION IN 8051
1. MOV TMOD, #20H 12. CLR TI
2. MOV TH1, #-3 13. MOV SBUF, #'M‘
3. MOV SCON, #50H
14. HERE2:
4. SETB TR1
15. JNB TI,HERE2
5. AGAIN:
16. CLR TI
6. MOV SBUF, #'M'
17. MOV SBUF, #'C'
7. HERE:
18. HERE3:
8. JNB TI,HERE
19. JNB TI,HERE3
9. CLR TI
20. CLR TI
10. MOV SBUF, #'P'
11. HERE1:
21. X:SJMP X

12. JNB TI,HERE1 22. END

End of Lecture
Thank You
Queries?

*Discussion*