18ECC203J – Module 3

8086 Interfacing with Memory and Programmable Devices

S – 1, 2, 3

Prepared by,
Mr. R. Prithiviraj
Dr. Diwakar R. Marur
2

S–1
Semiconductor memory interfacing & Dynamic
RAM interfacing
3 Semiconductor RAM
🠶  
4 RECAP:- Physical Memory Organisation
(Module 1, Session 6, Slide No. 12)

• Certain locations in memory are reserved for specific CPU operations. The locations
from FFFF0H to FFFFFH are reserved for operations including jump to initialisation
programme and I/O-processor initialisation.
• The locations 00000H to 003FFH are reserved for interrupt vector table.
5 Procedure to Interface RAM
🠶  
6 Example Problem

🠶 Problem: Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips

with 8086. Select suitable maps.
🠶 Solution: We know that, after reset, the IP and CS are initialized to
form address FFFF0h. Hence, this address must lie in the EPROM.
The address of RAM may be selected any where in the 1 MB
address space of 8086, but we will select the RAM address such
that the address map of the system is continuous.
7 Memory Map Table
8 Solution (cont…)
🠶  
9 Address Map
10 Diagram
11 Dynamic RAM
🠶 Whenever a large capacity memory is required in a microcomputer system, the
memory subsystem is generally designed using dynamic RAM (DRAM).

🠶 Advantages of DRAM over Static RAM

1. Higher packing density,
2. lower cost and
3. less power consumption
🠶 A static RAM cell has 6 transistors while the dynamic RAM cell has 1 transistor
and a capacitor. This leads to higher packaging density and low cost per unit.

🠶 The function of capacitor is carried out by diode that operates in a reverse bias
mode.
12 Dynamic RAM (Contd…)
🠶 The reverse-biased diode has leakage current that tends to discharge the capacitor giving
rise to the possibility of data loss. To avoid this, the stored data in the cell is refreshed in
regular intervals. The process is called as Refresh cycle.
🠶 The refresh activity is similar to reading the data from each and every cell of memory,
independent of the requirement of microprocessor. During this refresh period all other
operations related to the memory subsystem are suspended. Hence the refresh activity
causes loss of time, resulting in reduce system performance.

🠶 However keeping in view the advantages of dynamic RAM, like low power consumption,
high packaging density and low cost, most of the advanced computing system are
designed using dynamic RAM, at the cost of operating speed.

🠶 A dedicated hardware chip called as dynamic RAM controller is the most important part
of the interfacing circuit.
13 Refresh Cycle
🠶 The Refresh cycle is different from the memory read cycle in the following aspects.

1. The memory address is not provided by the CPU address bus, rather it is generated by a
refresh mechanism counter called as refresh counter.

2. Unlike memory read cycle, more than one memory chip may be enabled at a time so as to
reduce the number of total memory refresh cycles.

3. The data enable control of the selected memory chip is deactivated, and data is not
allowed to appear on the system data bus during refresh, as more than one memory units
are refreshed simultaneously. This is to avoid the data from the different chips to appear on
the bus simultaneously.

4. Memory read is either a processor initiated or an external bus master initiated and carried
out by the refresh mechanism.
14 Refresh Cycle (2)
🠶 Dynamic RAM is available in units of several kilobits to megabits of memory. This
memory is arranged internally in a 2 – D matrix so that it will have n rows and m
columns. The row address n and column address m are important for the
refreshing operation.

🠶 A 4 K bit dynamic RAM chip is internally arranged bit array of dimension 64 *

64 , i.e. 64 rows and 64 columns. The row address and column address will
require 6 bits each (since 26 = 64). These 6 bits for each row address and column
address are generated by the refresh counter, during the refresh cycles.

🠶 A complete row of 64 cells is refreshed at a time to minimize the refreshing time.

Thus the refresh counter generate row addresses only. The row address are
multiplexed, over lower order address lines.
15 Refresh Cycle (3)
🠶 During refresh cycle is in process the refresh counter puts the row address over
the address bus.

🠶 During normal processor-initiated activities the address bus of the processor is

connected to the address bus of DRAM.

🠶 A timer, called refresh timer, derives a pulse for refreshing action after each
refresh interval.

🠶 Refresh interval can be qualitatively defined as the time for which a dynamic
RAM cell can hold data charge level practically constant, i.e. no data loss takes
place.

🠶 If a dynamic RAM chip has 64 rows, then all the 64 rows are to refreshed in a
single refresh interval.
16 Refresh Cycle (4)
🠶  
17 DRAM

Dynamic RAM refresh Logic

18 Refresh Cycle (5)

🠶  
19

S–2
Programmable Peripheral Interface 8255 & Interfacing
8255 with 8086 and programming
 20 8255 – Ports
🠶 The Parallel Input-Output Port chip 8255 is also called as Programmable
Peripheral Input-Output Port. The Intel’s 8255 is designed for use with Intel’s 8-
bit, 16-bit and higher capability microprocessors. It has 24 input/output lines
which may be individually programmed in two groups of 12 lines each, OR or
three groups of eight lines.

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 GROUP A

Port A PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PC7 PC6 PC5 PC4

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port A Port C upper

Port B GROUP B
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0

Port C Port B Port C lower

21 8255 – Ports (2)
🠶 The two groups of I/O pins are named as Group A and Group B. Each of these two groups
contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four
lines or a 4-bit port. Thus, Group A contains an 8-bit port A along with a 4-bit port C
upper.

🠶 The port A lines are identified by symbols PA 0-PA7 while the port C upper lines are
identified as PC7-PC4. Similarly, Group B contains an 8-bit port B, containing lines PB 0-PB7
and a 4-bit port C with lower bits PC 0- PC3. The port C upper and port C lower can be used
in combination as an 8-bit port C. Upper and lower port C are assigned the same address.

🠶 Either Three 8- bit I/O ports or two 8-bit and two 4-bit C ports from 8255 are possible. All
of these ports can function independently either as input or as output ports. This can be
achieved by programming the bits of an internal register of 8255 called as Control Word
Register (CWR).
22 8255 – Ports (3)
🠶  
23 Pin Diagram

Pin Diagram of 8255

24 Signal Description
🠶 PA7 – PA0 : These are eight port A lines that acts as either latched output or
buffered input lines depending upon the control word loaded into the CWR.

🠶 PC7 – PC4 : Upper nibble of port C lines. They may act as either output latches or
input buffers lines. This port also can be used for generation of handshake lines
in mode 1 or mode 2.

🠶 PC3 – PC0 : These are the lower port C lines; other details are the same as PC 7 –
PC4 lines.

🠶 PB7 – PB4 : These are the eight port B lines which are used as latched output lines
or buffered input lines in the same way as port A.
25 Signal Description (2)
🠶  
26 8255 –
Addressing
Ports

Image Courtesy : 8255 data sheet

27 Signal Description (3)

🠶 In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus,
the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

🠶 D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.

🠶 RESET: A logic high on this line clears the control word register of 8255. All ports
are set as input ports by default after reset.

🠶 It has a 40 pins of 4 groups.

28 8255 –
Internal
Architecture

SECTIONS
1. Data bus
2. Read Write control logic
3. Group A and Group B
controls
4. Port A, B and C

8255 Internal Architecture

29 Architecture – Explanation
🠶  
30 Architecture – Explanation (2)
4. Port A, B and C
o Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be
programmed in 3 modes – mode 0, mode 1, mode 2
o Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode 1.
o Port C : This has an 8 bit latched input buffer and 8 bit output latched/buffer.
This port can be divided into two 4 bit ports and can be used as control
signals for port A and port B. it can be programmed in mode 0.
31 BSR and IO Mode
🠶 These are two basic modes of operation of 8255.

🠶 I/O mode and Bit Set-Reset (BSR) mode.

🠶 In BSR mode only port C (PC0-PC7) can be used to set or reset its individual port
bits. In I/O mode, the 8255 ports work as programmable I/O ports. Under the
I/O mode of operation, mode 0, mode 1 and mode 2 is possible

🠶 BSR Mode: In this mode any of the 8-bits of port C can be set or reset
depending on D0 of the control word. The bit to be set or reset is selected by bit
select flags D3, D2 and D1 of the CWR.
 32 BSR Mode

Port C bits can be

SET or RESET

Example
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 1 1 0 1

Port C: 6th bit is SET

Image Courtesy: 8255 Data sheet

 33
I/O Mode CWR

Example
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0
IO Mode 0 Port A Port C Mode Port B Port C
mode input (up) 0 output (low)
input output

Image Courtesy: 8255 Data sheet

34 Mode 0 (Basic I/O mode)
🠶 This mode is also called as basic Input/Output mode. This mode provides simple
input and output capabilities using each of the three ports. Data can be simply
read from and written to the input and output ports respectively, after
appropriate initialisation.

🠶 The salient features

1. Two 8-bit ports (port A and port B )and two 4-bit ports (port C upper and
lower ) are available. The two 4-bit ports can be combinedly used as a third
8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of 4 ports are available. so, 16 I/O configuration are possible.
35 Mode 1 (Strobed input/output mode )
🠶 In this mode the handshaking control the input and output action of the specified
port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group
which includes port B and PC0-PC2 is called as group B for Strobed data input/output.
Port C lines PC3-PC5 provide strobe lines for port A. This group including port A and
PC3-PC5 from group A. Thus, port C is utilized for generating handshake signals.

🠶 The salient features of mode 1 are listed as follows:

1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and
outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and
PC3-PC5 are used to generate control signals for port A. the lines PC 6, PC7 may be
used as independent data lines.
36 Mode 2 (Strobed bidirectional I/O)
🠶  
37

S–3
Interfacing ADC with 8086 and programming &
Interfacing DAC with 8086 and programming
38 Analog-to-Digital Converter (ADC)

🠶 µP considers ADC as a input device. So, it sends Start of Conversation (SoC) signal
(pulse of a specific duration) to ADC.

🠶 Analog to digital conversion is a slow process. So, ADC will send a End of
Conversion (EoC) signal to µP, when the conversion is over. Then µP can take the
result from the buffer. EoC signal can trigger a interrupt in 8086 or µP can poll
the EoC signal.

🠶 Usually µP will use the IO ports of 8255 to interact with ADC. Like reading EoC
signal from ADC and reading digital output of ADC.
39 Analog-to-Digital Converter (2)
🠶 The time taken by the ADC from the active edge of SoC pulse till the active edge
of EoC signal is called as the conversion delay of the ADC.

🠶 Conversion delay: few µs (fast ADC) to few 100 ms (slow ADC).

🠶 Most popular conversion techniques in integrated ADC chips

• Successive Approximation Techniques

• Dual Slope Integration Techniques

40 ADC Interfacing – General Algorithm

1. Ensure the stability of analog input, applied to the ADC.

2. Issue SoC pulse to ADC
3. Read EoC signal to mark the end of conversion processes.
4. Read digital data output of the ADC as equivalent digital output.
5. Analog input voltage must be constant at the input of the ADC right from the
start of conversion till the end of the conversion to get correct results.
This may be ensured by a sample and hold circuit (S-H) which samples the analog signal
and holds it constant for a specific time duration. µP issue a hold signal to the S-H circuit.
6. If the applied input changes before the complete conversion process is over, the
digital equivalent of the analog input calculated by the ADC may not be correct.
41 ADC 808 and 809 Characteristics
🠶 The ADC chips 0808 and 0809 are 8-bit CMOS, successive approximation converters.
The conversion delay is 100 µs at a clock frequency of 640 KHz.

🠶 No need of external zero or full scale adjustments. They are inbuilt in the chip.

🠶 These converters internally have a 3:8 analog multiplexer so that at a time 8 different
analog conversion can be carried out. Use address lines - ADD A, ADD B, ADD C.

🠶 In multichannel applications – The CPU drive the lines using output port.
In single channel applications – the lines are hardwired to select the input.

🠶 There are unipolar analog to digital converters, i.e. they are able to convert only
positive analog input voltage to their digital equivalent. These chips do no contain any
internal sample and hold circuit.
42 Table

Address mapping
NOTE
▪ The signal I/P0 is referred as IN0 in Pin Diagram
▪ The signals O0, O2, … O7 are referred as 2-8, 2-7 … 2-1 in Pin Diagram
43 Block
Diagram

Image Courtesy: 808 IC data sheet

44 Pin Diagram

Image Courtesy: ADC 808 Data sheet

45 Example Interfacing Problem
🠶 Example: Interfacing ADC 0808 with 8086 using 8255 ports. Use port A of 8255 for
transferring digital data output of ADC to the CPU and port C for control signals. Assume that
an analog input is present at I/P2 of the ADC and a clock input of suitable frequency is
available for ADC.
🠶 Solution: The analog input I/P2 is used and therefore address pins A,B,C should be 0,1,0
respectively to select I/P2. The OE and ALE pins are already kept at +5V to select the ADC
and enable the outputs.
🠶 Port C upper receives the EoC D7 D6 D5 D4 D3 D2 D1 D0
signal. Port C lower sends 1 0 0 1 1 0 0 0
(output) SoC to the ADC. IO Mode 0 Port A Port C Mode 0 Port B Port C
mode input (up) output (low)
Port A acts as a 8-bit input data input output
🠶 .
port to receive the digital data
output from the ADC. CWR is holding a value 98h
46 Interfacing Diagram

Image Courtesy: A. K. Ray Book

47 ALP to MOV AL, 98h ; initialise 8255 as OUT
OUT CWR, AL ; discussed above.
interface MOV AL, 02h ; Select I/P2 as analog input
8086 and 808OUT PortB, AL ; PortB – Port address
MOV AL, 00h ; Give SoC pulse to ADC
OUT PortC, AL ; PortC – Port address
MOV AL, 01h
OUT PortC, AL
MOV AL, 00h
OUT PortC, AL
WAIT: IN AL, PortC ; Check for EoC by
RCR ; reading port C upper and
JNC WAIT ; rotating through carry.
IN AL, PortA ; If EoC, read digital equivalent in AL
HLT ; Stop.
48 Digital Analog Converters

🠶 The digital to analog converters convert binary number into their

equivalent voltages (analog).

🠶 The DAC find applications in areas like digitally controlled gains, motors
speed controls, programmable gain amplifiers etc. AD 7523

🠶 8-bit Multiplying DAC : This is a 16 pin DIP, multiplying digital to analog

converter, containing R-2R ladder for D-A conversion along with single
pole double thrown NMOS switches to connect the digital inputs to the
ladder.
49 Digital Analog Converters (2)
🠶 The supply range is from +5V to +15V, while Vref may be anywhere between -10 V
to +10 V. The maximum analog output voltage will be anywhere between -10 V
to +10 V, when all the digital inputs are at logic high state.

🠶 Usually a Zener is connected between OUT1 and OUT2 to save the DAC from
negative transients. An operational amplifier is used as a current to voltage
converter at the output of AD to convert the current output of AD to a
proportional output voltage.

🠶 It also offers additional drive capability to the DAC output.

🠶 An external feedback resistor acts to control the gain. No need to connect any
external feedback resistor, if no gain control is required.
50
Pin Diagram

Image Courtesy: A.K. Ray book

51 8086 – AD7253 Interface Diagram
52 Code 🠶EXAMPLE: Interfacing DAC AD7523 with an 8086 CPU running at 8 MHz and
write an ALP to generate a sawtooth waveform of period 1 ms with V max 5V.

ASSUME CS: CODE

CODE SEGMENT
START : MOV AL ,80h ;make all ports output
OUT CWR, AL
AGAIN : MOV AL,00h ;start voltage for ramp
BACK : OUT PA, AL
INC AL
D7 D6 D5 D4 D3 D2 D1 D0
CMP AL, 0FFh
JB BACK 1 0 0 0 0 0 0 0
IO Mode 0 Port A Port C Mode Port B Port C
JMP AGAIN mode output (up) 0 output (low)
output output
CODE ENDS
END START CWR is holding a value 80h
53 ALP - Explanation
🠶 Port A is initialized as the output port for sending the digital data as input to DAC.
The ramp starts from the 0 V (analog), hence AL starts with 00H.

🠶 To increment the ramp, the content of AL is increased during each execution of

loop till it reaches F2H.

🠶 After that the saw tooth wave again starts from 00H, i.e. 0 V (analog) and the
procedure is repeated.

🠶 The ramp period given by this program is precisely 1.000625 msec.

🠶 Here the count F2H has been calculated by dividing the required delay of 1ms by
the time required for the execution of the loop once. The ramp slope can be
controlled by calling a controllable delay after the OUT instruction.
54 Learning Resource
[1] K. M. Bhurchandi and A. K. Ray, “Advanced Microprocessors
and Peripherals – with ARM and an Introduction to
Microcontrollers and Interfacing”, Tata McGraw Hill, 3rd ed.,
2015.

Note: Almost all figures and text content taken from the above
stated book.
Thank You